Memristor, spiking neuron with random discarding function and neural network

Abstract

The invention discloses a memristor, a spiking neuron with a random discarding function and a neural network, and relates to the technical field of neural networks, the memristor comprises an active electrode layer, a resistance change layer and an inert electrode layer which are stacked, the resistance change layer has an ion migration characteristic, the memristor obtains a volatile analog switch resistance change behavior through the resistance change layer, and the active electrode layer and the inert electrode layer are stacked. The memristor obtains a digital switch resistance change behavior by applying a positive voltage to the active electrode layer, and the digital switch resistance change behavior of the memristor randomly changes between a volatile digital switch resistance change behavior and a non-volatile digital switch resistance change behavior. Through the mode, the memristors have three different resistance change behaviors, after the two memristors are connected in series, one memristor realizes a Dropout function by utilizing volatile and non-volatile digital switch resistance change behaviors, the other memristor realizes an LIF function by utilizing volatile analog switch behaviors, and a spiking neuron with a probability-adjustable Dropout function and a neural network are constructed on hardware.

Description

Technical Field

[0001] This application relates to the field of neural network technologies, and particularly to memristors, spiking neurons with a dropout function, and neural networks. Background Art

[0002] Neurons are the basic units of neural networks. Neural networks achieve complex information processing and decision-making functions through the combination of multiple layers of neurons. The Dropout function can reduce the dependence on specific neurons by randomly discarding neurons, improving the generalization ability of neural network models. In recent years, it has begun to be applied in the fields of neuromorphic computing and brain-inspired chips. Most current research focuses on the algorithm level, using Dropout to improve the performance of neural networks, while the hardware implementation of the Dropout function still faces many challenges. First, it is necessary to efficiently generate randomness in hardware to simulate the random discarding of neurons. However, due to the existence of noise, the generation of high-quality randomness is more complex. Second, the hardware implementation needs to have an adjustable probability to support flexible adjustment of the Dropout probability to adapt to different task requirements. Third, the hardware implementation needs to balance low power consumption and high integration, and also ensure that the Dropout unit can be seamlessly integrated into the existing neural network hardware architecture.

[0003] The above content is only used to assist in understanding the technical solution of the present invention, and does not represent an admission that the above content is prior art. Summary of the Invention

[0004] The main purpose of this application is to provide a memristor, a spiking neuron with a dropout function, and a neural network, aiming to solve the technical problem in the prior art that it is difficult to simulate the random discarding function of neurons in hardware.

[0005] To achieve the above purpose, this application provides a memristor. The memristor includes an active electrode layer, a resistive switching layer, and an inert electrode layer. The resistive switching layer is located above the active electrode layer, and the inert electrode layer is located above the resistive switching layer. The resistive switching layer has ion migration characteristics. The memristor obtains volatile analog switch resistive switching behavior through the resistive switching layer, and obtains digital switch resistive switching behavior by applying a positive voltage to the active electrode layer. The digital switch resistive switching behavior of the memristor randomly changes between volatile digital switch resistive switching behavior and non-volatile digital switch resistive switching behavior.

[0006] In one embodiment, the random appearance probability of the volatile digital switch resistive switching behavior in the random change decreases with the increase of the limiting current, and the random appearance probability of the non-volatile digital switch resistive switching behavior in the random change increases with the increase of the limiting current.

[0007] In one embodiment, when a positive voltage is applied, a conductive filament is formed in the resistive switching layer. The breakage of the conductive filament is random. If the conductive filament breaks after the voltage is removed, the memristor obtains volatile digital switching resistive switching behavior. If the conductive filament does not break after the voltage is removed, the memristor obtains non-volatile digital switching resistive switching behavior. The ion migration characteristics of the resistive switching layer enable the resistance value of the memristor to change according to the electric field strength and direction, obtaining volatile analog switching resistive switching behavior.

[0008] In addition, to achieve the above object, the present application provides a spiking neuron with a random dropout function. The spiking neuron with a random dropout function includes a first functional neuron and a second functional neuron. Both the first functional neuron and the second functional neuron are memristors as described above. The first functional neuron and the second functional neuron are connected in series through a shared active electrode layer. A target voltage is applied to the shared active electrode layer, and the inert electrode layer of the second functional neuron is grounded. The first functional neuron is used to simulate the process of random dropout based on the volatile digital switching resistive switching behavior and non-volatile digital switching resistive switching behavior that vary randomly. The second functional neuron is used to simulate the reaction process of a biological neuron receiving external stimuli based on the volatile analog switching resistive switching behavior.

[0009] In one embodiment, the target limit current of the first functional neuron is set according to the target random performance probability in the random variation of the volatile digital switching resistive switching behavior and the non-volatile digital switching resistive switching behavior. The target random performance probability is set according to the target dropout probability of the random dropout.

[0010] In addition, to achieve the above object, the present application provides a spiking neuron circuit with a random dropout function. The spiking neuron circuit with a random dropout function includes a digital resistive switching memristor and an analog resistive switching memristor connected in series. Both the digital resistive switching memristor and the analog resistive switching memristor are memristors as described above. The digital resistive switching memristor is connected to a target voltage, and the analog resistive switching memristor is connected to an output terminal. The analog resistive switching memristor is used to simulate the reaction process of a biological neuron receiving external stimuli based on the volatile analog switching resistive switching behavior. The digital resistive switching memristor is used to simulate the process of random dropout based on the volatile digital switching resistive switching behavior and non-volatile digital switching resistive switching behavior that vary randomly.

[0011] In one embodiment, the pulsed neuron circuit with a random dropout function further includes a switching element and a transistor. The digital resistive random access memory (RRAM) and the analog RRAM are connected through the switching element. The first end of the transistor is respectively connected to the digital RRAM and the switching element, and the second end of the transistor is grounded. The analog RRAM obtains the volatile analog switching resistive behavior when the transistor is turned off and the switching element is closed. The digital RRAM obtains the volatile digital switching resistive behavior with random variation and the non-volatile digital switching resistive behavior when the transistor is turned on and the switching element is open.

[0012] In addition, to achieve the above object, the present application provides a neural network with a random dropout function. The neural network with a random dropout function includes a hidden layer, and the hidden layer includes a random dropout layer. The random dropout layer includes a plurality of pulsed neurons with a random dropout function as described above arranged in an array. The random dropout layer is configured to, when receiving external data, perform neuron dropout according to a target dropout probability to determine effective neurons, so that the hidden layer performs feature extraction based on the effective neurons to obtain target features.

[0013] In one embodiment, the neural network with a random dropout function further includes an input layer and an output layer, and the hidden layer is respectively connected to the input layer and the output layer. The input layer is configured to obtain the external data and input the external data into the hidden layer. The output layer is configured to generate a prediction result based on the target features.

[0014] In addition, to achieve the above object, the present application further provides a preparation method for a resistive random access memory (RRAM). The preparation method includes: Providing a substrate; Depositing an active metal on the substrate to form an active electrode layer; Transferring a functional material with ion migration characteristics onto the active electrode layer to form a resistive layer; Depositing an inert metal on the resistive layer to form an inert electrode layer.

[0015] In one embodiment, the step of depositing an active metal on the substrate to form an active electrode layer includes: Performing patterning on the substrate based on a first preset pattern; Depositing an active metal on the patterned substrate based on a first preset thickness to form the active electrode layer; The step of depositing an inert metal on the resistive layer to form an inert electrode layer includes: Pattern the resistive switching layer based on a second preset pattern; Deposit an inert metal on the patterned resistive switching layer based on a second preset thickness to form the inert electrode layer.

[0016] This application provides a memristor, including an active electrode layer, a resistive switching layer, and an inert electrode layer which are stacked. The resistive switching layer has ion migration characteristics. The memristor obtains volatile analog switch resistive switching behavior through the resistive switching layer, and obtains digital switch resistive switching behavior by applying a positive voltage to the active electrode layer. The digital switch resistive switching behavior of the memristor randomly changes between volatile digital switch resistive switching behavior and non-volatile digital switch resistive switching behavior. The memristor in this application has three different resistive switching behaviors. After two memristors are connected in series, one uses the randomly changing volatile and non-volatile digital switch resistive switching behaviors to implement the Dropout function, and the other uses the volatile analog switch behavior to implement the LIF (Leaky-Integrate-Fire) function, thereby constructing a pulsed neuron and neural network with the Dropout function on hardware. At the same time, by regulating the magnitude of the applied voltage, the polarity of the applied voltage, and the magnitude of the limiting current, the randomness of the volatile and non-volatile digital switch resistive switching behaviors can be regulated, and then the Dropout function with adjustable probability can be realized, solving the technical problem of being difficult to simulate the random dropout function of neurons in hardware. Description of the Drawings

[0017] The drawings here are incorporated into the specification and form a part of this specification, showing embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0019] Figure 1 It is a schematic structural diagram of an embodiment of the memristor provided by this application; Figure 2 It is a schematic diagram of the resistive switching curve of the analog switch resistive switching behavior of the memristor provided by the embodiment of this application; Figure 3 It is a schematic diagram of the analog LIF model of the memristor provided by the embodiment of this application; Figure 4 It is a schematic diagram of the pulse test current change of the memristor provided by the embodiment of this application; Figure 5 It is a schematic diagram of the volatile digital switch resistive switching behavior of the memristor provided by the embodiment of this application; Figure 6 Schematic diagram of the non-volatile digital switching resistive switching behavior of the memristor provided by the embodiment of the present application; Figure 7 Schematic diagram of the structure of an embodiment of the spiking neuron with random dropout function provided by the present application; Figure 8 Schematic diagram of the structure of an embodiment of the spiking neuron circuit with random dropout function provided by the present application; Figure 9 Schematic diagram of the structure of an embodiment of the neural network provided by the present application; Figure 10 Schematic diagram of the Dropout layer of the neural network provided by the embodiment of the present application; Figure 11 Schematic diagram of the two-layer network structure of the neural network provided by the embodiment of the present application; Figure 12 Schematic diagram of the process of an embodiment of the preparation method of the memristor provided by the present application.

[0020] Explanation of the reference numerals in the drawings: 10. Memristor; 11. Active electrode layer; 11a. Shared active electrode layer; 12. Resistive switching layer; 12a. First resistive switching layer; 12b. Second resistive switching layer; 13. Inert electrode layer; 13a. First inert electrode layer; 13b. Second inert electrode layer; 14. Substrate; 100. Spiking neuron with random dropout function; 101. First functional neuron; 102. Second functional neuron; 200. Spiking neuron circuit with random dropout function; 201. Digital resistive switching memristor; 202. Analog resistive switching memristor; 203. Switching element; 204. Bipolar junction transistor; 1000. Neural network with random dropout function; 1001. Hidden layer; 1001a. Random dropout layer; 1002. Input layer; 1003. Output layer; V. Applied target voltage.

[0021] The realization, functional features and advantages of the object of the present application will be further described in conjunction with the embodiments with reference to the accompanying drawings. Detailed implementation manners

[0022] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0023] In order to better understand the technical solutions of the present application, the following will be described in detail in conjunction with the drawings of the specification and the specific implementation manners.

[0024] The main solution of the embodiment of the present application is: to provide a memristor, including an active electrode layer, a resistive switching layer, and an inert electrode layer which are stacked. The resistive switching layer has the characteristic of ion migration. The memristor obtains volatile analog switch resistive switching behavior through the resistive switching layer. The memristor obtains digital switch resistive switching behavior by applying a positive voltage to the active electrode layer. The digital switch resistive switching behavior of the memristor randomly changes between volatile digital switch resistive switching behavior and non-volatile digital switch resistive switching behavior.

[0025] The present application provides a solution to design a memristor with three different resistive switching behaviors. After two memristors are connected in series, one uses the volatile and non-volatile digital switch resistive switching behaviors that randomly change to implement the Dropout function, and the other uses the volatile analog switch behavior to implement the LIF function, so as to construct a pulsed neuron and neural network with the Dropout function on hardware. At the same time, by regulating the magnitude of the applied voltage, the polarity of the applied voltage, and the magnitude of the limited current, the randomness of the volatile and non-volatile digital switch resistive switching behaviors can be regulated, and then the Dropout function with adjustable probability can be realized, solving the technical problem that it is difficult to simulate the random dropout function of neurons in hardware.

[0026] It should be noted that if there are directional indications (such as up, down, left, right, front, back...) involved in the embodiments of the present application, the directional indications are only used to explain the relative position relationship and movement conditions between components in a specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0027] In addition, if there are descriptions such as "first", "second", etc. involved in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, if "and / or" or "and / or" appears throughout the text, its meaning includes three parallel solutions. Taking "A and / or B" as an example, it includes solution A, or solution B, or the solution where A and B are satisfied simultaneously. In addition, the technical solutions between the embodiments can be combined with each other, but it must be based on the fact that those skilled in the art can implement it. When the combination of technical solutions conflicts with each other or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention.

[0028] The embodiment of the present application provides a memristor, referring to Figure 1 , Figure 1 which is a schematic structural diagram of an embodiment of the memristor provided by the present application.

[0029] In this embodiment, the memristor 10 includes an active electrode layer 11, a resistive switching layer 12, and an inert electrode layer 13. The resistive switching layer 12 is located above the active electrode layer 11, and the inert electrode layer 13 is located above the resistive switching layer 12, forming a sandwich structure. In addition, the active electrode layer 11 is usually disposed above the substrate 14.

[0030] It should be noted that the resistive switching layer 12 is prepared using a functional material with ion migration characteristics. That is to say, the resistive switching layer 12 in this embodiment has ion migration characteristics. The active electrode layer 11 is usually an active electrode prepared using an active metal, and the inert electrode layer 13 is usually an inert electrode prepared using an inert metal.

[0031] It can be understood that the memristor 10 can obtain volatile analog switching resistive switching behavior through the resistive switching layer 12. At the same time, the memristor 10 can obtain digital switching resistive switching behavior by applying a positive voltage to the active electrode layer 11. The digital switching resistive switching behavior of the memristor 10 randomly changes between volatile digital switching resistive switching behavior and non-volatile digital switching resistive switching behavior. It can be seen that the memristor 10 in this embodiment has three different resistive switching behaviors: volatile analog switching resistive switching behavior, volatile digital switching resistive switching behavior, and non-volatile digital switching resistive switching behavior.

[0032] It should be understood that in this embodiment, the ion migration characteristics of the resistive switching layer 12 cause the resistance value of the memristor 10 to change according to the electric field strength, obtaining volatile analog switching resistive switching behavior. Since the functional material used as the resistive switching layer 12 has ion migration characteristics (the phenomenon of ions migrating through a medium under specific conditions), the ions in the functional material will migrate directionally under the action of an electric field, resulting in the accumulation of ions at the electrodes, thereby changing the barrier height at the interface between the functional material and the electrodes, realizing the change of the resistance of the memristor 10 and having a resistive switching effect. This also means that by changing the direction and strength of the electric field, a memristor 10 with analog switching behavior can be obtained. Since a concentration gradient appears in the functional material after ion migration, when the electric field is removed, the ions will migrate back, resulting in the change of the resistance being volatile. Therefore, in this mode, the resistance value of the memristor 10 will change with the change of the electric field strength and direction. At this time, the resistive switching behavior of the memristor 10 shows volatile analog switching resistive switching behavior, and its resistive switching curve is as Figure 2 shown.

[0033] It should be noted that the LIF model is a mathematical model used to simulate the behavior of biological neurons. A neuron is regarded as a capacitor that can accumulate the current passing through the membrane. When a neuron receives input signals from other neurons, these signals are injected into the capacitor as transient currents, causing the membrane potential to gradually increase. In the absence of external input, the membrane potential also gradually decreases over time back to the resting potential. Once the membrane potential reaches or exceeds a certain threshold, the neuron will "fire", that is, generate an action potential and transmit this signal to other neurons. The characteristics of the resistive switching behavior of the volatile analog switch highly match the LIF model. Refer to Figure 3 , the active electrode layer is regarded as dendrite A, the inert electrode layer is regarded as dendrite B, and the resistive switching layer is used as the axon. Dendrite A receives signals from other neurons and converts them into electrical signals. When the membrane potential reaches the threshold, the neuron will trigger an action potential, which is conducted along the axon to the axon terminal. The axon terminal releases neurotransmitters, which bind to the receptors on the membrane of the postsynaptic dendrite B, changing its membrane potential and completing the emission of the action potential.

[0034] In specific implementation, by using the continuous modulation function of the conductance of the memristor 10 under pulse testing, the LIF function can be simulated. Refer to Figure 4 , when the pulse voltage continuously stimulates, the conductance of the memristor 10 slowly increases, similar to the increase in the membrane potential of a neuron when it is stimulated; when the pulse stimulation continues to be maintained, the conductance of the memristor 10 increases to the threshold, realizing the emission of the neuron action potential; due to the volatility of the memristor 10, the device conductance will spontaneously decrease back to the resting potential. Therefore, the resistive switching behavior of the volatile analog switch based on this resistive switching mechanism can simulate the LIF function of biological neurons, that is, simulate the response process of biological neurons receiving external stimuli. Taking the memristor 10 as a pulse neuron that can simulate the LIF function, an efficient neuromorphic hardware can thus be constructed using its natural non-linear response and low power consumption characteristics, such as a spiking neural network (SNN) applied to simulate biological neural networks and transmitting information through the timing and frequency of pulses.

[0035] It can be understood that in this embodiment, the active electrode layer 11 is utilized to achieve the digital switching resistive switching behavior of the memristor 10. When a positive voltage is applied, the active electrode layer 11 is oxidized into ions, which migrate towards the negative electrode under the action of an electric field and are reduced to atoms at the negative electrode, forming conductive filaments (usually nano-conductive filaments) in the resistive switching layer 12. At this time, the memristor 10 becomes a low-resistance state; when a negative voltage is applied to the active electrode layer 11, on the one hand, the current density in the filaments increases, resulting in local fusing of the filaments, and on the other hand, the atoms in the resistive switching layer 12 are oxidized into ions, causing the filaments to break. At this time, the memristor 10 becomes a high-resistance state. Due to the migration of the ions formed by the active electrode layer 11 under the action of an electric field and the dynamic formation and breaking of the nano-conductive filaments, the memristor 10 can quickly switch between the high-resistance state and the low-resistance state, realizing the digital switching resistive switching behavior. The digital switching resistive switching behavior includes volatile digital switching resistive switching behavior and non-volatile digital switching resistive switching behavior. The radius of the formed conductive filaments plays an important role in the volatility and non-volatility of the memristor 10. When the radius of the conductive filaments is small (the radius is less than or equal to a certain value), after the applied electric field is removed, the conductive filaments break spontaneously, and the memristor 10 exhibits volatility; when the radius of the conductive filaments is large (the radius is greater than a certain value), it can still be maintained after the electric field is removed, and a reverse electric field is required to break it, and the memristor 10 exhibits non-volatility. It can be seen that the breaking of the conductive filaments is random. If the conductive filaments break after the voltage is removed, the memristor 10 obtains volatile digital switching resistive switching behavior. If the conductive filaments do not break after the voltage is removed, the memristor 10 obtains non-volatile digital switching resistive switching behavior. During voltage writing, due to the randomness of the formation and breaking of the conductive filaments, the volatility and non-volatility exhibited by the memristor 10 are also random and do not show a single characteristic. In addition, during voltage writing, whether the memristor 10 remains in the low-resistance state is also random, which means that the memristor 10 simultaneously has volatility and non-volatility. At this time, the volatile digital switching resistive switching behavior and non-volatile digital switching resistive switching behavior exhibited by the memristor 10 are random. A relatively large positive voltage is required to form conductive filaments using the active electrode layer 11. Before this, the resistive switching mechanism of the memristor 10 is dominated by the ion migration characteristics of the functional material.

[0036] It should be understood that by controlling some key conditions, the transition between volatile and non-volatile states can be achieved. In this embodiment, the random manifestation probability of the volatile digital switching resistive switching behavior in random variations decreases as the limiting current increases, while the random manifestation probability of the non-volatile digital switching resistive switching behavior in random variations increases as the limiting current increases. The random manifestation probability is the probability of randomly manifesting a certain resistive switching behavior. The random manifestation probability of the volatile digital switching resistive switching behavior is the probability that the memristor 10 randomly manifests the volatile digital switching resistive switching behavior, and the random manifestation probability of the non-volatile digital switching resistive switching behavior is the probability that the memristor 10 randomly manifests the non-volatile digital switching resistive switching behavior. Refer to Figure 5 , when the set limiting current is small, the memristor 10 exhibits volatile digital switching resistive switching behavior, which means that when the voltage is removed, the resistance value of the memristor 10 will spontaneously return to the high-resistance state. Refer to Figure 6 , when the set limiting current is large, the memristor 10 exhibits non-volatile digital switching resistive switching behavior, and a negative voltage is required to break the formed conductive filament, and the memristor 10 returns to the high-resistance state. In this embodiment, by increasing the limiting current, the memristor 10 can transition from volatile digital switching resistive switching behavior to non-volatile digital switching resistive switching behavior. This transition is not a sudden transition reaching a threshold. In specific implementation, the volatile digital switching resistive switching behavior and non-volatile digital switching resistive switching behavior of the memristor 10 at different limiting currents are random behaviors with specific probabilities. That is to say, when a certain limiting current is set, the memristor 10 has both volatile and non-volatile characteristics simultaneously. At this time, the volatile digital switching resistive switching behavior and non-volatile digital switching resistive switching behavior exhibited by the memristor 10 are random, that is, the digital switching resistive switching behavior of the memristor 10 randomly varies between volatile digital switching resistive switching behavior and non-volatile digital switching resistive switching behavior. If the limiting current is increased, the probability that the memristor 10 exhibits non-volatility will increase, that is, the memristor 10 is more inclined to obtain non-volatile digital switching resistive switching behavior; if the limiting current is decreased, the probability that the memristor 10 exhibits volatility will increase, that is, the memristor 10 is more inclined to obtain volatile digital switching resistive switching behavior. By setting an appropriate limiting current, after voltage writing, the current high and low resistance values of the memristor 10 are probabilistic. When the memristor 10 is in the low-resistance state, the state of the memristor 10 is on, allowing the transmission of current and information. When the memristor 10 is in the high-resistance state, the state of the memristor 10 is off. Utilizing the random variations of the volatile digital switching resistive switching behavior and non-volatile digital switching resistive switching behavior of the memristor 10, the Dropout function can be simulated, that is, the process of randomly discarding (neurons) can be simulated.

[0037] This embodiment provides a memristor, which includes an active electrode layer, a resistive switching layer, and an inert electrode layer arranged in a stacked manner. The resistive switching layer is located above the active electrode layer, and the inert electrode layer is located above the resistive switching layer. The resistive switching layer has the characteristic of ion migration. The memristor obtains volatile analog switch resistive switching behavior through the resistive switching layer, and obtains digital switch resistive switching behavior by applying a positive voltage to the active electrode layer. The digital switch resistive switching behavior of the memristor randomly changes between volatile digital switch resistive switching behavior and non-volatile digital switch resistive switching behavior. The memristor in this embodiment has three different resistive switching behaviors. By using the randomly changing volatile and non-volatile digital switch resistive switching behaviors, the Dropout function can be realized, and by using the volatile analog switch behavior, the LIF function can be realized, so as to construct a pulsed neuron and neural network with the Dropout function on hardware.

[0038] An embodiment of the present application provides a pulsed neuron with a random dropout function. Refer to Figure 7 , Figure 7 which is a schematic structural diagram of an embodiment of the pulsed neuron with a random dropout function provided by the present application.

[0039] In this embodiment, the pulsed neuron 100 with a random dropout function includes a first functional neuron 101 and a second functional neuron 102. Both the first functional neuron 101 and the second functional neuron 102 are the memristors 10 in the above embodiment, including an active electrode layer, a resistive switching layer, and an inert electrode layer. The specific structure can be referred to Figure 1 , and will not be elaborated here. In this embodiment, the first functional neuron 101 and the second functional neuron 102 are connected in series through a shared active electrode layer. A target voltage is applied to the shared active electrode layer, and the inert electrode layer (the second inert electrode layer 13b) of the second functional neuron 102 is grounded. The first functional neuron 101 includes a shared active electrode layer 11a, a first resistive switching layer 12a, and a first inert electrode layer 13a. The second functional neuron 101 includes a shared active electrode layer 11a, a second resistive switching layer 12b, and a second inert electrode layer 13b. The entire pulsed neuron 100 includes a shared active electrode layer 11a, a first resistive switching layer 12a, a first inert electrode layer 13a, a second resistive switching layer 12b, and a second inert electrode layer 13b arranged in a stacked manner from bottom to top.

[0040] It can be understood that the first functional neuron 101 is used to simulate the random dropout process based on the randomly changing volatile digital switch resistive switching behavior and non-volatile digital switch resistive switching behavior; the second functional neuron 102 is used to simulate the reaction process of a biological neuron receiving external stimuli based on the volatile analog switch resistive switching behavior.

[0041] It should be noted that in this embodiment, the volatile analog switch resistive switching behavior of the second functional neuron 102 is utilized to simulate the LIF function, and the volatile digital switch resistive switching behavior and non-volatile digital switch resistive switching behavior of the first functional neuron 101 are utilized to simulate the Dropout function. Since both the digital resistive random access memory (RRAM) 201 and the analog RRAM 202 are RRAMs 10. Each RRAM 10 can be used to simulate a neuron. By simulating the LIF function, the simulation of spiking neurons can be achieved. Connecting two RRAMs 10 in series can simulate the LIF function and the Dropout function, and at this time, spiking neurons with the Dropout function can be realized.

[0042] It can be understood that the target voltage is the voltage set to be applied to the first functional neuron 101. The polarity of the target voltage can be a positive voltage or a negative voltage, and the magnitude of the target voltage can be set according to actual requirements, and no specific limitation is made here. The target limit current is the limit current set for the first functional neuron 101. The target limit current of the first functional neuron 101 is set according to the target random manifestation probability in the random variation of the volatile digital switch resistive switching behavior and the non-volatile digital switch resistive switching behavior. The target random manifestation probability is the probability set for the first functional neuron 101 to randomly manifest a certain resistive switching behavior. The target random manifestation probability of the volatile digital switch resistive switching behavior is the probability that the first functional neuron 101 needs to randomly manifest the volatile digital switch resistive switching behavior, and the target random manifestation probability of the non-volatile digital switch resistive switching behavior is the probability that the first functional neuron 101 needs to randomly manifest the non-volatile digital switch resistive switching behavior. The target random manifestation probability is set according to the target dropout probability of random dropout. The target dropout probability is the probability set for the spiking neuron to be dropped, and the specific value is set according to actual requirements, and no specific limitation is made here.

[0043] In specific implementation, by adjusting the magnitude and polarity of the target voltage, the digital switch resistive switching behavior can be obtained. Further, by setting the limit current, the volatile digital switch resistive switching behavior and the non-volatile digital switch resistive switching behavior with random variation can be obtained. Further, by regulating the magnitude of the limit current, the regulation of the random manifestation probability of the volatile digital switch resistive switching behavior and the non-volatile digital switch resistive switching behavior can be realized. Therefore, by regulating the magnitude of the limit current and the magnitude and polarity of the target voltage, the first functional neuron 101 with the digital switch resistive switching behavior having the target random manifestation probability can be obtained, which is used to realize the Dropout function in the neural network.

[0044] It should be understood that by using the resistive switching layer with ion migration characteristics in the second functional neuron 102, the resistive switching behavior of a volatile analog switch is obtained, so that the LIF function of a biological neuron can be simulated. In this embodiment, the first functional neuron 101 and the second functional neuron 102 are connected in series. The first functional neuron 101 has a Dropout function, and the second functional neuron 102 simulates the LIF function, and a pulsed neuron 100 with a Dropout function can be implemented through hardware.

[0045] This embodiment provides a pulsed neuron with a Dropout function, including a first functional neuron and a second functional neuron. The first functional neuron and the second functional neuron are connected in series through a shared active electrode layer, and a target voltage is applied to the shared active electrode layer, and the inert electrode layer of the second functional neuron is grounded; the first functional neuron is used to simulate the process of random discarding based on the volatile digital switch resistive switching behavior and non-volatile digital switch resistive switching behavior that change randomly; the second functional neuron is used to simulate the reaction process of a biological neuron receiving external stimuli based on the volatile analog switch resistive switching behavior. This embodiment designs a memristor with three different resistive switching behaviors. After two memristors are connected in series, one uses the volatile and non-volatile digital switch resistive switching behavior that changes randomly to implement the Dropout function, and the other uses the volatile analog switch behavior to implement the LIF function, so as to construct a pulsed neuron with a Dropout function in hardware. At the same time, by adjusting the magnitude of the applied voltage, the polarity of the applied voltage, and the magnitude of the restricted current, the randomness of the volatile and non-volatile digital switch resistive switching behaviors can be regulated, and then the Dropout function with adjustable probability can be realized.

[0046] An embodiment of the present application provides a pulsed neuron circuit with a random discarding function, referring to Figure 8 , Figure 8 which is a schematic structural diagram of an embodiment of the pulsed neuron circuit with a random discarding function provided by the present application.

[0047] In this embodiment, the pulsed neuron circuit 200 with a random discarding function includes a digital resistive switching memristor 201 and an analog resistive switching memristor 202 connected in series. Both the digital resistive switching memristor 201 and the analog resistive switching memristor 202 use the memristor 10 in the above embodiment, including an active electrode layer 11, a resistive switching layer 12, and an inert electrode layer 13. The specific structure can be referred to Figure 1 , and details are not described herein again. The digital resistive switching memristor 201 is connected to the target voltage, and the analog resistive switching memristor 102 is connected to the output terminal.

[0048] It can be understood that the analog resistive switching memristor 202 is used to simulate the response process of a biological neuron receiving external stimuli based on the resistive switching behavior of a volatile analog switch; the digital resistive switching memristor 201 is used to simulate the process of random dropout based on the resistive switching behavior of a volatile digital switch with random variations and the resistive switching behavior of a non-volatile digital switch.

[0049] It should be noted that in this embodiment, the resistive switching behavior of the volatile analog switch of the analog resistive switching memristor 202 is used to simulate the LIF function, and the resistive switching behavior of the volatile digital switch and the resistive switching behavior of the non-volatile digital switch of the digital resistive switching memristor 201 are used to simulate the Dropout function. Since both the digital resistive switching memristor 201 and the analog resistive switching memristor 202 are memristors 10, it can be considered that the pulsed neuron circuit 200 is formed by connecting two identical memristors 10 in series.

[0050] It can be understood that the target voltage is the voltage set to be applied to the digital resistive switching memristor 201. The polarity of the target voltage can be a positive voltage or a negative voltage, and the magnitude of the target voltage can be set according to actual needs, and no specific limitation is made thereto. The target limit current is the limit current set for the digital resistive switching memristor 201. The target limit current of the digital resistive switching memristor 201 is set according to the target random performance probability in the random variations of the resistive switching behavior of the volatile digital switch and the resistive switching behavior of the non-volatile digital switch. The target random performance probability is the probability set for the digital resistive switching memristor 201 to randomly exhibit a certain resistive switching behavior. The target random performance probability of the resistive switching behavior of the volatile digital switch is the probability that the digital resistive switching memristor 201 needs to randomly exhibit the resistive switching behavior of the volatile digital switch, and the target random performance probability of the resistive switching behavior of the non-volatile digital switch is the probability that the digital resistive switching memristor 201 needs to randomly exhibit the resistive switching behavior of the non-volatile digital switch. The target random performance probability is set according to the target dropout probability of the target neuron. The target dropout probability is the probability set for the target neuron to be discarded, and the specific value is set according to actual needs, and no specific limitation is made thereto.

[0051] In specific implementation, by adjusting the magnitude and polarity of the target voltage, the resistive switching behavior of the digital switch can be obtained. Further, by setting the limit current, the resistive switching behavior of the volatile digital switch with random variations and the resistive switching behavior of the non-volatile digital switch can be obtained. Further, by controlling the magnitude of the limit current, the control of the random performance probability of the resistive switching behavior of the volatile digital switch and the resistive switching behavior of the non-volatile digital switch can be realized. Therefore, by controlling the magnitude of the limit current and the magnitude and polarity of the target voltage, a digital resistive switching memristor 201 with a target random performance probability of the resistive switching behavior of the digital switch can be obtained, which is used to implement the Dropout function in the neural network.

[0052] It should be understood that by utilizing the resistive switching layer with ion migration characteristics in the analog resistive switching memristor 202, a volatile analog switch resistive switching behavior can be obtained, thereby enabling the simulation of the LIF function of a biological neuron. In this embodiment, the digital resistive switching memristor 201 and the analog resistive switching memristor 202 are connected in series. The digital resistive switching memristor 201 has a Dropout function, and the analog resistive switching memristor 202 simulates the LIF function, and a pulsed neuron circuit 200 with a Dropout function can be implemented by hardware.

[0053] Furthermore, in addition to the series-connected digital resistive switching memristor 201 and analog resistive switching memristor 202, the pulsed neuron circuit 200 further includes a switching element 203 and a crystal triode (bipolar transistor) 102. The digital resistive switching memristor 201 and the analog resistive switching memristor 202 are connected through the switching element 203. The first end of the crystal triode 204 is respectively connected to the digital resistive switching memristor 201 and the switching element 203, and the second end of the crystal triode 204 is grounded. Among them, the crystal triode 204 is usually an NPN-type triode. The first end of the crystal triode 204 is usually the collector, and the second end of the crystal triode 204 is usually the emitter. The base of the crystal triode 204 is connected to the corresponding component according to actual needs, and the crystal triode 204 has a current-limiting effect in the circuit.

[0054] It can be understood that the analog resistive switching memristor 202 obtains a volatile analog switch resistive switching behavior when the crystal triode 204 is turned off and the switching element 203 is closed, and the digital resistive switching memristor 201 obtains a volatile digital switch resistive switching behavior with random variation and a non-volatile digital switch resistive switching behavior when the crystal triode 204 is turned on and the switching element 203 is open. Among them, when the analog resistive switching memristor 202 has a volatile analog switch resistive switching behavior, continuous stimulation with a pulsed voltage can be used to realize the simulation of the neuron LIF function.

[0055] This embodiment provides a pulsed neuron circuit with a random dropout function, including a series-connected digital resistive random access memory (RRAM) and an analog RRAM; the analog RRAM is used to simulate the response process of a biological neuron receiving external stimuli based on the volatile analog switch resistive switching behavior; the digital RRAM is used to simulate the process of randomly discarding target neurons based on the randomly varying volatile digital switch resistive switching behavior and non-volatile digital switch resistive switching behavior. In this embodiment, memristors with three different resistive switching behaviors are designed. After two memristors are connected in series, one uses the randomly varying volatile and non-volatile digital switch resistive switching behaviors to implement the Dropout function, and the other uses the volatile analog switch behavior to implement the LIF function, so as to construct a pulsed neuron with the Dropout function on hardware. At the same time, by adjusting the magnitude of the applied voltage, the polarity of the applied voltage, and the magnitude of the limited current, the randomness of the volatile and non-volatile digital switch resistive switching behaviors can be regulated, and then the Dropout function with adjustable probability can be realized.

[0056] An embodiment of the present application provides a neural network. Refer to Figure 9 , Figure 9 which is a schematic structural diagram of an embodiment of the neural network provided by the present application.

[0057] In this embodiment, the neural network 1000 includes a hidden layer (Hidden Layer) 1001, and the hidden layer 1001 includes a random dropout layer (Dropout layer) 1001a. The random dropout layer 1001a includes a plurality of pulsed neurons 100 arranged in an array. The specific structure of the pulsed neuron 100 can refer to Figure 7 , and details are not described herein again.

[0058] It should be noted that the random variations of the volatile digital switch resistive switching behavior and non-volatile digital switch resistive switching behavior of the memristor 10 can be applied to the neural network to implement the neural network 1000 with the Dropout function. Dropout is a regularization technique designed to prevent model overfitting. Its core idea is to randomly "turn off" some neurons in the network during the training process, forcing the network to learn more robust features. In each training iteration, each neuron is temporarily disabled (the output is set to zero) with probability p, and the remaining neurons scale the output with a weight of 1 / (1−p)1 / (1−p) to maintain the overall activation intensity. Under appropriate limited current, through voltage writing, the volatility and non-volatility are probabilistic, and the high and low resistance states of the memristor 10 after writing are also probabilistic. Using the high and low resistance states as switches also means that the switches of the memristor 10 are probabilistic. Only when the state of the memristor 10 is on can the subsequent current conduction be allowed. Therefore, the probabilistic resistive switching behaviors of the volatility and non-volatility of the memristor 10 can be used as switches and applied as a Dropout layer in the neural network 1000 to realize the update of weights. Refer toFigure 10 Based on using the memristor 10 as the basis for weight connection, the memristor 10 is regarded as a switch, and the probabilistic transitions of the volatile digital switching resistive switching behavior and the non-volatile digital switching resistive switching behavior are regarded as the Dropout layer. When the non-volatile digital switching resistive switching behavior is exhibited, the synaptic weight of the previous neuron can perform forward propagation; while when the volatile digital switching resistive switching behavior is exhibited, the synaptic weight is updated to 0, thus realizing the function of Dropout.

[0059] It can be understood that the random dropout layer 1001a is used to discard neurons according to the target dropout probability when receiving external data, so as to determine the effective neurons, enabling the hidden layer 1001 to perform feature extraction based on the effective neurons and obtain the target features.

[0060] It should be noted that the external data is the data input into the neural network 1000. The effective neurons are the neurons that are not discarded. According to the set target dropout probability, a part of the neurons are discarded. The effective neurons can normally perform feature extraction, and the output of the discarded neurons is zero, thereby reducing the dependence on specific neurons in the neural network. The target features are the finally extracted features.

[0061] Furthermore, the neural network 1000 further includes an input layer (Input Layer) 1002 and an output layer (Output Layer) 1003, and the hidden layer 1001 is respectively connected to the input layer 1002 and the output layer 1003. The input layer 1002 is used to obtain external data and input the external data into the hidden layer; the output layer 1003 is used to generate a prediction result based on the target features.

[0062] It can be understood that the input layer 1002 receives the external data, the hidden layer 1001 extracts features from the data, and the output layer generates the final prediction result. The random dropout layer 1001a, as a regularization technique, is usually located in the hidden layer. By randomly discarding neurons, overfitting of the model can be prevented and the generalization ability of the model can be improved.

[0063] In specific implementation, in combination with the multi-mode of the memristor 10, the LIF function is realized by using the volatile analog switching resistive switching behavior, and the Dropout function is realized by using the probabilistic transitions of the volatile digital switching resistive switching behavior and the non-volatile digital switching resistive switching behavior. Refer to Figure 11, design a two-layer fully connected neural network, use the LIF activation function, with the number of neurons in the two layers being 100 and 150 respectively, and set a certain Dropout probability (target dropout probability) for each layer except the output layer, recognize the MNIST dataset, and at this time, the training set has only 1000, and the rest are test sets. If the Dropout probability is not set, the training accuracy can reach 100%, while the test accuracy is only 85.55%, indicating the occurrence of overfitting; if the Dropout probability is set to 0.5, after 100 rounds of training, the training and test accuracies are similar, and overfitting can be significantly suppressed.

[0064] This embodiment provides a neural network, including a hidden layer, the hidden layer includes a random dropout layer, and the random dropout layer includes a plurality of spiking neurons arranged in an array; the random dropout layer is used to discard neurons according to the target dropout probability when receiving external data, determine the effective neurons, so that the hidden layer performs feature extraction based on the effective neurons to obtain the target features. This embodiment designs memristors with three different resistive switching behaviors. After two memristors are connected in series, one uses the randomly varying volatile and non-volatile digital switch resistive switching behaviors to implement the Dropout function, and the other uses the volatile analog switch behavior to implement the LIF function, so as to construct spiking neurons with the Dropout function in hardware, and further use the spiking neurons arranged in an array to construct a neural network with the Dropout function. At the same time, by adjusting the magnitude of the applied voltage, the polarity of the applied voltage, and the magnitude of the limiting current, the randomness of the volatile and non-volatile digital switch resistive switching behaviors can be regulated, and then the Dropout function with adjustable probability can be realized.

[0065] This application embodiment provides a preparation method of a memristor, referring to Figure 12 , Figure 12 is a schematic flowchart of an embodiment of the preparation method of the memristor provided by this application.

[0066] In this embodiment, the preparation method of the memristor includes steps S10~S40: Step S10, provide a substrate; It should be noted that the substrate can be obtained according to actual needs, and the substrate is cleaned and dried.

[0067] Step S20, deposit an active metal on the substrate to form an active electrode layer; In a feasible implementation manner, step S20 may include: performing patterning processing on the substrate based on a first preset pattern; depositing an active metal on the patterned substrate based on a first preset thickness to form the active electrode layer.

[0068] It should be noted that the first preset pattern is the pattern of the active electrode layer set in advance, and the first preset thickness is the thickness of the active electrode layer set in advance, which may include the thicknesses at different positions. Both the first preset pattern and the first preset thickness can be flexibly adjusted according to actual needs, and no specific limitations are imposed thereon.

[0069] It can be understood that in this embodiment, the substrate is patterned according to the first preset pattern by using a patterning technique, and then an active metal is deposited on the patterned substrate according to the first preset thickness by using a thin film deposition technique to form the final active electrode layer. The active electrode layer at this time can be regarded as an active electrode formed by the active metal, and the active metal can be potassium (K), calcium (Ca), sodium (Na), magnesium (Mg), aluminum (Al), zinc (Zn), iron (Fe), tin (Sn), lead (Pb), lithium (Li), etc., which can be selected according to actual needs, and no specific limitations are imposed thereon.

[0070] Step S30: Transfer a functional material with ion migration characteristics onto the active electrode layer to form a resistive switching layer; It should be noted that the resistive switching layer is prepared by using a functional material with ion migration characteristics. The functional material can be a perovskite solar cell, a solid electrolyte, a hydrogel electrolyte, etc., which can be selected according to actual needs, and no specific limitations are imposed thereon.

[0071] Step S40: Deposit an inert metal on the resistive switching layer to form an inert electrode layer.

[0072] In a feasible implementation manner, step S40 may include: patterning the resistive switching layer based on a second preset pattern; depositing an inert metal on the patterned resistive switching layer based on a second preset thickness to form the inert electrode layer.

[0073] It should be noted that the second preset pattern is the pattern of the inert electrode layer set in advance, and the second preset thickness is the thickness of the inert electrode layer set in advance, which may include the thicknesses at different positions. Both the second preset pattern and the second preset thickness can be flexibly adjusted according to actual needs, and no specific limitations are imposed thereon.

[0074] It can be understood that in this embodiment, the resistive switching layer is patterned according to the second preset pattern by using a patterning technique, and then an inert metal is deposited on the patterned resistive switching layer according to the second preset thickness by using a thin film deposition technique to form the final inert electrode layer. The inert electrode layer at this time can be regarded as an inert electrode formed by the inert metal, and the inert metal can be gold (Au), platinum (Pt), palladium (Pd), rhodium (Rh), etc., which can be selected according to actual needs, and no specific limitations are imposed thereon.

[0075] It should be understood that after the formation of the inert electrode layer, a memristor can be obtained. For the specific structure of the memristor, reference can be made to Figure 1 , which will not be elaborated here. In addition, during testing, a voltage is usually applied to the active electrode while the inert electrode is kept grounded.

[0076] This embodiment provides a method for preparing a memristor. A substrate is provided; an active metal is deposited on the substrate to form an active electrode layer; a functional material with ion migration characteristics is transferred onto the active electrode layer to form a resistive switching layer; an inert metal is deposited on the resistive switching layer to form an inert electrode layer. The memristor prepared in this embodiment has three different resistive switching behaviors. By utilizing the volatile and non-volatile digital switching resistive switching behaviors with random variations, the Dropout function can be achieved. By utilizing the volatile analog switching behavior, the LIF function can be achieved, so as to construct a pulsed neuron and neural network with the Dropout function on hardware.

[0077] The method for preparing a memristor provided in this application can prepare the memristor in the above embodiment and can solve the technical problem of being difficult to simulate the random dropout function of neurons in hardware. Compared with the prior art, the beneficial effects of the method for preparing a memristor provided in this application are the same as those provided in the above embodiment, and other technical features in the method for preparing a memristor are the same as the features disclosed in the above embodiment method, which will not be elaborated here.

[0078] It should be noted that the above examples are only for understanding this application and do not constitute a limitation on the method for preparing a memristor of this application. Based on this technical concept, more forms of simple transformation are within the protection scope of this application.

[0079] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in the flowchart or block diagram may represent a module, a program segment, or a part of code, and this module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, as well as the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0080] The modules involved in the embodiments of the present application can be implemented in software or in hardware. Among them, the name of the module does not constitute a limitation on the unit itself in some cases.

[0081] The above are only some embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structural transformation made by using the content of the specification and drawings of the present application under the technical concept of the present application, or any direct / indirect application in other related technical fields is included in the patent protection scope of the present application.

Claims

1. A memristor, characterized in that, The memristor includes an active electrode layer, a resistive switching layer, and an inert electrode layer. The resistive switching layer is located above the active electrode layer, and the inert electrode layer is located above the resistive switching layer. The resistive switching layer has ion migration characteristics. The memristor obtains volatile analog switch resistive switching behavior through the resistive switching layer, and obtains digital switch resistive switching behavior by applying a positive voltage to the active electrode layer. The digital switch resistive switching behavior of the memristor randomly changes between volatile digital switch resistive switching behavior and non-volatile digital switch resistive switching behavior.

2. The memristor according to claim 1, characterized in that, The random appearance probability of the volatile digital switch resistive switching behavior in the random change decreases with the increase of the limiting current, and the random appearance probability of the non-volatile digital switch resistive switching behavior in the random change increases with the increase of the limiting current.

3. The memristor according to claim 1, characterized in that, When a positive voltage is applied to the active electrode layer, a conductive filament is formed in the resistive switching layer. The breakage of the conductive filament is random. If the conductive filament breaks after the voltage is removed, the memristor obtains volatile digital switch resistive switching behavior. If the conductive filament does not break after the voltage is removed, the memristor obtains non-volatile digital switch resistive switching behavior. The ion migration characteristics of the resistive switching layer enable the resistance value of the memristor to change according to the electric field strength and direction, obtaining volatile analog switch resistive switching behavior.

4. A pulsed neuron with a random discard function, characterized in that, The pulsed neuron with a random dropout function includes a first functional neuron and a second functional neuron. Both the first functional neuron and the second functional neuron are memristors as described in any one of claims 1 to 3. The first functional neuron and the second functional neuron are connected in series through a shared active electrode layer. A target voltage is applied to the shared active electrode layer, and the inert electrode layer of the second functional neuron is grounded. The first functional neuron is used to simulate the process of random dropout based on the randomly changing volatile digital switch resistive switching behavior and non-volatile digital switch resistive switching behavior. The second functional neuron is used to simulate the reaction process of a biological neuron receiving external stimuli based on the volatile analog switch resistive switching behavior.

5. The pulsed neuron with a random discard function according to claim 4, wherein The target limiting current of the first functional neuron is set according to the target random appearance probability of the volatile digital switch resistive switching behavior and the non-volatile digital switch resistive switching behavior in the random change, and the target random appearance probability is set according to the target dropout probability of the random dropout.

6. A pulsed neuron circuit with a random discard function, characterized in that, The pulsed neuron circuit with a random dropout function includes a digital resistive switching memristor and an analog resistive switching memristor connected in series. Both the digital resistive switching memristor and the analog resistive switching memristor are memristors as described in any one of claims 1 to 3. The digital resistive switching memristor is connected to a target voltage, and the analog resistive switching memristor is connected to an output terminal. The analog resistive switching memristor is used to simulate the reaction process of a biological neuron receiving external stimuli based on the volatile analog switch resistive switching behavior. The digital resistive switching memristor is used to simulate the process of random dropout based on the randomly changing volatile digital switch resistive switching behavior and non-volatile digital switch resistive switching behavior.

7. The pulsed neuron circuit with a random dropout function as claimed in claim 6, wherein the pulsed neuron circuit with a random dropout function further comprises a switching element and a transistor. The digital resistive random access memory (RRAM) and the analog RRAM are connected through the switching element. The first end of the transistor is respectively connected to the digital RRAM and the switching element, and the second end of the transistor is grounded. The analog RRAM obtains the volatile analog switching resistive behavior when the transistor is turned off and the switching element is closed. The digital RRAM obtains the volatile digital switching resistive behavior with random variations and the non-volatile digital switching resistive behavior when the transistor is turned on and the switching element is open.

8. A neural network with a random discard function, characterized in that, The neural network with a random dropout function comprises a hidden layer, and the hidden layer comprises a random dropout layer. The random dropout layer comprises a plurality of pulsed neurons with a random dropout function as claimed in claim 4 or 5, which are arranged in an array. The random dropout layer is configured to perform neuron dropout according to a target dropout probability when receiving external data, and determine effective neurons, so that the hidden layer performs feature extraction based on the effective neurons to obtain target features.

9. The neural network with a random discard function as described in claim 8, wherein, The neural network with a random dropout function further comprises an input layer and an output layer, and the hidden layer is respectively connected to the input layer and the output layer. The input layer is configured to obtain the external data and input the external data into the hidden layer. The output layer is configured to generate a prediction result based on the target features.

10. A preparation method of a memristor, characterized in that, The preparation method comprises: providing a substrate; depositing an active metal on the substrate to form an active electrode layer; transferring a functional material with ion migration characteristics onto the active electrode layer to form a resistive switching layer; depositing an inert metal on the resistive switching layer to form an inert electrode layer.

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