Silicon wafer detection method and device

Abstract

The invention provides a silicon wafer detection method and device. The silicon wafer detection method comprises the following steps: acquiring a target image of a silicon wafer subjected to hardness test; the target image is input into a silicon wafer trace recognition model to obtain trace information of the silicon wafer, the silicon wafer trace recognition model is a pre-trained shallow convolutional neural network model with the image of the silicon wafer as input and the trace information of the silicon wafer as output, and the trace information comprises a trace type and a trace size; and calculating the hardness and fracture toughness test results of the silicon wafer according to the trace information. According to the embodiment of the invention, the test effect on the hardness and fracture toughness test of the silicon wafer can be achieved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a method and device for detecting silicon wafers. Background Art

[0002] The hardness and fracture toughness of silicon wafers are generally measured by indentation method. In general hardness indentation tests, hardness and fracture toughness are calculated from indentation size and crack size. The size of the indentation needs to be manually framed, which usually consumes a lot of manpower and material resources, increases the test cost, and reduces the silicon wafer test efficiency. Thus, the existing method has a poor test effect on silicon wafers. Summary of the Invention

[0003] Embodiments of the present invention provide a method and device for detecting silicon wafers to improve the test effect on silicon wafers.

[0004] To solve the above problems, the present invention is implemented as follows:

[0005] In a first aspect, the present invention provides a method for detecting a silicon wafer, including the following steps:

[0006] Obtain a target image of a silicon wafer that has undergone a hardness test;

[0007] Input the target image into a silicon wafer trace recognition model to obtain the trace information of the silicon wafer, where the silicon wafer trace recognition model is a pre-trained shallow convolutional neural network model that takes the image of the silicon wafer as input and outputs the trace information of the silicon wafer, and the trace information includes trace type and trace size;

[0008] Calculate the hardness and fracture toughness test results of the silicon wafer according to the trace information.

[0009] In some embodiments, the step of inputting the target image into a silicon wafer trace recognition model to obtain the trace information of the silicon wafer includes:

[0010] Extract a first feature of the target image, where the first feature includes the edge and texture information of the target image;

[0011] Extract a second feature of the target image, where the second feature includes the shape and object of the target image;

[0012] Fuse the first feature and the second feature to determine the trace type and trace coordinates of the trace on the silicon wafer;

[0013] Determine the trace size of the silicon wafer according to the trace coordinates and the target image scale.

[0014] In some of these embodiments, after the step of extracting the first feature of the target image and / or extracting the second feature of the target image, the step of inputting the target image into the silicon wafer trace recognition model to obtain the trace information of the silicon wafer further includes:

[0015] Perform a reduction operation on the target image to reduce the size of the feature map of the target image.

[0016] In some of these embodiments, before fusing the first feature and the second feature to determine the trace type and trace coordinates of the trace on the silicon wafer, the step of inputting the target image into the silicon wafer trace recognition model to obtain the trace information of the silicon wafer further includes:

[0017] Flatten the feature map of the target image into a one-dimensional vector.

[0018] In some of these embodiments, the trace types include indentation, crack, and test failure. Fusing the extracted feature information to determine the trace type and trace coordinates of the trace on the silicon wafer includes:

[0019] Respectively fuse the extracted feature information through an indentation detection node, a crack detection node, and a test failure detection node to confirm the trace type and trace coordinates.

[0020] In some of these embodiments, before inputting the target image into the silicon wafer trace recognition model to obtain the trace information of the silicon wafer, the method further includes:

[0021] Provide a training picture set, where the training picture set includes training pictures with trace types of indentation, crack, and test failure, and the ground truth of the trace information of the traces in the training pictures;

[0022] Input the training picture set into a training model to obtain the predicted trace information of the training pictures, where the training model is a shallow convolutional neural network model that takes the image of the silicon wafer as the input and the trace information of the silicon wafer as the output, and the trace information includes the trace type and the trace size;

[0023] Adjust the parameters of the training model according to the loss value, where the loss value is calculated by inputting the difference value between the predicted trace information and the ground truth of the trace information into a loss function;

[0024] After meeting the preset training conditions, use the training model as the silicon wafer trace recognition model, where the preset training conditions include at least one of the loss function converging or the number of iterative training times meeting a preset threshold.

[0025] In some of these embodiments, the loss function includes a first loss value determined according to the determination result of the trace type and a second loss value of the trace coordinate determination result, where the first loss value is a cross-entropy loss value and the second loss value is a mean squared error loss value.

[0026] In a second aspect, an embodiment of the present invention provides a silicon wafer detection device, including:

[0027] An acquisition module configured to acquire a target image of a silicon wafer that has undergone a hardness test;

[0028] An input module configured to input the target image into a silicon wafer trace recognition model to obtain the trace information of the silicon wafer, where the silicon wafer trace recognition model is a pre-trained shallow convolutional neural network model that takes an image of a silicon wafer as input and outputs the trace information of the silicon wafer, and the trace information includes the trace type and the trace size;

[0029] A calculation module configured to calculate the hardness and fracture toughness test results of the silicon wafer according to the trace information.

[0030] In a third aspect, an embodiment of the present invention provides an electronic device, including a processor, a memory, and a program or instruction stored on the memory and executable on the processor, where when the program or instruction is executed by the processor, the steps of the silicon wafer detection method described in any one of the first aspects are implemented.

[0031] In a fourth aspect, an embodiment of the present invention provides a readable storage medium, where a program or instruction is stored on the readable storage medium, and when the program or instruction is executed by a processor, the steps of the silicon wafer detection method described in any one of the first aspects are implemented.

[0032] The beneficial effects brought by the embodiments of the present disclosure are as follows:

[0033] The technical solution of the embodiment of the present invention extracts the trace information of the silicon wafer through a pre-trained shallow convolutional neural network model, and calculates the hardness and fracture toughness test results of the silicon wafer according to the trace information, which can simplify the recognition operation of the trace information on the silicon wafer, improve the processing speed, and thus improve the test effect of the hardness and fracture toughness test of the silicon wafer. Description of the Drawings

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0035] Figure 1It is a schematic flow chart of a silicon wafer detection method in an embodiment of the present invention;

[0036] Figure 2 It is a schematic diagram of a metal indentation test in an embodiment of the present invention;

[0037] Figure 3 It is a schematic diagram of a silicon wafer indentation test in an embodiment of the present invention;

[0038] Figure 4 It is a schematic diagram of a silicon wafer indentation test in another embodiment of the present invention;

[0039] Figure 5 It is a schematic diagram of trace size indexing in an embodiment of the present invention;

[0040] Figure 6 It is the result of indentation and crack identification in an embodiment of the present invention;

[0041] Figure 7 It is a schematic structural diagram of a silicon wafer detection device in an embodiment of the present invention. Detailed implementation manners

[0042] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0043] Terms such as "first" and "second" in the embodiments of the present invention are used to distinguish similar objects, and do not necessarily describe a specific order or sequence. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those clearly listed steps or units, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products or devices. In addition, in this application, the use of "and / or" means at least one of the connected objects. For example, A and / or B and / or C means including A alone, B alone, C alone, and both A and B exist, both B and C exist, both A and C exist, and all of A, B, and C exist, a total of 7 situations.

[0044] The embodiments of the present invention provide a silicon wafer detection method.

[0045] As Figure 1 shown, in one of the embodiments, the method includes the following steps:

[0046] Step 101: Obtain a target image of a silicon wafer that has undergone a hardness test.

[0047] The technical solution of this embodiment is mainly applied to the hardness test and fracture toughness test of silicon wafers. More specifically, it is applied to the hardness test using the indentation method. Its main working principle is to apply a force to the silicon wafer, then identify and analyze the marks generated on the silicon wafer by this force, and determine the hardness and fracture toughness of the silicon wafer based on these marks.

[0048] It should be understood that the test conditions can be adjusted according to needs or different test standards. In this embodiment, only the indentation detection under a 100 gf load is taken as an exemplary illustration.

[0049] During implementation, a 100 gf load is used to perform a hardness indentation test on the surface of a polished silicon wafer. In this embodiment, the load holding time is set to 10 seconds.

[0050] After the test is completed, a microscope and a camera are used to obtain microscopic images. It should be noted that the size of the indentation is usually small. Therefore, it is necessary to collect images through a microscope. In order to determine the exact size of the collected images, the magnification factor needs to be specified. In an exemplary embodiment, the eyepiece magnification is 10 and the objective magnification is 40, so the total magnification is 400. During implementation, it is necessary to record the parameters of the acquisition equipment such as the actually selected microscope for subsequent size calculation.

[0051] Step 102: Input the target image into the silicon wafer mark recognition model to obtain the mark information of the silicon wafer.

[0052] After collecting the target image of the silicon wafer processed by the indentation method, input this target image into the pre-trained silicon wafer mark recognition model. This silicon wafer mark recognition model is a pre-trained shallow convolutional neural network model (shallow CNN) that takes the image of the silicon wafer as the input and the mark information of the silicon wafer as the output. This mark information includes the mark type and mark size.

[0053] In this embodiment, by using a shallow convolutional neural network model, the automatic recognition of silicon wafer images can be realized, which helps to improve the extraction speed of mark information on the silicon wafer.

[0054] In some of these embodiments, the above step 102 includes:

[0055] Extract the first feature of the target image;

[0056] Extract the second feature of the target image;

[0057] Fuse the first feature and the second feature to determine the mark type and mark coordinates of the marks on the silicon wafer;

[0058] Determine the trace size of the silicon wafer according to the trace coordinates and the target image scale.

[0059] In the technical solution of this embodiment, first, an image is input into the silicon wafer trace recognition model through the input layer. During implementation, the input image can be normalized and standardized to unify the image processing standard. In an exemplary embodiment, a grayscale image of 640x640 can be input through the input layer as the target image.

[0060] Next, a first feature of the target image is extracted through a convolutional layer. Here, the first feature is a relatively simple feature. Exemplarily, the first feature includes the edge and texture information of the target image.

[0061] In an exemplary embodiment, a convolutional layer is used to extract the first feature, and ReLU is used as the activation function to introduce a non-linear transformation, alleviate the vanishing gradient, and improve the calculation efficiency.

[0062] In some of these embodiments, after extracting the first feature, the target image can be reduced to reduce the size of the feature map of the target image.

[0063] During implementation, a pooling layer can be used for max-pooling processing to reduce the size of the feature map of the target image. In this way, through the reduction operation of max-pooling processing, the most significant features in the feature map can be extracted, and at the same time, it helps to reduce the dimension and calculation amount, making the model invariant to local translations of the input data. On the premise of retaining the main features of the data, unnecessary detailed data is reduced, information redundancy is reduced, and thus the spatial resolution and calculation amount can be reduced.

[0064] Next, a second feature of the target image is extracted through a convolutional layer. Here, the second feature is a relatively complex feature. Exemplarily, the second feature includes the shape and object of the target image. In some of these embodiments, the sizes of the convolutional kernels of the convolutional layers for extracting the first feature and the second feature are the same. Since the second feature is relatively complex, correspondingly, the number of convolutional kernels of the convolutional layer for extracting the second feature is greater than the number of convolutional kernels of the convolutional layer for extracting the first feature.

[0065] In some of these embodiments, after extracting the second feature, the target image can be reduced again through max-pooling processing to reduce the size of the feature map of the target image.

[0066] In some of these embodiments, after extracting the features of the target image, the feature map can be flattened into a one-dimensional vector through a flattening layer.

[0067] The data is flattened into a one-dimensional vector by a flattening layer while maintaining the order of its features, which simplifies the data format and the number of parameters, facilitates transmission and processing, and also improves the generality of data processing, and can meet the processing requirements of more types of neuron nodes such as fully connected layers.

[0068] Finally, the information obtained in the above steps is input into the fully connected layer for fusion to generate the recognition result. In some of these embodiments, the fully connected layer uses ReLU as the activation function.

[0069] After fusing the features extracted by the fully connected layer, the fusion result is output through the output layer.

[0070] In some of these embodiments, the trace types include indentations, cracks, and test failures. Fusing the extracted feature information to determine the trace type and trace coordinates of the traces on the silicon wafer includes:

[0071] The extracted feature information is fused respectively through an indentation detection node, a crack detection node, and a test failure detection node to confirm the trace type and trace coordinates.

[0072] It should be understood that when performing hardness testing and fracture toughness testing by the indentation method, there are mainly two different states that may occur, namely the recognizable normal result and the unrecognizable abnormal result (NG).

[0073] As Figure 2 shown, for materials with a certain ductility such as metals, their normal result is usually to produce clear indentations, as Figure 3 shown, when the wafer produces an indentation, it will also produce cracks of a certain length, as Figure 4 shown, due to factors such as uneven stress, it may also cause local rupture of the wafer.

[0074] In summary, the recognition results for the indentations on the wafer mainly include three states: indentation, crack, and NG. Among them, indentation and crack can be understood as two features that need to be recognized in a normal test result.

[0075] In this embodiment, in the output layer, the detection results of whether the traces on the silicon wafer are indentations, cracks, and NG are classified and output through different neuron nodes respectively. For the output layer, the cross-entropy activation function can be used to identify indentations and cracks.

[0076] As Figure 5As shown, after identifying the trace features, the trace coordinates are further output. In this embodiment, the trace coordinates are output in the form of a bounding box. In the plane coordinate system, the abscissas of the bounding box of the crack are x1 and x2 respectively, and the ordinates are y1 and y2 respectively. In this way, the coordinate information of the crack can be expressed as [x1, y1, x2, y2]. In this way, the prediction of the trace coordinates of the crack can be realized through four neuron nodes.

[0077] Similarly, the prediction of the trace coordinates of the indentation can be realized through four neuron nodes, and the prediction of the trace coordinates of the NG trace can be realized through four neuron nodes. In this way, a total of twelve neuron nodes can realize the prediction of the trace coordinates of various types. During implementation, the bounding box coordinates can be predicted through linear activation.

[0078] Step 103: Calculate the hardness and fracture toughness test results of the silicon wafer according to the trace information.

[0079] After determining the type and size of the trace, the hardness and fracture toughness are calculated.

[0080] A feasible method for calculating the hardness Hv is:

[0081] Hv = 0.1995 * 0.98 / S...(1);

[0082] In the above formula, 0.1995 is a set constant, 0.98 is the experimental force, that is, corresponding to the above 100 gf, and S is the indentation surface area. Since the indentation is usually formed after a diamond indenter presses into the material and is not a planar structure, in this embodiment, d 2 is used as the approximate area of the indentation, where d is the diagonal length. In this embodiment, during specific calculation, the arithmetic mean of the two diagonals of the indentation is approximately used.

[0083] As Figure 6 shown, in an experiment, the sizes of the two diagonals are 13.51 microns and 13.62 microns respectively. Substituting into the above formula (1), the calculated result is 1063 Hv.

[0084] A feasible method for calculating the fracture toughness Kc is:

[0085] Kc = 0.016 * ((188 / (Hv / 102.04)) 0.5 ) * 0.98 / (((c1 + c2) / 4 / 1000) 2 ) * (((c1 + c2) / 4 / 10000

[0086] 00) 0.5 )...(2);

[0087] In the above formula (2), Hv is the hardness value measured by indentation, and c1 and c2 are the crack lengths respectively. In one experiment, c1 and c2 are 35.03 microns and 31.84 microns respectively, and the calculation result is 0.97 MPa*m 0.5 。

[0088] In the technical solution of this embodiment, the silicon wafer trace recognition model is pre-trained through model training.

[0089] In some of these embodiments, the steps of model training include:

[0090] Before inputting the target image into the silicon wafer trace recognition model to obtain the trace information of the silicon wafer, the method further includes:

[0091] Providing a training picture set, where the training picture set includes training pictures with trace types of indentation, crack, and test failure, and the true values of the trace information of the traces in the training pictures;

[0092] Inputting the training picture set into a training model to obtain the predicted trace information of the training pictures, where the training model is a shallow convolutional neural network model with the image of the silicon wafer as the input and the trace information of the silicon wafer as the output, and the trace information includes the trace type and the trace size;

[0093] Adjusting the parameters of the training model according to the loss value, where the loss value is calculated by inputting the difference value between the predicted trace information and the true value of the trace information into a loss function;

[0094] After meeting the preset training conditions, using the training model as the silicon wafer trace recognition model.

[0095] In the technical solution of this embodiment, a training model is first built. During the model training process, a training picture set including training pictures and the true values of the trace information of the training pictures is first provided. Among them, the true values of the trace information of the training pictures can be obtained by manual marking one by one to ensure its accuracy. Here, the training pictures need to include indentation, crack, and NG pictures, and the number of pictures of each type should be sufficient. Before inputting into the training model, the training pictures can also be augmented, that is, by randomly rotating, translating, and adjusting the color of the training pictures, etc., to further enrich the training data.

[0096] During the model training process, input the training pictures into the training model to obtain the predicted values generated by the training model, denoted as the predicted trace information. Then compare the predicted trace information with the true value of the trace information, and adjust the model parameters of the training model according to the comparison result.

[0097] In an exemplary embodiment, the loss function is defined as:

[0098] Total Loss = αMES Loss + βCross - Entropy Loss……(3);

[0099] In this embodiment, the total loss Total Loss of the loss function includes a first loss value determined according to the determination result of the trace type and a second loss value of the trace coordinate determination result. Among them, the first loss value is the cross - entropy loss value Cross - Entropy Loss, the second loss value is the mean square error loss value MES Loss, and α and β are respectively preset weight coefficients to balance the influence of the two parts of the loss values.

[0100] In this way, the model training is stopped after reaching the preset training conditions, where the preset training conditions include at least one of the convergence of the loss function or the number of iterative training times meeting the preset threshold. Further, the trained model can be used as a silicon wafer trace recognition model and deployed offline or on a cloud server for silicon wafer trace recognition.

[0101] Through testing and comparison, it is found that the technical solution of the present invention has high detection accuracy and fast response speed, improving the silicon wafer detection effect.

[0102] An embodiment of the present invention provides a silicon wafer detection device.

[0103] As Figure 7 shown, in some embodiments, the silicon wafer detection device 700 includes:

[0104] An acquisition module 701, configured to acquire a target image of a silicon wafer that has undergone a hardness test;

[0105] An input module 702, configured to input the target image into a silicon wafer trace recognition model to obtain the trace information of the silicon wafer. Among them, the silicon wafer trace recognition model is a pre - trained shallow convolutional neural network model that takes the image of the silicon wafer as input and the trace information of the silicon wafer as output, and the trace information includes the trace type and the trace size;

[0106] A calculation module 703, configured to calculate the hardness and fracture toughness test results of the silicon wafer according to the trace information.

[0107] In some embodiments, the input module 702 includes:

[0108] A first extraction sub - module, configured to extract a first feature of the target image, where the first feature includes the edge and texture information of the target image;

[0109] A second extraction sub-module, configured to extract a second feature of the target image, where the second feature includes the shape and object of the target image;

[0110] A fusion sub-module, configured to fuse the first feature and the second feature to determine the type and coordinates of the trace on the silicon wafer;

[0111] A trace size determination sub-module, configured to determine the trace size of the silicon wafer according to the trace coordinates and the target image scale.

[0112] In some embodiments, it further includes:

[0113] A reduction sub-module, configured to perform a reduction operation on the target image to reduce the size of the feature map of the target image.

[0114] In some embodiments, it further includes:

[0115] An unfolding sub-module, configured to flatten the feature map of the target image into a one-dimensional vector.

[0116] In some embodiments, the trace type includes indentation, crack, and test failure. Fusing the extracted feature information to determine the type and coordinates of the trace on the silicon wafer includes:

[0117] Respectively fuse the extracted feature information through an indentation detection node, a crack detection node, and a test failure detection node to confirm the trace type and coordinates.

[0118] In some embodiments, it further includes:

[0119] A training set providing module, configured to provide a training picture set, where the training picture set includes training pictures with trace types of indentation, crack, and test failure, and the true values of the trace information of the traces in the training pictures;

[0120] A training module, configured to input the training picture set into a training model to obtain the predicted trace information of the training pictures, where the training model is a shallow convolutional neural network model with the image of the silicon wafer as the input and the trace information of the silicon wafer as the output, and the trace information includes the trace type and the trace size;

[0121] An adjustment module, configured to adjust the parameters of the training model according to the loss value, where the loss value is obtained by inputting the difference value between the predicted trace information and the true value of the trace information into a loss function;

[0122] A model generation module, configured to use the training model as a silicon wafer trace recognition model after meeting preset training conditions, where the preset training conditions include at least one of the loss function converging or the number of iterative training times meeting a preset threshold.

[0123] In some embodiments, the loss function includes a first loss value determined according to the determination result of the trace type and a second loss value of the trace coordinate determination result, where the first loss value is a cross-entropy loss value and the second loss value is a mean square error loss value.

[0124] Since the silicon wafer detection device 700 in this embodiment can implement each step of the above silicon wafer detection method embodiment and can achieve the same or similar technical effects, it will not be elaborated here.

[0125] The embodiment of the present application further provides an electronic device, including a processor, a memory, and a program or instruction stored on the memory and executable on the processor. When the program or instruction is executed by the processor, it implements each process of the above method embodiment and can achieve the same technical effect. To avoid repetition, it will not be elaborated here.

[0126] It should be noted that the electronic device in the embodiment of the present application includes the above-mentioned mobile electronic device and non-mobile electronic device.

[0127] The embodiment of the present application further provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by the processor, it implements each process of the above method embodiment and can achieve the same technical effect. To avoid repetition, it will not be elaborated here.

[0128] Wherein, the processor is the processor in the electronic device in the above embodiment. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disc, etc.

[0129] It should be noted that in this text, the term "including", "comprising", or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or device that includes a series of elements not only includes those elements but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article, or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article, or device that includes such element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the reverse order according to the functions involved. For example, the described methods may be performed in an order different from that described, and various steps may be added, omitted, or combined. Additionally, the features described with reference to certain examples may be combined in other examples.

[0130] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-described example methods can be implemented by means of software plus a necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases, the former is a better implementation. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to enable a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in various embodiments of the present application.

[0131] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Those of ordinary skill in the art, under the inspiration of the present application, without departing from the spirit and scope protected by the claims of the present application, can also make many forms, all of which fall within the protection scope of the present application.

Claims

1. A silicon wafer detection method, characterized in that, Including the following steps: Obtain a target image of a silicon wafer that has undergone a hardness test; Input the target image into a silicon wafer trace recognition model to obtain the trace information of the silicon wafer. Among them, the silicon wafer trace recognition model is a pre-trained shallow convolutional neural network model that takes the image of the silicon wafer as input and the trace information of the silicon wafer as output. The trace information includes the trace type and the trace size; Calculate the hardness and fracture toughness test results of the silicon wafer according to the trace information.

2. The method according to claim 1, wherein The step of inputting the target image into the silicon wafer trace recognition model to obtain the trace information of the silicon wafer includes: Extract the first features of the target image, and the first features include the edge and texture information of the target image; Extract the second features of the target image, and the second features include the shape and object of the target image; Fuse the first features and the second features to determine the trace type and trace coordinates of the traces on the silicon wafer; Determine the trace size of the silicon wafer according to the trace coordinates and the target image scale.

3. The method according to claim 2, wherein After the step of extracting the first features of the target image and / or extracting the second features of the target image, the step of inputting the target image into the silicon wafer trace recognition model to obtain the trace information of the silicon wafer further includes: Perform a reduction operation on the target image to reduce the feature map size of the target image.

4. The method according to claim 2, wherein Before fusing the extracted features to determine the trace type and trace coordinates of the indentation on the silicon wafer, the step of inputting the target image into the silicon wafer trace recognition model to obtain the trace information of the silicon wafer further includes: Flatten the feature map of the target image into a one-dimensional vector.

5. The method according to claim 2, characterized in that, The trace type includes indentation, crack, and test failure. Fusing the extracted feature information to determine the trace type and trace coordinates of the traces on the silicon wafer includes: Respectively fuse the extracted feature information through an indentation detection node, a crack detection node, and a test failure detection node to confirm the trace type and trace coordinates.

6. The method according to any one of claims 1 to 5, characterized in that, Before the step of inputting the target image into the silicon wafer trace recognition model to obtain the trace information of the silicon wafer, the method further includes: Provide a training picture set, where the training picture set includes training pictures with trace types of indentation, crack, and test failure, and the ground truth of the trace information of the traces in the training pictures; Input the training picture set into a training model to obtain the predicted trace information of the training pictures. Among them, the training model is a shallow convolutional neural network model that takes the image of the silicon wafer as input and the trace information of the silicon wafer as output. The trace information includes the trace type and the trace size; Adjust the parameters of the training model according to the loss value, where the loss value is calculated by inputting the difference value between the predicted trace information and the ground truth of the trace information into a loss function; After meeting the preset training conditions, use the training model as the silicon wafer trace recognition model, where the preset training conditions include at least one of the convergence of the loss function or the number of iterative training times meeting a preset threshold.

7. The method according to claim 6, wherein The loss function includes a first loss value determined according to the determination result of the trace type and a second loss value of the trace coordinate determination result, wherein the first loss value is a cross-entropy loss value and the second loss value is a mean square error loss value.

8. A silicon wafer detection device, characterized in that, It includes: An acquisition module, configured to acquire a target image of a silicon wafer that has undergone a hardness test; An input module, configured to input the target image into a silicon wafer trace recognition model to obtain the trace information of the silicon wafer. The silicon wafer trace recognition model is a pre-trained shallow convolutional neural network model that takes the image of the silicon wafer as input and the trace information of the silicon wafer as output. The trace information includes the trace type and the trace size; A calculation module, configured to calculate the hardness and fracture toughness test results of the silicon wafer according to the trace information.

9. An electronic device, characterized in that, It includes a processor, a memory, and a program or instruction stored on the memory and executable on the processor. When the program or instruction is executed by the processor, the steps of the silicon wafer detection method according to any one of claims 1-7 are implemented.

10. A readable storage medium, characterized in that, A program or instruction is stored on the readable storage medium. When the program or instruction is executed by a processor, the steps of the silicon wafer detection method according to any one of claims 1-7 are implemented.

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