Discharge control circuit and display panel

Abstract

The present application belongs to the field of display drive technology, and specifically relates to a discharge control circuit and a display panel. The discharge control circuit includes a control module, a first discharge module, and a second discharge module. The first discharge module is used to control the multiple control signal terminals of the gate drive circuit to be electrically connected to the first voltage output terminal of the control module when detecting that the display panel enters the shutdown state. The second discharge module is used to control the data signal terminal of the source drive circuit to be electrically connected to the second voltage output terminal of the control module after the multiple control signal terminals of the gate drive circuit are electrically connected to the first voltage output terminal of the control module. Therefore, the present application solves the problem of screen flickering when the discharge function is turned on during shutdown by binding the voltage on the data signal terminal of the source drive circuit to the second target voltage after raising the voltage on the multiple control signal terminals of the gate drive circuit to the first target voltage.

Description

Technical Field

[0001] The present disclosure belongs to the field of display drive technology, and particularly relates to a discharge control circuit and a display panel. Background Art

[0002] When an LCD display device is turned off, a discharge function is usually required to allow the liquid crystal to fully release its charge. Specifically, when the device is turned off, various signals of the display panel (such as clock signals, frame start signals, reset signals, and pull-down control signals) are pulled to a high level, and then quickly released to the ground following the high level to prevent residual charge in the panel from causing liquid crystal polarization and leading to abnormalities such as screen flickering. However, when the discharge function is turned on, the decreasing data voltage will be coupled and pulled up, causing the pixels in the panel to suddenly light up, resulting in another type of screen flickering abnormality.

[0003] Therefore, currently, when the display panel turns on the discharge function when it is turned off, there is a problem of screen flickering, which affects the shutdown effect of the display panel. Summary of the Invention

[0004] The present application provides a discharge control circuit and a display panel. The present application solves the problem of screen flickering when the discharge function is turned on during shutdown by raising the voltages on multiple control signal terminals of the gate drive circuit to a first target voltage and then binding the voltage on the data signal terminal of the source drive circuit to a second target voltage.

[0005] In a first aspect, an embodiment of the present application provides a discharge control circuit, which is applied to a display panel, wherein the display panel includes a gate drive circuit and a source drive circuit, and the discharge control circuit includes: a control module, wherein the control module includes a first voltage output terminal for outputting a first target voltage and a second voltage output terminal for outputting a second target voltage; a first discharge module, wherein the first discharge module is respectively connected to the first voltage output terminal of the control module and multiple control signal terminals of the gate drive circuit, and is used to control the multiple control signal terminals of the gate drive circuit to be electrically connected to the first voltage output terminal of the control module when it is detected that the display panel enters a shutdown state, and The voltage on the first voltage output terminal is discharged after a first preset time period; wherein the multiple control signal terminals include a clock signal terminal, a frame start signal terminal and a pull-down control terminal; a second discharge module, the second discharge module is respectively connected to the second voltage output terminal of the control module, the data signal terminal of the source drive circuit and the first discharge module, and is used to control the data signal terminal of the source drive circuit to be electrically connected to the second voltage output terminal of the control module after the multiple control signal terminals of the gate drive circuit are electrically connected to the first voltage output terminal of the control module, and discharge the voltage on the second voltage output terminal after a second preset time period.

[0006] Optionally, the first discharge module includes: a shutdown detection unit, which is used to output a first enable signal through a first enable end when detecting that the display panel enters a shutdown state; a first transistor, the control end of the first transistor is connected to the first control end of the control module, and the first end of the first transistor is connected to the first enable end of the shutdown detection unit; multiple second transistors, the control ends of the multiple second transistors are connected to the second ends of the first transistor, the first ends of the multiple second transistors are connected to the first voltage output end of the control module, and the second ends of the multiple second transistors are respectively electrically connected one by one to the multiple control signal ends of the gate drive circuit.

[0007] Optionally, the shutdown detection unit is further used to output a second enable signal through a second enable terminal after outputting the first enable signal for a first preset time period; the first discharge module also includes: a third transistor, the control terminal of the third transistor is connected to the second enable terminal of the shutdown detection unit, the first terminal of the third transistor is connected to the first voltage output terminal of the control module, and the second terminal of the third transistor is grounded.

[0008] Optionally, the second discharge module includes: a fourth transistor, the control end of the fourth transistor is connected to the second end of the first transistor, and the first end of the fourth transistor is connected to the second control end of the control module; a fifth transistor, the control end of the fifth transistor is connected to the second end of the fourth transistor, and the first end of the fifth transistor is connected to the third control end of the control module; a sixth transistor, the control end of the sixth transistor is connected to the second end of the fifth transistor, and the first end of the sixth transistor is connected to the data signal end of the source drive circuit; and a seventh transistor, the control end of the seventh transistor is connected to the control end of the third transistor, the first end of the seventh transistor is connected to the second end of the sixth transistor, and the second end of the seventh transistor is grounded.

[0009] Optionally, the second discharge module further includes: a first capacitor, a first end of the first capacitor is connected to the control end of the sixth transistor, and a second end of the first capacitor is grounded.

[0010] Optionally, the second discharge module includes: a delay unit, a first end of the delay unit is connected to the first discharge module, and is used to output a delay control signal after the control signal end of the gate drive circuit is electrically connected to the first voltage output end of the control module; a fourth transistor, the control end of the fourth transistor is connected to the second end of the delay unit, and the first end of the fourth transistor is connected to the second control end of the control module; a fifth transistor, the control end of the fifth transistor is connected to the second end of the fourth transistor, and the first end of the fifth transistor is connected to the third control end of the control module; a sixth transistor, the control end of the sixth transistor is connected to the second end of the fifth transistor, and the first end of the sixth transistor is connected to the data signal end of the source drive circuit; a seventh transistor, the control end of the seventh transistor is connected to the control end of the third transistor, the first end of the seventh transistor is connected to the second end of the sixth transistor, and the second end of the seventh transistor is grounded.

[0011] Optionally, the delay unit includes: a first resistor, wherein the first end of the first resistor is connected to the second end of the first transistor; a second capacitor, wherein the first end of the second capacitor is connected to the second end of the first resistor, and the second end of the second capacitor is connected to the control end of the fourth transistor; a transistor, wherein the base of the transistor is connected to the first end of the second capacitor, the collector of the transistor is connected to the first end of the first resistor, and the emitter of the transistor is connected to the second end of the second capacitor; and a second resistor, wherein the first end of the second resistor is connected to the base of the transistor, and the second end of the second resistor is connected to the emitter of the transistor.

[0012] Optionally, the delay unit includes: an XENOR gate, the first input terminal of the XENOR gate is connected to the first terminal of the second transistor, the second input terminal of the XENOR gate is connected to the second terminal of the second transistor, and the output terminal of the XENOR gate is connected to the control terminal of the fourth transistor.

[0013] Optionally, the delay unit includes: a comparator, a first input end of the comparator connected to the first end of the second transistor, a second input end of the comparator connected to the second end of the second transistor, and an output end of the comparator connected to the control end of the fourth transistor.

[0014] In a second aspect, an embodiment of the present application provides a display panel comprising a display area and a non-display area, wherein the display area comprises a pixel array; the non-display area comprises a gate drive circuit, a source drive circuit and a discharge control circuit, and the discharge control circuit is electrically connected to the gate drive circuit and the source drive circuit respectively.

[0015] The technical solution provided by this application has at least the following beneficial effects:

[0016] In the present application, when the first discharge module detects that the display panel enters the shutdown state, the multiple control signal terminals of the gate drive circuit are electrically connected to the first voltage output terminal of the control module; then the voltage on the data signal terminal of the source drive circuit is bound to the second target voltage through the second discharge module, so that the voltage change of the multiple control signal terminals has no coupling effect on the data voltage or the coupling effect is small, thereby solving the problem of screen flickering when the discharge function is turned on after the power is turned off; finally, the first voltage output terminal and the second voltage output terminal of the control module are discharged respectively through the first discharge module and the second discharge module, thereby realizing rapid discharge of the liquid crystal capacitor and parasitic capacitor in the panel, thereby avoiding the screen flickering problem caused by liquid crystal polarization. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0018] Figure 1 FIG. 1 is a schematic diagram of data voltage coupling mutation in the related art.

[0019] Figure 2 Shown is a structural schematic diagram of a discharge control circuit provided in an embodiment of the present application.

[0020] Figure 3 Shown is a circuit diagram of a first discharge control circuit provided in an embodiment of the present application.

[0021] Figure 4 Shown is a circuit diagram of a second discharge control circuit provided in an embodiment of the present application.

[0022] Figure 5 Shown is a circuit diagram of a third discharge control circuit provided in an embodiment of the present application.

[0023] Figure 6 Shown is a circuit diagram of a fourth discharge control circuit provided in an embodiment of the present application.

[0024] Figure 7 Shown is a circuit diagram of the fifth discharge control circuit provided in an embodiment of the present application.

[0025] Figure 8 Shown is a circuit diagram of the sixth discharge control circuit provided in an embodiment of the present application.

[0026] Description of reference numerals:

[0027] 100, discharge control circuit; 110, control module; 120, first discharge module; 121, shutdown detection unit; 130, second discharge module; 131, delay unit; 200, gate drive circuit; 300, source drive circuit;

[0028] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; Q1, triode; R1, first resistor; R2, second resistor; C1, first capacitor; C2, second capacitor; U1, XNOR gate; U2, comparator; VGH, first voltage output terminal; Vcom, second voltage output terminal; Y1, first control terminal; Y2, second control terminal; Y3, third control terminal; EN1, first enable terminal; EN2, second enable terminal; EN3, third enable terminal; Sout, data signal terminal; CLK, clock signal terminal; STV, frame start signal terminal; LC, pull-down control terminal. DETAILED DESCRIPTION

[0029] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0030] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0031] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0032] When an LCD display device is turned off, charge is stored on the pixel capacitors. If the device is not actively discharged, the residual charge will cause long-term deflection damage to the liquid crystal molecules, which may cause screen flickering or screen aging. In order for the liquid crystal to fully release the charge, it is usually necessary to enable the discharge function. Specifically, when the device is turned off, the various control signals of the display panel (such as clock signals, frame start signals, reset signals, and pull-down control signals, etc.) are all pulled up to a high level (such as 30V), and then quickly released to the ground following the high level. The final result is to raise the potential of the scan lines in the panel and turn on all pixel transistors in the panel at the same time, so that the pixel capacitors are quickly discharged through a unified path, avoiding residual charge in the panel causing liquid crystal polarization and thus causing abnormalities such as screen flickering. In addition, the discharge function is enabled by identifying the reduction in power supply voltage when the device is turned off. That is, the discharge function is activated when the power supply voltage drops to a certain threshold.

[0033] The inventors of this application have found that, due to the parasitic capacitance between the scan line and the data line in the panel, and the data voltage will also drop out when the display device is turned off, if the discharge function is turned on during the data voltage dropout, the voltage on the data line will be coupled with the rising voltage of the scan line, such as Figure 1 As shown, Figure 1 In the figure, VDD represents the power supply voltage, Sout represents the voltage on the data signal terminal of the source driver circuit, and CLK represents the voltage on the clock signal terminal. When the power supply voltage VDD drops to a certain threshold, the discharge function is started, and the clock signal CLK, which is initially at a low potential, will be instantly pulled up to a high potential. At this time, the decreasing data voltage will be coupled to the high potential, causing the pixels in the panel to suddenly light up, resulting in serious screen flickering. It should be noted that in actual applications, it should be the combined action of the clock signal, frame start signal, pull-down control signal and reset signal in the gate driver circuit that causes the data voltage to be coupled suddenly. Figure 1 Only the effect of the change of the clock signal on the data voltage is illustrated, and other signals are not illustrated one by one.

[0034] In order to solve the problem of screen flickering when the pixel discharge function is turned on when the display panel is turned off, the embodiments of the present application provide a discharge control circuit, which specifically includes the following embodiments:

[0035] Figure 2 FIG. 1 is a structural diagram of a discharge control circuit provided in an embodiment of the present application; Figure 2As shown, the discharge control circuit 100 is applied to a display panel, which includes but is not limited to a gate drive circuit 200, a source drive circuit 300 and a pixel array; wherein the gate drive circuit 200 provides a gate drive signal for turning on the scan line to the pixel array, and the source drive circuit 300 provides a data voltage to the pixel array; the gate drive circuit 200 includes a plurality of control signal terminals, which include but are not limited to a clock signal terminal CLK, a frame start signal terminal STV, a pull-down control terminal LC and a reset signal terminal. The signal output by each control signal terminal is the same as that in the related art and will not be repeated here; in addition, the source drive circuit 300 includes a data signal terminal Sout for outputting a data voltage. In actual applications, the source drive circuit 300 includes a plurality of data signal terminals Sout, and the function of each data signal terminal Sout is the same. In this application, all data signal terminals Sout of the source drive circuit 300 are collectively referred to as data signal terminals Sout.

[0036] The discharge control circuit 100 of the present application includes a control module 110, which includes a first voltage output terminal VGH for outputting a first target voltage and a second voltage output terminal Vcom for outputting a second target voltage. It should be noted that the first target voltage represents a high voltage corresponding to the multiple control signal output signals of the gate driver circuit 200, for example, 30V; the second target voltage represents a common voltage corresponding to the data voltage, for example, 5V. Furthermore, the control module 110 also includes a first control terminal Y1 for outputting a first control signal, a second control terminal Y2 for outputting a second control signal, and a third control terminal Y3 for outputting a third control signal. The functions of the first, second, and third control signals are described in the following embodiments.

[0037] In this embodiment, the discharge control circuit 100 further includes a first discharge module 120, which is respectively connected to the first voltage output terminal VGH of the control module 110 and multiple control signal terminals of the gate drive circuit 200. The first discharge module 120 is configured to control the multiple control signal terminals of the gate drive circuit 200 to be electrically connected to the first voltage output terminal VGH of the control module 110 when detecting that the display panel enters the shutdown state, and to discharge the voltage on the first voltage output terminal VGH after a first preset time period.

[0038] It should be noted that before the first discharge module 120 discharges the voltage on the first voltage output terminal VGH of the control module 110, the first voltage output terminal VGH of the control module 110 continues to output the first target voltage. When the first discharge module 120 detects that the display panel begins to enter the shutdown state, it controls the multiple control signal terminals of the gate drive circuit 200 to be electrically connected to the first voltage output terminal VGH of the control module 110, so that the voltages on the multiple control signal terminals of the gate drive circuit 200 are all pulled up to the first target voltage. After the voltages on the multiple control signal terminals are pulled up to the first target voltage for a first preset period of time, the first discharge module 120 discharges the voltage on the first voltage output terminal VGH, and the first voltage output terminal VGH of the control module 110 stops outputting the first target voltage, thereby achieving the purpose of discharging the multiple control signal terminals of the gate drive circuit 200, that is, realizing the activation of the discharge function, and quickly discharging the liquid crystal capacitors and parasitic capacitors in the panel to prevent liquid crystal polarization. In addition, while the first discharge module 120 discharges the voltage on the first voltage output terminal VGH of the control module 110, the first discharge module 120 sends a feedback signal to the control module 110. The control module 110 stops the first voltage output terminal VGH from outputting the first target voltage according to the feedback signal.

[0039] In this embodiment, the discharge control circuit 100 further includes a second discharge module 130, which is respectively connected to the second voltage output terminal Vcom of the control module 110, the data signal terminal Sout of the source driver circuit 300, and the first discharge module 120. The second discharge module 130 is configured to control the data signal terminal Sout of the source driver circuit 300 to be electrically connected to the second voltage output terminal Vcom of the control module 110 after the multiple control signal terminals of the gate driver circuit 200 are electrically connected to the first voltage output terminal VGH of the control module 110, and to discharge the voltage on the second voltage output terminal Vcom after a second preset time period.

[0040] It should be noted that the second discharge module 130 can obtain the information that the multiple control signal terminals of the gate drive circuit 200 are electrically connected to the first voltage output terminal VGH of the control module 110 by being connected to the first discharge module 120; when the second discharge module 130 learns that the multiple control signal terminals of the gate drive circuit 200 are electrically connected to the first voltage output terminal VGH of the control module 110, it controls the data signal terminal Sout of the source drive circuit 300 to be electrically connected to the second voltage output terminal Vcom of the control module 110; therefore, the reason why the pixel brightness does not suddenly change at this time is that: (1) after the voltages on the multiple control signal terminals of the gate drive circuit 200 are pulled up to the first target voltage, the voltage on the data signal terminal Sout of the source drive circuit 300 is then pulled up to the first target voltage. The voltage is bound to the second target voltage, that is, when the voltages of the multiple control signal terminals are pulled up to the first target voltage, the data signal terminal Sout is still outputting a stable data voltage, and the data voltage is less affected by the coupling; however, if the data signal terminal Sout does not output a data voltage, the decreasing data voltage will be more affected by the coupling; (2) when the data signal terminal Sout still outputs a stable data voltage, the display panel still displays a normal picture, and even if the data voltage has a small coupling effect, the display picture will not have a significant brightness change, and the human eye will not notice it; however, when the data voltage drops to a black grayscale or close to a black grayscale picture and is coupled to a high potential, it will cause the pixels in the panel to be significantly bright, resulting in a flickering problem that is noticeable to the human eye. It can be seen from this that the present application solves the problem of pixel brightness sudden change caused by turning on the discharge function when the power is turned off by pulling the voltages on the multiple control signal terminals of the gate drive circuit 200 to the first target voltage and then binding the voltage on the data signal terminal Sout of the source drive circuit 300 to the second target voltage.

[0041] Furthermore, after the voltage at the data signal terminal Sout is bound to the second target voltage for a first predetermined time period, the second discharge module 130 simultaneously discharges the voltage at the second voltage output terminal Vcom, while the second voltage output terminal Vcom of the control module 110 stops outputting the second target voltage. This achieves the purpose of discharging the data signal terminal Sout of the source driver circuit 300, quickly discharging the liquid crystal capacitors and parasitic capacitors within the panel, and preventing liquid crystal polarization. Furthermore, while the first discharge module 120 simultaneously discharges the voltage at the first voltage output terminal VGH of the control module 110, the first discharge module 120 sends a feedback signal to the control module 110. Based on the feedback signal, the control module 110 stops outputting the first target voltage at the first voltage output terminal VGH and stops outputting the second target voltage at the second voltage output terminal Vcom.

[0042] In summary, the present application controls the electrical connection of multiple control signal terminals of the gate driving circuit 200 with the first voltage output terminal VGH of the control module 110 when detecting that the display panel enters the shutdown state through the first discharge module 120; then, the voltage on the data signal terminal Sout of the source driving circuit 300 is bound to the second target voltage through the second discharge module 130, so that the voltage change of the multiple control signal terminals has no coupling effect on the data voltage or the coupling effect is small, thereby solving the problem of screen flickering when the power-off discharge function is turned on; finally, the first voltage output terminal VGH and the second voltage output terminal Vcom of the control module 110 are discharged respectively through the first discharge module 120 and the second discharge module 130, thereby realizing rapid discharge of the liquid crystal capacitor and parasitic capacitor in the panel, thereby avoiding the screen flickering problem caused by liquid crystal polarization.

[0043] Figure 3 FIG. 1 is a circuit diagram of a first discharge control circuit provided in an embodiment of the present application; FIG. Figure 3 As shown, the first discharge module 120 of this embodiment includes a shutdown detection unit 121, a first transistor T1 and multiple second transistors T2; the shutdown detection unit 121 is used to output a first enable signal through the first enable terminal EN1 when detecting that the display panel enters the shutdown state; the control terminal of the first transistor T1 is connected to the first control terminal Y1 of the control module 110, and the first terminal of the first transistor T1 is connected to the first enable terminal EN1 of the shutdown detection unit 121; the control terminals of the multiple second transistors T2 are connected to the second terminal of the first transistor T1, the first terminals of the multiple second transistors T2 are connected to the first voltage output terminal VGH of the control module 110, and the second terminals of the multiple second transistors T2 are respectively electrically connected one by one to the multiple control signal terminals of the gate drive circuit 200.

[0044] Optionally, the shutdown detection unit 121 is further configured to output a second enable signal through the second enable terminal EN2 after outputting the first enable signal for a first preset time period.

[0045] Optionally, the first discharge module 120 further includes: a third transistor T3, the control end of the third transistor T3 is connected to the second enable end EN2 of the shutdown detection unit 121, the first end of the third transistor T3 is connected to the first voltage output end VGH of the control module 110, and the second end of the third transistor T3 is grounded.

[0046] In addition, the turn-on voltage of the first transistor T1 can be a low level, which can be understood as the first transistor T1 being a P-type MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor), and the turn-on voltage of the second transistor T2 can be a high level, which can be understood as the second transistor T2 being an N-type MOS transistor; conversely, the first transistor T1 can also be an N-type MOS transistor, and the second transistor T2 can also be a P-type MOS transistor. The specific types of transistors in this application can be flexibly matched according to actual application scenarios.

[0047] Here, the specific working principle of the first discharge module 120 is described by taking the first transistor T1 as a P-type MOS transistor, the second transistor T2 as an N-type MOS transistor, and the third transistor T3 as an N-type MOS transistor as an example:

[0048] (1) The shutdown detection unit 121 determines whether the display panel enters the shutdown state by detecting in real time whether the power supply voltage is less than or equal to the threshold voltage. When it is detected that the power supply voltage drops to the threshold voltage, it is determined that the display panel enters the shutdown state, and a high-level first enable signal is output through the first enable terminal EN1; at the same time, the first control terminal Y1 of the control module 110 outputs a low level, turning on the first transistor T1; the high-level first enable signal acts on the control terminals of the plurality of second transistors T2 through the turned-on first transistor T1, and the plurality of second transistors T2 are turned on at the same time, so that the plurality of control signal terminals of the gate drive circuit 200 are electrically connected to the first output terminal of the control module 110 through the turned-on second transistors T2, thereby realizing the function of the first discharge module 120 controlling the plurality of control signal terminals of the gate drive circuit 200 to be electrically connected to the first voltage output terminal VGH of the control module 110 when detecting that the display panel enters the shutdown state.

[0049] (2) After the voltages of the multiple control signal terminals are pulled up to the first target voltage, that is, after the first preset time period after the shutdown detection unit 121 outputs the first enable signal, a high-level second enable signal is output through the second enable terminal EN2, turning on the third transistor T3; at the same time, the third enable terminal EN3 of the shutdown detection unit 121 is also connected to the control module 110, for outputting the third enable signal to the control module 110, and the control module 110 stops the first voltage output terminal VGH from outputting the first target voltage according to the third enable signal, thereby realizing the function of the first discharge module 120 discharging the voltage on the first voltage output terminal VGH and the voltages on the multiple control signal terminals simultaneously after the first preset time period.

[0050] like Figure 3As shown, the second discharge module 130 of this embodiment includes a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The control end of the fourth transistor T4 is connected to the second end of the first transistor T1, and the first end of the fourth transistor T4 is connected to the second control end Y2 of the control module 110; the control end of the fifth transistor T5 is connected to the second end of the fourth transistor T4, and the first end of the fifth transistor T5 is connected to the third control end Y3 of the control module 110; the control end of the sixth transistor T6 is connected to the second end of the fifth transistor T5, and the first end of the sixth transistor T6 is connected to the data signal end Sout of the source driver circuit 300; the control end of the seventh transistor T7 is connected to the control end of the third transistor T3, the first end of the seventh transistor T7 is connected to the second end of the sixth transistor T6, and the second end of the seventh transistor T7 is grounded.

[0051] It should be noted that, in this embodiment, the fourth transistor T4 is an N-type MOS transistor, the fifth transistor T5 is a P-type MOS transistor, the sixth transistor T6 is an N-type MOS transistor, and the seventh transistor T7 is an N-type MOS transistor. The working principle of the second discharge module 130 in this embodiment is described as follows:

[0052] (1) After the first transistor T1 is turned on, the first enable signal output by the shutdown detection unit 121 acts on the control terminal of the fourth transistor T4 in the second discharge module 130 through the turned-on first transistor T1, and the fourth transistor T4 is turned on, so that the low level output by the second control terminal Y2 of the control module 110 turns on the fifth transistor T5, and then the high level output by the third control terminal Y3 of the control module 110 turns on the sixth transistor T6, thereby realizing the function of controlling the data signal terminal Sout of the source drive circuit 300 to be electrically connected to the second voltage output terminal Vcom of the control module 110; since the high level output by the first transistor T1 can realize the gate drive circuit 200 through a transistor (i.e., the second transistor T2), Multiple control signal terminals are electrically connected to the first voltage output terminal VGH of the control module 110. However, the high level output by the first transistor T1 needs to pass through three transistors (i.e., the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6) to achieve the electrical connection between the data signal terminal Sout of the source drive current and the second voltage output terminal Vcom of the control module 110. The conduction time of the three transistors is longer than the conduction time of one transistor. Therefore, after the multiple control signal terminals of the gate drive circuit 200 are electrically connected to the first voltage output terminal VGH of the control module 110, the function of controlling the data signal terminal Sout of the source drive circuit 300 to be electrically connected to the second voltage output terminal Vcom of the control module 110 is achieved.

[0053] (2) The second enable signal output by the shutdown detection unit 121 turns on the seventh transistor T7; at the same time, under the action of the third enable signal output by the shutdown detection unit 121, the control module 110 causes the first voltage output terminal VGH and the second voltage output terminal Vcom to simultaneously stop outputting the first target voltage and the second target voltage, thereby realizing the function of the second discharge module 130 to simultaneously discharge the voltage on the second voltage output terminal Vcom and the voltage on the data signal terminal Sout after the second preset time period.

[0054] Figure 4 FIG. 1 is a circuit diagram of a second discharge control circuit provided in an embodiment of the present application; Figure 4 exist Figure 3 On the basis of the second discharge module 130, the first capacitor C1 is added; Figure 4 As shown, the second discharge module 130 further includes: a first capacitor C1 , a first end of the first capacitor C1 is connected to the control end of the sixth transistor T6 , and a second end of the first capacitor C1 is grounded.

[0055] It should be noted that, in this embodiment, by providing the first capacitor C1 at the control terminal of the sixth transistor T6, the turn-on time of the sixth transistor T6 can be delayed, so that after the multiple control signal terminals of the gate driver circuit 200 are pulled up by the output voltage of the first voltage output terminal VGH of the control module 110, the data signal terminal Sout of the source driver circuit 300 is controlled to be electrically connected to the second voltage output terminal Vcom of the control module 110, thereby effectively avoiding the problem of coupling mutation during the falling data voltage.

[0056] Figure 5 FIG. 1 is a circuit diagram of a third discharge control circuit provided in an embodiment of the present application; Figure 5 exist Figure 3 On the basis of the second discharge module 130, a delay unit 131 is added to the input end; Figure 5 As shown, the second discharge module 130 of this embodiment includes a delay unit 131, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7.

[0057] Specifically, a first end of the delay unit 131 is connected to the first discharge module 120, and is configured to output a delay control signal after the control signal end of the gate drive circuit 200 is electrically connected to the first voltage output end VGH of the control module 110; a control end of the fourth transistor T4 is connected to the second end of the delay unit 131, and a first end of the fourth transistor T4 is connected to the second control end Y2 of the control module 110; a control end of the fifth transistor T5 is connected to the second end of the fourth transistor T4, and a first end of the fifth transistor T5 is connected to the third control end Y3 of the control module 110; a control end of the sixth transistor T6 is connected to the second end of the fifth transistor T5, and a first end of the sixth transistor T6 is connected to the data signal end Sout of the source drive circuit 300; a control end of the seventh transistor T7 is connected to the control end of the third transistor T3, a first end of the seventh transistor T7 is connected to the second end of the sixth transistor T6, and a second end of the seventh transistor T7 is grounded.

[0058] It should be noted that the function of the delay unit 131 in this embodiment is the same as Figure 4 The first capacitor C1 has the same function: delaying the turn-on time of the sixth transistor T6, and providing sufficient buffer time for the voltages of the multiple control signal terminals of the gate driving circuit 200 to be pulled up to the second target voltage; Figure 4 The first capacitor C1 is set at the control terminal of the sixth transistor T6, and the delay unit 131 of this embodiment is set at the input terminal of the second discharge module 130; the delay unit 131 outputs the delay control signal for controlling the fourth transistor T4 after the control signal terminal of the gate drive circuit 200 is electrically connected to the first voltage output terminal VGH of the control module 110. Figure 3 The delayed control signal for controlling the fourth transistor T4 is directly obtained from the second terminal of the first transistor T1, which has a certain delay time. In addition, the functions and working principles of the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 in this embodiment are similar to those in FIG. Figure 3 The same, no longer repeated here.

[0059] Figure 6 FIG. 1 is a circuit diagram of a fourth discharge control circuit provided in an embodiment of the present application; Figure 6 Shown Figure 5 A specific implementation of the delay unit 131 is as follows: Figure 6As shown: the delay unit 131 includes a first resistor R1, a second capacitor C2, a transistor Q1 and a second resistor R2, the first end of the first resistor R1 is connected to the second end of the first transistor T1; the first end of the second capacitor C2 is connected to the second end of the first resistor R1, and the second end of the second capacitor C2 is connected to the control end of the fourth transistor T4; the base of the transistor Q1 is connected to the first end of the second capacitor C2, the collector of the transistor Q1 is connected to the first end of the first resistor R1, and the emitter of the transistor Q1 is connected to the second end of the second capacitor C2; the first end of the second resistor R2 is connected to the base of the transistor Q1, and the second end of the second resistor R2 is connected to the emitter of the transistor Q1.

[0060] It should be noted that when the first transistor T1 is turned on and outputs a high level, the multiple second transistors T2 will be turned on immediately, so that the voltages of the multiple control signal terminals are gradually pulled up to the first target voltage; at the same time, the high level output by the first transistor T1 is charged to the second capacitor C2 through the first resistor R1. When the voltage of the second capacitor C2 reaches the turn-on voltage of the transistor after a certain period of time, the transistor Q1 is turned on, and the high level output by the first transistor T1 is given to the control terminal of the fourth transistor T4, and then the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned on in sequence, thereby achieving the delay of the data signal terminal Sout being pulled down to the second target voltage; the delay time is determined by the capacitance of the second capacitor C2. The larger the capacitance, the longer the charging time, and the time required for charging, that is, the longer the delay time, can be set according to actual conditions.

[0061] Figure 7 FIG. 5 is a circuit diagram of a fifth discharge control circuit provided in an embodiment of the present application; Figure 7 Shown Figure 5 Another specific implementation of the delay unit 131 is as follows: Figure 7 As shown, the delay unit 131 includes: an XNOR gate, a first input terminal of the XNOR gate is connected to the first terminal of the second transistor T2, a second input terminal of the XNOR gate is connected to the second terminal of the second transistor T2, and an output terminal of the XNOR gate is connected to the control terminal of the fourth transistor T4.

[0062] It should be noted that this embodiment uses an XOR gate for voltage detection. The two inputs of the XOR gate are connected to the first voltage output terminal VGH of the control module 110 and the control signal terminal of the gate driver circuit 200, respectively. The output of the XOR gate controls the turning on and off of the fourth transistor T4. When the voltage at the control signal terminal of the gate driver circuit 200 is not pulled up to the first target voltage, the voltages at the two inputs of the XOR gate are different. Therefore, the XOR gate outputs a low level, preventing the fourth transistor T4 from turning on and the voltage at the data signal terminal Sout of the source driver circuit 300 from changing. After the voltage at the control signal terminal of the gate driver circuit 200 is pulled up to the first target voltage, the voltages at the two inputs of the XOR gate are the same. Therefore, the XOR gate outputs a high level, turning on the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 in sequence. The voltage at the data signal terminal Sout of the source driver circuit 300 then changes in accordance with the second target voltage, thereby preventing the changing data voltage from being coupled with abrupt changes.

[0063] Figure 8 FIG. 1 is a circuit diagram of a sixth discharge control circuit provided in an embodiment of the present application; Figure 8 Shown Figure 5 Another specific implementation of the delay unit 131 is as follows: Figure 8 As shown, the delay unit 131 includes: a comparator, a first input terminal of the comparator is connected to the first terminal of the second transistor T2, a second input terminal of the comparator is connected to the second terminal of the second transistor T2, and an output terminal of the comparator is connected to the control terminal of the fourth transistor T4.

[0064] It should be noted that this embodiment uses a comparator for voltage detection and determination. The comparator's two inputs are connected to the first voltage output terminal VGH of the control module 110 and the control signal terminal of the gate driver circuit 200, respectively. The comparator's output controls the on and off of the fourth transistor T4. When the voltage at the control signal terminal of the gate driver circuit 200 is not pulled up to the first target voltage, the voltages at the two inputs of the comparator differ, causing the NOR gate to output a low level, preventing the fourth transistor T4 from turning on and the voltage at the data signal terminal Sout of the source driver circuit 300 from changing. After the voltage at the control signal terminal of the gate driver circuit 200 is pulled up to the first target voltage, the voltages at the two inputs of the comparator become the same, causing the comparator to output a high level, turning on the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 in sequence. The voltage at the data signal terminal Sout of the source driver circuit 300 then changes in accordance with the second target voltage, thereby preventing the changing data voltage from being coupled with abrupt changes.

[0065] In another embodiment, the present application can also be Figure 6 、 Figure 7 and Figure 8On the basis of the delay unit 131 shown, a first capacitor C1 is added to the control terminal of the sixth transistor T6 to further control the turn-on time of the sixth transistor T6.

[0066] In summary, the present application solves the problem of screen flickering when the discharge function is turned on during shutdown by pulling the voltage on multiple control signal terminals of the gate drive circuit 200 to a first target voltage and then binding the voltage on the data signal terminal Sout of the source drive circuit 300 to a second target voltage.

[0067] In a second aspect, an embodiment of the present application provides a display panel including a display area and a non-display area, wherein the display area includes a pixel array; the non-display area includes a gate drive circuit, a source drive circuit and a discharge control circuit, and the discharge control circuit is electrically connected to the gate drive circuit and the source drive circuit respectively.

[0068] Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," or "third" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0069] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0070] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. A discharge control circuit, characterized in that: Applied to a display panel, the display panel includes a gate drive circuit and a source drive circuit, and the discharge control circuit includes: a control module, the control module comprising a first voltage output terminal for outputting a first target voltage and a second voltage output terminal for outputting a second target voltage; a first discharge module, the first discharge module being connected to the first voltage output terminal of the control module and the plurality of control signal terminals of the gate drive circuit, respectively, and being configured to control the plurality of control signal terminals of the gate drive circuit to be electrically connected to the first voltage output terminal of the control module when detecting that the display panel enters a shutdown state, and to discharge the voltage on the first voltage output terminal after a first preset time period; wherein the plurality of control signal terminals include a clock signal terminal, a frame start signal terminal, and a pull-down control terminal; A second discharge module, the second discharge module is respectively connected to the second voltage output terminal of the control module, the data signal terminal of the source drive circuit and the first discharge module, and is used to control the data signal terminal of the source drive circuit to be electrically connected to the second voltage output terminal of the control module after the multiple control signal terminals of the gate drive circuit are electrically connected to the first voltage output terminal of the control module, and discharge the voltage on the second voltage output terminal after a second preset time.

2. The discharge control circuit according to claim 1, wherein: The first discharge module includes: a shutdown detection unit, configured to output a first enable signal via a first enable terminal when detecting that the display panel has entered a shutdown state; a first transistor, wherein a control terminal of the first transistor is connected to a first control terminal of the control module, and a first terminal of the first transistor is connected to a first enable terminal of the shutdown detection unit; Multiple second transistors, the control ends of the multiple second transistors are connected to the second end of the first transistor, the first ends of the multiple second transistors are connected to the first voltage output end of the control module, and the second ends of the multiple second transistors are respectively electrically connected one by one to the multiple control signal ends of the gate drive circuit.

3. The discharge control circuit according to claim 2, characterized in that: The shutdown detection unit is further configured to output a second enable signal via a second enable terminal after outputting the first enable signal for a first preset time period; The first discharge module further includes: a third transistor, a control end of the third transistor is connected to the second enable end of the shutdown detection unit, a first end of the third transistor is connected to the first voltage output end of the control module, and a second end of the third transistor is grounded.

4. The discharge control circuit according to claim 3, characterized in that: The second discharge module includes: a fourth transistor, wherein a control terminal of the fourth transistor is connected to the second terminal of the first transistor, and a first terminal of the fourth transistor is connected to the second control terminal of the control module; a fifth transistor, wherein a control terminal of the fifth transistor is connected to the second terminal of the fourth transistor, and a first terminal of the fifth transistor is connected to the third control terminal of the control module; a sixth transistor, wherein a control terminal of the sixth transistor is connected to the second terminal of the fifth transistor, and a first terminal of the sixth transistor is connected to the data signal terminal of the source driving circuit; a seventh transistor, wherein a control end of the seventh transistor is connected to the control end of the third transistor, a first end of the seventh transistor is connected to the second end of the sixth transistor, and a second end of the seventh transistor is grounded.

5. The discharge control circuit according to claim 4, characterized in that: The second discharge module further includes: A first capacitor, wherein a first end of the first capacitor is connected to the control end of the sixth transistor, and a second end of the first capacitor is grounded.

6. The discharge control circuit according to claim 3, characterized in that: The second discharge module includes: a delay unit, wherein a first end of the delay unit is connected to the first discharge module and is configured to output a delay control signal after the control signal end of the gate drive circuit is electrically connected to the first voltage output end of the control module; a fourth transistor, wherein a control terminal of the fourth transistor is connected to the second terminal of the delay unit, and a first terminal of the fourth transistor is connected to the second control terminal of the control module; a fifth transistor, wherein a control terminal of the fifth transistor is connected to the second terminal of the fourth transistor, and a first terminal of the fifth transistor is connected to the third control terminal of the control module; a sixth transistor, wherein a control terminal of the sixth transistor is connected to the second terminal of the fifth transistor, and a first terminal of the sixth transistor is connected to the data signal terminal of the source driving circuit; a seventh transistor, wherein a control end of the seventh transistor is connected to the control end of the third transistor, a first end of the seventh transistor is connected to the second end of the sixth transistor, and a second end of the seventh transistor is grounded.

7. The discharge control circuit according to claim 6, characterized in that: The delay unit comprises: a first resistor, wherein a first end of the first resistor is connected to the second end of the first transistor; a second capacitor, wherein a first end of the second capacitor is connected to the second end of the first resistor, and a second end of the second capacitor is connected to the control end of the fourth transistor; a transistor, wherein the base of the transistor is connected to the first end of the second capacitor, the collector of the transistor is connected to the first end of the first resistor, and the emitter of the transistor is connected to the second end of the second capacitor; A second resistor, wherein a first end of the second resistor is connected to the base of the transistor, and a second end of the second resistor is connected to the emitter of the transistor.

8. The discharge control circuit according to claim 6, wherein: The delay unit comprises: An XNOR gate, wherein a first input terminal of the XNOR gate is connected to the first terminal of the second transistor, a second input terminal of the XNOR gate is connected to the second terminal of the second transistor, and an output terminal of the XNOR gate is connected to the control terminal of the fourth transistor.

9. The discharge control circuit according to claim 6, characterized in that: The delay unit comprises: A comparator, wherein a first input terminal of the comparator is connected to the first terminal of the second transistor, a second input terminal of the comparator is connected to the second terminal of the second transistor, and an output terminal of the comparator is connected to the control terminal of the fourth transistor.

10. A display panel comprising a display area and a non-display area, characterized in that: The display area includes a pixel array; The non-display area includes a gate driving circuit, a source driving circuit, and the discharge control circuit according to any one of claims 1 to 9, and the discharge control circuit is electrically connected to the gate driving circuit and the source driving circuit respectively.

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