Memory circuit and operating method thereof

Abstract

Embodiments of the present invention provide a memory circuit comprising: a memory array comprising a plurality of memory cells, where each of the plurality of memory cells is accessible through a plurality of bit lines; a comparator configured to receive a first address signal indicating a first row along which the first memory cells are arranged and a second address signal indicating a second row along which the second memory cells are arranged, and generate a control signal having a logic state indicating whether the first row is the same as the second row; and a timing circuit configured to skip pre-charging the bit line of the second memory cell after accessing the first memory cell based on a logic state of the control signal. The embodiment of the invention also provides a method for operating the memory circuit.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of electronic circuits, and more particularly, to memory circuits and methods of operating the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. As the size of ICs continues to shrink, more and more devices are integrated onto a single chip. This scaling process generally provides many benefits by increasing production efficiency and reducing associated costs. Summary of the Invention

[0003] Embodiments of the present invention provide a memory circuit, comprising: a memory array including a plurality of memory cells, wherein each of the plurality of memory cells is accessible via a plurality of bit lines; a comparator configured to receive a first address signal indicative of a first row along which a first memory cell is arranged and a second address signal indicative of a second row along which a second memory cell is arranged, and to generate a control signal having a logical state indicative of whether the first row is the same as the second row; and a timing circuit configured to skip precharging of the bit lines of the second memory cell after accessing the first memory cell based on the logical state of the control signal.

[0004] Another embodiment of the present invention provides a memory circuit, comprising: a comparator configured to compare a first address signal with a second address signal to generate a control signal, wherein the first address signal partially indicates a first row of a first memory cell, the second address signal partially indicates a second row of a second memory cell, and wherein the control signal has a logical state indicative of whether the first row is the same as the second row; and a timing circuit configured to skip precharging of the bit lines of the second memory cell after accessing the first memory cell based on the logical state of the control signal.

[0005] Another embodiment of the present invention provides a method for operating a memory circuit, including: precharging the bit line of a first memory cell; comparing a first address signal and a second address signal to generate a control signal, wherein the first address signal indicates a first row of the first memory cell, the second address signal indicates a second row of a second different memory cell, and wherein the control signal has a logic state indicating that the first row is the same as the second row; generating a precharging signal having a logic state that stops precharging the bit line of the first memory cell; accessing the first memory cell for a read or write operation in response to a first clock pulse of a clock signal being set; skipping precharging the bit line of a second memory cell in response to recognizing the logic state of the control signal; and accessing the second memory cell for a read or write operation in response to a second clock pulse of the clock signal being set. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1 A block diagram illustrating an example circuit in accordance with some embodiments.

[0008] Figure 2 A block diagram illustrating an example circuit in accordance with some embodiments.

[0009] Figure 3 A block diagram illustrating an example circuit in accordance with some embodiments.

[0010] Figure 4 A block diagram illustrating an example circuit in accordance with some embodiments.

[0011] Figure 5 A block diagram illustrating an example circuit in accordance with some embodiments.

[0012] Figure 6 A block diagram illustrating an example circuit in accordance with some embodiments.

[0013] Figure 7 A block diagram illustrating example waveforms related to a circuit in accordance with some embodiments.

[0014] Figure 8A A block diagram illustrating an example circuit in accordance with some embodiments.

[0015] Figure 8B A block diagram illustrating an example circuit in accordance with some embodiments.

[0016] Figure 9ABlock diagram showing an example circuit according to some embodiments.

[0017] Figure 9B Block diagram showing an example circuit according to some embodiments.

[0018] Figure 10A Waveform diagram showing an example related to a circuit according to some embodiments.

[0019] Figure 10B Waveform diagram showing an example related to a circuit according to some embodiments.

[0020] Figure 11A Block diagram showing an example circuit according to some embodiments.

[0021] Figure 11B Block diagram showing an example circuit according to some embodiments.

[0022] Figure 12 Block diagram showing an example circuit according to some embodiments.

[0023] Figure 13 Waveform diagram showing an example related to a circuit according to some embodiments.

[0024] Figure 14 Waveform diagram showing an example related to a circuit according to some embodiments.

[0025] Figure 15 Block diagram showing an example circuit according to some embodiments.

[0026] Figure 16 Block diagram showing an example circuit according to some embodiments.

[0027] Figure 17 Block diagram showing an example circuit according to some embodiments.

[0028] Figure 18 Block diagram showing an example circuit according to some embodiments.

[0029] Figure 19 Waveform diagram showing an example related to a circuit according to some embodiments.

[0030] Figure 20 Waveform diagram showing an example related to a circuit according to some embodiments.

[0031] Figure 21 Block diagram showing an example circuit and related waveforms according to some embodiments.

[0032] Figure 22 Flowchart showing a method of operating a circuit according to some embodiments.

[0033] Figure 23A flowchart showing a method of operating a circuit according to some embodiments. Detailed Description

[0034] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first component formed is in direct contact with the second component, and may also include embodiments where additional components may be formed between the first component and the second component such that the first component and the second component are not in direct contact. Also, the present invention may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity, but in and of itself does not specify a relationship between the various embodiments and / or configurations being discussed.

[0035] In addition, for ease of description, spatial relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another as shown in the figures. Spatial relationship terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented otherwise (rotated 90 degrees or at other orientations), and the spatial relationship descriptors used herein may be interpreted accordingly.

[0036] Typically, bit line precharging is usually performed in a memory device, e.g., before performing an access (e.g., read, write) operation on the memory device. The percentage of power consumed by bit line precharging can be significant. With the trend of continuously shrinking the size and dimensions of memory devices, this can have an adverse impact on the overall performance of the memory device, and thus it is desirable to reduce the power consumed by bit line precharging. The present disclosure provides various embodiments of a memory circuit that can skip one or more precharging steps based on the locations of two subsequently accessed memory cells, thereby reducing dynamic power. In some embodiments, precharging can be skipped based on the location (e.g., row) of a first memory cell and a second memory cell accessed after the first memory cell. The memory circuit can be configured to compare a first address (e.g., row) of the first memory cell and a second address (e.g., row) of the second memory cell, and to skip precharging based on a signal indicating that the first address and the second address indicate the same row. In some embodiments, precharging can be skipped based on an operation (e.g., read or write) associated with the second memory cell. The memory circuit can be configured to decode an address signal, and to skip precharging based on a signal indicating that a write operation is performed on the address signal. This provides a simple and flexible solution to effectively reduce the power consumed by precharging, while being applicable to any memory macro that can use bit line precharging.

[0037] Figure 1 FIG. 4 is a block diagram illustrating an example circuit 100 according to some embodiments. The circuit 100 may be referred to as a memory device. The circuit 100 includes a memory array 120 and a memory controller 105. Figure 1 A non-limiting example of the circuit 100 is shown in FIG. 4. In some embodiments, the circuit 100 may include more, fewer, or different components than Figure 1 shown in FIG. 4 or as described with respect to Figure 1 FIG. 4.

[0038] In some embodiments, the memory array 120 includes a plurality of memory circuits or memory cells. The memory array 120 also includes word lines WL0, WL1...WLJ, each extending in a first direction (e.g., the X direction), and bit lines BL0, BL1...BLK, each extending in a second direction (e.g., the Y direction). Each memory circuit or memory cell of the memory array 120 can be accessed through a plurality of bit lines BL and / or a plurality of word lines WL. The word lines WL and the bit lines BL can each be a conductive metal or a conductive track. In some embodiments, each memory cell is coupled to a corresponding word line WL and a corresponding bit line BL, and can be operated according to the voltage or current through the corresponding word line WL and the corresponding bit line BL. In some embodiments, each bit line includes bit lines BL, BLB coupled to one or more memory cells in a set of memory cells arranged along the second direction (e.g., the Y direction). The bit lines BL, BLB can receive and / or provide differential signals. In some embodiments, each memory cell in the memory array 120 can include a six-transistor (6T) static random access memory (SRAM) cell.

[0039] Each memory cell can include a volatile memory cell, a non-volatile memory cell, or a combination thereof. For example, each memory cell is embodied as a static random access memory (SRAM) cell. However, it should be understood that the memory cell can be implemented as any of various other non-volatile memory cells, such as a resistive random access memory (RRAM) cell, a magnetoresistive random access memory (MRAM) cell, a phase change random access memory (PCRAM) cell, an eFuse, an anti-fuse, etc., while still being within the scope of the present disclosure. In some embodiments, the memory array 120 includes additional lines (e.g., selection lines, reference lines, reference control lines, power rails, etc.).

[0040] Memory controller 105 is a hardware component that controls the operation of memory array 120. In some embodiments, memory controller 105 includes a bit line (BL) controller 112, a word line (WL) controller 114, and a voltage supply circuit 110. BL controller 112, WL controller 114, and voltage supply circuit 110 may be embodied as logic circuits, analog circuits, or a combination thereof. In one configuration, WL controller 114 is a circuit that provides voltage or current through one or more word lines WL of memory array 120, and BL controller 112 is a circuit that provides or senses voltage or current through one or more bit lines BL of memory array 120. In one configuration, voltage supply circuit 110 is a circuit that provides a voltage signal to BL controller 112 and / or WL controller 114. BL controller 112 may be coupled to bit lines BL of memory array 120, and WL controller 114 may be coupled to word lines WL of memory array 120. In some embodiments, memory controller 105 includes more, fewer, or different components compared to the Figure 1 components shown.

[0041] In some embodiments, memory controller 105 may include a comparator and / or be operatively coupled to a comparator. The comparator may be configured to receive an address signal indicating a row along which one of the memory cells is arranged. For example, the comparator may receive a first address signal indicating a first row along which a first one of the memory cells is arranged and a second address signal indicating a second row along which a second one of the memory cells is arranged. The comparator may generate a control signal having a logical state indicating whether the first row is the same as the second row. In some embodiments, the comparator may compare the first address signal with the second address signal to generate the control signal. The first address signal may partially indicate the first row of the first memory cell, and the second address signal may partially indicate the second row of the second memory cell. The control signal may have a logical state indicating whether the first row is the same as the second row. In some embodiments, the comparator may be operatively coupled to at least one of BL controller 112, WL controller 114, or voltage supply circuit 116.

[0042] In some embodiments, memory controller 105 may include a decoder and / or be operatively coupled to a decoder. The decoder may be configured to receive an address signal. The address signal may partially indicate a column address of the memory cell. In some embodiments, the decoder may be configured to decode the address signal. Based on the decoding result, the decoder may be configured to generate a control signal. The control signal may include the decoding result. In some embodiments, the control signal may include a result of a power. For example, when the address signal includes 3 bits (e.g., AYB<2:0>), the control signal may include the decoding result, which includes the result of the power (e.g., 2 3)。The decoder can be configured to provide a control signal to the timing circuit. In some embodiments, the decoder can be operably coupled to at least one of the BL controller 112, the WL controller 114, or the voltage supply circuit 116.

[0043] In some embodiments, the memory controller 105 can include a timing circuit and / or be operably coupled to a timing circuit. The timing circuit can be configured to skip precharging of the bit line BL of the second memory cell after accessing the first memory cell based on a control signal (e.g., the logical state of the control signal). In some embodiments, the timing circuit can be operably coupled to at least one of the BL controller 112, the WL controller 114, or the voltage supply circuit 116.

[0044] Figure 2 A block diagram showing an example circuit according to some embodiments. More specifically, Figure 2 the circuit shown is the memory controller 105 operably coupled to the example memory circuit 220. The memory circuit 220 can be substantially similar to the memory array 120 and / or include features of the memory array 120. The memory circuit 220 can include a plurality of columns <0>,..., <m-1>, each column includes a plurality of memory cells and a BL precharge circuit 225, and includes a plurality of word lines WL WL<0>,..., WL <n-1>。 Figure 2 A non - limiting example of the circuit is shown. In some embodiments, the circuit may include more, fewer, or different components than those shown in Figure 2 or described with respect to Figure 2 In some embodiments, the memory circuit 220 may include or be operably coupled to a multiplexer 260, an input / output (IO) interface 270, etc.

[0045] In some embodiments, the memory circuit 220 may include a BL pre - charge circuit 225. The BL pre - charge circuit 225 may be configured to control the memory cells of the memory circuit 220. In some embodiments, the BL pre - charge circuit 225 may be configured to charge the bit line BL, for example, during a memory read or write operation. The BL pre - charge circuit 225 may receive a signal from the memory controller 105 and may control the memory cells of the memory circuit 220 based on that signal. In some embodiments, the BL pre - charge circuit 225 may include transistors (e.g., n - type transistors, p - type transistors, combinations thereof, etc.).

[0046] The memory controller 105 may generate a pre - charge signal BLPREB to control the BL pre - charge circuit 225. In some embodiments, the memory controller 105 may receive a clock pulse ICLK, a phase signal PHASE, a first address signal AXA, a second address signal AXB, etc. Based on the reception of at least the first address signal AXA and the second address signal AXB, the memory controller 105 may generate a pre - charge signal BLPREB to control the BL pre - charge circuit 225, as discussed in detail below.

[0047] In some embodiments, the memory circuit 220 may be operably coupled to the IO interface 270. The IO interface 270 may include circuitry configured to read data from the memory circuit 220 via the bit lines BL / BLB and / or configured to write data to the memory circuit 220 via the bit lines BL / BLB. In some embodiments, the IO interface 270 may be operably coupled to the memory circuit 220 via the multiplexer 260. The IO interface 270 may perform read and / or write operations on the bit lines BL / BLB selected from the multiplexer 260.

[0048] Figure 3 A block diagram showing an example circuit according to some embodiments. More specifically, Figure 3 an example memory controller 305 is shown. The memory controller 305 may be substantially similar to the memory controller 105 and / or include features of the memory controller 105. The memory controller 305 may include an address comparator 330 and a timing circuit 350, which may be related to Figure 1 The described address comparator and timing circuit are substantially similar and / or include features regarding Figure 1 the described address comparator and timing circuit. Figure 3 A non-limiting example of the memory controller 305 is shown in Figure 3 . In some embodiments, the memory controller 305 may include more, fewer, or different components than those shown in Figure 3 or regarding Figure 3 as described in Figure 3 the description.

[0049] The address comparator 330 may be configured to receive a first address signal AXA. The first address signal AXA may partially indicate a first row of a first memory cell (e.g., the first memory cell 221). For example, the first address signal AXA may indicate the first row along which the first memory cell is disposed. The address comparator 330 may receive a second address signal AXB. The second address signal AXB may partially indicate a second row of a second memory cell (e.g., the second memory cell 222). For example, the second address signal AXB may indicate the second row along which the second memory cell is disposed.

[0050] In some embodiments, the address comparator 330 may be configured to compare the first address signal AXA with the second address signal AXB. Based on the comparison between the first address signal AXA and the second address signal AXB, the address comparator 330 may be configured to generate a control signal CR. The control signal CR may include a comparison result. In some embodiments, the control signal CR may indicate whether the first row is the same as the second row. In some embodiments, the control signal CR may have a logic state indicating whether the first row is the same as the second row. For example, a control signal CR having a logic state (e.g., "1") may indicate that the first row is the same as the second row, while a control signal CR having a logic state (e.g., "0") may indicate that the first row is not the same as the second row.

[0051] The timing circuit 350 may be configured to receive a clock pulse ICLK, a phase signal PHASE, and the control signal CR. Based at least on the reception of the control signal CR, the timing circuit 350 may provide a precharge signal BLPREB. The precharge signal BLPREB may be configured to skip precharging of the bit lines BL of the second memory cell (e.g., the second memory cell 222) after accessing the first memory cell (e.g., the first memory cell 221) based on the logic state of the control signal CR. In some embodiments, the phase signal PHASE may be a signal configured to transition between different logic states (e.g., "0" and "1") when accessing the respective memory cells of the memory array.

[0052] In some embodiments, the timing circuit 350 may be operably coupled to an external circuit or pin. The timing circuit 350 may receive a signal from the external circuit or pin indicating whether a first row is the same as a second row.

[0053] Figure 4 A block diagram showing an example circuit in accordance with some embodiments. More specifically, Figure 4 An example timing circuit 450 is shown. The timing circuit 450 may be substantially similar to the timing circuit 350 and / or include features of the timing circuit 350. Figure 4 A non-limiting example of the timing circuit 450 is shown. In some embodiments, the timing circuit 450 may include more, fewer, or different components than Figure 4 shown or described with respect to Figure 1 more, fewer, or different components.

[0054] In some embodiments, the timing circuit 450 may include at least one logic gate. In some embodiments, the timing circuit 450 may include a first NAND gate 451 and a second NAND gate 452. The first NAND gate 451 may be configured to receive a control signal CR and a phase signal PHASE. Based on the control signal CR and the phase signal PHASE, the first NAND gate 451 may provide an output PCB. The second NAND gate 452 may be configured to receive the output PCB and a logically inverted clock pulse (e.g., the clock pulse ICLK through an inverter 453). Based on the output PCB and the logically inverted clock pulse, the second NAND gate 452 may provide a precharge signal BLPREB.

[0055] In some embodiments, the timing circuit 450 may be configured to control the precharge of the bit lines BL of a memory array. In some embodiments, the precharge signal BLPREB may be configured for the precharge of the bit lines BL of a memory array (e.g., the memory array 120). For example, the precharge signal BLPREB may cause a BL precharge circuit (e.g., the BL precharge circuit 225) to precharge the bit lines BL of the memory array. In some embodiments, the precharge signal BLPREB may be configured for a precharge operation. For example, the precharge signal BLPREB may cause the BL precharge circuit (e.g., the BL precharge circuit 225) to skip the precharge of the bit lines BL of the memory array. In some embodiments, the timing circuit 450 may be configured to skip the precharge of the bit lines BL based on an access timing. For example, the timing circuit 450 may be configured to skip the precharge of the bit lines BL of a second memory cell (e.g., the second memory cell 222) after accessing a first memory cell (e.g., the first memory cell 221) based on the logical state of the control signal CR.

[0056] For example, when the control signal CR has a logic state (e.g., "0") (e.g., the first row is different from the second row) and the output PCB has a logic state of "1", which is synchronized with the clock pulse ICLK, the precharge signal BLPREB can cause the BL precharge circuit (e.g., BL precharge circuit 225) to precharge the bit lines BL of the memory array. When the control signal CR has a logic state (e.g., "1") (e.g., the first row is the same as the second row) and the output PCB has a logic state of "0", the logic state of the precharge signal BLPREB is "1", so that the BL precharge circuit (e.g., BL precharge circuit 225) skips the precharging of the bit lines BL of the memory array. In some embodiments, the transistors of the BL precharge circuit (e.g., BL precharge circuit 225) can be turned off to stop the precharging of the bit lines BL.

[0057] Figure 5 A block diagram showing an example circuit according to some embodiments. More specifically, Figure 5 An example address comparator 530 is shown. The address comparator 530 can be substantially similar to the address comparator 330 and / or include the features of the address comparator 330. Figure 5 An example address comparator 530 is shown therein. In some embodiments, the address comparator 530 can include Figure 5 shown therein or with respect to Figure 5 more, fewer, or different components than those described.

[0058] In some embodiments, the address comparator 530 can include at least one logic gate. In some embodiments, the address comparator 530 can include a plurality of first XNOR gates 531, a plurality of NAND gates 532, and a NOR gate 533. Each first XNOR gate 531 can include two inputs. The first input can receive a first address signal AXA (e.g., AXA<0>,..., AXA <y-1>), indicating a first row along which the first memory cells (e.g., memory array 120) are arranged. The second input may receive a second address signal AXB (e.g., AXB<0>,..., AXB <y-1>), indicating a second row along which second memory cells (e.g., memory array 120) are arranged. Here, y = 9 is shown as a non-limiting example of an address comparator 530 with 9 bits and n = 512. The first XNOR gate 531 can provide the output of the XNOR operation to a corresponding one of a plurality of NAND gates 532.

[0059] The address comparator 530 can include k ([ Figure 5 where k = 3 is shown as an example) NAND gates 532. In some embodiments, each NAND gate 532 can include l inputs ([ Figure 5 where l = 3 is shown as an example). In some embodiments, the number k of NAND gates 532 can be the number of XNOR gates 531 divided by l, such that each NAND gate 532 can be configured to receive the output from at least one XNOR gate 531 (e.g., the XNOR operation of the first address signal AXA and the second address signal AXB). The NAND gates 532 can provide the output of the NAND operation to the NOR gate 533.

[0060] In some embodiments, the NOR gate 533 can include h inputs ([ Figure 5 where h = 3 is shown as an example). Each input of the NOR gate 533 can receive the output from the NAND gate 532 (e.g., the NAND operation). The NOR gate 533 can provide the output of the NOR operation. As discussed herein, based on at least one logic operation, the address comparator 530 can provide a control signal CR.

[0061] In some embodiments, the control signal CR can include and / or indicate a logic state. For example, when the first row along which the first memory cells are arranged (e.g., indicated by the first address signal AXA) is the same as the second row along which the second memory cells are arranged (e.g., indicated by the second address signal AXB), the logic state of the control signal CR can be "1", and when the first row and the second row are different, the logic state of the control signal CR can be "0", and vice versa.

[0062] Figure 6 A block diagram showing an example circuit according to some embodiments. More specifically, Figure 6 An example address comparator 630 is shown. The address comparator 630 can be substantially similar to the address comparator 330 and / or include features of the address comparator 330. Figure 6 An example address comparator 630 is shown in [ Figure 6 shown or with respect to [ Figure 5 described more, fewer, or different components.

[0063] In some embodiments, the address comparator 630 may include at least one logic gate. In some embodiments, the address comparator 630 may include a plurality of first XOR gates 631 and a plurality of n-type transistors 632. Each first XOR gate 631 may include two inputs. The first input may receive a first address signal AXA (e.g., AXA<0>,..., AXA <y-1>), indicating a first row along which the first memory cells (e.g., memory array 120) are arranged. The second input may receive a second address signal AXB (e.g., AXB<0>,..., AXB <y-1>) that indicates a second row along which second memory cells (e.g., memory array 120) are arranged. Each of the first XOR gates 631 may provide the output of the XOR operation to a corresponding one of the plurality of n-type transistors 632.

[0064] For example, when the first row arranged along the first memory cells (e.g., indicated by the first address signal AXA) is the same as the second row arranged along the second memory cells (e.g., indicated by the second address signal AXB), a corresponding one of the first XOR gates 631 may provide an output having a logic state of "1". A corresponding n-type transistor 632 may receive the output from the corresponding one of the first XOR gates 631 and may conduct. When the first row and the second row are not the same, a corresponding one of the first XOR gates 631 may provide an output having a logic state of "0". A corresponding n-type transistor 632 may receive the output from the corresponding one of the first XOR gates 631 and may be cut off.

[0065] In some embodiments, the address comparator 630 may include an inverter (not shown) configured to invert the logic state of the output of the n-type transistor 632. For example, when a corresponding one of the n-type transistors 632 conducts (e.g., in response to the output of the corresponding one of the XOR gates 631), the address comparator 630 may provide a control signal CR having a logic state of "0". When a corresponding one of the n-type transistors 632 is cut off (e.g., in response to the output of the corresponding one of the XOR gates 631), the address comparator 630 may provide a control signal CR having a logic state of "1".

[0066] In some embodiments, the address comparator 630 may receive an internal clock signal. In some embodiments, the address comparator 630 may include a p-type transistor through which the internal clock signal may be provided. In some embodiments, the address comparator 630 may provide the control signal CR based on the internal clock signal. In some embodiments, the address comparator 630 may selectively provide the control signal CR from one of the XOR gates 631 based on the internal clock signal.

[0067] Figure 7 An example waveform 700 related to a circuit according to some embodiments is shown. In some embodiments, the waveform 700 may be associated with the operation of the memory controller 305. Figure 7 A non-limiting example of the waveform 700 is shown.

[0068] A circuit (e.g., memory controller 305) may operate based on an external clock signal CLK. An address comparator (e.g., address comparator 330) may receive a first address signal AXA and a second address signal AXB. The address comparator may provide a control signal CR based on a comparison between the first address signal AXA<8:0> and the second address signal AXB<8:0>. A timing circuit (e.g., timing circuit 350) may receive a logically inverted clock pulse ICLK and a phase signal PHASE. The timing circuit may provide an output PCB based on a logical operation of the phase signal PHASE and the control signal CR. The timing circuit may provide a precharge signal BLPREB based on a logical operation of the output PCB and the logically inverted clock pulse ICLK. Waveform 700 includes a word line signal WL and bit line signals BL / BLB (e.g., a first memory cell and a second memory cell in a selected column, and an unselected column).

[0069] During period (a), each of the first address signal AXA (e.g., AXA<8:0>) and the second address signal AXB (e.g., AXB<8:0>) may have 9 bits and select the 512th row in the logical state "1". (For example, Figure 7 an example with n = 512 is shown in

[0070] During period (b), when the external clock signal CLK is set, a clock pulse ICLK may be generated. Then, the word line signal WL may be set synchronously with the first address signal AXA and the clock pulse ICLK. The address comparator may compare the first address signal AXA and the second address signal AXB, and then provide a control signal CR with a logical state of "1" because the first row indicated by the first address signal AXA is the same as the second row indicated by the second address signal AXB. Based on the control signal CR, the phase signal PHASE, and the clock pulse ICLK, the timing circuit may provide a precharge signal BLPREB with a logical state of "1", thereby skipping the BL precharge and allowing access to the selected column for write / read operations. For unselected columns, only the word line WL is selected, resulting in a decrease in the BL voltage through a pseudo-read operation.

[0071] During period (c), the clock pulse ICLK is negated. The operation corresponding to the first address signal AXA may end, and the word line WL corresponding to the first address signal AXA may be turned off. Since the output PCB has a logical state of "0", the precharge signal BLPREB has a logical state of "1", the control signal has a logical state of "1", and the phase signal PHASE has a logical state of "1", the precharge of the bit line BL may be skipped during period (c). Since the precharge is skipped, period (c) may be reduced and / or shortened.

[0072] During period (d), when the clock pulse ICLK is made active, the operation for the second address signal AXB can start. The word line signal WL can be set synchronously with the second address signal AXB and the clock pulse ICLK. Since the phase signal PHASE can transition between different logic states when accessing each memory cell of the memory array, the phase signal PHASE has a logic state (e.g., "0") during period (d). The precharge signal BLPREB can be synchronous with the clock pulse ICLK. Since the clock pulse ICLK has a logic state of "1", the precharge signal BLPREB can have a logic state of "1", thereby skipping the precharge. In some embodiments, the voltage of the bit lines BL / BLB can be kept the same as the voltage at the end of period (b). That is, for the selected columns associated with the first address signal AXA, the written data can be retained, and for the unselected columns, the pseudo-read data can be retained.

[0073] In some embodiments, when a read operation is selected for the second address signal AXB, the IO interface (e.g., IO interface 270) can determine the data based on the voltage associated with the second address signal AXB of the selected column. Although a pseudo-read operation is performed using the second address signal AXB of the unselected column, since this operation is performed in the same row as the operation performed for the first address signal AXA, the data from the same cell can also be pseudo-read, so the logical data can remain unchanged.

[0074] In some embodiments, a first memory cell is accessed first based on setting a first clock pulse (e.g., the clock pulse ICLK at (b)), and then a second memory cell is accessed based on setting a second clock pulse (e.g., the clock pulse ICLK at (d)). In some embodiments, the first clock pulse and the second clock pulse can be within one clock cycle (e.g., the clock signal CLK).

[0075] When the clock pulse ICLK is negated during period (e), the operation corresponding to the second address signal AXB can end, and the word line WL corresponding to the second address signal AXB can be turned off. The precharge signal BLPREB can be synchronous with the clock pulse ICLK and can have a logic state of "0", thereby performing a precharge (e.g., for the next cycle). In some embodiments, when the selected row corresponding to the first address signal AXA remains unchanged in the next cycle, the precharge can be skipped.

[0076] Although described for two address signals (e.g., the first address signal AXA and the second address signal AXB), the circuits and their operations disclosed herein are not limited to the number of address signals. For example, the circuits disclosed herein can operate based on any number of multiple address signals.

[0077] In some embodiments, Figure 10B the waveform 1050 of can be used for the first cycle of the clock signal CLK, and Figure 10A the waveform 1000 of can be used for the second cycle after the first cycle. In some embodiments, during the first cycle of the clock signal CLK, in which the first and second memory cells are sequentially accessed, the timing circuit can be configured to generate a precharge signal BLPREB having a first logic state (e.g., "0") before accessing the first memory cell to precharge the bit line BL of the first memory cell before accessing the first memory cell. The timing circuit can be configured to generate a precharge signal BLPREB having a second logic state (e.g., "1") after accessing the first memory cell in response to receiving the logic state of the control signal CR indicating that the first row is the same as the second row to skip precharging the bit line BL of the second memory cell.

[0078] In some embodiments, the first memory cell can be accessed based on the first pulse of the clock pulse ICLK within the first cycle of the clock signal CLK, and the second memory cell can be accessed based on the second pulse of the clock pulse ICLK within the first cycle of the clock signal CLK. In some embodiments, during the first cycle of the clock signal CLK, the timing circuit can be configured to generate a precharge signal BLPREB having a second logic state (e.g., "1") after accessing the second memory cell to skip precharging the bit line BL of the third memory cell again, which is configured to be accessed during the second subsequent cycle of the clock signal CLK in response to receiving the logic state (e.g., "1") of the control signal CR, which indicates that the second row is the same as the third row of the third memory cell.

[0079] Figure 8A A block diagram showing an example circuit 801 according to some embodiments. More specifically, the circuit 801 is an example memory array including a plurality of memory cells (MC), wherein the first row of the first memory cell 811 indicated by the first address signal AXA is different from the second row of the second memory cell 812 indicated by the second address signal AXB, while the first memory cell 811 and the second memory cell 812 are in the same column.

[0080] The word line WLA of the first memory cell 811 is turned on, and the data of the first memory cell 811 connected to the word line WLA is connected to the bit lines BL / BLB. The data connected to the word line WLA can be on the bit lines BL / BLB. According to the second address signal AXB, the word line WLB is turned on, and the data of the second memory cell 812 connected to the word line WLB is connected to the bit lines BL / BLB. Due to the word line WLA turned on by the first address signal AXA, the accessed memory cells are different. Therefore, the second memory cell 812 connected to the second address signal AXB with data opposite to that of the first address signal AXA is accessed. At this time, if pre-charging is not performed, turning on the word line WLB with opposite data on the bit lines BL / BLB may cause the inverted data to be written into the second memory cell 812, resulting in a failure of the circuit 801. Therefore, when the first row of the first memory cell 811 indicated by the first address signal AXA is different from the second row of the second memory cell 812 indicated by the second address signal AXB, pre-charging can be performed without skipping.

[0081] Figure 8B A block diagram showing an example circuit 802 according to some embodiments. More specifically, the circuit 802 is an example memory array including a plurality of memory cells (MC), wherein the first row of the first memory cell 821 indicated by the first address signal AXA is different from the second row of the second memory cell 822 indicated by the second address signal AXB, and the first memory cell 821 and the second memory cell 822 are in different columns.

[0082] The word line WLA of the first memory cell 821 is turned on, and the data of the first memory cell 821 connected to the word line WLA is connected to the bit lines BLA / BLBA. The data connected to the word line WLA can be on the bit lines BLA / BLBA. Based on the second address signal AXB, the word line WLB is turned on, and the data of the second memory cell 822 connected to the word line WLB is connected to the bit lines BLB / BLBB. Due to the word line WLA turned on by the first address signal AXA, the accessed memory cells are different. Therefore, the second memory cell 822 connected to the second address signal AXB with data opposite to that of the first address signal AXA is accessed. At this time, if pre-charging is not performed, turning on the word line WLB with opposite data on the bit lines BLB / BLBB may cause the inverted data to be written into the second memory cell 822, resulting in a failure of the circuit 802. Therefore, when the first row of the first memory cell 821 indicated by the first address signal AXA is different from the second row of the second memory cell 822 indicated by the second address signal AXB, pre-charging can be performed without skipping.

[0083] Figure 9A Block diagram showing an example circuit 901 according to some embodiments. More specifically, circuit 901 is an example memory array including a plurality of memory cells (MC), wherein a first row of a first memory cell 911 indicated by a first address signal AXA is the same as a second row of a second memory cell 912 indicated by a second address signal AXB, and the first memory cell 911 and the second memory cell 912 are in different columns.

[0084] The word line WLA of the first memory cell 911 is turned on, and data of the first memory cell 911 connected to the word line WLA is connected to bit lines BLA / BLBA. The data connected to the word line WLA can be on the bit lines BLA / BLBA. Based on the second address signal AXB, the word line WLB (the same as the word line WLA) is turned on, and data of the second memory cell 912 connected to the word line WLB is connected to the bit lines BLB / BLBB. Since the first memory cell 911 and the second memory cell 912 are in the same row and the word line WLA and the word line WLB are the same, the data on the BL / BLB of the first address signal AXA and the data on the BL / BLB of the second address signal AXB can be the same, which can prevent failures caused by miswriting data, and thus allows precharge to be skipped.

[0085] Figure 9B Block diagram showing an example circuit 902 according to some embodiments. More specifically, circuit 902 is an example memory array including a plurality of memory cells (MC), wherein a first row of a first memory cell 921 indicated by a first address signal AXA is the same as a second row of a second memory cell 922 indicated by a second address signal AXB, and the first memory cell 921 and the second memory cell 922 are in the same column. Here, the first memory cell 921 and the second memory cell 922 are the same, but are represented by different numbers respectively to clarify that the first memory cell 921 is indicated by the first address signal AXA and the second memory cell 922 is indicated by the second address signal AXB.

[0086] The word line WLA of the first memory cell 921 is turned on, and the data of the first memory cell 921 connected to the word line WLA is connected to the bit lines BLA / BLBA. The data connected to the word line WLA can be on the bit lines BLA / BLBA. Based on the second address signal AXB, the word line WLB (the same as the word line WLA) is turned on, and the data of the second memory cell 922 connected to the word line WLB is connected to the bit lines BLB / BLBB (the same as the bit lines BLA / BLBA). Since the first memory cell 921 and the second memory cell 922 are in the same row, and the word line WLA and the word line WLB are the same, the data on the BLA / BLBA of the first address signal AXA can be the same as the data on the BLB / BLBB of the second address signal AXB, which can prevent malfunctions caused by miswriting data, and thus allows skipping the precharge.

[0087] Figure 10A FIG. 1000 shows an example waveform related to a circuit according to some embodiments. In some embodiments, the waveform 1000 may be related to the operations of the memory controller 305, the circuit 901, the circuit 902, etc. Figure 10A FIG. shows a non-limiting example of the waveform 1000. In some embodiments, the waveform 1000 may be substantially similar to the waveform 700 or include features of the waveform 700.

[0088] In some embodiments, a circuit (e.g., the memory controller 305) may operate based on an external clock signal CLK. An address comparator (e.g., the address comparator 330) may receive a first address signal AXA and a second address signal AXB. The address comparator may provide a control signal CR based on a comparison between the first address signal AXA<8:0> and the second address signal AXB<8:0>. A timing circuit (e.g., the timing circuit 350) may receive a logic inverted clock pulse ICLK and a phase signal PHASE. The timing circuit may provide an output PCB according to a logical operation of the phase signal PHASE and the control signal CR. The timing circuit may provide a precharge signal BLPREB according to a logical operation of the output PCB and the logic inverted clock pulse ICLK. The waveform 1000 includes a word line signal WL and bit line signals BL / BLB (e.g., the first memory cell and the second memory cell in a selected column, and unselected columns).

[0089] In some embodiments, when the rows of the first memory cell (e.g., the first memory cell 911, the first memory cell 921, etc.) indicated by the first address signal AXA are the same as the rows of the second memory cell (e.g., the second memory cell 912, the second memory cell 922, etc.) indicated by the second address signal AXB, the precharge may be skipped during the period (c1). Since the precharge can be skipped, the period (c1) can be reduced and / or shortened.

[0090] Figure 10B Shows an example waveform 1050 related to a circuit according to some embodiments. In some embodiments, the waveform 1050 may be related to the operations of a memory controller 305, a circuit 801, a circuit 802, etc. Figure 10B A non-limiting example of the waveform 1050 is shown.

[0091] A circuit (e.g., the memory controller 305) may operate based on an external clock signal CLK. An address comparator (e.g., the address comparator 330) may receive a first address signal AXA and a second address signal AXB. The address comparator may provide a control signal CR based on a comparison between the first address signal AXA<8:0> and the second address signal AXB<8:0>. A timing circuit (e.g., the timing circuit 350) may receive a logically inverted clock pulse ICLK and a phase signal PHASE. The timing circuit may provide an output PCB according to a logical operation of the phase signal PHASE and the control signal CR. The timing circuit may provide a precharge signal BLPREB according to a logical operation of the output PCB and the logically inverted clock pulse ICLK. The waveform 1050 includes a word line signal WL and a bit line signal BL / BLB (e.g., a first memory cell and a second memory cell in a selected column, and an unselected column).

[0092] In some embodiments, when the row of a first memory cell (e.g., the first memory cell 811, the first memory cell 821, etc.) indicated by the first address signal AXA is different from the row of a second memory cell (e.g., the second memory cell 812, the second memory cell 822, etc.) indicated by the second address signal AXB, precharging may be performed in a period (c2). Due to the precharging, in some embodiments, Figure 10A the period (c1) of Figure 10B may be shorter than

[0093] Figure 11A Shows a block diagram of an example circuit according to some embodiments. More specifically, Figure 11A shows an example memory controller 1105. The memory controller 1105 may be substantially similar to the memory controller 305 and / or include the features of the memory controller 305. The memory controller 1105 may include an address comparator 1130 and a timing circuit 1150, which may be substantially similar to the address comparator 330 and the timing circuit 350 respectively and / or include the features of the address comparator 330 and the timing circuit 350. In some embodiments, the memory controller 1105 may include a latch 1140. Figure 11A A non-limiting example of the memory controller 1105 is shown. In some embodiments, the memory controller 1105 may include more than Figure 11A More, fewer, or different components as shown or described therein.

[0094] Latch 1140 is operatively coupled between address comparator 1130 and timing circuit 1150. Latch 1140 can latch control signal CR from address comparator 1130. In some embodiments, latch 1140 can be configured to receive control signal CR as an input and latch control signal CR. In some embodiments, latch 1140 can be configured to provide an output to timing circuit 1150. In some embodiments, latch 1140 can be configured to receive external clock signal CLK.

[0095] Figure 11B A block diagram showing an example circuit according to some embodiments. More specifically, Figure 11B Latch 1140A is shown, which is an example of latch 1140. Latch 1140A can include transistors, inverters, etc. to latch control signal CR from address comparator 1130. Figure 11B A non - limiting example of latch 1140 is shown. In some embodiments, latch 1140 can include more, fewer, or different components than Figure 11B shown therein or relative to Figure 11B described therein.

[0096] Figure 12 A block diagram showing an example circuit according to some embodiments. More specifically, Figure 12 Example memory controller 1205 is shown therein. Memory controller 1205 can be substantially similar to memory controller 1105 and / or include features of memory controller 105. Memory controller 1205 can include address comparator 1230, latch circuit 1240, and timing circuit 1250, which can be substantially similar to address comparator 1130, latch 1140, and timing circuit 1150 and / or include features of address comparator 1130, latch 1140, and timing circuit 1150. In some embodiments, memory controller 1205 can include more, fewer, or different components than Figure 12 shown or described therein.

[0097] Address comparator 1230 can be configured to provide control signal CR. When the first row of the first memory cell indicated by the first address signal AXA is the same as the second row of the second memory cell indicated by the second address signal AXB, control signal CR can be set to a first logic state (e.g., "1"). When the first row of the first memory cell indicated by the first address signal AXA is different from the second row of the second memory cell indicated by the second address signal AXB, control signal CR can be set to a second logic state (e.g., "0").

[0098] The first phase signal PHASE can be provided to the latch circuit 1240 and the timing circuit 1250. The phase signal PHASE can be set to a first logic state (e.g., "1") during the first precharge and to a second logic state (e.g., "0") during the second precharge. The second phase signal PHASE2 can be the inverted signal of the first phase signal PHASE. The second phase signal can be set to the second logic state (e.g., "0") during the first precharge and can be set to the first logic state (e.g., "1") during the second precharge.

[0099] In some embodiments, the first latch 1341 can be configured to hold the control signal CR during the first period when the first phase signal has the first logic state (e.g., "1"). For example, the first latch 1341 can be configured to hold the control signal CR during the first precharge of the first period. In some embodiments, the second latch 1342 can be configured to hold the control signal CR provided based on the comparison of the first address signal of the second period and the second address signal of the first period when the second phase signal PHASE2 has the first logic state (e.g., "1"). For example, the second latch 1342 can be configured to hold the control signal CR during the second precharge.

[0100] In some embodiments, any signal that can be set to the first logic state (e.g., "1") during the first precharge can be used as the first phase signal PHASE. In some embodiments, any signal that can be set to the first logic state (e.g., "1") during the second precharge can be used as the second phase signal PHASE2.

[0101] In some embodiments, when the first phase signal PHASE is set to the first logic state (e.g., "1") and the output signal PCB can be the first inverted signal ICR1, the output of the first NAND gate 1251 in the timing circuit 1250 can be set to the first logic state (e.g., "1") to skip the first precharge. In some embodiments, the first latch 1241 can be configured to latch the control signal CR as the first inverted signal ICR1 through the first phase signal PHASE. In some embodiments, when the second phase signal PHASE2 is set to the first logic state (e.g., "1") and the output signal PCB can be the second inverted signal ICR2, the output of the second NAND gate 1252 in the timing circuit 1250 can be set to the first logic state (e.g., "1") to skip the second precharge. In some embodiments, the second latch 1242 can be configured to latch the control signal CR as the second inverted signal ICR2 through the second phase signal PHASE2.

[0102] Figure 13 FIG. 1300 shows an example waveform related to a circuit according to some embodiments. In some embodiments, waveform 1300 may be associated with the operation of memory controller 305, memory controller 1105, etc. Figure 13 FIG. 1300 shows a non-limiting example of the waveform.

[0103] A circuit (e.g., memory controller 305) may operate based on an external clock signal CLK. An address comparator (e.g., address comparator 330) may receive a first address signal AXA and a second address signal AXB. The address comparator may provide a control signal CR based on a comparison between the first address signal AXA<8:0> and the second address signal AXB<8:0>. A timing circuit (e.g., timing circuit 350) may receive a logic inverted clock pulse ICLK and a phase signal PHASE. An output PCB may be provided based on a logical operation of the phase signal PHASE and the control signal CR. The timing circuit may provide a precharge signal BLPREB according to a logical operation of the output PCB and the logic inverted clock pulse ICLK. Waveform 1300 includes a word line signal WL and bit line signals BL / BLB (e.g., a first memory cell and a second memory cell in a selected column, and unselected columns).

[0104] In some embodiments, a second control signal CR2 may be used to control precharging. When the first address signal AXA and the second address signal AXB indicate the same row, the second control signal CR2 may be provided to identify that the first address signal AXA and the second address signal AXB indicate the same row. The second control signal CR2 may indicate that the first address signal AXA and the second address signal AXB indicate the same row before a second precharge of the memory cells during a first period (Period 1).

[0105] In some embodiments, a second phase signal PHASE2 may be used to control precharging. The second phase signal PHASE2 may be provided during a first period (Period 1) to specify a second precharge during the first period (Period 1). During the second precharge, the precharge control signal BLPREB may be set to a first logic state (e.g., "1") to skip the second precharge.

[0106] Figure 14 FIG. 1400 shows an example waveform related to a circuit according to some embodiments. In some embodiments, waveform 1400 may be related to the operation of memory controller 305, memory controller 1105, memory controller 1205, etc. Figure 14 FIG. 1400 shows a non-limiting example of the waveform.

[0107] An address comparator (e.g., address comparator 1230) can be configured to provide a control signal CR. When the first row of the first memory cell indicated by the first address signal AXA is the same as the second row of the second memory cell indicated by the second address signal AXB, the control signal CR can be set to a first logic state (e.g., "1"). When the first row of the first memory cell indicated by the first address signal AXA is different from the second row of the second memory cell indicated by the second address signal AXB, the control signal CR can be set to a second logic state (e.g., "0").

[0108] A first phase signal PHASE can be provided to a latch circuit (e.g., latch 1140) and a timing circuit (e.g., timing circuit 1150). The phase signal PHASE can be set to a first logic state (e.g., "1") during a first precharge and set to a second logic state (e.g., "0") during a second precharge. A second phase signal PHASE2 can be an inverted signal of the first phase signal PHASE. The second phase signal PHASE2 can be set to the second logic state (e.g., "0") during the first precharge and can be set to the first logic state (e.g., "1") during the second precharge.

[0109] In some embodiments, a first latch (e.g., first latch 1341) can be configured to hold the control signal CR during a first period (period 1) when the first phase signal has the first logic state (e.g., "1"). For example, the first latch can be configured to hold the control signal CR during the first precharge of the first period (period 1). In some embodiments, a second latch (e.g., second latch 1342) can be configured to hold the control signal CR provided based on a comparison between the first address signal AXA of a second period (period 2) and the second address signal AXB of the first period (period 1) when the second phase signal PHASE2 has the first logic state (e.g., "1"). For example, the second latch can be configured to hold the control signal CR during the second precharge.

[0110] In some embodiments, any signal that can be set to the first logic state (e.g., "1") during the first precharge can be used as the first phase signal PHASE. In some embodiments, any signal that can be set to the first logic state (e.g., "1") during the second precharge can be used as the second phase signal PHASE2.

[0111] In some embodiments, when the first phase signal PHASE is set to a first logic state (e.g., "1"), and the output signal PCB can be the first inverted signal ICR1, the output of the first NAND gate in the timing circuit can be set to the first logic state (e.g., "1") to skip the first precharge. In some embodiments, the first latch can be configured to latch the control signal CR as the first inverted signal ICR1 via the first phase signal PHASE. In some embodiments, when the second phase signal PHASE2 is set to the first logic state (e.g., "1"), and the output signal PCB can be the second inverted signal ICR2, the output of the second NAND gate in the timing circuit can be set to the first logic state (e.g., "1") to skip the second precharge. In some embodiments, the second latch can be configured to latch the control signal CR as the second inverted signal ICR2 via the second phase signal PHASE2.

[0112] In some embodiments, the first latch and the second latch can have different latch clock signals. For example, the first latch can have the first phase signal PHASE as a clock, while the second latch can have the second phase signal PHASE as a clock. In some embodiments, after changing the first address signal AXA of the second period (period 2), the second inverted signal ICR2 can be a latch control signal.

[0113] Figure 15 A block diagram showing an example circuit according to some embodiments. More specifically, Figure 15 The circuit shown is a memory controller 1505 operably coupled to the example memory circuit 1520. The memory circuit 1520 can be substantially similar to and / or incorporate features of the memory array 120. Figure 15 A non-limiting example of the circuit is shown. In some embodiments, the circuit can include more, fewer, or different components than Figure 15 shown or described with respect to Figure 15 the description.

[0114] The memory controller 1505 can generate a precharge signal BLPREB to control the BL precharge circuit of the memory circuit 1520. In some embodiments, the memory controller 1505 can receive a clock pulse ICLK, a phase signal PHASE, a write enable signal WEB, an address signal AYB, etc. Based on the reception of at least the address signal AYB, the memory controller 1505 can generate a precharge signal BLPREB to control the BL precharge circuit of the memory circuit 1520, as discussed in detail below. In some embodiments, the precharge signal BLPREB can include multiple bits (e.g., BLPREB<0>,..., BLPREB <m-1>), each bit corresponding to a logical state. Multiple bits in the precharge signal BLPREB (e.g., BLPREB<0>,..., BLPREB <m-1>) can be configured to control the corresponding columns (e.g., column<0>,..., column <m-1>) corresponding precharge circuit.

[0115] Figure 16 A block diagram showing an example circuit according to some embodiments. More specifically, Figure 16 an example memory controller 1605 is shown. The memory controller 1605 may be substantially similar to and / or incorporate the features of the memory controller 105, the memory controller 305, the memory controller 1505, etc. The memory controller 1605 may include a column decoder 1630 and a timing circuit 1650, which may be substantially similar to and / or incorporate the features of the column decoder and the timing circuit described with respect to Figure 1 the column decoder and the timing circuit described. Figure 16 A non-limiting example of the memory controller 1605 is shown. In some embodiments, the memory controller 1605 may include more, fewer, or different components than Figure 16 shown or described.

[0116] The column decoder 1630 may be configured to receive an address signal AYB. The address signal AXA may partially indicate the column address of the memory cell. In some embodiments, the column decoder 1630 may be configured to decode the address signal AYB. Based on the decoding result, the column decoder 1630 may be configured to generate a control signal BY. The control signal BY may include the decoding result. In some embodiments, the control signal BY may include the result of exponentiation. For example, when the address signal AYB includes 3 bits (e.g., AYB<2:0>), the control signal BY may include the decoding result, which includes the result of exponentiation (e.g., 2 3 ).

[0117] The decoder 1630 may be configured to provide the control signal BY to the timing circuit 1650. The timing circuit 1650 may be configured to receive a clock pulse ICLK, a phase signal PHASE, a write enable signal WEB, and the control signal BY. Based on at least the reception of the control signal BY, the timing circuit 1650 may provide a precharge signal BLPREB. The precharge signal BLPREB may be configured to skip the precharge of the bit line BL of the memory cell based on the logical state of the control signal BY after accessing the first memory cell. In some embodiments, the precharge signal BLPREB may include a plurality of logical bits, each logical bit corresponding to a corresponding logical state (e.g., BLPREB<0>,..., BLPREB <m-1>)。In some embodiments, when the write enable signal WEB includes a first logic state (e.g., "1"), one of the control signals BY can be set to the first logic state (e.g., "1"), and one of the precharge signals BLPREB can be set to the first logic state (e.g., "1"), thereby stopping the BL precharge of the selected column corresponding to the address signal AYB.

[0118] Figure 17 A block diagram showing an example circuit according to some embodiments. More specifically, Figure 17 An example timing circuit 1750 is shown. Figure 17 A non-limiting example of the timing circuit 1750 is shown. In some embodiments, the timing circuit 1750 may include more, fewer, or different components than Figure 17 shown or described with respect to Figure 17 described.

[0119] In some embodiments, the timing circuit 1750 may include at least one logic gate. In some embodiments, the timing circuit 1750 may include a plurality of first NAND gates 1705, a plurality of NOR gates 1710, a plurality of inverters 1715, and a plurality of second NAND gates 1720 (plurality 8 is shown as a non-limiting example).

[0120] In some embodiments, the plurality of first NAND gates 1705 may be configured to receive the control signal BY and the write enable signal WEB. Based on the control signal BY and the write enable signal WEB, the plurality of first NAND gates 1705 may be configured to provide the output of a NAND operation to the corresponding gate among the plurality of NOR gates 1710. In some embodiments, the plurality of NOR gates 1710 may be configured to receive the output from the plurality of first NAND gates 1705 and the phase signal PHASE. The plurality of NOR gates 1710 may be configured to provide the output of a NOR operation to the corresponding gate among the plurality of second NAND gates 1720 through the corresponding inverters 1715. In some embodiments, the plurality of second NAND gates 1720 may be configured to receive the output from the plurality of NOR gates 1710. The plurality of second NAND gates 1720 may be configured to provide the control signal BLPREB as an output.

[0121] In some embodiments, the timing circuit 1750 may be configured to control the precharging of the bit lines BL of the memory array. In some embodiments, the precharge signal BLPREB may be configured to precharge the bit lines BL of the memory array (e.g., memory array 120). For example, the precharge signal BLPREB may cause a BL precharge circuit (e.g., BL precharge circuit 1525) to precharge the bit lines BL of the memory array. In some embodiments, the precharge signal BLPREB may be configured to perform a precharge operation. For example, the precharge signal BLPREB may cause a BL precharge circuit (e.g., BL precharge circuit 1525) to skip the precharging of the bit lines BL of the memory array. In some embodiments, the timing circuit 1750 may be configured to skip the precharging of the bit lines BL based on an operation (e.g., read or write). For example, the timing circuit 1750 may be configured to skip the precharging of the bit lines BL of a second memory cell (e.g., second memory cell 1722) after accessing a first memory cell (e.g., first memory cell 1721) based on an indication of a write operation (e.g., the logic state "1" in the write enable signal WEB).

[0122] Figure 18 A block diagram showing an example circuit in accordance with some embodiments. More specifically, Figure 18 An example timing circuit 1850 is shown therein. Figure 18 A non-limiting example of the timing circuit 1850 is shown therein. In some embodiments, the timing circuit 1850 may include more, fewer, or different components than Figure 18 shown therein or described with respect to Figure 18 more, fewer, or different components.

[0123] In some embodiments, the timing circuit 1850 may include an inverter 1805, a first OR gate 1810, a first AND gate 1815, a second OR gate 1820, and a plurality of second AND gates 1825. In some embodiments, the first OR gate 1810 may receive a write enable signal WEB and a phase signal PHASE through the inverter 1805. The OR gate 1810 may provide an output of an OR operation to the first AND gate 1815. In some embodiments, the first AND gate 1815 may be configured to receive the output from the first OR gate 1810 and the phase signal PHASE. The first AND gate 1815 may be configured to provide an output of an AND operation to the second OR gate 1820. In some embodiments, the second OR gate 1820 may be configured to receive the output from the first AND gate 1815 and a clock pulse ICLK. The second OR gate 1820 may be configured to provide an output PC of an AND operation to the plurality of second AND gates 1820. In some embodiments, the plurality of second AND gates 1825 may be configured to receive the output PC from the second OR gate 1820 and a control signal BY. The plurality of second AND gates 1825 may be configured to provide a precharge signal BLPREB based on the output PC and the control signal BY.

[0124] In some embodiments, the timing circuit 1850 may be configured to control the precharging of the bit lines BL of the memory array. In some embodiments, the precharge signal BLPREB may be configured to precharge the bit lines BL of the memory array (e.g., memory array 120). For example, the precharge signal BLPREB may cause a BL precharge circuit (e.g., BL precharge circuit 1525) to precharge the bit lines BL of the memory array. In some embodiments, the precharge signal BLPREB may be configured for a precharge operation. For example, the precharge signal BLPREB may cause a BL precharge circuit (e.g., BL precharge circuit 1525) to skip the precharging of the bit lines BL of the memory array. In some embodiments, the timing circuit 1850 may be configured to skip the precharging of the bit lines BL based on an operation (e.g., read or write). For example, the timing circuit 1850 may be configured to skip the precharging of the bit lines BL of a second memory cell (e.g., second memory cell 1822) after accessing a first memory cell (e.g., first memory cell 1821) based on an indication of a write operation (e.g., a logical state "1" in the write enable signal WEB).

[0125] Figure 19 An example waveform 1900 related to a circuit according to some embodiments is shown. In some embodiments, the waveform 1900 may be associated with the operation of a memory controller 1505, a memory controller 1605, etc. Figure 19 A non-limiting example of the waveform 1900 is shown.

[0126] A circuit (e.g., memory controller 1605) may operate based on an external clock signal CLK. A column decoder (e.g., column decoder 1630) may receive an address signal AYB. In some embodiments, the address signal AYB may include an address signal for a selected column and an address signal for an unselected column. The column decoder may provide a control signal BY based on a decoding result of the address signal AYB. In some embodiments, the column decoder may provide a control signal BY<7> corresponding to the selected column and may provide a control signal BY<6:0> corresponding to the unselected column. A timing circuit (e.g., timing circuit 1650) may receive a logically inverted clock pulse ICLK, a phase signal PHASE, and a write enable signal WEB. In some embodiments, the write enable signal WEB may include a first signal for the selected column and may include a second signal for the unselected column. The timing circuit may provide an output PCB based on a logical operation of the phase signal PHASE, the clock pulse ICLK, and the write enable signal WEB. The timing circuit may provide a precharge signal BLPREB based on a logical operation of the output PCB and the address signal AYB. Waveform 1900 includes a word line signal WL and a bit line signal BL / BLB.

[0127] In period (a), the address signal AYB has 3 bits, each having a first logic state "1", which may indicate that column <7> is selected.

[0128] In period (b), when the external clock signal CLK is set, a clock pulse ICLK is generated and a first operation may start. According to the row address indicated in the address signal AYB, the word line WL corresponding to the first operation may be synchronized with the clock pulse ICLK <n>Set. The precharge signal BLPREB can be set to a first logic state (e.g., "1") synchronously with the clock pulse ICLK. This can stop the BL precharge and the selected column can be accessed for a read operation. For unselected columns, the bitline voltage can drop during a pseudo-read operation. The column decoder can decode the address signal AYB to set the control signal BY<7> to the first logic state (e.g., "1") for the selected column and set the control signals BY<6:0> to the second logic state (e.g., "0") for unselected columns.

[0129] In period (c), the clock pulse ICLK is negated. The output PCB<7> of the selected column has a logic state of "0", and the precharge signal BLPREB<7> of the selected column can have a logic state of "1", thus skipping the precharge of the bitlines of the selected column. The outputs PCB<6:0> of the unselected columns have a logic state of "1", and the precharge signals BLPREB<6:0> of the unselected columns can have a logic state of "1", thus performing the precharge of the bitlines of the unselected columns.

[0130] In period (d), the clock pulse ICLK is set again and the second operation can start. According to the row address indicated in the address signal AYB, the wordline WL corresponding to the second operation can be enabled synchronously with the clock pulse ICLK SET. In some embodiments, the first operation and the second operation may select the same row or different rows. The bit line BL of the selected column may hold the voltage at the end of the first operation because the precharge during the first operation is skipped. Since the write enable signal WEB is set to "1", a write operation can be performed in the second operation. Therefore, the logical state of the bit line BL at the end of the first operation and the data of the accessed memory cell of the selected column <7> can be different without causing problems because the data can be overwritten. For the unselected columns during the second operation, a dummy read operation can be performed, so a dummy write state may occur if the accessed memory cell is different between the first operation and the second operation, and the memory cell data can be overwritten. This does not allow skipping the precharge of the unselected columns.

[0131] In period (e), the clock pulse ICLK is negated again, and the second operation ends, and the word line WL Turn off. The precharge signal BLPREB can be set to a logic state (e.g., "0") synchronized with the clock pulse ICLK, and a second precharge can be performed to prepare for the next cycle. If the next operation is a write operation, the second precharge for the selected columns in the next cycle can be skipped.

[0132] Figure 20 An example waveform 2000 related to a circuit according to some embodiments is shown. In some embodiments, the waveform 2000 can be associated with the operations of the memory controller 1505, the memory controller 1605, etc. Figure 20 A non-limiting example of the waveform 2000 is shown.

[0133] In some embodiments, as shown, precharge can be skipped during two or more consecutive cycles. The waveform 2000 includes a first cycle (Cycle 1) and a second cycle (Cycle 2), during which precharge can be performed. For example, when the next cycle (Cycle 2) is a write operation, precharge can be performed subsequently. In some embodiments, the decoder can receive the address signal AY<4> before the second precharge in the first cycle (Cycle 1). In some embodiments, the second phase signal PHASE2 can be used to indicate the second precharge during the first cycle. In some embodiments, at the second precharge in the first cycle, the output PCA<4> can be set to a logic state (e.g., "0"), thereby holding the precharge signal BLPREB<4> in the first logic state "1". Therefore, during the second precharge in the first cycle, the precharge of the bit lines BL / BLB<4> can be skipped.

[0134] Figure 21 A block diagram showing an example circuit and related waveforms according to some embodiments is shown. More specifically, Figure 21 An example six-transistor (6T) static random access memory (SRAM) cell 2100 and a related timing diagram 2150 are shown. Figure 21 A non-limiting example is shown, and the 6T SRAM 2100 can include more, fewer, or different components than Figure 21 shown in or regarding Figure 21 described.

[0135] In some embodiments, the memory cells of the memory array disclosed herein can include 6T SRAM 2100. For example, the circuits and operations discussed regarding Figures 1 to 20 can include the 6T SRAM 2100 and its operations.

[0136] In some embodiments, the 6T SRAM 2100 can include a first port (Port-A) and a second port (Port-B). Refer to Figure 21 , the operations associated with the first port A are referred to as "_A", and the operations associated with the first port B are referred to as "_B".

[0137] In some embodiments, the 6T SRAM 2100 can be operated with a single clock signal CLK. For example, the operations of the first port Port-A and the second port Port-B can be sequentially executed within a single clock signal CLK. In some embodiments, the 6T SRAM 2100 can be included within or operatively coupled to a packaging circuit 2102 configured to switch operations between the first port Port-A and the second port Port-B. In some embodiments, when the clock signal CLK is set to a first logic state (e.g., "1"), two clock pulses ICLK can be generated for the first port Port-A and the second port Port-B.

[0138] In some embodiments, during the stage of the first port Port-A, inputs can be input into the 6T SRAM 2100 through the first port Port-A (e.g., input A from input A_A and input D from input D_A). During the stage of the second port Port-B, inputs can be input into the 6T SRAM 2100 through the second port Port-B (e.g., input A from input A_B and input D from input D_B). In some embodiments, the 6T SRAM 2100 can perform various operations, including RR, RW, WR, and WW operations (where "R" represents "read" and "W" represents "write").

[0139] Figure 22 A flowchart of a method 2200 for operating a memory system according to some embodiments is shown. It should be noted that the method 2200 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that additional, fewer, or different operations can be performed Figure 22 in the method 2200. Here, only additional operations and some other operations provided before, during, and after the method 2200 are briefly described. In some embodiments, the method 2200 is executed by a circuit (e.g., the memory controller 105, the memory controller 305, etc.). Figure 22

[0140] ​Brief overview, method 2200 may begin with operation 2210 of precharging the bitline of a first memory cell. Method 2200 may proceed to operation 2220 of comparing a first address signal and a second address signal to generate a control signal, where the first address signal indicates a first row of the first memory cell, the second address signal indicates a second row of a second different memory cell, and the control signal has a logic state indicating that the first row is the same as the second row. Method 2200 may proceed to operation 2230 of generating a precharge signal having a logic state that stops precharging the bitline of the first memory cell. Method 2200 may proceed to operation 2240 of accessing the first memory cell for a read or write operation in response to a first clock pulse of a clock signal being set. Method 2200 may proceed to operation 2250 of skipping precharging the bitline of a second memory cell in response to recognizing the logic state of the control signal. Method 2200 may proceed to operation 2260 of accessing the second memory cell for a read or write operation in response to a second clock pulse of the clock signal being set.

[0141] Method 2200 may begin with operation 2210, which precharges the bitline of a first memory cell. Method 2200 may proceed to operation 2220 of comparing a first address signal and a second address signal to generate a control signal, where the first address signal indicates a first row of the first memory cell, the second address signal indicates a second row of a second different memory cell, and the control signal has a logic state indicating that the first row is the same as the second row. An address comparator (e.g., address comparator 330) may compare the first address signal (e.g., first address signal AXA) and the second address signal (e.g., second address signal AXB) to generate a control signal (e.g., control signal CR). The control signal may have a first logic state (e.g., 1), indicating that the first row is the same as the second row.

[0142] Method 2200 may continue to operation 2230, which generates a precharge signal having a logic state that stops precharging the bitline of the first memory cell (e.g., first memory cell 221). A timing circuit (e.g., timing circuit 350) may be configured to generate a precharge signal (e.g., precharge signal BLPREB) to stop precharging the bitline of the first memory cell.

[0143] Method 2200 may proceed to operation 2240, in response to a first clock pulse of a clock signal being set, to access a first memory cell for a read or write operation. Method 2200 may proceed to operation 2250, in response to identifying a logical state of a control signal, to skip precharging a bit line of a second memory cell (e.g., second memory cell 222). Method 2200 may proceed to operation 2260, in response to a second clock pulse of the clock signal being set, to access the second memory cell for a read or write operation.

[0144] Figure 23 FIG. shows a flowchart of a method 2300 of operating a memory system according to some embodiments. It should be noted that method 2300 is merely an example and is not intended to limit the present disclosure. Thus, it should be understood that additional, fewer, or different operations may be performed in Figure 23 method 2300 of, and additional operations and some other operations provided before, during, and after method 2300 of are briefly described herein only. In some embodiments, method 2300 is performed by a circuit (e.g., memory controller 105, memory controller 1605, etc.). Figure 23 Briefly summarized, method 2300 may begin with operation 2310 of precharging a bit line of a first memory cell. Method 2300 may proceed to operation 2320 to decode an address signal to generate a control signal, where the address signal indicates a row of the first memory cell and the control signal has a logical state indicating a write operation is to be performed on the address signal. Method 2300 may proceed to operation 2330 to generate a precharge signal having a logical state that stops precharging the bit line of the first memory cell. Method 2300 may proceed to operation 2340, in response to a first clock pulse of a clock signal being set, to access the first memory cell for a read or write operation. Method 2300 may proceed to operation 2350, in response to identifying a logical state of the control signal, to skip precharging the bit line of a second memory cell. Method 2300 may proceed to operation 2360 to access the second memory cell for a write operation.

[0145]

[0146] ​Method 2300 may begin with operation 2310, i.e., precharging the bit line of the first memory cell (e.g., the first memory cell 221). Method 2300 may proceed to operation 2320, decoding an address signal (e.g., the address signal AYB) to generate a control signal (e.g., the control signal BY), where the address signal indicates the row of the first memory cell, and the control signal has a logical state indicating a write operation is to be performed on the address signal. A column decoder (e.g., the column decoder 1630) may decode the address signal to generate the control signal. Column decoding may provide a decoding result, including bit data indicating whether a write operation is to be performed on the address signal.

[0147] Method 2300 may proceed to operation 2330, generating a precharge signal (e.g., the precharge signal BLPREB) having a logical state to stop precharging the bit line of the first memory cell. A timing circuit (e.g., the timing circuit 1650) may be configured to generate the precharge signal. Method 2300 may proceed to operation 2340, accessing the first memory cell for a read or write operation in response to the first clock pulse of the clock signal being set. Method 2300 may proceed to operation 2350, skipping precharging the bit line of the second memory cell in response to recognizing the logical state of the control signal. Method 2300 may proceed to operation 2360, accessing the second memory cell for a write operation.

[0148] One aspect of this specification relates to a memory circuit. The memory circuit includes: a memory array including a plurality of memory cells, where each of the plurality of memory cells may be accessed via a plurality of bit lines; a comparator configured to receive a first address signal indicating a first row along which a first memory cell is arranged and a second address signal indicating a second row along which a second memory cell is arranged, and generate a control signal having a logical state indicating whether the first row is the same as the second row; a timing circuit configured to, based on the logical state of the control signal, skip precharging the bit line of the second memory cell after accessing the first memory cell. In some embodiments, the first memory cell is accessed first based on setting a first clock pulse, and then the second memory cell is accessed based on setting a second clock pulse.

[0149] In some embodiments, the first clock pulse and the second clock pulse are within one clock cycle.

[0150] In some embodiments, the comparator includes: a plurality of first XNOR gates each having 2 inputs, a plurality of NAND gates each having 3 inputs, and a second NOR gate having 3 inputs.

[0151] In some embodiments, the comparator includes a plurality of XOR gates each having 2 inputs, an inverter, and a plurality of n-type transistors.

[0152] In some embodiments, the timing circuit includes a first NAND gate and a second NAND gate.

[0153] In some embodiments, the first NAND gate is configured to receive the control signal and the phase signal to provide an output, and the second NAND gate is configured to receive the output and a logically inverted clock pulse to provide a precharge signal, the precharge signal being configured to precharge the bit lines of the memory array.

[0154] In some embodiments, when accessing the respective memory cells of the memory array, the phase signal transitions between different logical states.

[0155] In some embodiments, the memory circuit further includes a latch operatively coupled between the comparator and the timing circuit.

[0156] In some embodiments, each of the memory cells includes a six-transistor static random access memory (SRAM) cell.

[0157] One aspect of the present specification relates to a memory circuit. The memory circuit includes: a comparator configured to compare a first address signal with a second address signal to generate a control signal, wherein the first address signal partially indicates a first row of a first memory cell, the second address signal partially indicates a second row of a second memory cell, and the control signal has a logical state indicating whether the first row is the same as the second row; and a timing circuit configured to, based on the logical state of the control signal, skip precharging the bit lines of the second memory cell after accessing the first memory cell.

[0158] In some embodiments, during a first cycle of a clock signal for sequentially accessing the first memory cell and the second memory cell, the timing circuit is configured to: before accessing the first memory cell, generate a precharge signal having a first logical state to precharge the bit lines of the first memory cell before accessing the first memory cell; after accessing the first memory cell, in response to receiving the logical state of the control signal indicating that the first row is the same as the second row, generate a precharge signal having a second logical state to skip precharging the bit lines of the second memory cell.

[0159] In some embodiments, the first memory cell is accessed based on a first clock pulse within the first cycle of the clock signal, and the second memory cell is accessed based on a second clock pulse within the first cycle of the clock signal.

[0160] In some embodiments, during a first cycle of the clock signal, the timing circuit is configured to: after accessing the second memory cell, in response to receiving a logical state of a control signal indicating that a second row is the same as a third row of a third memory cell, generate a precharge signal having the second logical state to skip precharging of the bit lines of the third memory cell again, the third memory cell being configured to be accessed during a second subsequent cycle of the clock signal.

[0161] In some embodiments, the comparator includes: a plurality of first XNOR gates each having 2 inputs, a plurality of NAND gates each having 3 inputs, and a second NOR gate having 3 inputs.

[0162] In some embodiments, the comparator includes a plurality of XOR gates each having 2 inputs, an inverter, and a plurality of n-type transistors.

[0163] In some embodiments, the memory circuit further includes a latch operatively coupled between the comparator and the timing circuit.

[0164] In some embodiments, the timing circuit includes a first NAND gate configured to receive the control signal and provide an output, and a second NAND gate configured to receive the output and provide a precharge signal. One aspect of the present specification relates to a method of operating a memory circuit. The method includes: precharging bit lines of a first memory cell; comparing a first address signal and a second address signal to generate a control signal, wherein the first address signal indicates a first row of a first memory cell, the second address signal indicates a second row of a second different memory cell, and wherein the control signal has a logical state indicating that the first row is the same as the second row; generating a precharge signal having a logical state to stop precharging the bit lines of the first memory cell; accessing the first memory cell for a read or write operation in response to a first clock pulse of the clock signal being set; skipping precharging of the bit lines of the second memory cell in response to identifying the logical state of the control signal; and accessing the second memory cell for a read or write operation in response to a second clock pulse of the clock signal being set.

[0165] In some embodiments, the first memory cell includes a six-transistor static random access memory (SRAM) cell.

[0166] The components of several embodiments are described above, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that it is easy to use the present invention as a basis to design or modify other processes and structures to achieve the same purpose and / or realize the same advantages as the embodiments introduced in the present invention. Those skilled in the art should also realize that these equivalent structures do not depart from the spirit and scope of the present invention, and various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present invention. < / n>

Claims

1. A memory circuit, comprising: A memory array including a plurality of memory cells, wherein each of the plurality of memory cells is accessible via a plurality of bit lines; A comparator configured to receive a first address signal indicating a first row along which a first memory cell is arranged and a second address signal indicating a second row along which a second memory cell is arranged, and generate a control signal having a logical state indicating whether the first row is the same as the second row; A timing circuit configured to skip precharging the bit lines of the second memory cell after accessing the first memory cell based on the logical state of the control signal.

2. The memory circuit according to claim 1, wherein, The first memory cell is accessed first based on setting a first clock pulse, and then the second memory cell is accessed based on setting a second clock pulse.

3. The memory circuit according to claim 2, wherein, The first clock pulse and the second clock pulse are within one clock cycle.

4. The memory circuit according to claim 1, wherein, The comparator includes: a plurality of first XNOR gates each having 2 inputs, a plurality of NAND gates each having 3 inputs, and a second NOR gate having 3 inputs.

5. A memory circuit, comprising: A comparator configured to compare a first address signal with a second address signal to generate a control signal, wherein the first address signal partially indicates a first row of a first memory cell, the second address signal partially indicates a second row of a second memory cell, and wherein the control signal has a logical state indicating whether the first row is the same as the second row; and A timing circuit configured to skip precharging the bit lines of the second memory cell after accessing the first memory cell based on the logical state of the control signal.

6. The memory circuit according to claim 5, wherein, During a first period of a clock signal for sequentially accessing the first memory cell and the second memory cell, the timing circuit is configured to: Before accessing the first memory cell, generate a precharge signal having a first logical state to precharge the bit lines of the first memory cell before accessing the first memory cell; After accessing the first memory cell, in response to receiving the logical state of the control signal indicating that the first row is the same as the second row, generate a precharge signal having a second logical state to skip precharging the bit lines of the second memory cell.

7. The memory circuit according to claim 6, wherein, The first memory cell is accessed based on a first clock pulse within the first period of the clock signal, and the second memory cell is accessed based on a second clock pulse within the first period of the clock signal.

8. The memory circuit according to claim 6, wherein, During the first period of the clock signal, the timing circuit is configured to: After accessing the second memory cell, in response to receiving the logical state of the control signal indicating that the second row is the same as a third row of a third memory cell, generate a precharge signal having the second logical state to skip precharging the bit lines of the third memory cell again, the third memory cell being configured to be accessed during a second subsequent period of the clock signal.

9. A method for operating a memory circuit, comprising: Precharging the bit lines of a first memory cell; Compare a first address signal and a second address signal to generate a control signal, wherein the first address signal indicates a first row of the first memory cell, the second address signal indicates a second row of a second different memory cell, and wherein the control signal has a logic state indicating that the first row is the same as the second row; Generate a precharge signal having a logic state that stops precharging the bit lines of the first memory cell; In response to a first clock pulse of a clock signal being set, access the first memory cell for a read or write operation; In response to identifying the logic state of the control signal, skip precharging the bit lines of the second memory cell; and In response to a second clock pulse of the clock signal being set, access the second memory cell for a read or write operation.

10. The method according to claim 9, wherein, The first memory cell includes a six-transistor static random access memory (SRAM) cell.

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