Method for improving doping uniformity of semiconductor

Abstract

The invention provides a method for improving the doping uniformity of a semiconductor, and the method comprises the steps: forming a drift layer at one side of a substrate layer in a first direction, and the drift layer comprises a plurality of chip regions; an epitaxial layer is formed on the side, away from the substrate layer, of the chip region of the drift layer, the epitaxial layer, the drift layer and the substrate layer form a basic wafer, and the doping concentration of the epitaxial layer is smaller than the concentration of the drift layer; performing ion implantation on the epitaxial layer to enable at least part of the epitaxial layer to form a semiconductor layer; the ion implantation comprises a first implantation step, so that the semiconductor layer comprises a first doped region; the first injection step comprises first daughter ion injection and / or second daughter ion injection; the injection direction of the first daughter ion injection is along the first crystal orientation of the epitaxial layer, and the injection direction of the second daughter ion injection is along the second crystal orientation of the epitaxial layer; the first crystal orientation is the crystal orientation with the highest linear arrangement density of atoms in the epitaxial layer; the linear arrangement density of the atoms in the epitaxial layer along the second crystal orientation is 40%-70% of the linear arrangement density of the atoms in the epitaxial layer along the first crystal orientation.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a method for improving the doping uniformity of a semiconductor. Background Art

[0002] In semiconductor processes, it is often necessary to form a semiconductor layer with a relatively high doping concentration. For example, in semiconductor power devices, in order to improve the current-carrying capacity and conduction characteristics of the device, it is usually necessary to form a current spreading layer with excellent conductive characteristics above the drift layer. The traditional process mainly forms this current spreading layer by epitaxial growth technology on the side of the drift layer facing away from the substrate layer. Specifically, after the epitaxial growth of the drift layer is completed, by adjusting the process parameters of the reaction chamber (such as temperature, pressure, gas source flow ratio, etc.), a semiconductor layer with a relatively high doping concentration is continuously epitaxially grown on the surface of the drift layer as the current spreading layer.

[0003] However, this conventional epitaxial growth method has obvious technical limitations: First, due to the limitations of gas-phase mass transfer effects and surface reaction kinetics during the epitaxial growth process, the doping concentration distribution in the longitudinal and transverse directions of the growth layer is uneven, especially more significant on large-sized wafers; Second, the segregation effect of dopants during the epitaxial growth process will further exacerbate the non-uniformity of the doping distribution; In addition, the transition region at the epitaxial growth interface will also introduce an additional concentration gradient. These factors together result in doping concentration fluctuations in the semiconductor layer formed by the traditional epitaxial method on a macroscopic scale. When the semiconductor layer is a current spreading layer, it seriously affects the current spreading uniformity and the consistency of the on-resistance of the device, reducing the chip yield. Summary of the Invention

[0004] The technical problem to be solved by the present invention is how to improve the doping concentration uniformity of the semiconductor layer.

[0005] To solve the above technical problems, the present invention provides a method for improving the doping uniformity of a semiconductor, including: forming a drift layer on one side of a substrate layer along a first direction, the drift layer including a plurality of chip regions; forming an epitaxial layer on a side of the chip regions of the drift layer facing away from the substrate layer, the epitaxial layer, the drift layer, and the substrate layer forming a basic wafer, the doping concentration of the epitaxial layer being less than that of the drift layer; and performing ion implantation on the epitaxial layer to form at least a part of the epitaxial layer into a semiconductor layer; wherein the ion implantation includes a first implantation step, such that the semiconductor layer includes a first doping region, the distance from the surface of the side of the first doping region facing away from the drift layer to the drift layer being less than the distance from the surface of the side of the epitaxial layer facing away from the drift layer to the drift layer; the first implantation step includes a first sub-ion implantation and / or a second sub-ion implantation; wherein the implantation direction of the first sub-ion implantation is along a first crystal direction of the epitaxial layer, and the implantation direction of the second sub-ion implantation is along a second crystal direction of the epitaxial layer; the first crystal direction is the crystal direction with the highest linear atomic arrangement density in the epitaxial layer; the linear atomic arrangement density of the atoms in the epitaxial layer along the second crystal direction is 40% - 70% of the linear atomic arrangement density of the atoms in the epitaxial layer along the first crystal direction.

[0006] Optionally, the material of the epitaxial layer is 4H-SiC, the first crystal direction is <0001>, and the second crystal direction is <11-23>.

[0007] Optionally, the epitaxial layer on the side of the first doping region facing away from the drift layer forms a second doping region in the semiconductor layer, and the doping concentration of the second doping region is less than that of the first doping region.

[0008] Optionally, the ion implantation further includes: after performing the first implantation step, performing a second implantation step such that the semiconductor layer includes a second doping region, the second doping region is located on the side of the first doping region facing away from the drift layer and is connected to the first doping region, and the distance from the surface of the side of the second doping region facing away from the drift layer to the drift layer is equal to the distance from the surface of the side of the epitaxial layer facing away from the drift layer to the drift layer.

[0009] Optionally, the thickness of the second doping region along the first direction is less than the thickness of the first doping region along the first direction.

[0010] Optionally, the implantation energy of the second implantation step is less than or equal to the implantation energy of the first implantation step.

[0011] Optionally, the implantation dose of the second implantation step is less than or equal to the implantation dose of the first implantation step.

[0012] Optionally, the injection direction of the second injection step is vertical injection.

[0013] Optionally, it further includes: during the process of performing the first injection step, the first injection step also forms an additional semiconductor layer in the area of the drift layer close to the semiconductor layer, the doping concentration of the additional semiconductor layer is greater than that of the semiconductor layer, and the thickness of the additional semiconductor layer in the first direction is less than the thickness of the semiconductor layer in the first direction.

[0014] Optionally, the thickness of the additional semiconductor layer in the first direction is 0.5 micrometers - 2 micrometers.

[0015] Optionally, the thickness of the semiconductor layer in the first direction is 1 micrometer - 4 micrometers.

[0016] Optionally, for the base wafer, the first injection step is a full-surface injection, and the first doping region is a full-surface structure.

[0017] Optionally, for the epitaxial layer on each chip region of the base wafer, the first injection step is a masked ion injection.

[0018] Optionally, on each chip region, the semiconductor layers are multiple and are arranged at intervals, and the epitaxial layer between adjacent semiconductor layers on each chip region is a JFET region.

[0019] Optionally, it further includes: repeating the steps of forming the drift layer to the steps of forming the semiconductor layer so that the drift layer and the semiconductor layer are alternately arranged in the first direction.

[0020] Optionally, in the first sub-ion injection, the barrier height of the incident ions is blocked by the atoms arranged along the first crystal direction in the epitaxial layer; in the second sub-ion injection, the barrier height of the incident ions is blocked by the atoms arranged along the second crystal direction in the epitaxial layer; wherein, the barrier height in the second sub-ion injection is 35% - 65% of the barrier height in the first sub-ion injection.

[0021] The technical solution of the present invention has the following technical effects:

[0022] The method for improving the doping uniformity of a semiconductor provided by the technical solution of the present invention forms an epitaxial layer on the side of the chip region of the drift layer facing away from the substrate layer. The epitaxial layer, the drift layer, and the substrate layer form a basic wafer. The doping concentration of the epitaxial layer is less than that of the drift layer, and the difference in the doping concentration of the epitaxial layer with a low doping concentration on different chip regions has a small impact on the performance between devices. Ion implantation is performed on the epitaxial layer so that at least a part of the epitaxial layer forms a semiconductor layer. The ion implantation includes a first implantation step, so that the semiconductor layer includes a first doping region, and the surface of the first doping region facing away from the drift layer is spaced from the surface of the semiconductor layer facing away from the drift layer. The first implantation step includes a first sub-ion implantation and / or a second sub-ion implantation. Since the implantation direction of the first sub-ion implantation is along the first crystal direction of the epitaxial layer, and the implantation direction of the second sub-ion implantation is along the second crystal direction of the epitaxial layer, the first sub-ion implantation and the second sub-ion implantation can be implanted through the voids inside the lattice of the epitaxial layer, and the scattering of the ion implantation is small. While reducing the implantation energy, the implantation depth can be increased, and the implantation damage is reduced, so that the thickness of the first doping region in the first direction is larger. The difference in the doping concentration of the epitaxial layer with a low doping concentration on different chip regions has a small impact on the performance between devices, and since the ion implantation performed on the epitaxial layer can avoid the influence of uneven temperature during epitaxial growth, the concentration uniformity of the semiconductor layer is improved. Description of the Drawings

[0023] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0024] Figure 1 It is a schematic diagram of the preparation process of a semiconductor doping in the related art;

[0025] Figure 2 It is a flowchart of the method for improving the doping uniformity of a semiconductor in an embodiment of the present application;

[0026] Figures 3 to 4 It is a schematic structural diagram of the method for improving the doping uniformity of a semiconductor in an embodiment of the present application;

[0027] Figures 5 to 7 It is a schematic structural diagram of the method for improving the doping uniformity of a semiconductor in another embodiment of the present application;

[0028] Figures 8 to 10 It is a schematic structural diagram of the method for improving the doping uniformity of a semiconductor in another embodiment of the present application;

[0029] Figures 11 to 13 It is a schematic structural diagram of a method for improving semiconductor doping uniformity in another embodiment of the present application;

[0030] Figures 14 to 16 It is a schematic structural diagram of a method for improving semiconductor doping uniformity in another embodiment of the present application;

[0031] Figures 17 to 18 It is a schematic structural diagram of a method for improving semiconductor doping uniformity in another embodiment of the present application. Detailed implementation manners

[0032] A preparation method for semiconductor doping in related technologies, referring to Figure 1 , includes: forming a drift layer 110 on one side of a substrate layer 100, the drift layer 110 having a plurality of spaced chip areas; the drift layer and the substrate layer constitute a basic wafer; using an epitaxial growth process to form a semiconductor layer 120 on the surface of the drift layer 110 facing away from the substrate layer 100. The doping concentration of the semiconductor layer 120 is greater than that of the drift layer 110.

[0033] Since the semiconductor layer 120 has a certain thickness, it is difficult to form a semiconductor layer 120 with a large thickness by using a conventional ion implantation process. Therefore, in the above method, an epitaxial growth process is used to form a semiconductor layer 120 with a large thickness.

[0034] In the above method, due to the limitations of the gas-phase mass transfer effect and surface reaction kinetics during the epitaxial growth process, the doping concentration distribution in the longitudinal and transverse directions of the growth layer is uneven, especially more significant on large-size wafers; secondly, the segregation effect of dopants during the epitaxial growth process will further exacerbate the non-uniformity of the doping distribution; in addition, the transition region at the epitaxial growth interface will also introduce an additional concentration gradient. These factors together result in fluctuations in the doping concentration of the semiconductor layer 120 formed by the traditional epitaxial method in different chip areas, and there is a large difference in the doping concentration of the semiconductor layer 120 between the central region and the edge region of the basic wafer.

[0035] On this basis, the present application provides a method for improving semiconductor doping uniformity, which improves the uniformity of the doping concentration of the semiconductor layer.

[0036] Next, the technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts fall within the scope of protection of the present invention.

[0037] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0038] In the description of the present invention, it should be noted that unless otherwise clearly specified and defined, the terms "mounted", "connected", "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, and can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0039] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0040] An embodiment of the present application provides a method for improving the doping uniformity of a semiconductor. Referring to Figure 2 , it includes:

[0041] S1: Form a drift layer on one side of the substrate layer along a first direction, and the drift layer includes a plurality of chip regions;

[0042] S2: Form an epitaxial layer on the side of the chip region of the drift layer facing away from the substrate layer. The epitaxial layer, the drift layer, and the substrate layer form a basic wafer. The doping concentration of the epitaxial layer is less than that of the drift layer; and

[0043] S3: Perform ion implantation on the epitaxial layer so that at least part of the epitaxial layer forms a semiconductor layer;

[0044] Wherein, the ion implantation includes a first implantation step, so that the semiconductor layer includes a first doping region, and the distance from the surface of the side of the first doping region facing away from the drift layer to the drift layer is less than the distance from the surface of the side of the epitaxial layer facing away from the drift layer to the drift layer; the first implantation step includes a first sub-ion implantation and / or a second sub-ion implantation;

[0045] Among them, the implantation direction of the first sub-ion implantation is along the first crystal orientation of the epitaxial layer, and the implantation direction of the second sub-ion implantation is along the second crystal orientation of the epitaxial layer; the first crystal orientation is the crystal orientation with the highest linear atomic arrangement density in the epitaxial layer; the linear atomic arrangement density of the atoms in the epitaxial layer along the second crystal orientation is 40%-70% of the linear atomic arrangement density of the atoms in the epitaxial layer along the first crystal orientation.

[0046] In this embodiment, an epitaxial layer is formed on the side of the chip region of the drift layer facing away from the substrate layer. The epitaxial layer, the drift layer, and the substrate layer form a basic wafer. The doping concentration of the epitaxial layer is less than that of the drift layer. The difference in the doping concentration of the low-doping-concentration epitaxial layers on different chip regions has little effect on the performance between devices. Ion implantation is performed on the epitaxial layer so that at least part of the epitaxial layer forms a semiconductor layer. The ion implantation includes a first implantation step, which makes the semiconductor layer include a first doping region, and the surface of the first doping region facing away from the drift layer is spaced from the surface of the semiconductor layer facing away from the drift layer; the first implantation step includes a first sub-ion implantation and / or a second sub-ion implantation. Since the implantation direction of the first sub-ion implantation is along the first crystal orientation of the epitaxial layer and the implantation direction of the second sub-ion implantation is along the second crystal orientation of the epitaxial layer, the first sub-ion implantation and the second sub-ion implantation can be implanted through the voids inside the lattice of the epitaxial layer. The scattering of the ion implantation is small. While reducing the implantation energy, the implantation depth can be increased, the implantation damage is reduced, and the thickness of the first doping region in the first direction is larger. The difference in the doping concentration of the low-doping-concentration epitaxial layers on different chip regions has little effect on the performance between devices, and since the ion implantation performed on the epitaxial layer can avoid the influence of uneven temperature during epitaxial growth, the concentration uniformity of the semiconductor layer is improved.

[0047] In this embodiment, the method for improving the semiconductor doping uniformity is used to form a semiconductor power device, such as a SiC-based semiconductor power device. The SiC-based semiconductor power device is, for example, a SiC-based MOSFET. The method for improving the semiconductor doping uniformity can also form other semiconductor devices.

[0048] Next, refer to Figures 3 to 4 to describe the method for improving the semiconductor doping uniformity.

[0049] Refer to Figure 3 , a drift layer 210 is formed on one side of the substrate layer 200 along the first direction. The drift layer 210 includes a plurality of chip regions; an epitaxial layer 220 is formed on the side of the chip region of the drift layer 210 facing away from the substrate layer 200. The epitaxial layer 220, the drift layer 210, and the substrate layer 200 form a basic wafer, and the doping concentration of the epitaxial layer 220 is less than that of the drift layer 210.

[0050] In some embodiments, the drift layer 210 further includes a dicing street area located between adjacent chip areas.

[0051] In some embodiments, the concentration of the drift layer 210 is 5E15 atom / cm 3 ~5E16 atom / cm 3 .

[0052] In some embodiments, the doping concentration of the epitaxial layer 220 is 1E13 atom / cm 3 -3E15 atom / cm 3 .

[0053] In some embodiments, the conductivity type of the epitaxial layer 220 is the same as that of the drift layer 210. In other embodiments, the conductivity type of the epitaxial layer 220 is opposite to that of the drift layer 210.

[0054] Since the doping concentration of the epitaxial layer 220 is less than that of the drift layer 210, the difference in the doping concentration of the epitaxial layer 220 with a low doping concentration on different chip areas has a small impact on the performance between devices.

[0055] In one embodiment, the material of the epitaxial layer 220 is SiC. In other embodiments, the material of the epitaxial layer can also be other materials.

[0056] Refer to Figure 4 , ion implantation is performed on the epitaxial layer 220 so that at least a part of the epitaxial layer 220 forms a semiconductor layer A; wherein, the ion implantation includes a first implantation step, so that the semiconductor layer A includes a first doping region A1, and the distance from the surface of the first doping region A1 facing away from the drift layer 210 to the drift layer 210 is less than the distance from the surface of the epitaxial layer 220 facing away from the drift layer 210 to the drift layer 210; the first implantation step includes a first sub-ion implantation and / or a second sub-ion implantation; wherein, the implantation direction of the first sub-ion implantation is along the first crystal direction of the epitaxial layer 220, and the implantation direction of the second sub-ion implantation is along the second crystal direction of the epitaxial layer 220.

[0057] The first crystal direction is the crystal direction with the highest linear atomic arrangement density in the epitaxial layer 220; the linear atomic arrangement density of the atoms in the epitaxial layer 220 along the second crystal direction is 40% - 70% of the linear atomic arrangement density of the atoms in the epitaxial layer 220 along the first crystal direction.

[0058] In one embodiment, the material of the epitaxial layer 220 is 4H - SiC, the first crystal direction is <0001>, and the second crystal direction is <11 - 23>.

[0059] In this embodiment, the implantation depth of the first implantation step is relatively deep, and few incident ions stop on the surface of the epitaxial layer 220. Therefore, the distance from the surface of one side of the first doped region facing away from the drift layer 210 to the drift layer 210 is less than the distance from the surface of one side of the epitaxial layer 220 facing away from the drift layer 210 to the drift layer 210. The epitaxial layer 220 on the side of the first doped region A1 facing away from the drift layer 210 forms the second doped region A2 in the semiconductor layer A, and the doping concentration of the second doped region A2 is less than that of the first doped region A1. The second doped region A2 is in contact with the first doped region A1.

[0060] In one embodiment, the doping concentration of the first doped region A1 is 2E16 atom / cm 3 -6E16 atom / cm 3 .

[0061] The thickness of the second doped region A2 in the first direction is less than the thickness of the first doped region A1 in the first direction.

[0062] In one embodiment, the thickness of the first doped region A1 in the first direction is 0.6 um - 4 um; the thickness of the second doped region A2 in the first direction is less than 0.6 um.

[0063] In one embodiment, for the base wafer, the first implantation step is a full-surface implantation, the first doped region is a full-surface structure, and correspondingly, the second doped region is a full-surface structure.

[0064] In one embodiment, the implantation energy of the first sub-ion implantation is 300 keV - 900 keV. The implantation energy of the second sub-ion implantation is 300 keV - 900 keV.

[0065] In one embodiment, the thickness of the semiconductor layer A is 1 micron - 4 microns, such as 1 micron, 2 microns, 3 microns or 4 microns.

[0066] In one embodiment, in the first sub-ion implantation, the height of the blocking potential barrier of the incident ions by the atoms arranged along the first crystal direction in the epitaxial layer; in the second sub-ion implantation, the height of the blocking potential barrier of the incident ions by the atoms arranged along the second crystal direction in the epitaxial layer; wherein, the height of the blocking potential barrier in the second sub-ion implantation is 35% - 65% of the height of the blocking potential barrier in the first sub-ion implantation.

[0067] The included angle between the second crystal direction and the first crystal direction is greater than zero.

[0068] In one embodiment, the method for improving semiconductor doping uniformity further includes: forming a well region in the semiconductor layer, where a channel region is provided in the well region. Exemplarily, the well region is formed in the first doping region and the second doping region. Since the doping concentration of the second doping region is relatively small, the well region with the opposite conduction type formed in the second doping region has a stable ion distribution. Therefore, the ion distribution in the channel region located in the second doping region is relatively stable, and thus the threshold voltage of the semiconductor power device is relatively stable.

[0069] In one embodiment, the semiconductor layer A is a current spreading layer.

[0070] In this embodiment, it further includes: cutting along the scribe lane region to form a plurality of discrete chips.

[0071] Figures 5 to 7 It is a schematic diagram of the method for improving semiconductor doping uniformity in another embodiment of the present application.

[0072] Referring to Figure 5 , a drift layer 210 is formed on one side of the substrate layer 200 along the first direction, and the drift layer 210 includes a plurality of chip regions; an epitaxial layer 220 is formed on the side of the chip region of the drift layer 210 away from the substrate layer 200. The epitaxial layer 220, the drift layer 210, and the substrate layer 200 form a basic wafer. The doping concentration of the epitaxial layer 220 is less than that of the drift layer 210.

[0073] In some embodiments, the drift layer 210 further includes a scribe lane region located between adjacent chip regions.

[0074] In some embodiments, the concentration of the drift layer 210 is 5E15 atom / cm 3 ~5E16 atom / cm 3 .

[0075] In some embodiments, the doping concentration of the epitaxial layer 220 is 1E13 atom / cm 3 -3E15 atom / cm 3 .

[0076] In some embodiments, the conduction type of the epitaxial layer 220 is the same as that of the drift layer 210. In other embodiments, the conduction type of the epitaxial layer 220 is opposite to that of the drift layer 210.

[0077] In one embodiment, the material of the epitaxial layer 220 is SiC. In other embodiments, the material of the epitaxial layer can also be other materials.

[0078] Referring to Figure 6 and Figure 7, ion implantation is performed on the epitaxial layer 220 to form a semiconductor layer A in at least a part of the epitaxial layer 220.

[0079] Among them, the ion implantation includes a first implantation step, so that the semiconductor layer A includes a first doped region A1 (refer to Figure 6 ), the distance from the surface of the first doped region A1 facing away from the drift layer 210 to the drift layer 210 is less than the distance from the surface of the epitaxial layer 220 facing away from the drift layer 210 to the drift layer 210; the first implantation step includes a first sub-ion implantation and / or a second sub-ion implantation; among them, the implantation direction of the first sub-ion implantation is along the first crystal orientation of the epitaxial layer 220, and the implantation direction of the second sub-ion implantation is along the second crystal orientation of the epitaxial layer 220.

[0080] The first crystal orientation is the crystal orientation with the highest linear atomic arrangement density in the epitaxial layer 220; the linear atomic arrangement density of the atoms in the epitaxial layer 220 along the second crystal orientation is 40% - 70% of the linear atomic arrangement density of the atoms in the epitaxial layer 220 along the first crystal orientation.

[0081] In one embodiment, the material of the epitaxial layer 220 is 4H - SiC, the first crystal orientation is <0001>, and the second crystal orientation is <11 - 23>.

[0082] In one embodiment, the doping concentration of the first doped region A1 is 2E16atom / cm 3 -6E16atom / cm 3 .

[0083] In one embodiment, the implantation energy of the first sub-ion implantation is 300keV - 900keV. The implantation energy of the second sub-ion implantation is 300keV - 900keV.

[0084] In one embodiment, in the first sub-ion implantation, the barrier height of the incident ions blocked by the atoms arranged along the first crystal orientation in the epitaxial layer; in the second sub-ion implantation, the barrier height of the incident ions blocked by the atoms arranged along the second crystal orientation in the epitaxial layer; among them, the barrier height in the second sub-ion implantation is 35% - 65% of the barrier height in the first sub-ion implantation.

[0085] The angle between the second crystal orientation and the first crystal orientation is greater than zero.

[0086] Among them, the ion implantation further includes: after performing the first implantation step, performing a second implantation step so that the semiconductor layer A includes a second doped region A2 (refer to Figure 7) The second doping region A2 is located on a side of the first doping region A1 away from the drift layer 210 and is connected to the first doping region A1. The distance between the surface of the second doping region A2 away from the drift layer 210 and the drift layer 210 is equal to the distance between the surface of the epitaxial layer 220 away from the drift layer 210 and the drift layer 210.

[0087] The thickness of the second doping region A1 in the first direction is less than the thickness of the first doping region A1 in the first direction.

[0088] In one embodiment, the thickness of the first doping region A1 in the first direction is 0.6 um - 4 um; the thickness of the second doping region A2 in the first direction is less than 0.6 um. In one embodiment, the doping concentration of the second doping region A1 is 2E16 atom / cm 3 - 6E16 atom / cm 3 .

[0089] The implantation energy of the second implantation step is less than or equal to the implantation energy of the first implantation step.

[0090] The implantation dose of the second implantation step is less than or equal to the implantation dose of the first implantation step.

[0091] The implantation direction of the second implantation step is vertical implantation. The implantation direction of the second implantation step is perpendicular to the surface of the substrate layer 200.

[0092] In one embodiment, for the base wafer, the first implantation step is a full - surface implantation, the first doping region is a full - surface structure, correspondingly, the second implantation step is a full - surface implantation, and the second doping region is a full - surface structure.

[0093] In one embodiment, the thickness of the semiconductor layer A is 1 micron - 4 microns, such as 1 micron, 2 microns, 3 microns, or 4 microns.

[0094] In one embodiment, the method for manufacturing the semiconductor power device further includes: forming a well region in the semiconductor layer A, and a channel region is provided in the well region. Exemplarily, a well region is formed in the first doping region A1 and the second doping region A2.

[0095] In one embodiment, the semiconductor layer A is a current spreading layer.

[0096] In this embodiment, it further includes: cutting along the dicing - lane region to form a plurality of discrete chips.

[0097] Figures 8 to 10 It is a schematic diagram of a method for improving semiconductor doping uniformity in another embodiment of the present application.

[0098] ReferenceFigure 8 On one side of the substrate layer 200 along the first direction, a drift layer 210 is formed, and the drift layer 210 includes a plurality of chip regions; on a side of the chip regions of the drift layer 210 facing away from the substrate layer 200, an epitaxial layer 220 is formed. The epitaxial layer 220, the drift layer 210, and the substrate layer 200 form a basic wafer. The doping concentration of the epitaxial layer 220 is less than that of the drift layer 210.

[0099] In some embodiments, the drift layer 210 further includes a dicing channel region located between adjacent chip regions.

[0100] In some embodiments, the concentration of the drift layer 210 is 5E15 atom / cm 3 ~5E16 atom / cm 3 .

[0101] In some embodiments, the doping concentration of the epitaxial layer 220 is 1E13 atom / cm 3 -3E15 atom / cm 3 .

[0102] In some embodiments, the conductivity type of the epitaxial layer 220 is the same as that of the drift layer 210. In other embodiments, the conductivity type of the epitaxial layer 220 is opposite to that of the drift layer 210.

[0103] In one embodiment, the material of the epitaxial layer 220 is SiC. In other embodiments, the material of the epitaxial layer can also be other materials.

[0104] Reference Figures 9 to 10 , ion implantation is performed on the epitaxial layer 220 so that at least a part of the epitaxial layer 220 forms a semiconductor layer A.

[0105] Among them, the ion implantation includes a first implantation step, so that the semiconductor layer A includes a first doping region A1 (reference Figure 9 ), and the distance from the surface of the first doping region A1 facing away from the drift layer 210 to the drift layer 210 is less than the distance from the surface of the epitaxial layer 220 facing away from the drift layer 210 to the drift layer 210; the first implantation step includes a first sub-ion implantation and / or a second sub-ion implantation; among them, the implantation direction of the first sub-ion implantation is along the first crystal direction of the epitaxial layer 220, and the implantation direction of the second sub-ion implantation is along the second crystal direction of the epitaxial layer 220.

[0106] The first crystal direction is the crystal direction with the highest linear atomic arrangement density in the epitaxial layer 220; the linear atomic arrangement density of the atoms in the epitaxial layer 220 along the second crystal direction is 40% - 70% of the linear atomic arrangement density of the atoms in the epitaxial layer 220 along the first crystal direction.

[0107] In one embodiment, the material of the epitaxial layer 220 is 4H-SiC, the first crystal orientation is <0001>, and the second crystal orientation is <11-23>.

[0108] In one embodiment, the doping concentration of the first doped region A1 is 2E16 atom / cm 3 -6E16 atom / cm 3 .

[0109] In one embodiment, the implantation energy of the first sub-ion implantation is 300 keV - 900 keV. The implantation energy of the second sub-ion implantation is 300 keV - 900 keV.

[0110] In one embodiment, in the first sub-ion implantation, the barrier height of the incident ions is blocked by the atoms arranged along the first crystal orientation in the epitaxial layer; in the second sub-ion implantation, the barrier height of the incident ions is blocked by the atoms arranged along the second crystal orientation in the epitaxial layer; wherein, the barrier height in the second sub-ion implantation is 35% - 65% of the barrier height in the first sub-ion implantation.

[0111] The included angle between the second crystal orientation and the first crystal orientation is greater than zero.

[0112] In this embodiment, during the process of performing the first implantation step, the first implantation step further forms an additional semiconductor layer B in the region of the drift layer 210 close to the semiconductor layer A. The doping concentration of the additional semiconductor layer B is greater than that of the semiconductor layer A, and the thickness of the additional semiconductor layer B along the first direction is less than the thickness of the semiconductor layer A along the first direction. The conduction type of the ions implanted in the first implantation step is the same as that of the drift layer.

[0113] In one embodiment, the thickness of the additional semiconductor layer is 0.5 micrometers - 2 micrometers, such as 0.5 micrometers, 1 micrometer, 1.5 micrometers or 2 micrometers.

[0114] Among them, the ion implantation further includes: after performing the first implantation step, performing a second implantation step to make the semiconductor layer A include a second doped region A2 (refer to Figure 10 ), the second doped region A2 is located on the side of the first doped region A1 away from the drift layer 210 and is connected to the first doped region A1. The distance from the surface of the side of the second doped region A2 away from the drift layer 210 to the drift layer 210 is equal to the distance from the surface of the side of the epitaxial layer 220 away from the drift layer 210 to the drift layer 210.

[0115] The thickness of the second doped region A1 in the first direction is less than the thickness of the first doped region A1 in the first direction.

[0116] In one embodiment, the thickness of the first doped region A1 in the first direction is 0.6 um - 4 um; the thickness of the second doped region A2 in the first direction is less than 0.6 um.

[0117] In one embodiment, the doping concentration of the second doped region A1 is 2E16 atom / cm 3 -6E16 atom / cm 3 .

[0118] The implantation energy of the second implantation step is less than or equal to the implantation energy of the first implantation step.

[0119] The implantation dose of the second implantation step is less than or equal to the implantation dose of the first implantation step.

[0120] The implantation direction of the second implantation step is vertical implantation. The description of the second implantation step refers to the foregoing embodiments.

[0121] In one embodiment, for the base wafer, the first implantation step is a full-surface implantation, the first doped region is a full-surface structure, correspondingly, the second implantation step is a full-surface implantation, and the second doped region is a full-surface structure.

[0122] In one embodiment, the thickness of the semiconductor layer A is 1 micron - 4 microns, such as 1 micron, 2 microns, 3 microns or 4 microns.

[0123] In one embodiment, a well region is formed in the semiconductor layer A, and a channel region is provided in the well region. Exemplarily, a well region is formed in the first doped region A1 and the second doped region A2.

[0124] In one embodiment, the semiconductor layer A is a current spreading layer.

[0125] In this embodiment, it further includes: cutting along the scribe lane region to form a plurality of discrete chips.

[0126] Figures 11 to 13 It is a schematic diagram of a method for improving semiconductor doping uniformity in another embodiment of the present application.

[0127] Reference Figure 11 , a drift layer 210 is formed on one side of the substrate layer 200 in the first direction, the drift layer 210 includes a plurality of chip regions; an epitaxial layer 220 is formed on the side of the chip region of the drift layer 210 facing away from the substrate layer 200, the epitaxial layer 220, the drift layer 210 and the substrate layer 200 form a base wafer, and the doping concentration of the epitaxial layer 220 is less than the concentration of the drift layer 210.

[0128] In some embodiments, the drift layer 210 further includes a dicing channel region located between adjacent chip regions.

[0129] In some embodiments, the concentration of the drift layer 210 is 5E15 atom / cm 3 ~5E16 atom / cm 3 .

[0130] In some embodiments, the doping concentration of the epitaxial layer 220 is 1E13 atom / cm 3 -3E15 atom / cm 3 .

[0131] In some embodiments, the conductivity type of the epitaxial layer 220 is the same as that of the drift layer 210. In other embodiments, the conductivity type of the epitaxial layer 220 is opposite to that of the drift layer 210.

[0132] In one embodiment, the material of the epitaxial layer 220 is SiC. In other embodiments, the material of the epitaxial layer may also be other materials.

[0133] Reference Figure 12 and Figure 13 , ion implantation is performed on the epitaxial layer 220 to form at least a part of the epitaxial layer 220 into a semiconductor layer A.

[0134] Among them, the ion implantation includes a first implantation step, so that the semiconductor layer A includes a first doping region A1 (reference Figure 12 ), for the epitaxial layer 220 on each chip region of the base wafer, the first implantation step is masked ion implantation. The distance between the surface of the first doping region A1 facing away from the drift layer 210 and the drift layer 210 is less than the distance between the surface of the epitaxial layer 220 facing away from the drift layer 210 and the drift layer 210; the first implantation step includes a first sub-ion implantation and / or a second sub-ion implantation; among them, the implantation direction of the first sub-ion implantation is along the first crystal direction of the epitaxial layer 220, and the implantation direction of the second sub-ion implantation is along the second crystal direction of the epitaxial layer 220.

[0135] The first crystal direction is the crystal direction with the highest linear atomic arrangement density in the epitaxial layer 220; the linear atomic arrangement density of the atoms in the epitaxial layer 220 along the second crystal direction is 40% - 70% of the linear atomic arrangement density of the atoms in the epitaxial layer 220 along the first crystal direction.

[0136] In one embodiment, the material of the epitaxial layer 220 is 4H - SiC, the first crystal direction is <0001>, and the second crystal direction is <11 - 23>.

[0137] In one embodiment, the doping concentration of the first doping region A1 is 2E16atom / cm 3 -6E16atom / cm 3 .

[0138] In one embodiment, the implantation energy of the first sub-ion implantation is 300 keV-900 keV, and the implantation energy of the second sub-ion implantation is 300 keV-900 keV.

[0139] In one embodiment, in the first sub-ion implantation, the incident ions are subjected to the blocking barrier height of the atoms arranged along the first crystal direction in the epitaxial layer; in the second sub-ion implantation, the incident ions are subjected to the blocking barrier height of the atoms arranged along the second crystal direction in the epitaxial layer; wherein the blocking barrier height in the second sub-ion implantation is 35%-65% of the blocking barrier height in the first sub-ion implantation. The angle between the second crystal direction and the first crystal direction is greater than zero.

[0140] Wherein, the ion implantation further comprises: after performing the first implantation step, performing a second implantation step so that the semiconductor layer A includes a second doping region A2 (reference Figure 13 ), for the epitaxial layer 220 on each chip region of the base wafer, the second implantation step is masked ion implantation. The second doping region A2 is located on a side of the first doping region A1 away from the drift layer 210 and is connected to the first doping region A1, and the spacing distance between the side surface of the second doping region A2 away from the drift layer 210 and the drift layer 210 is equal to the spacing distance between the side surface of the epitaxial layer 220 away from the drift layer 210 and the drift layer 210.

[0141] A thickness of the second doping region A1 along the first direction is smaller than a thickness of the first doping region A1 along the first direction.

[0142] In one embodiment, the thickness of the first doping region A1 along the first direction is 0.6um-4um; the thickness of the second doping region A2 along the first direction is less than 0.6um. In one embodiment, the doping concentration of the second doping region A1 is 2E16atom / cm 3 -6E16atom / cm 3 .

[0143] The implantation energy of the second implantation step is less than or equal to the implantation energy of the first implantation step.

[0144] An implantation dose of the second implantation step is less than or equal to an implantation dose of the first implantation step.

[0145] The injection direction of the second injection step is vertical injection.

[0146] In one embodiment, the thickness of semiconductor layer A is 1 to 4 microns, such as 1 micron, 2 microns, 3 microns, or 4 microns.

[0147] In this embodiment, on each chip region, a plurality of semiconductor layers A are arranged at intervals, and the epitaxial layer between adjacent semiconductor layers A on each chip region is a JFET region 300. On each chip region, a plurality of first doping regions A1 are arranged at intervals, and a plurality of second doping regions A2 are arranged at intervals.

[0148] In one embodiment, the method for manufacturing a semiconductor power device further includes: forming a well region in semiconductor layer A, and a channel region is provided in the well region. Exemplarily, a well region is formed in the first doping region A1 and the second doping region A2.

[0149] In one embodiment, the semiconductor layer A is a current spreading layer.

[0150] Another embodiment of the present application further provides a schematic diagram of a method for improving semiconductor doping uniformity. The method of this embodiment is different from Figures 11 to 13 the method in that: the second implantation step is not performed. Correspondingly, the epitaxial layer 220 on the side of the first doping region A1 facing away from the drift layer 210 forms the second doping region A2 in the semiconductor layer A. The doping concentration of the second doping region A2 is less than the doping concentration of the first doping region A1.

[0151] For the description of the second doping region A2, reference can be made to Figures 3 to 4 the description of the second doping region A2 in the method of

[0152] Figures 14 to 16 This is a schematic diagram of a method for improving semiconductor doping uniformity in another embodiment of the present application.

[0153] Refer to Figure 14 , a drift layer 210 is formed on one side of the substrate layer 200 along the first direction, and the drift layer 210 includes a plurality of chip regions; an epitaxial layer 220 is formed on the side of the chip region of the drift layer 210 facing away from the substrate layer 200. The epitaxial layer 220, the drift layer 210, and the substrate layer 200 form a basic wafer. The doping concentration of the epitaxial layer 220 is less than the concentration of the drift layer 210.

[0154] In some embodiments, the drift layer 210 further includes a dicing street region located between adjacent chip regions.

[0155] In some embodiments, the concentration of the drift layer 210 is 5E15 atom / cm 3 ~5E16 atom / cm 3 .

[0156] In some embodiments, the doping concentration of the epitaxial layer 220 is 1E13 atom / cm 3 -3E15 atom / cm 3 .

[0157] In some embodiments, the conductivity type of the epitaxial layer 220 is the same as that of the drift layer 210. In other embodiments, the conductivity type of the epitaxial layer 220 is opposite to that of the drift layer 210.

[0158] In one embodiment, the material of the epitaxial layer 220 is SiC. In other embodiments, the material of the epitaxial layer may also be other materials.

[0159] Reference Figure 15 and Figure 16 , ion implantation is performed on the epitaxial layer 220 to form at least a part of the epitaxial layer 220 into a semiconductor layer A.

[0160] Among them, the ion implantation includes a first implantation step, so that the semiconductor layer A includes a first doped region A1 (reference Figure 15 ), for the epitaxial layer 220 on each chip region of the base wafer, the first implantation step is masked ion implantation. The distance between the surface of the first doped region A1 facing away from the drift layer 210 and the drift layer 210 is less than the distance between the surface of the epitaxial layer 220 facing away from the drift layer 210 and the drift layer 210; the first implantation step includes a first sub-ion implantation and / or a second sub-ion implantation; among them, the implantation direction of the first sub-ion implantation is along the first crystal direction of the epitaxial layer 220, and the implantation direction of the second sub-ion implantation is along the second crystal direction of the epitaxial layer 220.

[0161] The first crystal direction is the crystal direction with the highest linear atomic arrangement density in the epitaxial layer 220; the linear atomic arrangement density of the atoms in the epitaxial layer 220 along the second crystal direction is 40%-70% of the linear atomic arrangement density of the atoms in the epitaxial layer 220 along the first crystal direction.

[0162] In one embodiment, the material of the epitaxial layer 220 is 4H-SiC, the first crystal direction is <0001>, and the second crystal direction is <11-23>.

[0163] In one embodiment, the doping concentration of the first doped region A1 is 2E16 atom / cm 3 -6E16 atom / cm 3 .

[0164] In one embodiment, the implantation energy of the first sub-ion implantation is 300 keV-900 keV. The implantation energy of the second sub-ion implantation is 300 keV-900 keV.

[0165] In one embodiment, in the first sub-ion injection, the incident ions are subjected to the blocking barrier height of the atoms arranged along the first crystal direction in the epitaxial layer; in the second sub-ion injection, the incident ions are subjected to the blocking barrier height of the atoms arranged along the second crystal direction in the epitaxial layer; wherein the blocking barrier height in the second sub-ion injection is 35%-65% of the blocking barrier height in the first sub-ion injection.

[0166] An angle between the second crystal direction and the first crystal direction is greater than zero.

[0167] In this embodiment, during the process of performing the first implantation step, the first implantation step further forms an additional semiconductor layer B in a region of the drift layer close to the semiconductor layer A, the doping concentration of the additional semiconductor layer B is greater than the doping concentration of the semiconductor layer A, and the thickness of the additional semiconductor layer B along the first direction is less than the thickness of the semiconductor layer A along the first direction. The conductivity type of the ions implanted in the first implantation step is the same as the conductivity type of the drift layer.

[0168] In one embodiment, the thickness of the additional semiconductor layer is 0.5 micrometers to 2 micrometers, for example, 0.5 micrometers, 1 micrometer, 1.5 micrometers or 2 micrometers.

[0169] Wherein, the ion implantation further comprises: after performing the first implantation step, performing a second implantation step so that the semiconductor layer A includes a second doping region A2 (reference Figure 16 ), for the epitaxial layer 220 on each chip region of the base wafer, the second implantation step is masked ion implantation. The second doping region A2 is located on a side of the first doping region A1 away from the drift layer 210 and is connected to the first doping region A1, and the spacing distance between the side surface of the second doping region A2 away from the drift layer 210 and the drift layer 210 is equal to the spacing distance between the side surface of the epitaxial layer 220 away from the drift layer 210 and the drift layer 210.

[0170] A thickness of the second doping region A1 along the first direction is smaller than a thickness of the first doping region A1 along the first direction.

[0171] In one embodiment, the thickness of the first doping region A1 along the first direction is 0.6 um-4 um; the thickness of the second doping region A2 along the first direction is less than 0.6 um.

[0172] In one embodiment, the doping concentration of the second doping region A1 is 2E16atom / cm 3 -6E16atom / cm 3 .

[0173] The implantation energy of the second implantation step is less than or equal to the implantation energy of the first implantation step.

[0174] An implantation dose of the second implantation step is less than or equal to an implantation dose of the first implantation step.

[0175] The injection direction of the second injection step is vertical injection.

[0176] In this embodiment, on each chip region, the semiconductor layers A are arranged in a plurality at intervals, and the epitaxial layer between adjacent semiconductor layers A and the drift layer between adjacent additional semiconductor layers B on each chip region are JFET regions 300. On each chip region, the first doping regions A1 are arranged in a plurality at intervals, and the second doping regions A2 are arranged in a plurality at intervals.

[0177] In one embodiment, the method for preparing a semiconductor power device further includes: forming a well region in the semiconductor layer A, wherein the well region has a channel region. Exemplarily, the well region is formed in the first doping region A1 and the second doping region A2.

[0178] In one embodiment, the semiconductor layer A is a current spreading layer.

[0179] In this embodiment, the method further includes: cutting along the cutting path area to form a plurality of discrete chips.

[0180] Another embodiment of the present application also provides a schematic diagram of a method for improving semiconductor doping uniformity. The method of this embodiment is Figures 14 to 16 The difference between the method and the method is that the second implantation step is not performed, and accordingly, the epitaxial layer 220 on the side of the first doping region A1 away from the drift layer 210 forms a second doping region A2 in the semiconductor layer A. The doping concentration of the second doping region A2 is less than the doping concentration of the first doping region A1.

[0181] For the description of the second doping region A2, please refer to Figures 3 to 4 Description of the second doping region A2 in the method.

[0182] Figures 17 to 18 It is a schematic diagram of a method for preparing a semiconductor power device in another embodiment of the present application.

[0183] The manufacturing method of the semiconductor power device of this embodiment is different from the above-mentioned embodiment in that the manufacturing method further comprises: repeating the step of forming the drift layer to the step of forming the semiconductor layer, so that the drift layer and the semiconductor layer are alternately arranged in the first direction.

[0184] refer to Figure 17, a drift layer 210 is formed on one side of the substrate layer 200 along the first direction, and the drift layer 210 includes a plurality of chip regions; a semiconductor layer A is formed on the side of the drift layer 210 facing away from the substrate layer 200.

[0185] For the process of forming the semiconductor layer A, refer to the description of the foregoing embodiments.

[0186] Reference Figure 18 , repeat the steps of forming the drift layer 210 to the semiconductor layer A, so that the drift layer 210 and the semiconductor layer A are alternately arranged in the first direction.

[0187] For the same description of this embodiment as the foregoing embodiments, it will not be elaborated herein.

[0188] Obviously, the above embodiments are merely examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made on the basis of the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or variations derived therefrom are still within the protection scope of the present invention.

Claims

1. A method for improving the doping uniformity of a semiconductor, characterized in that, Comprising: A drift layer is formed on one side of the substrate layer along a first direction, and the drift layer includes a plurality of chip regions; An epitaxial layer is formed on a side of the chip region of the drift layer facing away from the substrate layer. The epitaxial layer, the drift layer, and the substrate layer form a basic wafer. The doping concentration of the epitaxial layer is less than that of the drift layer; and Ion implantation is performed on the epitaxial layer to form a semiconductor layer in at least a part of the epitaxial layer; Wherein, the ion implantation includes a first implantation step, such that the semiconductor layer includes a first doped region. The distance from the surface of the first doped region facing away from the drift layer to the drift layer is less than the distance from the surface of the epitaxial layer facing away from the drift layer to the drift layer; the first implantation step includes a first sub-ion implantation and / or a second sub-ion implantation; Wherein, the implantation direction of the first sub-ion implantation is along a first crystal direction of the epitaxial layer, and the implantation direction of the second sub-ion implantation is along a second crystal direction of the epitaxial layer; the first crystal direction is the crystal direction with the highest linear atomic arrangement density in the epitaxial layer; the linear atomic arrangement density of the atoms in the epitaxial layer along the second crystal direction is 40% - 70% of the linear atomic arrangement density of the atoms in the epitaxial layer along the first crystal direction.

2. The method for improving semiconductor doping uniformity according to claim 1, wherein The material of the epitaxial layer is 4H-SiC, the first crystal direction is <0001>, and the second crystal direction is <11-23>.

3. The method for improving semiconductor doping uniformity according to claim 1, characterized in that, The epitaxial layer on the side of the first doped region facing away from the drift layer forms a second doped region in the semiconductor layer, and the doping concentration of the second doped region is less than that of the first doped region.

4. The method for improving semiconductor doping uniformity according to claim 1, wherein The ion implantation further includes: after performing the first implantation step, performing a second implantation step such that the semiconductor layer includes a second doped region. The second doped region is located on the side of the first doped region facing away from the drift layer and is connected to the first doped region. The distance from the surface of the second doped region facing away from the drift layer to the drift layer is equal to the distance from the surface of the epitaxial layer facing away from the drift layer to the drift layer.

5. The method for improving the doping uniformity of a semiconductor according to claim 3 or 4, characterized in that, The thickness of the second doped region along the first direction is less than the thickness of the first doped region along the first direction.

6. The method for improving semiconductor doping uniformity according to claim 4, wherein The implantation energy of the second implantation step is less than or equal to the implantation energy of the first implantation step; Preferably, the implantation dose of the second implantation step is less than or equal to the implantation dose of the first implantation step; Preferably, the implantation direction of the second implantation step is perpendicular implantation.

7. The method for improving the doping uniformity of a semiconductor according to claim 1, characterized in that, Further comprising: During the process of performing the first implantation step, the first implantation step also forms an additional semiconductor layer in a region of the drift layer close to the semiconductor layer. The doping concentration of the additional semiconductor layer is greater than that of the semiconductor layer, and the thickness of the additional semiconductor layer in the first direction is less than the thickness of the semiconductor layer in the first direction; Preferably, the thickness of the additional semiconductor layer along the first direction is 0.5 μm - 2 μm.

8. The method for improving semiconductor doping uniformity according to claim 1, wherein The thickness of the semiconductor layer along the first direction is 1 μm - 4 μm.

9. The method for improving the doping uniformity of a semiconductor according to claim 1, wherein For the basic wafer, the first implantation step is a full-surface implantation, and the first doped region is a full-surface structure.

10. The method for improving the doping uniformity of a semiconductor according to claim 1, characterized in that, For the epitaxial layer on each chip area of the base wafer, the first implantation step is a masked ion implantation; Preferably, on each chip area, the semiconductor layers are multiple and arranged at intervals, and the epitaxial layer between adjacent semiconductor layers on each chip area is a JFET area.

11. The method for improving semiconductor doping uniformity according to claim 1, wherein It further includes: Repeatedly perform the step of forming the drift layer to the step of forming the semiconductor layer, so that the drift layer and the semiconductor layer are alternately arranged in the first direction.

12. The method for improving semiconductor doping uniformity according to claim 1, characterized in that, In the first sub-ion implantation, the incident ions are blocked by the barrier height of the atoms arranged along the first crystal orientation in the epitaxial layer; in the second sub-ion implantation, the incident ions are blocked by the barrier height of the atoms arranged along the second crystal orientation in the epitaxial layer; Wherein, the barrier height in the second sub-ion implantation is 35% - 65% of the barrier height in the first sub-ion implantation.

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