Semiconductor structure manufacturing method and semiconductor structure

Abstract

The invention discloses a semiconductor structure manufacturing method and a semiconductor structure, and the manufacturing method comprises the steps: carrying out the periodic cycle etching of a preset number of times on a substrate through employing an etching technology, forming a first intermediate structure on the substrate, and carrying out the first processing of the first intermediate structure, including employing a first gas and a second gas, removing a part of thickness of the passivation layer deposited on the side wall of the first intermediate structure, and reacting with the substrate material which exists on the side wall and is exposed on the surface of the convex part to generate a reaction product layer; and removing the reaction product layer by using a third gas and a fourth gas so as to remove at least part of the lug boss, and repeatedly executing the etching process and the first processing process until a high aspect ratio etching structure is formed on the substrate. According to the method, the etching process and the side wall processing technology are organically combined, the etching rate and the side wall quality are balanced through alternate circulation, and deep silicon etching with the higher aspect ratio and the smaller nanoscale size can be achieved.

Description

Technical Field

[0001] This application relates to the field of semiconductor processing technology, and particularly to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] In the rapidly developing field of advanced packaging, higher-density interconnections are required, and deep silicon etching (DSE) needs to meet nanoscale line widths (less than 50 nm) and higher aspect ratios (greater than 100:1). The existing etching process is a periodic cyclic process formed by deposition and etching in sequence. Due to the influence of corresponding physical limitations (such as ion shadow effect, reaction gas transport efficiency), it is difficult to meet the above-mentioned extreme aspect ratio requirements. At the same time, nanoscale line widths are more sensitive to the thickness fluctuations of the sidewall passivation layer (such as C-F polymer). When the thickness fluctuations of the sidewall passivation layer are large, it is extremely easy to cause line width deviation and etching tilt (for the stacking of three-dimensional through-silicon vias and memories, the etching perpendicularity error is required to be less than ±0.2°). In addition, the existing etching process also has problems such as plasma chemical residues and local rough peaks (Ra > 5 nm) caused by random deposition of C-F polymer on the sidewalls. These factors all have important impacts on achieving higher aspect ratios and deep silicon etching with nanoscale dimensions. Therefore, it is necessary to study a process method that can significantly improve the above problems. Summary of the Invention

[0003] The purpose of this application is to overcome the above problems existing in the prior art, and provide a method for manufacturing a semiconductor structure and a semiconductor structure, so as to solve the deficiencies that the existing etching process is difficult to achieve deep silicon etching with higher aspect ratios and nanoscale dimensions due to the existence of corresponding physical limitations, large fluctuations in the thickness of the sidewall passivation layer, and sidewall roughness.

[0004] To achieve the above purpose, the technical solution of this application is as follows: According to the first aspect of this application, an embodiment of this application provides a method for manufacturing a semiconductor structure, including: Providing a substrate; Forming a plurality of organic mask patterns on the surface of the substrate; Using an etching process and using the organic mask patterns as masks, performing a preset number of periodic cyclic etching on the substrate to form a first intermediate structure on the substrate; Using a first processing process different from the etching process to perform a first processing on the first intermediate structure, including: Using a first gas and a second gas, a partial thickness of the passivation layer deposited on the sidewalls of the first intermediate structure is removed, and reacts with the substrate material on the surface of the protruding portion that exists and is exposed on the sidewalls to generate a reaction product layer; and using a third gas and a fourth gas, the reaction product layer is removed to remove at least a part of the protruding portion; The etching process and the first treatment process are repeatedly executed to sequentially form one or more second intermediate structures below the first intermediate structure, and after each new second intermediate structure is formed, the first treatment is performed on the new second intermediate structure until a high aspect ratio etching structure composed of each intermediate structure is formed on the substrate.

[0005] In some embodiments, when performing the first treatment process, by using the plasma of the first gas in a mixed state and the plasma of the second gas to react with the passivation layer, a partial thickness of the passivation layer deposited on the sidewalls is removed to adjust the thickness uniformity of the passivation layer on the sidewalls; by reacting the plasma of the first gas with the substrate material on the surface of the exposed protruding portion, a first reaction product layer is in-situ oxidized, and by reacting the plasma of the second gas with the substrate material on the surface of the exposed protruding portion, a second reaction product layer with low volatility is generated, and the sidewalls are bombarded with the plasma of the third gas in a mixed state and the plasma of the fourth gas to remove the first reaction product layer and the second reaction product layer to remove at least a part of the protruding portion and smooth the sidewalls.

[0006] In some embodiments, when performing the first treatment process, a second treatment process is further used to perform a second treatment on the organic mask pattern, including: Using the plasma of the second gas to bombard the surface of the organic mask pattern to improve the etching resistance of the organic mask pattern by modification.

[0007] In some embodiments, the etching process includes periodic cyclic steps sequentially formed by a deposition step, a first etching step, and a second etching step. After each completion of the preset number of the periodic cyclic steps, the first treatment and the second treatment are both performed once.

[0008] In some embodiments, the substrate material includes silicon, the first gas includes oxygen, and the first reaction product layer includes a silicon oxide layer.

[0009] In some embodiments, the second gas includes hydrogen bromide, and the second reaction product layer includes a silicon tetrabromide layer.

[0010] In some embodiments, the third gas includes a fluorine-based gas.

[0011] In some embodiments, the fourth gas includes noble gases.

[0012] In some embodiments, before forming the first intermediate structure, it further includes: bombarding the interface of the substrate with a plasma of a fifth gas to form a carbon-based protective film.

[0013] In some embodiments, after forming the high aspect ratio etching structure, it further includes: removing the organic mask pattern and the carbon-based protective film with a plasma of a sixth gas.

[0014] In some embodiments, the organic matter includes photoresist.

[0015] In some embodiments, the fifth gas includes noble gases.

[0016] In some embodiments, the sixth gas includes an oxidizing gas.

[0017] In some embodiments, the temperature for performing the etching process and the first processing process is lower than 60 °C.

[0018] In some embodiments, the time for performing the deposition step, the first etching step, and / or the second etching step is 0.1 s to 2 s.

[0019] In some embodiments, the time for using the first gas and the second gas is 0.5 s to 2 s.

[0020] In some embodiments, the time for using the third gas and the fourth gas is 0.5 s to 2 s.

[0021] In some embodiments, the preset number of times is 1 to 2 times.

[0022] According to the second aspect of the present application, an embodiment of the present application further provides a semiconductor structure obtained by using the semiconductor structure manufacturing method provided in any one of the embodiments of the first aspect above.

[0023] Embodiments of the present application may / at least have the following advantages: (1) During the etching process of the substrate using an etching process, each time a preset number of periodic cycle steps are completed, the formed intermediate structure is processed once (the first process). By removing a partial thickness of the passivation layer deposited on the sidewalls and at least part of the protruding portions existing and exposed on the sidewalls, the thickness uniformity of the passivation layer on the sidewalls can be adjusted, and the surface of the sidewalls can be smoothed. By alternately cycling between the periodic cycles of the etching process and the processing, the etching rate and the sidewall quality can be balanced, thereby achieving a high etching rate and high etching accuracy (atomic-level accuracy) for the high aspect ratio etching structure, increasing the diffusion coefficient, enhancing the reaction gas transport efficiency, solving the problems of plasma chemical residues (the thickness fluctuation of the polymer has a great impact on the control of the nanoscale linewidth) and ion shadow effects (the nanoscale involves the atomic size level), effectively improving the uniformity and roughness of the local C-F polymer, solving the problem of linewidth offset (tilting), achieving a higher perpendicularity (90°±0.2°), and achieving better uniformity (the upper, middle, and lower position dimensions of the high aspect ratio etching structure are uniform), and better sidewall smoothness.

[0024] (2) By embedding the above-mentioned processing technology during the periodic cycle steps of the etching process, the by-products generated in the intermediate structure (deep holes or trenches) during the etching process can be removed in a timely manner, preventing the excessive thickness of the polymer from accumulating. At the same time, the sidewall roughness can be improved, avoiding the occurrence of an etching stop phenomenon or the inward inclination of the bottom angle (it is difficult to achieve high perpendicularity) after etching to a certain depth, and the problem that the generated by-products are difficult to be removed from the deep holes or trenches in a timely manner, resulting in limited process adjustment and difficulty in realizing a more refined structure.

[0025] (3) By using oxygen to process the sidewalls, the protruding portions can be selectively removed by reacting with the silicon material of the protruding portions exposed on the sidewalls. By using hydrogen bromide in combination with oxygen, it can react with the exposed silicon material to generate a low-volatility by-product, silicon tetrabromide, which can be adsorbed at the concave portions on the sidewalls at low temperature, making the entire sidewall surface flat, which is beneficial to the smooth treatment when removing the reaction product layer and the continuous cyclic processing steps. Moreover, through the modification effect of hydrogen bromide plasma on the organic mask pattern (photoresist), the C / H ratio of the photoresist material can be changed, making the photoresist material more stable in structure, improving the etching resistance of the photoresist, and thus improving the etching blocking ability of the organic mask pattern during the deep silicon etching process, that is, improving the etching selectivity of the organic mask pattern.

[0026] (4) By adopting a cyclic manner of an inlaid etching process and an inlaid processing process, performing fine etching and surface treatment of the internal structure, it is possible to perform sidewall treatment and by-product treatment while gradually etching the required high aspect ratio etching structure in the same processing chamber, thereby laying a foundation for achieving deep silicon etching with a higher aspect ratio (for example, greater than 100:1) and nanoscale dimensions (for example, less than 50 nm) (currently, the mainstream width dimension is above 140 nm, and the aspect ratio is about 50:1).

[0027] Other advantages of this application will be elaborated in the following specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a flowchart of a method for manufacturing a semiconductor structure according to a preferred embodiment of this application.

[0029] Figure 2 It is a schematic structural diagram after forming an organic mask pattern on a substrate according to a preferred embodiment of this application.

[0030] Figure 3 It is a schematic structural diagram after forming an intermediate structure of a first trench on a substrate according to a preferred embodiment of this application.

[0031] Figure 4 It is a schematic diagram of the principle for treating sidewalls according to a preferred embodiment of this application. Among them Figure 4 (a) is adsorption and reaction, Figure 4 (b) is desorption.

[0032] Figure 5 It is a schematic structural diagram after treating an intermediate structure of a first trench according to a preferred embodiment of this application.

[0033] Figure 6 It is a schematic structural diagram after forming an intermediate structure of a second trench according to a preferred embodiment of this application.

[0034] Figure 7 It is a schematic structural diagram after treating an intermediate structure of a second trench according to a preferred embodiment of this application.

[0035] Figure 8 It is a schematic diagram after forming a complete structure of a deep trench on a substrate according to a preferred embodiment of this application.

[0036] Figure 9 It is a schematic structural diagram after removing an organic mask pattern according to a preferred embodiment of this application.

[0037] In the figure, 10. Substrate; 11. Opening; 12. Organic mask pattern; 13. Carbon-based protective film; 14. Deep trench; 141. First trench intermediate structure; 142. Second trench intermediate structure; 15. Scalloped stripe; 16. Protrusion; 17. Depression. Detailed implementation mode

[0038] The purpose of the embodiment of the present application is to solve the deficiencies that in the existing etching process during deep silicon etching, due to corresponding physical limitations, the thickness fluctuation of the sidewall passivation layer is large, and problems such as sidewall roughness exist, making it difficult to achieve a deep silicon etching structure with a higher aspect ratio and nanoscale dimensions.

[0039] To solve the above problems, the embodiment of the present application provides a semiconductor structure manufacturing method, including: Providing a substrate; Forming a plurality of organic mask patterns on the surface of the substrate; Using an etching process and using the organic mask pattern as a mask, performing a preset number of periodic cyclic etching on the substrate to form a first intermediate structure on the substrate; Using a first processing process different from the etching process to perform a first processing on the first intermediate structure, including: Using a first gas and a second gas to remove a part of the thickness of the passivation layer deposited on the sidewall of the first intermediate structure and react with the substrate material on the surface of the protrusion existing and exposed on the sidewall to generate a reaction product layer; and using a third gas and a fourth gas to remove the reaction product layer to remove at least part of the protrusion; Repeatedly executing the etching process and the first processing process to sequentially form one or more second intermediate structures below the first intermediate structure, and performing the first processing on each newly formed second intermediate structure until a high aspect ratio etching structure composed of each intermediate structure is formed on the substrate.

[0040] By providing the above-mentioned novel high aspect ratio etching structure etching method, the embodiment of the present application organically combines the etching process with the sidewall treatment technology, alternately cycles to balance the etching rate and the sidewall quality, thereby achieving a high etching rate and high etching accuracy of the high aspect ratio etching structure, increasing the diffusion coefficient, improving the reaction gas transmission efficiency, solving the problems of plasma chemical residue and ion shadow effect, effectively improving the uniformity and roughness of the local C-F polymer, and finally achieving deep silicon etching with a higher aspect ratio and nanoscale dimensions.

[0041] The embodiment of the present application also provides a semiconductor structure obtained by using the semiconductor structure manufacturing method as described above.

[0042] The following will describe the specific embodiments of the present application in detail with reference to the accompanying drawings.

[0043] Reference Figure 1 The embodiment of the present application provides a method for manufacturing a semiconductor structure, which successively includes the following steps: Step S11: Provide a substrate.

[0044] Reference Figure 2 In some embodiments, the material of the substrate 10 includes silicon (i.e., a silicon substrate).

[0045] In some embodiments, a silicon wafer may be used as the substrate 10 to further form a required high aspect ratio etching structure on the substrate 10.

[0046] In some embodiments, the high aspect ratio etching structure includes deep trenches, deep vias, or through vias, etc. Hereinafter, taking the formation of deep trenches as the high aspect ratio etching structure on the substrate 10 as an example, the embodiments of the present application will be described in detail.

[0047] In some embodiments, the silicon wafer may be doped to provide the substrate 10 with required electrical properties.

[0048] In some embodiments, an integrated circuit, such as a transistor structure, etc., may be fabricated on the substrate 10, so that after forming deep trenches (high aspect ratio etching structures), the required vertical interconnection can be achieved through the deep trenches filled with conductive materials.

[0049] Step S12: Form a plurality of organic mask patterns on the surface of the substrate.

[0050] Reference Figure 2 In some embodiments, an organic mask layer is formed on the upper surface of the substrate 10, and the organic mask layer is patterned to form a plurality of organic mask patterns 12 on the upper surface of the substrate 10. Among them, there is an opening 11 serving as an etching window between any two adjacent organic mask patterns 12, and the surface of the substrate 10 between the two adjacent organic mask patterns 12 is exposed at the bottom of the opening 11.

[0051] It should be noted that Figure 2 only schematically shows the case where 2 organic mask patterns 12 are formed on the upper surface of the substrate 10. However, it can be understood that more organic mask patterns may be formed on the upper surface of the substrate 10, such as 3 organic mask patterns, 4 organic mask patterns, 10 organic mask patterns, etc., and it is not limited thereto.

[0052] In some embodiments, the organic matter includes photoresist. That is, the organic mask layer includes a photoresist layer.

[0053] In some embodiments, a spin coating process is adopted to form a photoresist layer on the upper surface of the substrate 10. Then, a photolithography process is used to perform photolithography on the photoresist layer, thereby forming a plurality of photoresist patterns on the upper surface of the substrate 10, that is, the organic mask patterns 12.

[0054] In some embodiments, before etching the substrate 10, the interface (upper surface) of the substrate 10 is bombarded with the plasma of the fifth gas to form a carbon-based protective film 13 at the junction of the bottom of the organic mask pattern 12 and the upper surface of the substrate 10 (i.e., the inner bottom corner of the opening 11). The plasma of the fifth gas is obtained by ionizing the fifth gas introduced into the process chamber.

[0055] Due to the mask edge effect, when the main etching is performed using the etching process subsequently, the passivation layer is insufficiently deposited in the edge region, which exacerbates the etching behavior at the top. The ion bombardment is more concentrated at the top, and the lateral etching in this region is aggravated during etching, resulting in deeper and rougher sidewall scalloped ripples at the top of the deep trench. Therefore, by pre-forming the carbon-based protective film 13 at the junction of the bottom of the organic mask pattern 12 and the upper surface of the substrate 10, the morphology of the etched top can be effectively protected when the substrate 10 is etched using the etching process subsequently, preventing abnormal excessive lateral etching behavior at the top, and ensuring the dimensional uniformity at different depth positions of the upper, middle, and lower parts during the subsequent high aspect ratio etching, that is, ensuring the perpendicularity of the sidewalls.

[0056] In some embodiments, the fifth gas includes noble gases.

[0057] In this embodiment, argon is used as the fifth gas, and the photoresist material of the organic mask pattern 12 and the upper surface of the substrate 10 are bombarded by the formed argon plasma (the plasma of the fifth gas) to form a carbon-based protective film 13 (a protective film made of a carbon-based material containing C, N, and O) at the junction of the bottom of the organic mask pattern 12 and the upper surface of the substrate 10.

[0058] In some embodiments, in the process of bombarding with argon to form the carbon-based protective film 13, the temperature is -20°C to 60°C. For example, the temperature can be -20°C, -10°C, 0°C, 10°C, 20°C, 30°C, 40°C, 50°C, or 60°C, etc., or any value between any two of the aforementioned temperature values.

[0059] In some embodiments, in the process of bombarding with argon gas to form the carbon-based protective film 13, the pressure is 50 mTorr to 800 mTorr. For example, the pressure can be 50 mTorr, 100 mTorr, 200 mTorr, 300 mTorr, 400 mTorr, 500 mTorr, 600 mTorr, 700 mTorr or 800 mTorr, or any value between any two of the foregoing pressure values.

[0060] In some embodiments, in the process of bombarding with argon gas to form the carbon-based protective film 13, the source power is 50 W to 100 W. For example, the source power can be 50 W, 55 W, 60 W, 65 W, 70 W, 75 W, 80 W, 85 W, 90 W, 95 W or 100 W, or any value between any two of the foregoing source power values.

[0061] In some embodiments, in the process of bombarding with argon gas to form the carbon-based protective film 13, the bias power is 10 W to 50 W. For example, the bias power can be 10 W, 15 W, 20 W, 25 W, 30 W, 35 W, 40 W, 45 W or 50 W, etc., or any value between any two of the foregoing bias power values.

[0062] In some embodiments, in the process of bombarding with argon gas to form the carbon-based protective film 13, the time is 5 s to 20 s. For example, the time can be 5 s, 10 s, 15 s or 20 s, or any value between any two of the foregoing time values.

[0063] Step S13: Use an etching process and use the organic mask pattern as a mask to perform a periodic cyclic etching on the substrate a preset number of times to form a first trench intermediate structure on the substrate, and use a first processing process to perform a first processing on the first trench intermediate structure.

[0064] Reference Figure 3 . In some embodiments, use an etching process and use the organic mask pattern 12 as a mask to perform a periodic cyclic etching on the upper surface of the substrate 10 exposed at the bottom of the opening 11 a preset number of times to first form a first trench intermediate structure 141 (first intermediate structure) on the substrate 10, with the aim of ultimately forming a completed structure of a deep trench on the substrate 10 (reference Figure 8 ).

[0065] In some embodiments, the etching process includes multiple (a plurality of) periodic cycle steps formed in sequence by a passivation layer deposition step, a first etching step, and a second etching step. Among them, the passivation layer deposition step is used to form a passivation layer on the sidewalls to protect the sidewalls during etching; the first etching step is used to remove the passivation layer on the bottom so as to continue etching downward through the second etching step. By implementing multiple periodic cycle steps, deep trenches are formed on the substrate 10.

[0066] However, the existing etching process has difficulty meeting the requirements of the ultimate aspect ratio for nanoscale line widths (less than 50 nm) and higher aspect ratios (greater than 100:1). The reason is that the existing etching process is affected by corresponding physical limitations (such as ion shadow effect, reaction gas transport efficiency). Nanoscale line widths are more sensitive to the thickness fluctuations of the sidewall passivation layer (such as C-F polymer), which easily leads to problems such as line width deviation and increased perpendicularity error.

[0067] At the same time, due to the characteristics of the existing etching process, regular multi-channel scalloped stripes 15 will be formed on the sidewalls during multiple periodic cycle etching processes. Among them, each scalloped stripe 15 has a recess 17 at the bottom and a protrusion 16 at the junction of two scalloped stripes 15, making the sidewalls have a rough surface topography. In addition, there are also problems such as plasma chemical residues and local roughness differences (local rough peaks) caused by random deposition of C-F polymer on the sidewalls. The existence of the above factors will cause an etching stop phenomenon after etching to a certain depth, or the bottom angle tilts inward (it is difficult to achieve high perpendicularity), and the by-products generated are difficult to be removed from the deep holes or trenches in time, resulting in limited process adjustment and difficulty in realizing more refined structures. Therefore, the embodiments of the present application timely remove the excessive polymer on the sidewalls, prevent uneven etching caused by too thick passivation layer, and reduce the roughness of the sidewalls through treatment, improve the smoothness of the sidewalls, increase the diffusion coefficient, and enhance the reaction gas transport efficiency, solve the problems of plasma chemical residues and ion shadow effect, effectively improve the uniformity and roughness of the local C-F polymer, so as to be able to achieve deep silicon etching of nanoscale dimensions with a higher aspect ratio.

[0068] In some embodiments, when etching the substrate 10 using an etching process, after each completion of a preset number of periodic cycle steps (periodic cyclic etching), and after forming an intermediate structure before forming a deep trench (high aspect ratio etching structure) on the substrate 10, a step of processing the intermediate structure is inserted. That is, after each completion of a preset number of periodic cycle steps, a special processing process (first processing process) different from the etching process is used to perform the following processing (first processing) on the intermediate structure formed before the deep trench is formed: removing a partial thickness of the passivation layer deposited on the sidewalls, and removing at least a part of the protrusion 16 existing on the sidewalls and exposed from the surface of the remaining passivation layer.

[0069] In some embodiments, an etching process is used, and the substrate 10 is etched using the organic mask pattern 12 as a mask, and after completing a preset number of periodic cycle steps, a first trench intermediate structure 141 is formed on the substrate 10 as the first intermediate structure before the deep trench is formed, as Figure 3 shown. The first trench intermediate structure 141 is an intermediate structure before the deep trench of the required depth is formed, that is, the depth of the first trench intermediate structure 141 is less than the total depth of the deep trench. Then, the sidewalls of the first trench intermediate structure 141 are subjected to the first processing using a first processing process different from the etching process.

[0070] When etching the substrate 10, due to the presence of the carbon-based protective film 13, when etching to form the first trench intermediate structure 141, over-etching of the top is avoided, making the size of the first trench intermediate structure 141 relatively uniform, thus laying a good foundation for ensuring the uniformity of the sizes at different positions of the upper, middle, and lower parts of the entire deep trench.

[0071] In some embodiments, when etching the substrate 10 using an etching process (until the etching of the entire deep trench is completed, the same hereinafter), the time for performing the deposition step, the first etching step, and / or the second etching step is limited to be very short and is limited within the range of 0.1 s to 2 s, and the three steps are quickly switched. For example, the time for performing the deposition step can be 0.1 s, 0.2 s, 0.3 s, 0.4 s, 0.5 s, 0.7 s, 0.9 s, 1 s, 1.2 s, 1.5 s, 1.8 s, or 2 s, or any value between any two of the foregoing time values. The time for performing the first etching step can be 0.1 s, 0.2 s, 0.3 s, 0.4 s, 0.5 s, 0.7 s, 0.9 s, 1 s, 1.2 s, 1.5 s, 1.8 s, or 2 s, or any value between any two of the foregoing time values. The time for performing the second etching step can be 0.1 s, 0.2 s, 0.3 s, 0.4 s, 0.5 s, 0.7 s, 0.9 s, 1 s, 1.2 s, 1.5 s, 1.8 s, or 2 s, or any value between any two of the foregoing time values.

[0072] In some embodiments, when the substrate 10 is etched using an etching process, the temperature is -20°C to 60°C. For example, the temperature can be -20°C, -10°C, 0°C, 10°C, 20°C, 30°C, 40°C, 50°C, or 60°C, etc., or any value between any two of the aforementioned temperature values.

[0073] In some embodiments, when the substrate 10 is etched using an etching process, the pressure is 10 mTorr to 200 mTorr. For example, the pressure can be 10 mTorr, 20 mTorr, 50 mTorr, 80 mTorr, 100 mTorr, 130 mTorr, 150 mTorr, 190 mTorr, or 200 mTorr, or any value between any two of the aforementioned pressure values.

[0074] In some embodiments, when the substrate 10 is etched using an etching process, the source power is 1000 W to 4000 W. For example, the source power can be 1000 W, 1500 W, 2000 W, 2500 W, 3000 W, 3500 W, or 4000 W, or any value between any two of the aforementioned source power values.

[0075] In some embodiments, when the substrate 10 is etched using an etching process, the bias power is 10 W to 200 W. For example, the bias power can be 10 W, 20 W, 50 W, 70 W, 100 W, 130 W, 160 W, 180 W, or 200 W, etc., or any value between any two of the aforementioned bias power values. Among them, by setting the bias power, pulsed etching can be achieved.

[0076] In some embodiments, when the substrate 10 is etched using an etching process, the process gas used in the deposition step includes a mixed gas of C4F8 and Ar. The process gases used in the first etching step and the second etching step include a mixed gas of SF6 and Ar. By alternately using C4F8 to deposit a passivation layer and using SF6 for etching, a vertical deep trench is formed.

[0077] In some embodiments, if the preset number is n times and the total number of times of the periodic cycling step is m, then: 1 < n < m.

[0078] In some embodiments, m / n ≥ 10, that is, m / n is the number of times of the first treatment. During the process of etching to form a deep trench, the sidewalls need to be subjected to the first treatment at least 10 times, and at least 1 treatment needs to be performed on different positions of the upper, middle, and lower parts of the deep trench respectively.

[0079] In some embodiments, the total number of times (m / n) of performing the first treatment on the sidewalls can be more than 3 times, more than 5 times, more than 10 times, more than 20 times, more than 50 times, more than 100 times, more than 200 times, more than 500 times, or more than 1000 times, or any number of times between any two of the foregoing numbers. However, it is not limited thereto.

[0080] In some embodiments, the preset number of times n is 1 to 2 times. For example, the preset number of times n can be 1 time or 2 times.

[0081] In some other embodiments, the preset number of times n can be 1 to 10 times. For example, the preset number of times n can be 1 time, 2 times, 3 times, 4 times, 5 times, 6 times, 7 times, 8 times, 9 times, or 10 times, or more than 10 times.

[0082] In this embodiment, the preset number of times n is set to 2 times. The formed intermediate structure 141 of the first trench is as Figure 3 shown. Among them, after 2 cycles of the periodic cycle steps, 2 scalloped stripes 15 will be correspondingly formed on the sidewalls of the intermediate structure 141 of the first trench. Each scalloped stripe 15 has a recess 17 at the bottom, and a protrusion 16 at the junction of two adjacent scalloped stripes 15, so that the sidewalls of the intermediate structure 141 of the first trench have a rough surface topography. It is necessary to use the first treatment process to perform the first treatment on the sidewalls of the intermediate structure 141 of the first trench to improve the rough topography of the sidewall surface, smooth the sidewall, which is beneficial to the timely removal of by-products, avoid excessive deposition of polymers on the sidewalls, and improve the etching perpendicularity.

[0083] In some embodiments, when performing the first treatment on the sidewalls of the intermediate structure 141 of the first trench, by using a reaction gas to react with the passivation layer (polymer) on the sidewalls, a part of the thickness of the passivation layer is removed to adjust the thickness uniformity of the passivation layer on the sidewalls. Among them, when the thickness of the passivation layer gradually thins due to removal, the protrusions 16 on the sidewalls will gradually expose from the surface of the passivation layer. During this process, by reacting the reaction gas with the substrate 10 material on the surface of the exposed protrusions 16 to generate a reaction product layer, the purpose of removing at least part of the protrusions 16 can be achieved by removing the reaction product layer, making the sidewalls smooth after removing the protrusions 16.

[0084] For deep silicon etching with nanoscale line widths and higher aspect ratios, due to the influence of the process characteristics of the etching process itself, the problem that the deposition rate gradually becomes greater than the etching rate will occur, making it easy for the polymer (passivation layer) to accumulate at the bottom and affecting the timely removal of by-products. Therefore, after etching to a certain depth, problems such as etching stop will occur. In the embodiments of the present application, after each preset number of periodic cycle steps are completed, a partial thickness of the passivation layer deposited on the sidewalls is removed, which can prevent the passivation layer from being repeatedly deposited and forming a passivation layer with too thick a thickness on the sidewalls, affecting the etching uniformity and the timely removal of by-products. At the same time, taking advantage of the fact that the thickness of the passivation layer on the protrusion 16 is thinner than that on the recess 17, when removing the overly thick passivation layer on the sidewalls, the top of the protrusion 16 can be exposed from the surface of the remaining passivation layer after removing the partial thickness. Therefore, by reacting to remove this part of the protrusion 16, the sidewall surface can be made smoother. And it can play a role in reducing the accumulation of the passivation layer and facilitating the timely removal of by-products. Moreover, the smooth sidewalls are also beneficial for providing a vertical guiding effect during downward etching, thereby enabling a higher perpendicularity and improving the electrical performance after deep trench filling.

[0085] In some embodiments, a first processing process different from the etching process is used to perform a first processing on the first trench intermediate structure 141. The method includes: using a first gas and a second gas to remove a partial thickness of the passivation layer deposited on the sidewalls of the first trench intermediate structure 141 and react with the substrate 10 material on the surface of the exposed protrusion 16 existing on the sidewalls to generate a reaction product layer; and using a third gas and a fourth gas to remove the reaction product layer to remove at least a part of the protrusion 16.

[0086] In some embodiments, when performing the first processing process, first, the plasma of the first gas in a mixed state and the plasma of the second gas are used to adsorb on the sidewall surface of the first trench intermediate structure 141 and react with the passivation layer to remove a partial thickness of the passivation layer deposited on the sidewalls, so that the thickness of the passivation layer will not be too thick to adjust the thickness uniformity of the passivation layer on the sidewalls. And, the plasma of the first gas undergoes an oxidation reaction with the substrate 10 material on the surface of the protrusion 16 exposed from the surface of the remaining passivation layer to in-situ oxidize and generate a first reaction product layer on the surface of the exposed protrusion 16. At the same time, the plasma of the second gas undergoes a displacement reaction with the substrate 10 material on the surface of the exposed protrusion 16 to generate a layer of low-volatility second reaction product layer on the sidewall surface of the first trench intermediate structure 141. The plasma of the first gas and the plasma of the second gas are obtained by ionizing the first gas and the second gas (reaction gases) introduced into the process chamber.

[0087] In some embodiments, the first gas includes oxygen, and the second gas includes hydrogen bromide. Nitrogen can be used as a dilution gas simultaneously. By ionizing the oxygen and hydrogen bromide gases introduced into the process chamber, an oxygen plasma (plasma of the first gas) and a hydrogen bromide plasma (plasma of the second gas) are formed. The oxygen plasma and the hydrogen bromide plasma are used as reaction gases to perform the above-mentioned first treatment on the sidewalls of the first trench intermediate structure 141, and a silicon oxide (SiO2) layer as the first reaction product layer and a silicon tetrabromide layer (SiBr4) as the second reaction product layer are correspondingly generated.

[0088] The passivation layer is formed by a passivation layer deposition step and is used to protect the sidewalls during the etching step. Due to the influence of the scalloped stripes 15 on the sidewalls, the deposition thickness of the passivation layer on the sidewalls is not uniform, and the random deposition of C-F polymer on the sidewalls will also cause local rough peaks, exacerbating the roughness of the sidewalls. When the size of the deep trench enters the nanoscale, the already small channels in the trench will be further affected by factors such as the scalloped stripes 15, the random deposition of C-F polymer, the ion shadow effect, the reaction gas transport efficiency, and the plasma chemical residues, which will make it more difficult to discharge the by-products and easily cause the accumulation of polymers in the trench, resulting in problems such as line width deviation, poor perpendicularity, and inconsistent etching depth. Therefore, before the deep trench etching is completed, it is necessary to gradually process the intermediate structure of the forming deep trench. This is because after the etching process is used to etch to the final depth of the deep trench, the effects caused by the above factors have been finalized (for example, the roughness and overall morphology of the sidewalls have been finalized), and it is difficult to change them through post-treatment. Moreover, the polymers generated on the sidewalls by the existing etching process methods will increase with the increase of the etching depth, and finally will cause an "etching stop" problem due to excessive polymer accumulation, which will hinder the higher aspect ratio vertical etching in the nanoscale lateral dimension and limit the final etching depth at the nanoscale.

[0089] When the oxygen plasma and the hydrogen bromide plasma are used in the embodiments of the present application to perform the first treatment on the sidewalls of the first trench intermediate structure 141, by-products and the like existing in the first trench intermediate structure 141 will be removed, and a reaction will occur with the polymer material of the passivation layer on the sidewalls to remove a part of the thickness of the passivation layer on the sidewalls, avoiding accumulation caused by too thick a passivation layer. During the process of removing a part of the thickness of the passivation layer, the top of the protrusion 16 will gradually be exposed from the surface of the remaining passivation layer after removing a part of the thickness. At this time, oxygen ions (O 2- ) and bromide ions (Br - ) will continue to adsorb on the surface of the exposed protrusion 16 and can penetrate into the exposed protrusion 16 from multiple directions and react with the silicon (Si) material of the substrate 10, such asFigure 4 As shown in (a). Among them, after the oxygen ions react with the silicon (Si) material of the substrate 10, a silicon oxide layer is in-situ generated on the surface of the exposed protrusion 16, causing the silicon material interface to gradually retreat in the direction of the outside of the sidewall. As a result, the undulation degree of the new interface of the silicon material formed after the reaction (i.e., the new sidewall surface to be formed subsequently, refer to Figure 4 Figure (b)) becomes relatively gentle. The low-volatility silicon tetrabromide (SiBr4) layer generated by the reaction of bromine ions with the silicon (Si) material of the substrate 10 can be adsorbed at the concave portions on the sidewalls at low temperatures, making the entire sidewall surface flat, which is beneficial for the smooth treatment when removing the reaction product layer subsequently and the continuous cyclic treatment steps.

[0090] It should be noted that the adsorption and reaction of oxygen ions on the surface of the silicon material on the sidewalls are self-limiting reactions. Therefore, when the silicon material on the sidewall surface is oxidized to a certain extent, the reaction will no longer continue, thus avoiding the silicon material on the sidewall surface at the protrusion 16 from being over-etched by the reaction, effectively realizing longitudinal cyclic etching and surface treatment with atomic-level precision in the transverse direction. When the protrusion 16 is fully removed and the sidewall surface after removal becomes relatively smooth, the passivation layer redeposited during subsequent cycles can be used to protect the processed upper sidewalls, thereby avoiding loss of the width dimension.

[0091] In some embodiments, when using the plasma of the first gas and the second gas for adsorption and reaction, the temperature is -20°C to 60°C. For example, the temperature can be -20°C, -10°C, 0°C, 10°C, 20°C, 30°C, 40°C, 50°C or 60°C, etc., or any value between any two of the aforementioned temperature values.

[0092] In some embodiments, when using the plasma of the first gas and the second gas for adsorption and reaction, the time is 0.5 s to 2 s. For example, the time can be 0.5 s, 0.6 s, 0.7 s, 0.8 s, 0.9 s, 1 s, 1.1 s, 1.3 s, 1.5 s, 1.7 s or 2 s, or any value between any two of the aforementioned time values.

[0093] In some embodiments, when using the plasma of the first gas and the second gas for adsorption and reaction, the pressure is 10 mTorr to 50 mTorr. For example, the pressure can be 10 mTorr, 15 mTorr, 20 mTorr, 25 mTorr, 30 mTorr, 35 mTorr, 40 mTorr, 45 mTorr or 50 mTorr, or any value between any two of the aforementioned pressure values.

[0094] In some embodiments, when using the plasma of the first gas and the second gas for adsorption and reaction, the source power is 200 W to 2000 W. For example, the source power can be 200 W, 500 W, 800 W, 1000 W, 1200 W, 1500 W, 1800 W, or 2000 W, or any value between any two of the aforementioned source power values.

[0095] In some embodiments, when using the plasma of the first gas and the second gas for adsorption and reaction, the bias power is 5 W to 30 W. For example, the bias power can be 5 W, 6 W, 8 W, 10 W, 15 W, 20 W, 25 W, or 30 W, etc., or any value between any two of the aforementioned bias power values.

[0096] In some embodiments, when performing the first processing step, the second processing step is also used simultaneously to perform a second processing on the organic mask pattern 12. The method includes: using the plasma of the second gas to bombard the surface of the organic mask pattern 12 to improve the etch resistance of the organic mask pattern 12 through modification.

[0097] In some embodiments, the second gas used in the second processing step is the same as the second gas used when performing the first processing step. For example, the second gas is both hydrogen bromide gas.

[0098] When using hydrogen bromide gas as the second gas and oxygen as the first gas to perform the first processing on the sidewalls of the formed first trench intermediate structure 141, through the hydrogen bromide plasma, the photoresist material of the organic mask pattern 12 can also be modified simultaneously to improve the etch resistance of the organic mask pattern 12. The principle is as follows: Through the action of the hydrogen bromide plasma, the C=O, C-O, and C-H chemical bonds in the photoresist material of the organic mask pattern 12 are broken and reorganized, causing the CH3 group to become two CH2 groups. The two CH2 groups are more likely to recombine chemical bonds. By recombination, a high-molecular polymer chain is formed, changing the C / H ratio of the photoresist material, making the photoresist material more stable in structure, thus improving the etch resistance of the photoresist, and therefore improving the etch blocking ability of the upper organic mask pattern 12 during the deep silicon etching process, that is, improving the etch selectivity of the organic mask pattern 12.

[0099] In some embodiments, after each completion of the periodic cycle steps of the preset number of etching processes, a first processing and a second processing are performed once. In other words, the second processing is completed synchronously during the adsorption and reaction process of the first processing.

[0100] Thereafter, the sidewall surface of the first trench intermediate structure 141 is bombarded with the plasma of the third gas in a mixed state and the plasma of the fourth gas to remove the first reaction product layer and the second reaction product layer, so as to remove at least part of the protrusions 16 and smooth the sidewalls. The plasma of the third gas and the plasma of the fourth gas are obtained by ionizing the third gas and the fourth gas introduced into the process chamber.

[0101] In some embodiments, the third gas includes a fluorine-based gas, such as CF4 or the like.

[0102] In some embodiments, the fourth gas includes a noble gas, such as argon or the like.

[0103] In this embodiment, low-energy fluoride ions (F - ) and argon ions (Ar + ) are used to bombard the sidewall surface of the first trench intermediate structure 141 to etch and remove the silicon oxide on the protrusions 16 and desorb the tetrabromosilane to be removed from the sidewalls, so as to form a relatively smooth new sidewall. Among them, the fluoride ions react with the silicon oxide on the protrusions 16 to decompose the silicon oxide, generating gaseous silicon tetrafluoride (SiF4) which is removed from the sidewalls.

[0104] In some embodiments, when using the plasma of the third gas and the fourth gas to remove the reaction product layer, the temperature is -20°C to 60°C. For example, the temperature can be -20°C, -10°C, 0°C, 10°C, 20°C, 30°C, 40°C, 50°C or 60°C, etc., or any value between any two of the foregoing temperature values.

[0105] In some embodiments, when using the plasma of the third gas and the fourth gas to remove the reaction product layer, the time is 0.5 s to 2 s. For example, the time can be 0.5 s, 0.6 s, 0.7 s, 0.8 s, 0.9 s, 1 s, 1.1 s, 1.3 s, 1.5 s, 1.7 s or 2 s, or any value between any two of the foregoing time values.

[0106] In some embodiments, when using the plasma of the third gas and the fourth gas to remove the reaction product layer, the pressure is 2 mTorr to 10 mTorr. For example, the pressure can be 2 mTorr, 3 mTorr, 4 mTorr, 5 mTorr, 6 mTorr, 7 mTorr, 8 mTorr, 9 mTorr or 10 mTorr, or any value between any two of the foregoing pressure values.

[0107] In some embodiments, when using the plasma of the third gas and the fourth gas to remove the reaction product layer, the source power is 50 W to 500 W. For example, the source power can be 50 W, 80 W, 100 W, 200 W, 300 W, 400 W, or 500 W, or any value between any two of the foregoing source power values.

[0108] In some embodiments, when using the plasma of the third gas and the fourth gas to remove the reaction product layer, the bias power is 5 W to 30 W. For example, the bias power can be 5 W, 6 W, 8 W, 10 W, 15 W, 20 W, or 30 W, etc., or any value between any two of the foregoing bias power values.

[0109] In some embodiments, when using the plasma of the third gas and the fourth gas to remove the reaction product layer, the total flow rate of the third gas and the fourth gas is 20 sccm to 200 sccm. For example, the flow rate can be 20 sccm, 50 sccm, 80 sccm, 100 sccm, 130 sccm, 160 sccm, or 200 sccm, or any value between any two of the foregoing flow rate values.

[0110] In some embodiments, when using the plasma of the third gas and the fourth gas to remove the reaction product layer, the flow rate ratio of the third gas to the fourth gas is 1:1 to 1:3. For example, the flow rate ratio can be 1:1, 1:2, or 1:3, and is not limited thereto.

[0111] After removing the reaction product layer using the plasma of the third gas and the fourth gas as described above, the newly formed sidewall surface becomes smoothed, thereby reducing the roughness of the sidewall surface, as Figure 4 shown in (b). The sidewall topography of the processed first trench intermediate structure 141 is as Figure 5 shown. Compared with Figure 3 , it can be seen that the sidewall is significantly smoothed, resulting in a significant reduction in the roughness of the sidewall. Thus, the passivation layer deposited in subsequent cycles can more uniformly cover the smoothed upper sidewall surface after processing, enabling a good sidewall protection effect with a relatively thin deposition thickness, and effectively avoiding local rough peaks (Ra > 5 nm) caused by random deposition of C-F polymers on the sidewall.

[0112] After that, based on the processed first trench intermediate structure 141, the above-described etching process can be used to continue etching the substrate 10 below the first trench intermediate structure 141 to form a deeper trench. And the above-described first processing process can be used to perform the first processing on the sidewall.

[0113] Step S14: Using an etching process, the substrate under the first trench intermediate structure is continuously etched in a periodic cycle for a preset number of times to successively form a second trench intermediate structure under the first trench intermediate structure, and a first treatment process is used to perform a first treatment on the second trench intermediate structure.

[0114] Reference Figure 6 . In some embodiments, the same method as that for forming the first trench intermediate structure 141 is adopted, that is, using an etching process and taking the organic mask pattern 12 as a mask, the substrate 10 under the bottom of the first trench intermediate structure 141 is etched again in a periodic cycle for a preset number of times to successively form a second trench intermediate structure 142 under the first trench intermediate structure 141 (for ease of understanding, Figure 6 the original bottom of the first trench intermediate structure 141 is schematically shown by an arc-shaped dotted line). The second trench intermediate structure 142 (second intermediate structure) and the first trench intermediate structure 141 together form an intermediate structure formed before the deep trench is formed.

[0115] In this embodiment, the preset number n can also be set to 2 times. The formed second trench intermediate structure 142 is as Figure 6 shown. Among them, after another 2 periodic cycle steps, 2 scalloped stripes 15 will also be formed on the sidewall of the newly formed second trench intermediate structure 142 etched under the first trench intermediate structure 141 with the sidewall treated (reference Figure 3 ). The bottom of each scalloped stripe 15 also has a recessed portion 17, and the junction of two adjacent scalloped stripes 15 also has a protruding portion 16, so that the sidewall of the second trench intermediate structure 142 has a rough surface topography ( Figure 6 the protruding degree of the protruding portion 16 on the sidewall of the second trench intermediate structure 142 shown by a vertical dotted line is greater than that of the sidewall of the first trench intermediate structure 141 after treatment for easy comparison). Therefore, the same first treatment method as in the previous step is also needed to treat the sidewall of the second trench intermediate structure 142 to remove the thick passivation layer on the sidewall and improve the rough topography of the sidewall surface. The sidewall topography of the treated second trench intermediate structure 142 is as Figure 7 shown. It can be seen that Figure 6 the 2 scalloped stripes 15 on the sidewall of the second trench intermediate structure 142 shown have been significantly eliminated in terms of the protruding degree after treatment, making Figure 7 the overall sidewall topography of the treated second trench intermediate structure 142 shown become relatively smoothed and approach the smoothed topography of the sidewall of the treated first trench intermediate structure 141 ( Figure 7In the figure, the vertical dotted line reflects the situation where the side walls of the processed second trench intermediate structure 142 are consistent with the side walls of the first trench intermediate structure 141 for easy comparison), so that the roughness of the overall side walls is significantly reduced. For the specific process of processing the side walls of the second trench intermediate structure 142, reference can be made to the corresponding description in step S13 and combined with Figure 4 to understand, and details will not be repeated.

[0116] Step S15: Repeat step S14 until a deep trench with a target depth is formed on the substrate.

[0117] In some embodiments, the method of step S13 and step S14 can be adopted to continue etching the substrate 10 in the depth direction, that is, by using the method of forming the first trench intermediate structure 141 and the second trench intermediate structure 142, using an etching process, with the organic mask pattern 12 as a mask, the substrate 10 under the bottom of the second trench intermediate structure 142 is etched again for a preset number of periodic cycles, so as to continue to form a new second trench intermediate structure (not shown in the figure) under the second trench intermediate structure 142, and a new intermediate structure with a deeper depth before the formation of the deep trench is obtained. And by using the same processing method as described above, the side walls of the new second trench intermediate structure are subjected to the first treatment to remove the excessive passivation layer on the side walls and improve the rough morphology of the side wall surface.

[0118] And so on, the etching process and the first treatment process are repeated to sequentially form one or more second trench intermediate structures under the first intermediate structure, and after each new second trench intermediate structure is formed, the new second trench intermediate structure is subjected to the first treatment until a deep trench 14 (a high aspect ratio etching structure) with a target depth and processed side walls composed of each intermediate structure is formed on the substrate 10, as Figure 8 shown.

[0119] Each process of adsorption and reaction and removal of the reaction product layer in the above first treatment process is regarded as one treatment cycle. After every 1 to 2 periodic cycle steps of the etching process, at least 1 treatment cycle is inserted. After the last treatment of the last second trench intermediate structure formed before the formation of the deep trench 14, the deep trench 14 with smooth side walls and high perpendicularity of the completed structure is obtained.

[0120] It should be noted that as the etching depth continuously increases and the aspect ratio becomes larger and larger, the process of the etching reactants generated in the etching process diffusing upward from the bottom and volatilizing out becomes more and more difficult. As a result, the phenomenon that the deeper the etching depth, the more polymers remain at the bottom occurs. Therefore, when the etching depth is deeper, the time of the deposition step in the etching process cycle can be shortened (compared with the etching step), so that the polymers generated in the deposition step are also correspondingly reduced, thereby maintaining the same degree of polymer residue on the sidewalls from the upper part to the lower part, which is beneficial to the control and optimization of the two-step time of adsorption and reaction and removal of the reaction product layer in the first treatment process, especially for the control and optimization of the reaction time for removing polymers in the first treatment process.

[0121] In some embodiments, as the etching depth continuously increases, the reaction time for removing polymers in the first treatment process can remain unchanged or be slightly lengthened to facilitate the full volatilization of the volatiles generated by the reaction.

[0122] In some embodiments, as the etching depth continuously increases, the temperature during the etching process can be gradually increased appropriately to increase the etching effect on the bottom of the deep trench, which is beneficial to adjusting the uniformity of the upper, middle, and lower dimensions of the obtained deep trench and improving the perpendicularity of the sidewalls of the deep trench.

[0123] In some embodiments, the critical dimension of the deep trench 14 can be below 50 nm, and the aspect ratio of the deep trench 14 can be greater than or equal to 100:1.

[0124] After that, the following step S16 can also be included.

[0125] Step S16: Remove the organic mask pattern.

[0126] In some embodiments, after forming the deep trench 14, the surface of the substrate 10 is bombarded with the plasma of the sixth gas to remove the organic mask pattern 12 and the carbon-based protective film 13 on the surface of the substrate 10. The plasma of the sixth gas is obtained by ionizing the sixth gas introduced into the process chamber. The semiconductor structure obtained after removing the organic mask pattern 12 and the carbon-based protective film 13 is as Figure 9 shown.

[0127] In some embodiments, the sixth gas includes an oxidizing gas. Among them, the oxidizing gas can be, for example, oxygen, and nitrogen can be simultaneously introduced as a dilution gas.

[0128] In a second aspect, an embodiment of the present application also provides a semiconductor structure, which is obtained by using the semiconductor structure manufacturing method provided in any one of the embodiments in the first aspect as described above.

[0129] Reference Figure 9。In some embodiments, the semiconductor structure includes a substrate 10 and deep trenches 14 formed on the substrate 10 using the semiconductor structure manufacturing method of the above embodiments.

[0130] In some embodiments, the semiconductor structure can be applied to MEMS devices (such as accelerometers, gyroscopes, pressure sensors, etc.), 3D integration and advanced packaging (such as through-silicon via (TSV) fabrication, chip stacking, etc.), optical devices (such as optical waveguides, diffraction gratings, etc.), power devices (such as trench structures of insulated gate bipolar transistors (IGBTs), power metal-oxide-semiconductor field effect transistors (MOSFETs), etc.).

[0131] In a third aspect, an embodiment of the present application further provides a plasma processing device, which is used to perform the semiconductor structure manufacturing method corresponding to the above embodiments to form deep trenches 14 on the semiconductor structure corresponding to the above embodiments. The plasma processing device includes an inductively coupled plasma (ICP) etching device, a capacitively coupled plasma (CCP) etching device, etc.

[0132] In other aspects, an embodiment of the present application further provides an electronic device, including the semiconductor structure of the above embodiments or a semiconductor structure obtained using the semiconductor structure manufacturing method of the above embodiments. The electronic device can be a storage device, a mobile phone, a computer, a tablet computer, an electronic instrument, a television, an artificial intelligence device, etc.

[0133] In summary, the embodiments of the present application organically combine the etching process and the sidewall treatment technology, and alternately cycle to balance the etching rate and the sidewall quality, thereby achieving a high etching rate and high etching accuracy for the high aspect ratio etching structure, increasing the diffusion coefficient, improving the reaction gas transport efficiency, solving the problems of plasma chemical residue and ion shadow effect, and effectively improving the uniformity and roughness of the local C-F polymer. Therefore, it can optimize the defects of the existing etching process and meet the stringent requirements for deep silicon vertical topography and high aspect ratio in advanced semiconductor manufacturing, so that a deeper silicon etching with a higher aspect ratio and smaller nanoscale size can be achieved compared with the prior art.

[0134] The above are only the preferred embodiments of the present application, and the embodiments are not intended to limit the protection scope of the present application. Therefore, all equivalent changes made by using the specification and drawings of the present application should be equally included in the protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming a plurality of organic mask patterns on the surface of the substrate; Using an etching process and using the organic mask patterns as masks, performing periodic cyclic etching on the substrate a preset number of times to form a first intermediate structure on the substrate; Using a first processing process different from the etching process to perform a first treatment on the first intermediate structure, including: Using a first gas and a second gas to remove a partial thickness of the passivation layer deposited on the sidewalls of the first intermediate structure and react with the substrate material on the surface of the protruding portion exposed on the sidewalls to generate a reaction product layer; and Using a third gas and a fourth gas to remove the reaction product layer to remove at least a part of the protruding portion; Repeatedly performing the etching process and the first processing process to sequentially form one or more second intermediate structures below the first intermediate structure, and performing the first treatment on each newly formed second intermediate structure until a high aspect ratio etching structure composed of each intermediate structure is formed on the substrate.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein When performing the first processing process, by using the plasma of the first gas in a mixed state and the plasma of the second gas to react with the passivation layer, a partial thickness of the passivation layer deposited on the sidewalls is removed to adjust the thickness uniformity of the passivation layer on the sidewalls; by reacting the plasma of the first gas with the substrate material on the surface of the exposed protruding portion to in-situ oxidize and generate a first reaction product layer, and reacting the plasma of the second gas with the substrate material on the surface of the exposed protruding portion to generate a second reaction product layer with low volatility, and using the plasma of the third gas in a mixed state and the plasma of the fourth gas to bombard the sidewalls to remove the first reaction product layer and the second reaction product layer to remove at least a part of the protruding portion and smooth the sidewalls.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein, When performing the first processing process, a second processing process is further used to perform a second treatment on the organic mask patterns, including: Using the plasma of the second gas to bombard the surface of the organic mask patterns to improve the etching resistance of the organic mask patterns by modification.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein The etching process includes a periodic cyclic step formed by sequentially performing a deposition step, a first etching step, and a second etching step. After each completion of the preset number of the periodic cyclic steps, the first treatment and the second treatment are performed once.

5. The method for manufacturing a semiconductor structure according to claim 2, wherein The substrate material includes silicon, the first gas includes oxygen, the first reaction product layer includes a silicon oxide layer, the second gas includes hydrogen bromide, the second reaction product layer includes a silicon tetrabromide layer; and / or, the third gas includes a fluorine-based gas, and the fourth gas includes a noble gas.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein, Before forming the first intermediate structure, it further includes: using the plasma of a fifth gas to bombard the interface of the substrate to form a carbon-based protective film; after forming the high aspect ratio etching structure, it further includes: using the plasma of a sixth gas to remove the organic mask patterns and the carbon-based protective film.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein, The organic matter includes photoresist, the fifth gas includes noble gas, and the sixth gas includes oxidizing gas.

8. The method for manufacturing a semiconductor structure according to claim 4, wherein The temperature for performing the etching process and the first treatment process is lower than 60°C. The time for performing the deposition step, the first etching step, and / or the second etching step is 0.1 s to 2 s. The time for using the first gas and the second gas is 0.5 s to 2 s. The time for using the third gas and the fourth gas is 0.5 s to 2 s.

9. The method for manufacturing a semiconductor structure according to claim 1, wherein The preset number of times is 1 to 2 times.

10. A semiconductor structure, characterized in that, Obtained by using the semiconductor structure manufacturing method according to any one of claims 1-9.

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