Socket for testing before common sealing

Abstract

The invention discloses a socket for testing before co-packaging, which is used for testing a co-packaged chip with a plurality of chips to be tested and non-chips to be tested before co-packaging, and comprises a plurality of frame guide surfaces and a plurality of temperature control plate guide surfaces arranged on the non-chips to be tested, and the frame guide surface and the temperature control plate guide surface are connected end to end and tightly surround the to-be-tested chip or the mounting position of the to-be-tested chip so as to guide the to-be-tested chip to be placed in the mounting position. The invention aims to provide the socket for the collaborative test of the multi-chip particles before co-packaging, which plays a role in guiding and fixing the to-be-tested chip in the co-packaged chip.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip packaging and testing, and particularly relates to a socket for collaborative testing before co-packaging. Background Art

[0002] The co-packaged chip of HBM (High Bandwidth Memory) and GPU (Graphics Processing Unit) is an advanced heterogeneous integration technology. By integrating HBM and GPU in the same package, it significantly improves the memory bandwidth and energy efficiency, meeting the requirements of high-performance computing, artificial intelligence, graphics rendering and other fields. The co-packaged chip of HBM and GPU significantly improves the performance and energy efficiency of the GPU through high-bandwidth, low-power and high-integration design, and is widely used in artificial intelligence, high-performance computing, graphics rendering and other fields. Despite challenges such as high cost and complex thermal management, with the continuous progress of technology, the co-packaged chip of HBM and GPU will become the mainstream solution for future high-performance computing.

[0003] The test method of HBM is different from that of traditional DRAM, mainly because HBM has high bandwidth, stacked structure and complex interconnection technologies (such as TSV and micro-bumps). The test methods of HBM cover wafer-level testing, post-stacking testing, package-level testing and system-level testing, and need to solve technical challenges such as high bandwidth, stacked structure and complex interconnection. By combining advanced test equipment and technologies, the performance, reliability and yield of HBM can be ensured to meet the requirements of high-performance computing, artificial intelligence and other fields.

[0004] In package-level testing, after the HBM chip and the logic chip (such as GPU / CPU) are co-packaged (such as Figure 1 and Figure 2 ), the entire package is tested. Since the HBM chip and the GPU / CPU have been fully soldered to the package substrate, once any one of the HBMs is found to be unqualified, then this chip is defined as a defective product, regardless of the performance of the remaining HBM chips or the logic chips GPU / CPU. Therefore, it is necessary to perform a system-level SLT test by putting all the necessary several HBMs and the logic chips GPU / CPU together before soldering.

[0005] However, there are some problems with the current pre-co-packaging test, which are illustrated by the following examples: As Figure 1 and Figure 2 shown is a co-packaged chip, including 4 HBM chips 6 and a logic chip 7 GPU / CPU. If the HBM chips are relatively close to other chip particles (such as Figure 1 and Figure 2As shown in the figure, the HBM chip is very close to the logic chips GPU / CPU. Then, it is impossible for the test engineer to design a separate socket for this HBM chip alone. Otherwise, the socket may hit other chips that are too close, such as Figure 1 and Figure 2 the logic chips GPU / CPU shown in the figure. If the chip spacing is deliberately increased to design a socket specifically for testing, then this test condition is inconsistent with the actual use condition (the chip particles are very close). SUMMARY OF THE INVENTION

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a pre-co-packaging test socket that plays a guiding and fixing role for the chips to be tested in the co-packaged chips.

[0007] The solution of this application provides a pre-co-packaging test socket for performing pre-co-packaging tests on co-packaged chips having several chips to be tested and non-chips to be tested, including: a plurality of frame guiding surfaces and several thermostatic plate guiding surfaces provided on the non-chips to be tested. The frame guiding surfaces and the thermostatic plate guiding surfaces are closely surrounded by connecting the head and the tail around the chip to be tested or the installation position of the chip to be tested to guide the chip to be tested into its installation position. The thermostatic plate in this application includes both traditional active and passive heat dissipation cold plates and other thermostatic modules, such as heaters, such as TEC modules, or combinations of the above.

[0008] Specifically, both the frame guiding surface and the thermostatic plate guiding surface are inclined surfaces inclined towards the chip to be tested or the installation position of the chip to be tested.

[0009] Further, it also includes a thermostatic plate provided on the non-chip to be tested, and the thermostatic plate guiding surface is provided on the side of the thermostatic plate facing the chip to be tested or the installation position of the chip to be tested.

[0010] Further, it also includes a frame fixing surface and a thermostatic plate fixing surface; the frame fixing surface and the thermostatic plate fixing surface are respectively connected to the frame guiding surface and the thermostatic plate guiding surface from below to fix the chip to be tested located in the installation position.

[0011] Specifically, both the frame fixing surface and the thermostatic plate fixing surface are perpendicular to the chip to be tested or perpendicular to the packaging substrate of the chip to be tested.

[0012] Further, it also includes a hollow socket frame. The chip to be tested and the non-chip to be tested are arranged in the hollow part of the socket frame, and the frame guiding surface and the frame fixing surface are arranged on the inner side of the socket frame facing the chip to be tested.

[0013] Specifically, the frame guiding surface is formed by chamfering the inner side of the socket frame.

[0014] Further, an avoidance portion is formed by the inner side surface of the socket frame being recessed at a corner near the chip under test, or an avoidance portion is formed by the inner side surface of the socket frame being recessed at a corner near the installation position of the chip under test.

[0015] Specifically, the non-chip under test can be various chip particles such as logic chips, computing power chips, memory chips, or photon chips, and the chip under test can be various chip particles such as logic chips, computing power chips, memory chips, or photon chips. For the same type of chips, one or several can be used as non-chips under test, and the remaining chips of this type (which can also be combined with other types of chips) can be used as the chip under test.

[0016] The improvements of the present application bring the following advantages: The socket provided by the present application positions and guides the chip under test to be accurately placed into its installation position through multiple frame guiding surfaces and the temperature control board guiding surface provided on the non-chip under test, enabling the chip under test to be accurately and quickly installed, and at the same time solving the problem that it is impossible to design and install a socket due to the too-close distance between chip particles. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic structural diagram of the co-packaged chip of HBM and GPU according to an embodiment of the present application;

[0018] Figure 2 It is an exploded schematic diagram of the co-packaged chip of HBM and GPU according to an embodiment of the present application;

[0019] Figure 3 It is a schematic diagram of the process of placing the chip under test into the socket frame according to an embodiment of the present application;

[0020] Figure 4 It is a schematic structural diagram of the socket frame according to an embodiment of the present application;

[0021] Figure 5 It is a schematic diagram of a socket for pre-co-packaging test according to an embodiment of the present application applied to a co-packaged chip;

[0022] Figure 6 It is a schematic diagram of the installation of a socket for pre-co-packaging test according to an embodiment of the present application applied to a co-packaged chip;

[0023] Figure 7 It is a schematic diagram of soldering the non-chip under test to the packaging substrate according to an embodiment of the present application;

[0024] Figure 8 It is a schematic diagram of using a socket for pre-co-packaging test to place the chip under test according to an embodiment of the present application;

[0025] Figure 9 It is a schematic structural diagram of the temperature control board with a temperature control board guiding surface and a temperature control board fixing surface according to an embodiment of the present application;

[0026] Figure 10 This is a schematic diagram of the structure of a chip in which HBM and GPU are co-sealed in an embodiment of the present application;

[0027] Figure 11 This is a schematic diagram of a socket for testing before co-sealing applied to a co-sealed chip according to an embodiment of the present application;

[0028] Figure 12 This is a schematic diagram of the installation of a socket for testing before co-sealing applied to a co-sealed chip according to an embodiment of the present application;

[0029] Among them, packaging substrate-1; non-chip to be tested-2; socket frame-3; frame guide surface-31; frame fixing surface-32; temperature control board-4; temperature control board guide surface-41; temperature control board fixing surface-42; chip to be tested-5; installation position of chip to be tested-51; HBM chip-6; logic chip-7; air avoidance part-8. DETAILED DESCRIPTION

[0030] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] See also Figure 3-12 The present application embodiment provides a socket for testing a co-sealed chip having a plurality of chips to be tested 5 and non-chips to be tested 52 before co-sealing, comprising a plurality of guide surfaces which are connected end to end and tightly surround the chip to be tested 5 or the mounting position 51 of the chip to be tested 5, wherein one or more guide surfaces are provided on the non-chip to be tested 52, and together with other guide surfaces, provide a guiding and guiding function for placing the chip to be tested 5 into its mounting position 51.

[0032] As an embodiment, the guide surface includes a plurality of frame guide surfaces 31 and a plurality of temperature control board guide surfaces 41 arranged on the non-test chip 52. The frame guide surfaces 31 and the temperature control board guide surfaces 41 are connected end to end and tightly surround the test chip 5 or the mounting position 51 of the test chip 5 to guide the test chip 5 into its mounting position 51.

[0033] The frame guide surface 31 and the temperature control board guide surface 41 should be arranged in a manner that is most conducive to guiding the placement of the chip 5 to be tested. Figure 3-12 As shown, each side of the chip to be tested 5 or its mounting position 51 is provided with a guide surface, and the guide surface is as close to the chip to be tested 5 or its mounting position 51 as possible, so as to accurately and efficiently guide the chip to be tested 5 to be placed in its mounting position 51.

[0034] The working principle of the present application is as follows: First, the non-chip-to-be-tested 52 is fixed (such as by welding, pasting, bonding, etc.) on the packaging substrate 1, and then the temperature control board guiding surface 41 is arranged on the non-chip-to-be-tested 52, on the side facing and close to the mounting position 51 of the chip-to-be-tested 5, and a frame guiding surface 31 is arranged outside the chip-to-be-tested 5, so that the frame guiding surface 31 and the temperature control board guiding surface 41 are closely surrounded around the mounting position 51 of the chip-to-be-tested 5 end to end; or first a frame guiding surface 31 is arranged outside the chip-to-be-tested 5, and then the temperature control board guiding surface 41 is arranged on the non-chip-to-be-tested 52, on the side facing and close to the mounting position 51 of the chip-to-be-tested 5; finally, the chip-to-be-tested 5 is manually or automatically placed into the corresponding mounting position 51 through the guidance of the guiding surface.

[0035] In the present application, the position where the packaging substrate 1 is located is regarded as the bottom.

[0036] In this embodiment, the chip-to-be-tested 5 is positioned and guided accurately into its mounting position 51 through a plurality of frame guiding surfaces 31 and the temperature control board guiding surface 41 arranged on the non-chip-to-be-tested 52, so that the chip-to-be-tested 5 is installed accurately and quickly, and at the same time, the problem that it is impossible to design and install a socket due to the too-close distance between chip particles is solved.

[0037] As one specific example, the co-packaged chips to be tested before co-packaging are as Figure 1-2 shown. The co-packaged chips include a packaging substrate 1, a logic chip GPU / CPU arranged in the middle of the packaging substrate 1, and two pairs of HBM particles arranged on both sides of the GPU / CPU chip respectively.

[0038] In the existing pre-co-packaging test process, it is necessary to manually or use an automated robotic arm to place a socket. The bottom of the socket is provided with probes (such as but not limited to pogo pins), and these probes can be aligned with the contacts at the bottom of the chip and can well connect the electrical signals between the packaging substrate 1 (or the test main board, EVB or Loadboard) and supply power to the chip-to-be-tested 5.

[0039] As Figure 3 , 4 shown, in order to more accurately and efficiently install the chip-to-be-tested 5 on a certain mounting position 51 of the packaging substrate 1 and prevent the chip-to-be-tested 5 from shifting during the placement process, the present application designs a hollow socket frame 3 with a guiding surface, which is used to play a role in positioning and guiding the placement of the chip-to-be-tested 5. The chip-to-be-tested 5 is placed in the hollow part of the socket frame 3, and the frame guiding surface 31 is arranged inside the socket frame 3 close to the chip-to-be-tested 5. The process of placing the chip-to-be-tested 5 into the socket frame 3d is as Figure 3 shown ( Figure 3Only a single chip 5 to be tested is shown to be placed in the socket frame 3, rather than a co-sealed chip. Figure 3 The frame guide surface 31 is a chamfered surface or an inclined surface on the inner side of the socket frame 3 that is inclined toward the chip to be tested 5 .

[0040] However, as mentioned above, in the case of a co-sealed chip having a plurality of closely arranged chips to be tested 5, such as the chips listed in this embodiment (eg Figure 1-2 As shown in the figure, since the HBM particles are close to other chip particles and the HBM is very close to the logic chip GPU / CPU, the test engineer cannot design a socket for the co-sealed chip alone, otherwise the socket may collide with other chips that are too close, such as the logic chip GPU / CPU or HBM particles.

[0041] The HBM particles and the adjacent HBM particles have enough distance to be placed on the frame guide surface 31 of the socket frame 3, such as Figure 5 , 6 As shown, the socket frame 3 is roughly in the shape of a Japanese character interrupted by a horizontal line in the middle, and guide surfaces are provided on both sides of the two horizontal lines extending from the middle. However, if the HBM particles are too close to the logic chip, it is impossible to add a guide surface between the HBM particles and the logic chip GPU / CPU. This is a limiting factor that prevents the DUT test chip 5 of the HBM particles from testing their overall performance according to the actual test environment (such as the actual distance between various chip particles) before co-sealing and welding with the logic chip GPU / CPU.

[0042] like Figure 5 and Figure 6 As shown, if the test target DUT is a memory chip such as HBM, and the test purpose is to check the performance of the memory chip such as HBM when it runs together with a logic chip such as CPU / GPU, then the logic chip such as CPU / GPU does not belong to the chip to be tested 5 (that is, it is not the target to be tested), then these non-chips to be tested 52 can be permanently soldered to the packaging substrate 1 (such as Figure 7 and Figure 8 As shown), a square temperature control board 4 is installed on the non-test chip 52 (logic chip CPU / GPU) to cool down or control the temperature. Figure 5 and Figure 6 If the HBM particle is not shown, a socket is needed for temporary positioning. However, due to the distance between the HBM particle and the GPU / CPU, a guide surface cannot be inserted between the two.

[0043] The present application cleverly uses one side of the temperature control board 4 of the chip after welding as a supplement to the insufficient guide surface ( Figure 9 ).like Figure 5 , Figure 6 and Figure 8As shown, when the HBM particles are very close to the GPU / CPU, the socket only provides the guiding surfaces on three sides of this HBM particle, and the fourth guiding surface is replaced by the chamfered surface on this side of the temperature control board 4 ( Figure 9 ) to act as the guiding surface for the chip under test 5, that is, the temperature control board guiding surface 41 inclined towards the chip under test 5 or its installation position 51. In this way, each HBM particle to be tested has a guiding surface tightly surrounding its installation position 51 for accurately and efficiently positioning and guiding the HBM particle to be tested into its corresponding installation position 51.

[0044] The temperature control board guiding surface 41 can be formed by chamfering.

[0045] As one specific example, in the foregoing embodiment, there is not enough clearance between the HBM particles and the GPU / CPU, but there is enough clearance between the HBM particles themselves, and this solution can use the "day" - shaped socket frame 3 and the square temperature control board 4 as shown in Figure 5-8 However, if there is not only not enough clearance between the HBM particles and the GPU / CPU, but also the gap between the HBMs is very small (as shown in Figure 10 ), and the guiding surfaces cannot be inserted, then a trade - off can be made. For example, among two very close HBM particles, one is selected as the chip under test 5, and the other HBM, like the GPU / CPU, is permanently soldered to the packaging substrate 1 and cannot be used as the chip under test 5, as shown in Figure 11 . The shape of the temperature control board 4 is modified according to the specific positions and dimensions of the non - chip - under - test HBMs and non - chip - under - test GPU / CPUs in the actual Figure 11 , and the socket frame 3 and its guiding surfaces are modified according to the specific positions, dimensions, and number of the specific chip - under - test 5 particles.

[0046] Specifically, use a "mouth" - shaped socket frame 3 and a "Z" - shaped temperature control board 4, and then by setting a frame guiding surface 31 on the inner side of the socket frame 3 and a temperature control board guiding surface 41 on the lower side of the "Z" - shaped temperature control board 4, it plays a role in positioning and guiding the placement of the chip under test 5.

[0047] Figure 11 a - d show the implementation process of this solution. Among them, from Figure 11 a to b, these non - chip - under - test chips 52 are soldered and fixed to the packaging substrate 1; from Figure 11 b to c, the "mouth" - shaped socket frame 3 is accurately installed; from Figure 11 c to d, the "Z" - shaped temperature control board 4 is accurately installed, and finally the chip under test 5 (such as the HBM to be tested) is manually or automatically temporarily placed. After the test is completed, replace these tested DUTs with new chips under test 5 and cycle in turn.

[0048] As shown in Figure 4 、9 As shown, as an embodiment, a frame fixing surface 32 connected thereto is further provided below the frame guiding surface 31, and a temperature control board fixing surface 42 connected thereto is further provided below the temperature control board guiding surface 41.

[0049] Both the frame fixing surface 32 and the temperature control board fixing surface 42 are perpendicular to the packaging substrate 1.

[0050] After the chip under test 5 is placed, the frame fixing surface 32 and the temperature control board fixing surface 42 are closely attached to the edges of the chip under test 5 to temporarily fix the chip under test 5 and prevent the chip from shifting during the test.

[0051] As Figure 3 shown, as an embodiment, a plurality of clearance parts 8 are recessed at the inner side surface of the socket frame 3 near the corner of the chip under test 5 to facilitate the placement and installation of the chip under test 5.

[0052] All non-chips under test 52 described in this application not only include the HBM particles shown in the picture, but may also include other particles, such as semiconductor particles such as GPU, CPU, CPO, GDDR, DRAM, capacitor particles, etc. For example, if the chip under test 5 is a GPU / CPU instead of an HBM, then the HBM can be permanently fixed (such as welded) to the packaging substrate, and the temperature control board 4 can be designed and crimped to these non-chips under test 52 (HBM particles) according to the specific position and shape of the non-chips under test 52 (HBM particles) in this case, while the chip particles GPU / CPU in this case can be repeatedly positioned, tested and randomly replaced by the guiding surface. Therefore, the chip nature of the chip under test 5 and the non-chips under test 52 is not fixed as an HBM, but is changed accordingly according to specific requirements.

[0053] The number of memory particles (such as HBM) and GPU / CPU is not fixed at 4 and 1, but can be changed according to the specific number, such as 2 HBMs, 3 HBMs, or 6 HBMs, or 2 GPU / CPUs, or 4 GPU / CPUs, etc. This application does not limit the number of these chip particles.

[0054] This application describes the frame structure of the socket, and the electrical connection parts (such as but not limited to pogopin, elastomersocket, interposer, TSV, etc.) are omitted from the description.

[0055] As introduced in this application: during the test, the distance between the particles should be kept as consistent as possible with the distance after actual packaging. However, if necessary, their distance can be appropriately increased to provide more socket space, but the cost is that it may affect the electrical signals and test results, mainly depending on whether the tester can accept this difference.

[0056] If the co-packaged chip contains multiple chip particles of the same type, such as two or four or six HBM particles, then one, several or all of these particles can be selected as the chips to be tested (the remaining non-tested particles can be soldered to the packaging substrate), rather than all such particle chips must be used as the chips to be tested.

[0057] As described above, only the preferred specific embodiments of the present invention are provided, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A socket for pre - co - packaging testing, which is used to perform pre - co - packaging testing on a co - packaged chip having several chips to be tested and non - chips to be tested, characterized in that, Comprising: A plurality of frame guiding surfaces and several temperature control board guiding surfaces provided on the non-chip under test. The frame guiding surfaces and the temperature control board guiding surfaces are closely surrounded around the chip under test or the installation position of the chip under test in a head-to-tail connection manner to guide the chip under test into its installation position.

2. The socket for pre - co - packaging testing according to claim 1, characterized in that, Both the frame guiding surface and the temperature control board guiding surface are inclined surfaces inclined towards the chip under test or the installation position of the chip under test.

3. The socket for pre - co - packaging test according to claim 1, characterized in that, It further includes a temperature control board provided on the non-chip under test, and the temperature control board guiding surface is provided on the side of the temperature control board facing the chip under test or the installation position of the chip under test.

4. A socket for pre - co - packaging testing according to any one of claims 1 - 3, characterized in that, It further includes a frame fixing surface and a temperature control board fixing surface; the frame fixing surface and the temperature control board fixing surface are respectively connected to the frame guiding surface and the temperature control board guiding surface from below to fix the chip under test located in the installation position.

5. The socket for pre - co - packaging test according to claim 4, characterized in that, Both the frame fixing surface and the temperature control board fixing surface are perpendicular to the chip under test or perpendicular to the packaging substrate of the chip under test.

6. The socket for pre - co - packaging test according to claim 4, characterized in that, It further includes a hollow socket frame, the chip under test and the non-chip under test are arranged in the hollow part of the socket frame, and the frame guiding surface and the frame fixing surface are arranged on the inner side of the socket frame facing the chip under test.

7. The socket for pre - co - packaging test according to claim 6, characterized in that, The frame guiding surface is formed by an inner chamfer of the socket frame.

8. The socket for pre - co - packaging test according to claim 6, characterized in that, The inner side surface of the socket frame is recessed to form a clearance portion at the corner near the chip under test, or the inner side surface of the socket frame is recessed to form a clearance portion at the corner near the installation position of the chip under test.

9. A socket for pre - co - packaging testing according to any one of claims 1 - 3, characterized in that, The non-chip under test is a logic chip, or a computing power chip, or a memory chip, or a photon chip, and the chip under test is a logic chip, or a computing power chip, or a memory chip, or a photon chip.

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