Wafer level packaging structure

Abstract

The invention discloses a wafer level packaging structure, and belongs to the technical field of wafer packaging. The RDL circuit is arranged on the substrate; and the circular pad is arranged on the outer side of the RDL circuit. The circular pad is designed in the area except the RDL circuit design, the electroplating uniformity can be further effectively improved, through the optimization design, in the electroplating process, current distribution is more uniform, therefore, it is ensured that the thickness of a plating layer is consistent, the packaging quality and reliability are improved, the arrangement of the circular pad is beneficial to forming a high-density discontinuous Cu / PI interface, and the packaging quality is improved. The bonding force between different materials in the package is enhanced, the stability of the package structure is improved, and the overall performance of the wafer-level package in a board-level temperature cycle / drop reliability test is remarkably improved, wherein 2P1M / 2P2M (two PI layers and one metal layer) / (two PI layers and two metal layers), the PI layer is a polyimide layer, and the wafer-level package is subjected to a board-level temperature cycle / drop reliability test.

Description

Technical Field

[0001] The present invention belongs to the technical field of wafer packaging, and particularly relates to a wafer-level packaging structure. Background Art

[0002] In traditional wafer-level packaging, there are certain limitations in the processing method of the area outside the redistribution layer (RDL) circuit design. If this area lacks reasonable design, it will lead to poor electroplating uniformity and it is difficult to form an ideal high-density discontinuous copper / polyimide (Cu / PI) interface. This not only affects the overall performance of the packaging, but also makes it difficult to obtain satisfactory results in the board-level temperature cycle (Board level TC) / drop reliability test for 2P1M / 2P2M (2 layers of PI layer and 1 layer of metal layer) / (2 layers of PI layer and 2 layers of metal layer), where the PI layer is the polyimide layer, reducing the reliability and stability of the product in complex usage environments. Summary of the Invention

[0003] In view of the above situation, to overcome the defects of the prior art, the present invention effectively solves the problems in electroplating uniformity and interface formation in traditional packaging methods by optimizing the structure of the area outside the redistribution layer circuit design.

[0004] To achieve the above object, the following technical solution is adopted: The present invention provides a wafer-level packaging structure, including:

[0005] A substrate;

[0006] RDL circuits provided on the substrate;

[0007] Circular pads provided outside the RDL circuits.

[0008] The beneficial effect of the present invention is that circular pads are designed in the area outside the RDL circuit design, which can effectively further improve electroplating uniformity. Through this optimized design, during the electroplating process, the current distribution is more uniform, thus ensuring a consistent coating thickness, improving the quality and reliability of the packaging. The setting of the circular pads helps to form a high-density discontinuous Cu / PI interface, enhance the bonding force between different materials inside the packaging, improve the stability of the packaging structure, and significantly improve the overall performance of the wafer-level packaging in the board-level temperature cycle / drop reliability test. Description of the Drawings

[0009] Figure 1 It is a schematic structural diagram of a wafer-level packaging structure of the present invention;

[0010] Figure 2 It is a top view of a wafer-level packaging structure of the present invention.

[0011] Legend: 1. Substrate; 2. RDL circuit; 3. Circular pad.

[0012] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the present invention and do not constitute a limitation to the present invention. Detailed implementation manners

[0013] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0014] Unless otherwise defined, all professional and scientific terms used herein have the same meaning as those familiar to those skilled in the art. In addition, any methods and materials similar or equivalent to the described content can be applied to the present invention. The preferred implementation methods and materials described herein are only for demonstration purposes and do not limit the content of this application.

[0015] The experimental methods in the following embodiments are all conventional methods unless otherwise specified. The test materials used in the following embodiments are all obtained from commercial channels unless otherwise specified.

[0016] Embodiment

[0017] According to the attached Figure 1-2 , the present invention provides a wafer-level packaging structure, including:

[0018] Wafer:

[0019] The RDL circuit provided on the wafer:

[0020] The RDL circuit is used to realize the electrical connection redistribution between the internal circuit of the chip and the external pins. Its manufacturing process can adopt a method combining photolithography and electroplating. First, a photoresist is coated on the surface of the wafer, and the designed RDL circuit pattern is transferred to the photoresist through the photolithography process to form a photoresist mask with the circuit pattern.

[0021] Next, an electroplating process is carried out. Using copper as the conductive material, under the guidance of the photoresist mask, RDL lines are deposited on the surface of the wafer. Copper has good electrical conductivity and low resistance, which can ensure low loss when signals or currents are transmitted in the RDL lines. The line width and line pitch of the RDL lines are designed according to the high-density requirements of the package. Generally, the line width and line pitch can reach 5μm - 10μm. In this embodiment, the line width of the RDL lines is 8μm and the line pitch is 8μm to meet the electrical performance requirements of high-density packaging.

[0022] Circular pads provided outside the RDL lines:

[0023] The circular pads are located in the area outside the RDL line design. Their function is to improve the electroplating uniformity and form a good high-density discontinuous Cu / PI interface. The material of the circular pads is also copper, the same as that of the RDL lines, which helps to achieve good current conduction and coating growth during the electroplating process.

[0024] The diameter of the circular pads is optimized according to the size of the packaging area and the current distribution requirements, generally between 50μm - 200μm. In this embodiment, the diameter of the circular pads is set to 100μm. The pitch between the circular pads is also carefully calculated to ensure uniform current distribution during the electroplating process. Usually, the pitch between the circular pads is set at 100μm - 300μm. In this embodiment, the pitch between the circular pads is 200μm.

[0025] The circular pads are formed in the same electroplating process as the RDL lines. During the electroplating process, the current will be evenly distributed to the entire packaging area through the circular pads, making the coating thickness on the surface of the RDL lines and the circular pads more consistent, thus improving the quality and reliability of the package. At the same time, the presence of the circular pads helps to enhance the bonding force between copper and polyimide when forming the Cu / PI interface subsequently, improving the stability of the package structure.

[0026] Through the specific settings and process parameters in the above embodiments, the wafer-level packaging structure of the present invention can effectively improve the electroplating uniformity, form a high-quality high-density discontinuous Cu / PI interface, and significantly improve the overall performance of the 3-mask / 4-mask wafer-level chip-scale packaging in the board-level temperature cycle / drop reliability test.

[0027] Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

[0028] The above description of the present invention and its implementation manners is not restrictive. What is shown in the drawings is only one of the implementation manners of the present invention, and the actual application is not limited thereto. Generally speaking, if those of ordinary skill in the art are inspired by it and design, without creative work, similar manners and embodiments to the technical solution without departing from the gist of the present invention, they shall fall within the protection scope of the present invention.

Claims

1. A wafer-level packaging structure, characterized in that: Comprising: A wafer; An RDL circuit disposed on the wafer; A circular pad disposed outside the RDL circuit.

2. The wafer-level packaging structure according to claim 1, wherein: A circular pad disposed outside the RDL circuit, for improving plating uniformity and forming a high-density discontinuous Cu / PI interface.

Images