Chip module, chip module preparation method and electronic equipment

Abstract

The embodiment of the invention provides a chip module, a chip module preparation method and electronic equipment, and belongs to the technical field of chips, chips are arranged on the two opposite faces of a substrate of the chip module, packaging of the chips is achieved through a first packaging piece and a second packaging piece, heat dissipation of the first chip is achieved through a first heat dissipation piece, and the heat dissipation efficiency of the first chip is improved. The layout of the first heat dissipation piece is not limited by the preparation process, the short circuit prevention interval and the like, so that the projection of the first heat dissipation piece can at least partially cover the projection of the heat conduction area of the first chip, the heat dissipation path is shortened, the heat resistance is reduced, and the heat dissipation effect is improved. The end face of the first end of the first heat dissipation piece is recessed inwards relative to the face, back to the substrate, of the second packaging piece, a preset distance is formed between the end face and the face, back to the substrate, of the second packaging piece, and when the packaging layer is thinned to form the second packaging piece, thinning removal depth does not reach the first heat dissipation piece. The problems of layering, cracking and the like at the junction of the side wall of the first heat dissipation piece and the packaging layer are avoided, the grinding operability and reliability of the packaging layer are improved, and the yield is improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and particularly to a chip module, a method for manufacturing a chip module, and an electronic device. Background Art

[0002] With the continuous development of chip packaging technology, chip packaging devices have been widely used in electronic devices such as mobile phones, laptop computers, smart watches, etc. For example, the radio frequency chip module in a mobile phone can integrate chip devices that implement radio frequency functions through packaging, protect the chips, improve the integration degree, and at the same time enhance the performance of the entire radio frequency module.

[0003] Currently, electronic devices are developing towards the trend of "light, thin, short, small" and multi-functionalization, and chip packaging devices are also moving forward in the direction of high density, miniaturization, and high lead count. When the heat dissipation performance of chip packaging devices is poor, it will greatly affect the performance of the chips. Summary of the Invention

[0004] Embodiments of this application provide a chip module, a method for manufacturing a chip module, and an electronic device. The chip module has an outstanding heat dissipation effect, which is beneficial to improving the performance of the chip module.

[0005] In a first aspect of the embodiments of this application, a chip module is provided, which includes a substrate, a first package, and a second package. The substrate has a first surface and a second surface that face away from each other in the thickness direction. The first package is disposed on the first surface, and the second package is disposed on the second surface.

[0006] The chip module further includes a plurality of chips, which are respectively disposed on the first surface and the second surface, and at least part of the chips are wrapped in the first package or the second package. The plurality of chips include a first chip, and the first chip has a heat conduction area for realizing heat conduction contact. The heat generated by the first chip during operation can be transferred to the outside of the first chip through the heat conduction area, so as to realize heat dissipation of the first chip.

[0007] The chip module further includes a first heat sink. The first heat sink is located between the first surface and the side of the second package facing away from the substrate, and at least the first end of the first heat sink is located inside the second package. The first heat sink is used to dissipate heat from the first chip. Compared with the heat dissipation of the chip through the ball grid array composed of solder balls in the related art, different from the layout requirements of the ball grid array, the layout of the first heat sink is not restricted by the manufacturing process and design constraints such as preventing short circuits, and there is no need to maintain a spacing to prevent short circuits, ensuring that the first heat sink can be distributed under the heat conduction area of the first chip. That is, the vertical projection (projection along the thickness direction) of the first heat sink on the substrate can at least partially cover the vertical projection of the heat conduction area of the first chip on the substrate, so that the heat generated by the first chip can be transferred along the thickness direction through the heat conduction area to the first heat sink, and then transferred to the outside of the chip module through the first heat sink to achieve heat dissipation, effectively shortening the heat dissipation path of the first chip and having a small thermal resistance. Moreover, the first heat sink does not need to maintain a spacing to prevent short circuits, can achieve a large projection coverage area, significantly improve the heat dissipation effect, and thus greatly improve the performance of the first chip and the entire chip module.

[0008] Wherein, the end face of the first end of the first heat sink is recessed in the thickness direction with respect to the side of the second package facing away from the substrate, that is, the end face of the first end of the first heat sink is recessed inward with respect to the side of the second package facing away from the substrate. In the thickness direction, there is a preset distance between the end face of the first end of the first heat sink and the side of the second package facing away from the substrate. That is, during the process of thinning the encapsulation layer on the second surface of the substrate, the depth of grinding and removal (the thickness in the thickness direction) does not reach the position of the first heat sink (the position of the end face of the first end), so that after the encapsulation layer is thinned, the first end of the first heat sink is located inside the remaining part of the encapsulation layer (the thin encapsulation layer) that has not been removed. For example, there may be a preset distance between the end face of the first end of the first heat sink and the side of the thin encapsulation layer facing away from the substrate. After forming the second package through the thin encapsulation layer to make the end face of the first end of the first heat sink recessed inward, there is still this preset distance between the end face of the first end of the first heat sink and the side of the second package facing away from the substrate. Without thinning the first heat sink at the same time as thinning the encapsulation layer, it is possible to avoid problems such as delamination, cracking or separation at the junction between the circumferential side wall of the first heat sink and the encapsulation layer during the thinning process, improve the workability and reliability of grinding the side of the encapsulation layer facing away from the substrate during the thinning process, improve the yield rate, and also avoid problems such as short circuits, having higher reliability.

[0009] In a possible implementation, the preset distance is 10 μm to 20 μm, which ensures that the position of the first heat sink will not be removed during the thinning process of the encapsulation layer, and the first end of the first heat sink is located inside the remaining thin encapsulation layer after the encapsulation layer is thinned, improving the reliability and operability of the thinning process.

[0010] In a possible implementation, there are multiple heat conduction regions, and the multiple heat conduction regions at least include a first region. The first region is the region with the largest cross-sectional area among the multiple heat conduction regions. The vertical projection of the first heat dissipation component on the substrate at least partially covers the vertical projection of the first region on the substrate. This is conducive to dissipating the heat generated by the first chip through the electrical connection component with a larger cross-sectional area and the first heat dissipation component, further reducing the thermal resistance and achieving good heat dissipation for the first chip.

[0011] In a possible implementation, the vertical projection of the first heat dissipation component on the substrate covers at least 50% of the vertical projection area of the first region on the substrate, which can further improve the heat dissipation effect on the first chip.

[0012] In a possible implementation, the vertical projection of the first heat dissipation component on the substrate covers at least 50% of the vertical projection area of the first chip on the substrate, which is conducive to the vertical projection of the first heat dissipation component covering a larger area of the heat conduction region and achieving good heat dissipation for the first chip.

[0013] In a possible implementation, the vertical projection of the first heat dissipation component on the substrate completely covers the vertical projection of the first chip on the substrate, achieving a more excellent heat dissipation effect for the first chip.

[0014] In a possible implementation, the chip module further includes a plurality of spaced conductive components. The conductive components are fixed on the second surface, and the conductive components are electrically connected to the chips corresponding to them through the substrate. The conductive components are partially located inside the second package, and the end of the conductive component facing away from the substrate is exposed on the side of the second package facing away from the substrate, enabling the end of the conductive component facing away from the substrate to be electrically connected to the circuit board, thereby realizing the electrical connection between the chips of the chip module and the circuit board.

[0015] In a possible implementation, the cross-sectional area of the first heat dissipation component is larger than that of a conductive component. The area of the vertical projection of the first heat dissipation component on the substrate is larger than the area of the vertical projection of a conductive component on the substrate, enabling the first heat dissipation component to cover a larger region. The vertical projection of the first heat dissipation component can cover a larger area of the heat conduction region. Compared with dissipating the heat of the first chip through conductive components such as solder balls, the heat dissipation region is increased, and it has better heat dissipation performance.

[0016] In a possible implementation, the cross-sectional area of the first heat dissipation component is larger than π*(D / 2) 2 , where the range of D is 200μm to 300μm, ensuring that the first heat dissipation component can cover a larger area of the heat conduction region and achieve more excellent heat dissipation performance.

[0017] In a possible implementation, the thermal conductivity of the first heat sink is greater than 100 W / mK. The first heat sink is used to dissipate heat from the first chip, ensuring a small thermal resistance and achieving a good heat dissipation effect.

[0018] In a possible implementation, the thickness of the first heat sink is greater than 30 μm, ensuring that the first heat sink has good thermal conductivity and facilitating the achievement of a good heat dissipation effect for the first chip.

[0019] In a possible implementation, there is a groove on the side of the second package facing away from the substrate, and the groove extends to the first end of the first heat sink, so that the first end of a part of the first heat sink is exposed, enabling the heat of the first chip to be transferred to the outside of the chip module through the first heat sink and ensuring the heat dissipation performance of the first heat sink.

[0020] In a possible implementation, the chip module further includes a first connecting member fixed to the first end of the first heat sink, and the end of the first connecting member facing away from the first heat sink protrudes from the side of the second package facing away from the substrate. The first heat sink can be fixedly assembled with the circuit board through the first connecting member, improving the assembly stability between the chip module and the circuit board, and also transferring heat to the circuit board to achieve heat dissipation, with a good heat dissipation effect.

[0021] Among them, the end of the first connecting member facing away from the first heat sink can protrude from the side of the second package facing away from the substrate, that is, the first connecting member protrudes from the second package, facilitating the assembly connection between the first connecting member and the circuit board.

[0022] In a possible implementation, there is a gap between the first connecting member and the second package, enabling the first connecting member to have a higher interfacial freedom during the molding process, which is beneficial to improving the molding yield of the first connecting member. A part of the first heat sink can still be exposed from the side of the second package facing away from the substrate.

[0023] In a possible implementation, the end of the conductive member facing away from the substrate protrudes from the side of the second package facing away from the substrate, enabling the conductive member to be better exposed outside the second package and facilitating the electrical connection between the conductive member and the circuit board.

[0024] In a possible implementation, there is a gap between the conductive member and the second package, enabling the conductive member to have a higher interfacial freedom during the molding process, which is beneficial to improving the molding yield of the conductive member.

[0025] In a possible implementation, the conductive member and the first connecting member are respectively solder balls, facilitating the assembly of the conductive member and the first connecting member with the external circuit board.

[0026] In a possible implementation, the first chip is disposed on the first surface. On the side of the first chip facing the substrate, there is a first electrical connector, and the first chip is electrically connected to the substrate through the first electrical connector. The end face of the end of the first electrical connector connected to the substrate forms a heat conduction region.

[0027] In a possible implementation, in the thickness direction, the first heat sink further includes a second end opposite to the first end, and the second end of the first heat sink is fixed on the second surface. That is, the first chip and the first heat sink are respectively located on the opposite first surface and second surface of the substrate, and the structural design is relatively simple. When manufacturing the chip module, when setting the chip on the second surface, the first heat sink can be set on the second surface as well, which can be fully compatible with the manufacturing process flow of the chip module with chip scale ball grid array packaging in the related art, without adding additional processes, and is beneficial to cost saving.

[0028] In a possible implementation, the substrate has a second heat sink, and at least a part of the vertical projections of the second heat sink and the first heat sink on the substrate overlap. The thermal resistance on the heat dissipation path from the first chip to the first heat sink is reduced, which is beneficial to further improving the heat dissipation effect.

[0029] In a possible implementation, the second heat sink is located inside the substrate. That is, the second heat sink is located between the first surface and the second surface, and the second heat sink does not expose from the first surface and the second surface of the substrate. While improving the heat dissipation effect, the structural design is simplified and it is easy to implement.

[0030] In a possible implementation, one end of the second heat sink is located inside the substrate, and the other end of the second heat sink extends towards the inside of the second package along the thickness direction, and the second end of the first heat sink is fixed to the other end of the second heat sink, which is beneficial to increasing the thickness of the second heat sink, further reducing the thermal resistance, and enriching the fixing and assembling methods between the first heat sink and the second surface of the substrate, having better structural design flexibility.

[0031] In a possible implementation, in the thickness direction, the second end of the first heat sink is fixed inside the substrate. That is, the first heat sink is inserted into the substrate, a part of the first heat sink is located inside the substrate, and a part of the first heat sink is located inside the second package. Under the condition of further reducing the thermal resistance and improving the heat dissipation effect, it is beneficial to reduce the number of heat sinks arranged on the substrate, simplify the structural design and the forming process, and is conducive to cost reduction.

[0032] In a possible implementation, the first chip is disposed on the second surface. On the side of the first chip facing the substrate, there is a second electrical connector, and the first chip is electrically connected to the substrate through the second electrical connector.

[0033] The first heat sink is fixed on the side of the first chip facing away from the substrate. A heat conducting area is formed on the side of the first chip facing the first heat sink, further shortening the heat dissipation path, reducing the thermal resistance, and improving the heat dissipation efficiency.

[0034] In a possible implementation, the first chip includes a power amplifier, and the chip module is a radio frequency module.

[0035] A second aspect of the embodiments of the present application provides a method for manufacturing a chip module, the method including:

[0036] Providing a substrate, a first heat sink, and a plurality of chips, where the substrate includes a first surface and a second surface facing away from each other in the thickness direction. The plurality of chips include a first chip, and the first chip has a heat conducting area for realizing heat conducting contact.

[0037] Arranging some of the plurality of chips on the first surface, and forming a first encapsulation on the first surface, and the chips located on the first surface are at least partially encapsulated in the first encapsulation.

[0038] Arranging another part of the plurality of chips on the second surface, and at least the first end of the first heat sink is located on the second surface, and the vertical projection of the first heat sink on the substrate at least partially covers the vertical projection of the heat conducting area of the first chip on the substrate.

[0039] Forming an encapsulation layer on the second surface, and the encapsulation layer encapsulates the chips and the first heat sink located on the second surface.

[0040] Performing a thinning process on the encapsulation layer to form a thin encapsulation layer, and the first end of the first heat sink is encapsulated inside the thin encapsulation layer.

[0041] Processing the thin encapsulation layer to form a second encapsulation, so that the end face of the first end of the first heat sink is recessed in the thickness direction relative to the side of the second encapsulation facing away from the substrate. The chips located on the second surface are at least partially encapsulated in the second encapsulation, the first heat sink is located between the first surface and the side of the second encapsulation facing away from the substrate, and in the thickness direction, there is a preset distance between the end face of the first end of the first heat sink and the side of the second encapsulation facing away from the substrate.

[0042] This method can achieve excellent heat dissipation performance for the first chip by setting a first heat dissipation member and making the vertical projection of the first heat dissipation member on the substrate at least partially cover the vertical projection of the heat conduction area of the first chip on the substrate. Moreover, after the encapsulation layer is thinned, it is ensured that the first end of the first heat dissipation member is located inside the thinned encapsulation thin layer. For example, there may be a preset distance between the end face of the first end of the first heat dissipation member and the side of the encapsulation thin layer facing away from the substrate, and the first heat dissipation member does not expose on the side of the encapsulation thin layer facing away from the substrate. After processing the encapsulation thin layer to form a second encapsulation member so that the end face of the first end of the first heat dissipation member is recessed inward relative to one side of the second encapsulation member, the preset distance still remains between the end face of the first end and the side of the second encapsulation member facing away from the substrate. That is, during the process of thinning the encapsulation layer, the depth of grinding removal (in the thickness direction) does not reach the position of the first heat dissipation member, and the first heat dissipation member is not thinned during the process of thinning the encapsulation layer, thus avoiding problems such as delamination, cracking, or separation at the junction of the circumferential side wall of the first heat dissipation member and the encapsulation layer during the grinding and thinning process, improving the workability and reliability of grinding the encapsulation layer, improving the yield, and also being able to avoid problems such as short circuits.

[0043] In a possible implementation, before forming the encapsulation layer on the second surface, the method further includes: forming a plurality of spaced solder joints on the second surface, and the solder joints are electrically connected to the chip through the substrate.

[0044] Forming the encapsulation layer on the second surface further includes: making the encapsulation layer wrap the solder joints.

[0045] After forming the encapsulation layer on the second surface, the method further includes: thinning the solder joints to form conductive members, and one end of the conductive member facing away from the substrate is exposed on the side of the second encapsulation member facing away from the substrate. By this method, conductive members are formed on the second surface of the substrate and the conductive members are exposed from the second encapsulation member, so as to facilitate the electrical connection between the conductive members and an external circuit board.

[0046] In a possible implementation, thinning the solder joints to form conductive members includes:

[0047] Thinning the solder joints to form transition solder joints.

[0048] Forming a notch structure on the side of the encapsulation thin layer facing away from the substrate, and the notch structure is arranged around the transition solder joint.

[0049] Setting a first solder structure on the transition solder joint, and after subjecting the transition solder joint and the first solder structure to reflow treatment, forming a conductive member, and one end of the conductive member facing away from the substrate protrudes from the side of the second encapsulation member facing away from the substrate. By this method, the conductive member protrudes from the second encapsulation member. In addition, the setting of the notch structure can increase the interfacial freedom of the transition solder joint and the first solder structure, which is beneficial to the reflow forming of the conductive member, especially beneficial to the forming of a spherical conductive member.

[0050] In a possible implementation, forming the second encapsulation member by processing the encapsulation thin layer includes: forming a groove on the side of the encapsulation thin layer facing away from the substrate to form the second encapsulation member, where the groove extends to the first end of the first heat sink, so that the end surface of the first end of the first heat sink is recessed in the thickness direction relative to the side of the second encapsulation member facing away from the substrate, ensuring a preset distance between the end surface of the first end of the first heat sink and the side of the second encapsulation member facing away from the substrate. The groove can expose a part of the first end of the first heat sink, enabling the heat of the first chip to be transferred to the outside of the chip module through the first heat sink.

[0051] In a possible implementation, after forming the groove on the side of the encapsulation thin layer facing away from the substrate, the method further includes:

[0052] Providing a second solder structure on the first end of the first heat sink.

[0053] After subjecting the second solder structure to reflow treatment, a first connection member is formed, and the end of the first connection member facing away from the first heat sink protrudes from the side of the second encapsulation member facing away from the substrate. By this method, a first connection member is formed on the first heat sink to facilitate the connection of the first heat sink to an external circuit board or the like through the first connection member.

[0054] In a possible implementation, the side of the first chip facing the substrate has a first electrical connection member. Arranging some of the multiple chips on the first surface includes: arranging the first chip on the first surface and electrically connecting the first chip to the substrate through the first electrical connection member, and the end surface of the end of the first electrical connection member connected to the substrate forms a heat conduction region.

[0055] In a possible implementation, in the thickness direction, the first heat sink further includes a second end opposite to the first end.

[0056] Providing the substrate and the first heat sink includes: fixing the second end of the first heat sink on the second surface. By this method, a chip module with a layout where the first chip is located on the first surface and the first heat sink is located on the second surface can be obtained.

[0057] In a possible implementation, the substrate has a second heat sink.

[0058] Fixing the second end of the first heat sink on the second surface includes: making at least part of the vertical projection of the first heat sink on the substrate coincide with the vertical projection of the second heat sink on the substrate. By this method, a chip module with a second heat sink is obtained to improve the heat dissipation effect.

[0059] In a possible implementation, one end of the second heat sink is located inside the substrate, and the other end of the second heat sink extends towards the inside of the second encapsulation member in the thickness direction.

[0060] Fixing the second end of the first heat sink on the second surface includes: forming a second connecting member on the other end of the second heat sink, and fixing the second end of the first heat sink to the other end of the second heat sink through the second connecting member. Through this method, a chip module with a layout where the first chip is located on the first surface, the first heat sink is located on the second surface, one end of the second heat sink is inside the substrate, and the other end is fixed to the first heat sink can be obtained.

[0061] In a possible implementation, providing a substrate and a first heat sink includes: fixing the second end of the first heat sink inside the substrate. Through this method, a chip module with a layout where the first chip is located on the first surface and part of the first heat sink is fixed inside the substrate can be obtained.

[0062] In a possible implementation, the first chip has a second electrical connecting member on the side facing the substrate.

[0063] Arranging another part of the multiple chips on the second surface includes:

[0064] Arranging the first chip on the second surface, and electrically connecting the first chip to the substrate through the second electrical connecting member.

[0065] Fixing the first heat sink on the side of the first chip facing away from the substrate, and a heat conduction area is formed on the side of the first chip facing the first heat sink.

[0066] Through this method, a chip module with a layout where the first chip is located on the second surface and the first heat sink is located on the first chip can be obtained.

[0067] The second aspect of the embodiments of the present application provides an electronic device, including a housing, a circuit board, and the chip module described in any one of the above, the chip module is arranged on the circuit board and is electrically connected to the circuit board, and both the chip module and the circuit board are assembled in the housing. Description of the Drawings

[0068] Figure 1 It is a schematic cross-sectional structure diagram of an electronic device provided by an embodiment of the present application;

[0069] Figure 2 It is a schematic cross-sectional structure diagram of the assembly of a chip module and a circuit board in the related art;

[0070] Figure 2a It is a schematic bottom view structure diagram of a chip module in the related art;

[0071] Figure 3 It is a schematic cross-sectional structure diagram of a chip module provided by an embodiment of the present application;

[0072] Figure 4 is Figure 3 the upward view structural schematic diagram of the chip module in

[0073] Figure 5 the cross-sectional structural schematic diagram of another chip module provided by an embodiment of the present application;

[0074] Figure 6 is Figure 5 the schematic diagram of the assembly of the chip module and the circuit board in

[0075] Figure 7 the cross-sectional structural schematic diagram of yet another chip module provided by an embodiment of the present application;

[0076] Figure 8 is Figure 7 the schematic diagram of the junction-to-board thermal resistance model of the first chip in the chip module of

[0077] Figure 9 the schematic diagram of the heat conduction simulation of the first chip of the ball grid array chip module in the related art;

[0078] Figure 10 is Figure 7 the schematic diagram of the heat conduction simulation of the first chip in the chip module of

[0079] Figure 11 the cross-sectional structural schematic diagram of yet another chip module provided by an embodiment of the present application;

[0080] Figure 12 the cross-sectional structural schematic diagram of another chip module provided by an embodiment of the present application;

[0081] Figure 13 the cross-sectional structural schematic diagram of another chip module provided by an embodiment of the present application;

[0082] Figure 14 the cross-sectional structural schematic diagram of another chip module provided by an embodiment of the present application;

[0083] Figure 15 the schematic flow diagram of a method for manufacturing a chip module provided by an embodiment of the present application;

[0084] Figure 15a the schematic diagram of a part of the chips assembled on the substrate in a chip module provided by an embodiment of the present application;

[0085] Figure 15b the schematic diagram of the first package formed on the substrate in a chip module provided by an embodiment of the present application;

[0086] Figure 15c the schematic diagram of the chips and solder joints assembled on the substrate in a chip module provided by an embodiment of the present application;

[0087] Figure 15d Schematic diagram after forming the encapsulation layer on the second surface of the substrate in a chip module according to an embodiment of the present application;

[0088] Figure 15e Schematic diagram after thinning the encapsulation layer in a chip module according to an embodiment of the present application;

[0089] Figure 15f Schematic diagram after forming the second encapsulation member in a chip module provided by an embodiment of the present application;

[0090] Figure 15g Schematic diagram after providing the first solder structure and the second solder structure on the first heat sink in a chip module provided by an embodiment of the present application;

[0091] Figure 15h Bottom view schematic diagram after providing the first solder structure and the second solder structure on the first heat sink in a chip module provided by an embodiment of the present application;

[0092] Figure 15i Schematic diagram after reflow of the first solder structure in a chip module provided by an embodiment of the present application.

[0093] Explanation of reference numerals:

[0094] 100 - Electronic device;

[0095] 101 - Housing; 101a - Side frame; 101b - Rear cover;

[0096] 102 - Display screen;

[0097] 10 - Chip module;

[0098] 11 - Substrate; 11a - First surface; 11b - Second surface; 112 - Second heat sink;

[0099] 12a - First chip; 12b - Second chip; 12c - Third chip; 12d - Fourth chip;

[0100] 13 - First encapsulation member; 14 - Second encapsulation member;

[0101] 15 - Conductive member;

[0102] 17 - First heat sink;

[0103] 18 - Groove; 19 - Second groove;

[0104] 110 - First connecting member;

[0105] 120 - Second connecting member;

[0106] 130 - First solder structure; 140 - Second solder structure;

[0107] 20 - Circuit board;

[0108] 104 - Antenna module. Specific embodiments

[0109] The terms used in the embodiments section of this application are only for explaining the specific embodiments of this application and are not intended to limit this application.

[0110] Embodiments of this application provide an electronic device, which may include, but is not limited to, mobile phones, tablet personal computers, laptop computers, ultra-mobile personal computers (UMPCs), desktop computers, walkie-talkies, netbooks, personal digital assistants (PDAs), wearable devices, virtual reality (VR) devices (such as VR glasses, VR helmets, etc.), augmented reality (AR) devices (such as AR glasses, AR helmets, etc.), in-vehicle devices, surveillance camera devices, and other electronic devices with wireless communication functions.

[0111] In the embodiments of this application, a mobile phone is taken as an example for illustration.

[0112] Figure 1 It is a schematic cross-sectional structure diagram of an electronic device provided by an embodiment of this application.

[0113] See Figure 1 As shown, the electronic device 100 may include a housing 101 and a display screen 102. The housing 101 may include a rear cover 101b and a side frame 101a. The rear cover 101b and the display screen 102 may be respectively located on opposite sides of the side frame 101a. The rear cover 101b, the side frame 101a, and the display screen 102 may enclose an accommodation space for accommodating various structural components of the electronic device 100.

[0114] The electronic device 100 may further include an antenna module 104. For example, in some examples, part of the side frame 101a may be used to form the antenna module 104.

[0115] The electronic device 100 may further include a circuit board 20 and a chip module 10. The circuit board 20 and the chip module 10 are respectively assembled in the accommodation space. The chip module 10 is disposed on the circuit board 20 and electrically connected to the circuit board 20 to achieve signal transmission between the chip module 10 and the circuit board 20.

[0116] Exemplarily, the chip module 10 may be a radio frequency module, which can be used to modulate the frequency of the received electrical signal (such as the electrical signal sent by the processor of the electronic device 100) and amplify the power. For example, during the process of transmitting an electrical signal to the outside of the electronic device 100, the radio frequency module can modulate the electrical signal, modulate the electrical signal from a low frequency to a specified high frequency band, become a radio frequency signal that can be transmitted in the air, and amplify the power of the radio frequency signal to meet the communication requirements.

[0117] The circuit board 20 can be electrically connected to the antenna module 104 to achieve electrical connection between the chip module 10 and the antenna module 104.

[0118] The chip module 10 can transmit a radio frequency (RF) signal, and transmit the radio frequency signal to the antenna module 104 through the circuit board 20. The antenna module 104 can send out the radio frequency signal. The antenna module 104 can also receive external electromagnetic wave signals and transmit the electromagnetic wave signals to the chip module 10.

[0119] Of course, in some other examples, the chip module 10 may also be other chip integrated modules. For example, it may be a storage chip module, etc. In the embodiments of the present application, the chip module 10 is taken as an example of a radio frequency module for illustration.

[0120] It can be understood that the structure schematically shown in the embodiments of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer structural components than shown in the figure, or combine certain structural components, or split certain structural components, or have different arrangements of structural components. For example, the electronic device 100 may further include a camera, such as a front camera and a rear camera, sensors, a memory, a battery, a flash, etc.

[0121] With the development of electronic devices towards the direction of being thinner and lighter, chip modules are also gradually developing towards high density, miniaturization, and high pin count. Among them, the ball grid array packaging technology has advantages such as small packaging size and high density, and has become one of the commonly used chip packaging technologies. In particular, the chip module packaged by die size ball grid array (DSBGA) has been widely applied and studied.

[0122] Figure 2 It is a schematic cross-sectional structure diagram of the assembly of a chip module and a circuit board in the related art.

[0123] See Figure 2As shown, the chip module 400 with DABGA package may include a substrate 200 and multiple chips, and the multiple chips may be electrically connected to connection traces (not shown in the figure) within the substrate 200.

[0124] The substrate 200 may include opposite front and back surfaces, and the multiple chips may also be respectively disposed on the front and back surfaces of the substrate 200. For example, Figure 2 as shown in the figure, exemplarily, the multiple chips may include chip 400a, chip 400b, chip 400c, and chip 400d. Among them, chip 400a, chip 400b, and chip 400c may be located on the front surface of the substrate 200, and chip 400d may be located on the back surface of the substrate 200.

[0125] A plurality of solder balls 500 may be fixed on the back surface of the substrate 200, and the plurality of solder balls 500 are arranged in an array to form a ball grid array (refer to Figure 2a as shown in the figure), and the chips may be respectively and electrically connected to the plurality of solder balls 500 through the connection traces of the substrate 200.

[0126] For example, on the side of the chip facing the substrate 200, there may be copper bumps for realizing electrical connection. As Figure 2 shown in the figure, taking the chip 400c on the front surface of the substrate 200 as an example, on the side of the chip 400c facing the front surface of the substrate 200, there is a copper bump 401. The connection trace 201 within the substrate 200 may extend to the front surface of the substrate 200. The chip 400c may be in contact electrical connection with the connection trace 201 through the copper bump 401 to realize the electrical connection between the chip 400c and the substrate 200, and further be electrically connected to the solder ball 500 located on the back surface of the substrate 200 through the connection trace 201.

[0127] Among them, the forming material of the solder ball 500 mostly uses tin balls. For example, the forming material of the solder ball 500 may be an alloy material composed of three metal components of tin (Sn), silver (Ag), and copper (Cu). For example, it may be SAC305 material, that is, the mass percentages of Sn, Ag, and Cu are 96.5%, 3.0%, and 0.5% respectively.

[0128] On the front surface of the substrate 200, a front encapsulation member 600 may also be covered. The front encapsulation member 600 wraps and encapsulates at least part of the chips located on the front surface. On the back surface of the substrate 200, a back encapsulation member 700 may be covered. The back encapsulation member 700 wraps and encapsulates at least part of the chips located on the back surface. The plurality of solder balls 500 are also located within the back encapsulation member 700. One end of each solder ball 500 facing away from the substrate 200 protrudes from the back encapsulation member 700 to expose the solder ball 500.

[0129] Continue to refer to Figure 2As shown, the chip module 400 can be soldered to the circuit board 300 through a plurality of solder balls 500 to achieve electrical connection, so that a plurality of chips can achieve electrical connection with the circuit board 300.

[0130] The heat dissipation of multiple chips can also be achieved through a ball grid array composed of solder balls 500. The heat generated by the chips during operation can be transferred to the substrate 200, and then dissipated outside the chip module through the solder balls 500. The area where the chip contacts the substrate 200 can be the heat conduction area of the chip. Taking the chip 400c as an example, the copper bumps 401 of the chip 400c are in contact and electrically connected to the substrate 200. The chip 400c conducts heat to the substrate 200 through the copper bumps 401, thereby realizing the heat dissipation of the chip 400c. One end face of the copper bump 401 in contact with the substrate 200 can be used as the heat conduction area 402 of the chip 400c (refer to Figure 2a shown).

[0131] Figure 2a is a schematic bottom view structure of a chip module in the related art. Among them, Figure 2a The dotted line in shows the vertical projection of the chip 400c on the back encapsulation 700.

[0132] However, the distribution method of the ball grid array is relatively fixed and limited by the preparation process of the ball grid array. As shown in Figure 2a shown, there must be a spacing between multiple solder balls 500 in the ball grid array, which can also avoid problems such as short circuits caused by contact between the solder balls 500. It is difficult to ensure that the solder balls 500 are just arranged below the heat conduction area 402 of the chip. As shown in Figure 2a shown, that is, the vertical projection of the solder balls 500 on the substrate (or the back encapsulation 700) cannot cover the vertical projection of the heat conduction area 402 of the chip 400c on the substrate, increasing the heat dissipation path. Moreover, the back encapsulation 700 is mostly made of plastic packaging material with a lower thermal conductivity (such as 1W / (mK)), which will increase the thermal resistance and result in poor heat dissipation performance. In addition, the solder balls are mostly made of tin balls with a lower thermal conductivity (such as 58W / (mK)), and the cross-sectional area of each solder ball is small, which is also not conducive to heat dissipation, reducing the heat dissipation effect on the chip, and thus affecting the performance of the chip. Especially for heat-sensitive chips, such as the power amplifier (PA) in the radio frequency module, poor heat dissipation effect on the PA will greatly affect the function of the PA, and thus affect the performance of the entire chip module.

[0133] Based on this, an embodiment of the present application provides a chip module and a method for manufacturing the chip module. In this chip module, the chip can be electrically connected to the substrate through a conductive member (such as a ball grid array assembled by a plurality of conductive solder balls). By providing a first heat dissipation member in the chip module, the first heat dissipation member is used to dissipate heat from the first chip that is heat-sensitive or generates a large amount of heat. Compared with the heat dissipation of the ball grid array formed by solder balls between the chips, the first heat dissipation member is not limited by the molding process and local requirements constraints, and there is no need to reserve a spacing to prevent short circuits, etc. It can ensure that the first heat dissipation member can be distributed below the heat conduction area of the first chip, that is, it can ensure that the vertical projection of the first heat dissipation member on the substrate at least partially covers the vertical projection of the heat conduction area of the first chip on the substrate, effectively shortening the heat dissipation path of the first chip, having a small thermal resistance and a large coverage area, significantly improving the heat dissipation performance, and enabling the first chip and the entire chip module to achieve better performance.

[0134] In addition, the end face of the first end of the first heat dissipation member is recessed in the thickness direction relative to the side of the second encapsulation member facing away from the substrate, and a preset distance is reserved between the end face of the first end of the first heat dissipation member and the side of the second encapsulation member facing away from the substrate. That is, during the process of thinning the encapsulation layer, the grinding and removal depth does not reach the first heat dissipation member. After the thinning process, the first end of the first heat dissipation member is located inside the remaining part of the encapsulation layer (encapsulation thin layer) that has not been removed. After forming the second encapsulation member, a preset distance is reserved between the end face of the first end of the first heat dissipation member and the side of the second encapsulation member facing away from the substrate. The first heat dissipation member is not thinned while thinning the encapsulation layer, thus avoiding problems such as delamination, cracks, or separation at the junction between the circumferential side wall of the first heat dissipation member and the encapsulation layer during the thinning process, improving the workability and reliability of grinding the side of the encapsulation layer facing away from the substrate during the thinning process, improving the yield, and also being able to avoid problems such as short circuits, and having higher reliability.

[0135] Figure 3 It is a schematic cross-sectional structure diagram of a chip module provided by an embodiment of the present application.

[0136] See Figure 3 As shown, the chip module 10 includes a substrate 11. The substrate 11 can serve as a support structure for the entire chip module 10. Exemplarily, the substrate 11 can be a square plate-like structure member, with the thickness direction of the substrate 11 being Figure 3 the x direction shown therein.

[0137] The substrate 11 may include a first surface 11a and a second surface 11b facing away from each other. For example, the two opposite sides of the substrate 11 in the x direction can be the first surface 11a and the second surface 11b respectively.

[0138] The chip module 10 further includes a plurality of chips, which may be radio frequency integrated circuits (RFICs), power amplifiers, low noise amplifiers (LNAs), surface acoustic wave (SAW) filters, switches (SWs), etc.

[0139] Exemplarily, the plurality of chips may include a first chip 12a. The first chip 12a may be a chip with relatively serious heat generation among the plurality of chips, or the first chip 12a may also be a heat-sensitive chip. For example, the heat dissipation effect of the first chip 12a has a great impact on the performance of the first chip 12a. For example, in the embodiments of the present application, the first chip 12a is taken as a PA for illustration.

[0140] As Figure 3 shown in

[0141] The plurality of chips may be respectively disposed on the first surface 11a and the second surface 11b. As Figure 3 shown in

[0142] The chip module 10 further includes a first encapsulation 13 and a second encapsulation 14. The first encapsulation 13 and the second encapsulation 14 can play a role in encapsulating and protecting the chips, and at least part of each chip can be wrapped and encapsulated in the first encapsulation 13 or the second encapsulation 14. Exemplarily, the first encapsulation 13 is disposed on the first surface 11a. The first encapsulation 13 can cover the first surface 11a, and the chips located on the first surface 11a are at least partially wrapped and encapsulated in the first encapsulation 13. For example, the first chip 12a, the second chip 12b, and the third chip 12c are wrapped and encapsulated in the first encapsulation 13.

[0143] The second encapsulation 14 is disposed on the second surface 11b. The second encapsulation 14 can cover the second surface 11b, and the chips located on the second surface 11b are at least partially wrapped and encapsulated in the second encapsulation 14. For example, the fourth chip 12a can be partially wrapped and encapsulated in the second encapsulation 14.

[0144] The molding material of the first encapsulation member 13 may include materials such as plastics, ceramics, resins, and glass. The molding material of the second encapsulation member 14 may be the same as that of the first encapsulation member 13.

[0145] It should be noted that the chip is at least partially wrapped and encapsulated within the first encapsulation member 13 or the second encapsulation member 14. The chip may be located inside the encapsulation member without being exposed. For example, the chips located on the first surface 11a (such as the first chip 12a, the second chip 12b, and the third chip 12c) are wrapped inside the first encapsulation member 13, and there is a spacing between the side of the chip facing away from the substrate 11 and the side of the first encapsulation member 13 facing away from the substrate 11.

[0146] Alternatively, the chip may also be partially wrapped inside the encapsulation member and partially exposed from the encapsulation member. For example, the chip located on the second surface 11b (such as the fourth chip 12d) is partially located inside the second encapsulation member 14 and partially exposed from the side of the second encapsulation member 14 facing away from the substrate. For example, the side of the chip facing away from the substrate 11 may be flush with the side of the second encapsulation member 14 facing away from the substrate, causing the chip to be partially exposed.

[0147] Of course, in some examples, the chips located on the first surface 11a may also be exposed from the first encapsulation member 13. For example, the side of the chip facing away from the substrate 11 may also be flush with the side of the first encapsulation member 13 facing away from the substrate. The chips located on the second surface 11b may also be wrapped inside the second encapsulation member 14 without being exposed. The specific setting position of the chip inside the encapsulation member can be selected and set according to the functional requirements of the chip, etc.

[0148] Continuing to refer to Figure 3 As shown, the chip module 10 further includes a plurality of conductive members 15, and the plurality of conductive members 15 are arranged at intervals. Each conductive member 15 is fixed on the second surface 11b of the substrate 11, and the conductive member 15 is partially wrapped inside the second encapsulation member 14. The conductive member 15 can be electrically connected to the chip through the substrate 11, and thus the electrical connection between the chip and the external circuit board can be achieved through the conductive member.

[0149] Exemplarily, the substrate 11 may have a plurality of connection traces, and the connection traces can be used to achieve electrical connection between the chips. For example, referring to Figure 3 As shown, the substrate 11 may have a connection trace 111a and a connection trace 111b. The connection trace 111a and the connection trace 111b can extend to the first surface 11a. The first chip 12a and the third chip 12c can be electrically connected through the connection trace 111a, and the second chip 12b and the third chip 12c can be electrically connected through the connection trace 111b.

[0150] The connection traces can also be used to achieve electrical connection between the chip and the conductive member. For example, referring to Figure 3As shown, the substrate 11 may further include connection traces 111c that extend to the second surface 11b and are respectively electrically connected to the fourth chip 12d and the conductive member 15. It should be noted that Figure 3 only a part of the conductive members 15 and connection traces are shown. For example, the substrate 11 may further include connection traces 111d that extend to the first surface 11a, and the first chip 12a may be electrically connected to a conductive member (not shown in the figure) located on the second surface 11b through the connection traces 111d.

[0151] In some examples, the chip may have electrical connection components to achieve electrical connection with the substrate. For example, taking the first chip 12a disposed on the first surface 11a of the substrate 11 as an example, the first chip 12a may have a first electrical connection component 121a on the side facing the first surface 11a of the substrate 11. The first chip 12a is disposed on the first surface 11a and is electrically connected by contacting connection traces (such as connection traces 111d and 111a) extending to the first surface 11a through the first electrical connection component 121a, thereby achieving electrical connection between the chip and the substrate 11.

[0152] Among them, there may be multiple electrical connection components of the chip to meet the electrical connection requirements of the chip. For example, referring to Figure 3 as shown, taking the first chip 12a having two first electrical connection components 121a as an example, one of the first electrical connection components 121a of the first chip 12a may be in electrical contact connection with the connection trace 111d extending to the first surface 11a of the substrate 11, so that the first chip 12a can be electrically connected to the conductive member through the first electrical connection component 121a and the connection trace 111d. The other first electrical connection component 121a of the first chip 12a may be in electrical contact connection with the connection trace 111a extending to the first surface 11a of the substrate 11, so that the first chip 12a can be electrically connected to the third chip 12c through the first electrical connection component 121a and the connection trace 111a.

[0153] Exemplarily, the connection between the electrical connection component and the connection trace of the substrate 11 can be fixed by welding to maintain a stable electrical connection. For example, the chip module may further include a welding member 16. Taking Figure 3 the electrical connection between the first electrical connection component 121a of the first chip 12a and the connection trace 111d as an example, the first electrical connection component 121a is welded to the connection trace 111d through the welding member 16 to achieve reliable assembly and electrical connection between the first electrical connection component 121a of the first chip and the substrate 11.

[0154] The welded part 16 can be a welded structural part such as a solder joint or a pad. Of course, in some other examples, the electrical connection member and the substrate 11 can also be assembled and fixed and electrically connected in other ways. For example, the connection and routing of the electrical connection member of the chip and the substrate can be fixed and electrically connected through a clamping member or a fixing member with conductive properties.

[0155] In some other examples, the chip can also be electrically connected to the substrate 11 in other ways. For example, one side of the chip can be attached to the substrate 11, and leads can be provided on the side of the chip facing away from the substrate 11. The chip can be electrically connected to the substrate 11 through these leads.

[0156] It can be understood that the type, quantity, and connection method of the chip to the substrate can be selected and set according to the function and actual requirements of the chip module 10. The quantity, layout method, etc. of the connection routing can also be selected and set according to the connection requirements of the chip.

[0157] One end of each conductive member 15 facing away from the substrate 11 protrudes from the second encapsulation member 14, that is, one end of the conductive member 15 facing away from the substrate 11 can be exposed on the side of the second encapsulation member 14 facing away from the substrate 11, so that one end of the conductive member 15 facing away from the substrate 11 can be electrically connected to the circuit board 20 (refer to Figure 6 shown), thereby realizing the electrical connection between the chip of the chip module 10 and the circuit board.

[0158] For example, one end of the conductive member 15 facing away from the substrate 11 can protrude from the side of the second encapsulation member 14 facing away from the substrate 11, so that the conductive member 15 is better exposed outside the second encapsulation member 14, facilitating the electrical connection between the conductive member 15 and the circuit board 20.

[0159] Exemplarily, the conductive member 15 can be a solder ball, that is, a spherical welded part. For example, the conductive member 15 can be a tin ball formed of SAC305 material. The conductive member 15 can be welded and fixed to the conductive member on the circuit board by welding and achieve electrical connection.

[0160] It should be noted that the conductive member 15 is partially wrapped in the second encapsulation member 14, and the outer wall surface of the conductive member 15 can extend to the second encapsulation member 14, and the outer wall surface of the conductive member 15 is in contact with the second encapsulation member 14. Or, continue to refer to Figure 3 shown, there can also be a gap 19 between the outer wall surface of the conductive member 15 and the second encapsulation member, which can give the conductive member 15 a higher degree of interfacial freedom during the forming process. For example, during the preparation of the spherical conductive member 15, there can be a gap between the forming material of the conductive member 15 and the second encapsulation member to form a gap 19 after the conductive member 15 is formed, giving the forming material of the conductive member a high degree of interfacial freedom, facilitating the spherical forming of the conductive member 15 and improving the forming yield of the conductive member 15.

[0161] During the operation of the chip in the chip module 10, heat is generated. To ensure the performance of the chip, it is necessary to dissipate the heat generated by the chip. The chip may have a heat conduction area for achieving heat conduction contact. The heat generated by the chip during operation can be transferred to the outside of the chip through the heat conduction area, thereby realizing heat dissipation of the chip. Exemplarily, if the chip is disposed on the substrate 11, there is a heat conduction contact area between the chip and the substrate 11. The heat of the chip can be transferred to the substrate 11 through this heat conduction contact area, thereby realizing heat dissipation of the chip. The heat conduction contact area between the chip and the substrate 11 can be the heat conduction area of the chip.

[0162] For example, in an example where the chip is electrically connected to the substrate 11 through an electrical connector, the end face of the electrical connector connected to the substrate 11 can be the heat conduction area of the chip. Refer to Figure 3 As shown, taking the first chip 12a disposed on the first surface 11a of the substrate 11 as an example, the first electrical connector 121a of the first chip 12a is in electrical contact with the connection trace 111d of the substrate 11. The heat generated by the first chip 12a can be transferred to the substrate 11 through the first electrical connector 121a, thereby realizing heat dissipation of the first chip 12a. The end face of the first electrical connector 121a connected to the substrate 11 can form the heat conduction area 121 of the first chip 12a (refer to Figure 4 shown).

[0163] Of course, in some other examples, when the chip realizes heat transfer in other ways, the heat conduction area can also be other contact areas for the chip to realize heat transfer. For example, in an example where one side of the chip is attached to the substrate 11, the heat generated by the chip is transferred to the substrate 11 through the side of the chip attached to the substrate 11, and the side of the chip attached to the substrate 11 can form the heat conduction area of the chip. Or, in some other examples, when the chip is disposed on the substrate 11 and the chip can be attached to a heat dissipation member (such as the first heat dissipation member) with a higher thermal conductivity than the substrate 11, the heat generated by the chip is transferred to the heat dissipation member through the side of the chip attached to the heat dissipation member, thereby realizing heat dissipation of the chip. The side of the chip attached to the heat dissipation member can form the heat conduction area of the chip.

[0164] To improve the heat dissipation effect of the first chip 12a, continue to refer to Figure 3 shown. The chip module 10 further includes a first heat dissipation member 17. The first heat dissipation member 17 can be located between the first surface 11a of the substrate 11 and the side of the second package 14 facing away from the substrate 11, that is, the first heat dissipation member 17 does not expose from the first surface 11a.

[0165] And the first heat sink is at least partially encapsulated within the second encapsulation member 14. For example, the first heat sink 17 may include a first end 17a and a second end 17b that are opposite in the thickness direction (x-direction). Among them, the second end 17b may be disposed closer to the first surface 11a, and the first end 17a may be disposed farther from the first surface 11a. At least the first end 17a of the first heat sink 17 is located within the second encapsulation member 14. The second end 17b may extend into the substrate 11, such that the first heat sink 17 is partially located within the substrate 11 and partially located within the second encapsulation member 14. Alternatively, the second end 17b may also be fixed to the second surface 11b of the substrate 11.

[0166] Figure 4 For Figure 3 is a schematic bottom view structure diagram of the chip module. Among them, Figure 4 The dashed line in shows the vertical projection of the first chip 12a on the second encapsulation member 14.

[0167] The first heat sink 17 can be used to dissipate heat from the first chip 12a. It can be understood that, compared with the heat dissipation of the chip through the ball grid array composed of solder balls in the related art, different from the layout requirements of the ball grid array, the layout of the first heat sink 17 is not restricted by the manufacturing process and design constraints such as preventing short circuits. Refer to Figure 3 shown, to ensure that the first heat sink 17 can be distributed below the heat conduction area (i.e., the first electrical connection member 121a) of the first chip 12a. Combining Figure 4 shown, the vertical projection (projection along the x-direction) of the first heat sink 17 on the substrate (or the second encapsulation member 14) can at least partially cover the vertical projection (projection along the x-direction) of the heat conduction area 121 of the first chip 12a on the substrate (or the second encapsulation member 14), such that the heat generated by the first chip 12a can be transferred along the x-direction to the first heat sink 17 through the heat conduction area 121, and is transferred out of the chip module 10 through the first heat sink 17 to achieve heat dissipation, effectively shortening the heat dissipation path and having a smaller thermal resistance. Moreover, the first heat sink 17 does not need to maintain a spacing to prevent short circuits, and can achieve a larger projection coverage area, significantly improving the heat dissipation effect, and thus greatly improving the performance of the first chip 12a and the entire chip module 10.

[0168] It should be noted that the conductive member 15 can also be used to dissipate heat from the chip. For example, by making part of the conductive member 15 coincide with the vertical projection of the heat conduction area of the chip on the substrate 11, the heat generated by the chip during operation can also be transferred out of the chip module 10 through the conductive member 15.

[0169] Among them, the forming material of the first heat sink 17 can be a material with a high thermal conductivity. For example, the thermal conductivity of the first heat sink 17 is greater than that of the conductive member 15.

[0170] Exemplarily, the thermal conductivity of the first heat dissipation member 17 can be greater than 100 W / mK. Heat dissipation of the first chip 12a is achieved through the first heat dissipation member 17, ensuring a relatively small thermal resistance and achieving a good heat dissipation effect.

[0171] For example, in some examples, the thermal conductivity of the first heat dissipation member 17 can be 200 W / mK to 600 W / mK, which can further reduce the thermal resistance, improve the heat dissipation effect, and achieve a better heat dissipation effect for the first chip 12a.

[0172] In some examples, the thermal conductivity of the first heat dissipation member 17 can be approximately 400 W / mK. For example, the molding material of the first heat dissipation member 17 can include metallic copper, which can achieve a more excellent heat dissipation effect, with a relatively low cost and being convenient for production implementation.

[0173] Of course, in some other examples, the first heat dissipation member 17 can also be other types of metallic materials, such as materials like aluminum and silver.

[0174] Exemplarily, the thickness of the first heat dissipation member 17 can be greater than 30 μm, ensuring that the first heat dissipation member 17 has good thermal conductivity, which is conducive to achieving a good heat dissipation effect for the first chip 12a.

[0175] For example, in some examples, the thickness of the first heat dissipation member 17 can be 40 μm to 50 μm, which is conducive to achieving a better heat dissipation effect. For example, the thickness of the first heat dissipation member 17 can be approximately 40 μm or 50 μm, enabling the first heat dissipation member 17 to achieve a more excellent heat dissipation effect.

[0176] The first heat dissipation member 17 can be a structural member. For example, the first heat dissipation member 17 can be an integral heat dissipation block, and the shape of the first heat dissipation member 17 can be a regular or irregular shape such as a cylinder or a cube.

[0177] Alternatively, the first heat dissipation member 17 can also include multiple sub - heat dissipation members. For example, each sub - heat dissipation member can be a heat dissipation block, and the shape of each sub - heat dissipation member can be a regular or irregular shape such as a cylinder or a cube.

[0178] The cross - sectional area of the first heat dissipation member 17 can be greater than the cross - sectional area of a conductive member 15. In the embodiments of the present application, the cross - sectional area refers to the area of a cross - section formed by cutting a component (such as the first heat dissipation member or the conductive member) along a plane perpendicular to the thickness direction (x - direction). That is, the area of the vertical projection of the first heat dissipation member 17 on the substrate is greater than the area of the vertical projection of a conductive member 15 on the substrate, enabling the first heat dissipation member 17 to cover a larger area. The vertical projection of the first heat dissipation member 17 can cover a larger area of the heat - conducting region. Compared with achieving heat dissipation of the first chip through conductive members such as solder balls, the heat - dissipation region is increased, and better heat - dissipation performance is achieved.

[0179] Exemplarily, the cross-sectional area of the first heat sink 17 can be greater than π*(D / 2) 2 , where D can be the diameter of a spherical conductive member 15. For example, the range of D can be 200 μm to 300 μm, ensuring that the first heat sink 17 can cover a larger heat-conducting area and achieve more excellent heat dissipation performance.

[0180] It should be noted that the heat-conducting areas 121 of the first chip 12a can include multiple ones. For example, taking the case where the first chip 12a is electrically connected to the substrate through electrical connectors, multiple electrical connectors can be provided on the surface of the first chip 12a facing the substrate. Refer to Figure 4 as shown. Exemplarily, if the first chip 12a has a first electrical connector 121a and a third electrical connector 121b, the first chip 12a is electrically connected to the substrate through the first electrical connector 121a and the third electrical connector 121b respectively. The end face of the first electrical connector 121a connected to the substrate and the end face of the third electrical connector 121b connected to the substrate can respectively form the heat-conducting area 121 of the first chip 12a.

[0181] In some examples, the vertical projection of the first heat sink 17 on the substrate can completely cover the vertical projections of multiple heat-conducting areas 121 on the substrate, achieving more excellent heat dissipation effect.

[0182] Or, in some examples, the vertical projection of the first heat sink 17 on the substrate can also only cover part of the vertical projections of the heat-conducting areas 121 on the substrate, achieving good heat dissipation effect, reducing the area of the first heat sink 17, and facilitating the reduction of the structural design difficulty and production cost.

[0183] Exemplarily, multiple heat-conducting areas can at least include a first area, and the first area is the area with the largest cross-sectional area among multiple heat-conducting areas. For example, the end face of the first electrical connector 121a connected to the substrate forms a heat-conducting area 1211, and the end face of the third electrical connector 121b connected to the substrate forms a heat-conducting area 1212. The cross-sectional area of the first electrical connector 121a can be the largest among multiple electrical connectors, so that the heat-conducting area 1211 can be the area with the largest cross-sectional area among multiple heat-conducting areas 121, that is, the heat-conducting area 1211 can be the first area.

[0184] The vertical projection of the first heat sink 17 on the substrate can at least partially cover the vertical projection of the first area on the substrate, which is conducive to dissipating the heat generated by the first chip 12a through the electrical connector with a larger cross-sectional area and the first heat sink 17, further reducing the thermal resistance, and achieving good heat dissipation for the first chip 12a.

[0185] For example, the vertical projection of the first heat dissipation member 17 on the substrate covers at least 50% of the vertical projection area of the first region on the substrate, which can further improve the heat dissipation effect on the first chip 12a.

[0186] In some examples, such as the vertical projection of the first heat dissipation member 17 on the substrate can cover 80% - 90% of the vertical projection area of the first region on the substrate, which has a better heat dissipation effect on the first chip 12a.

[0187] Exemplarily, the vertical projection of the first heat dissipation member 17 on the substrate can cover at least 50% of the vertical projection area of the first chip 12a on the substrate, which is conducive to the vertical projection of the first heat dissipation member 17 covering a larger heat conduction region 121, and achieving good heat dissipation for the first chip 12a.

[0188] For example, the vertical projection of the first heat dissipation member 17 on the substrate can cover 80% - 90% of the vertical projection area of the first chip 12a on the substrate, which can also further improve the heat dissipation effect on the first chip 12a.

[0189] In some examples, the vertical projection of the first heat dissipation member 17 on the substrate can completely cover the vertical projection of the first chip 12a on the substrate, achieving a better heat dissipation effect on the first chip 12a. It should be noted that the shape, cross-sectional size, etc. of the first heat dissipation member 17 can be the same as those of the first chip 12a, so that the vertical projection of the first heat dissipation member 17 on the substrate can completely coincide with the vertical projection of the first chip 12a on the substrate. Or, the cross-sectional size of the first heat dissipation member 17 can be larger than that of the first chip 12a, so that the vertical projection area of the first heat dissipation member 17 on the substrate can be larger than the vertical projection of the first chip 12a on the substrate, and the projection of the first heat dissipation member 17 completely covers the projection of the first chip 12a.

[0190] It can be understood that in order to transfer the heat of the chip module 10 to the outside of the chip module 10, the first heat dissipation member 17 can be exposed or the first heat dissipation member 17 can be in contact connection with other structural members to transfer the heat and achieve heat dissipation. For example, the first heat dissipation member 17 can be connected to the circuit board to transfer the heat of the chip module 10 to the circuit board, thereby achieving heat dissipation.

[0191] To expose the first heat sink or connect it to other structural components, the first heat sink needs to be exposed from the second encapsulation component. Exemplarily, after covering the encapsulation layer on the second surface, the encapsulation layer can be thinned by grinding or other methods to form the second encapsulation component, and the conductive component and the first heat sink are exposed. Due to process tolerances and the like, to ensure the exposure of the first heat sink, it is usually necessary to grind away part of the first heat sink, that is, the grinding depth of the encapsulation layer (the thickness in the x direction) needs to reach the position where part of the first heat sink can be removed. When the encapsulation layer is thinned, the first heat sink is also thinned. However, since the forming materials of the first heat sink and the encapsulation layer are different, during the thinning process, problems such as delamination, cracks, or separation are likely to occur at the position where the circumferential side wall of the first heat sink meets the encapsulation layer, resulting in a poor yield. Moreover, when the chip module is fixed to the circuit board by welding or other means, the solder on the circuit board is likely to enter the delaminated, cracked, or separated part, resulting in problems such as short circuits.

[0192] Therefore, in the embodiments of the present application, as shown in Figure 3 the first end face of the first heat sink 17 is recessed in the thickness direction with respect to the side of the second encapsulation component 14 facing away from the substrate 11, that is, the first end face of the first heat sink 17 is recessed inward from the side of the second encapsulation component 14 facing away from the substrate 11. In the thickness direction (x direction), the distance from the first end face of the first heat sink 17 to the second surface 11b is less than the distance from the side of the second encapsulation component 14 facing away from the substrate 11 to the second surface 11b, so that a preset distance is reserved between the first end face of the first heat sink 17 and the side of the second encapsulation component 14 facing away from the substrate 11 in the x direction. It should be noted that since the first end face of the first heat sink 17 is recessed from the side of the second encapsulation component 14 facing away from the substrate 11, the side of the second encapsulation component 14 facing away from the substrate 11 is actually a non-planar surface. To illustrate that there is a preset distance between the first end face of the first heat sink 17 and the side of the second encapsulation component 14 facing away from the substrate 11 in the x direction, the side of the second encapsulation component 14 facing away from the substrate 11 can be a virtual plane, which can be consistent with the side of the encapsulation thin layer (the part of the encapsulation layer that has not been removed) facing away from the substrate after the encapsulation layer is thinned. The preset distance between the first end face of the first heat sink 17 and the side of the second encapsulation component 14 facing away from the substrate 11 can be the preset distance in the thickness direction between the virtual plane and the first end face of the first heat sink 17, such as Figure 3 h shown in

[0193] During the process of thinning the encapsulation layer, the grinding depth (the thickness in the x direction) does not reach the position of the first heat sink 17 (the position of the first end face), and after the encapsulation layer is thinned, the first end of the first heat sink 17 is located inside the part of the encapsulation layer that has not been removed (the encapsulation thin layer) (refer to Figure 15eAs shown in the figure, a preset distance can be provided between the end face of the first end of the first heat sink 17 and the side of the encapsulation thin layer facing away from the substrate. After forming the second encapsulation member 14 through the encapsulation thin layer so that the end face of the first end of the first heat sink 17 is recessed inward relative to one side of the second encapsulation member 14, the preset distance is still reserved between the end face of the first end of the first heat sink 17 and the side of the second encapsulation member 14 facing away from the substrate 11. Without thinning the first heat sink while thinning the encapsulation layer, problems such as delamination, cracks, or separation at the junction between the circumferential side wall of the first heat sink 17 and the encapsulation layer during the thinning process are avoided. This can improve the grindability and reliability of the side of the encapsulation layer facing away from the substrate 11 during the thinning process, improve the yield, and also avoid problems such as short circuits, having higher reliability.

[0194] Exemplarily, the range of the preset distance h between the end face of the first end of the first heat sink 17 and the side of the second encapsulation member 14 facing away from the substrate 11 can be 10 μm to 20 μm, ensuring that the position of the first heat sink 17 is not removed during the thinning process of the encapsulation layer. After the thinning process, the first end of the first heat sink 17 is located inside the non-removed encapsulation thin layer, improving the reliability and operability of the thinning process.

[0195] In some examples, referring to Figure 3 As shown in the figure, there can be a groove 18 on the side of the second encapsulation member 14 facing away from the substrate 11. For example, the encapsulation thin layer can be processed by laser grooving or other methods to form the second encapsulation member 14, and the groove 18 is formed on the side of the second encapsulation member 14 facing away from the substrate 11. The groove 18 can be located on the side of the first heat sink 17 facing away from the substrate 11, and the groove 18 extends to the first end of the first heat sink 17, so that the end face of the first end of the first heat sink 17 is recessed inward relative to the side of the second encapsulation member 14 facing away from the substrate 11.

[0196] Exemplarily, the first end of the first heat sink 17 can be partially exposed on the side of the second encapsulation member 14 facing away from the substrate 11 through the groove 18, so that the heat of the first chip 12a can be transferred to the outside of the chip module 10 through the first heat sink 17, or it is convenient to connect the first end of the first heat sink 17 to other structural members.

[0197] For example, when the chip module 10 is connected and assembled to the circuit board, the first end of the first heat sink 17 can be fixedly assembled to the circuit board, so that the heat of the first chip 12a can be transferred to the circuit board to achieve heat dissipation. For example, referring to Figure 4As shown, one end of the conductive member 15 facing away from the substrate and one end of the first heat sink 17 facing away from the substrate can be respectively exposed from the second encapsulation member 14. When the chip module 10 is connected and assembled with the circuit board, the end of the conductive member 15 facing away from the substrate can be fixed to the circuit board and electrically connected by means such as soldering. The exposed part of the first heat sink 17 can be fixedly assembled with the circuit board so that the heat of the first chip is transferred to the outside of the chip module.

[0198] The shape of the groove 18 can be circular. Alternatively, in some examples, the shape of the groove 18 can also be other regular or irregular shapes such as rectangular, oval, etc.

[0199] Figure 5 It is a schematic cross-sectional structure diagram of another chip module provided by an embodiment of the present application.

[0200] Alternatively, in some examples, referring to Figure 5 As shown, the chip module 10 may further include a first connecting member 110. The first connecting member 110 can be disposed on the first heat sink 17, and the first connecting member 110 can be located in the opened groove.

[0201] Among them, the setting of the groove can enable the first connecting member to have a higher interfacial freedom during the forming process. For example, during the process of preparing the spherical first connecting member, the forming material of the first connecting member can be placed in the groove and have a gap with the second encapsulation member, so that the forming material of the first connecting member has a high degree of freedom, which is beneficial to the spherical forming of the first electrical connecting member and improves the forming yield of the first electrical connecting member.

[0202] It should be noted that the first connecting member 110 can partially fill the groove to keep a higher interfacial freedom during the forming process of the first connecting member 110. For example, the vertical projection of the formed first connecting member 110 on the substrate 11 partially covers the vertical projection of the groove on the substrate 11. Referring to Figure 5 As shown, there can be a gap 181 between the outer wall surface of the first connecting member 110 and the second encapsulation member 14, that is, the vertical projection of the first connecting member 110 on the first end of the first heat sink 17 partially covers the exposed part of the first end of the first heat sink 17, so that part of the first heat sink 17 can still be exposed from the side of the second encapsulation member 14 facing away from the substrate 11.

[0203] Alternatively, the first connecting member 110 can also fill the entire groove. For example, the vertical projection of the formed first connecting member 110 on the substrate 11 completely covers the vertical projection of the groove on the substrate 11, and the outer wall surface of the first connecting member 110 located in the groove extends to the second encapsulation member 14, so that the vertical projection of the first connecting member 110 on the first end of the first heat sink 17 can completely cover the exposed part of the first end of the first heat sink 17, and the first heat sink 17 will not be exposed from the side of the second encapsulation member 14 facing away from the substrate 11.

[0204] Figure 6 For Figure 5 the schematic diagram of the chip module and the circuit board assembly in

[0205] See Figure 6 As shown, when assembled and connected to the circuit board 20, the first heat sink 17 can be fixedly assembled with the circuit board 20 through the first connecting member 110, improving the assembly stability of the chip module 10 and the circuit board 20, and can also transfer heat to the circuit board 20 for heat dissipation, improving the heat dissipation effect.

[0206] Exemplarily, one end of the first connecting member 110 facing away from the first heat sink 17 can protrude from the side of the second encapsulation member 14 facing away from the substrate 11, that is, one end of the first connecting member 110 facing away from the first heat sink 17 protrudes from the second encapsulation member 14, which is convenient for realizing the assembly of the first connecting member 110 and the circuit board 20.

[0207] In some examples, the first connecting member 110 can be a welding part. For example, the first connecting member 110 can also be a solder ball, such as a tin ball, and the first connecting member 110 can be fixedly welded to the conductive part on the circuit board 20 by welding.

[0208] In some examples, the first connecting member 110 can be electrically connected to the circuit board 20, and the first heat sink 17 can be electrically connected to the chip through the substrate 11, so that the chip can be electrically connected to the circuit board 20 through the first heat sink 17 and the first connecting member 110. For example, see Figure 6 As shown, the substrate 11 can have a connection trace 111e, and the fourth chip 12d located on the second surface 11b can be electrically connected to the first heat sink 17 through the connection trace 111e. The first heat sink 17 can be electrically connected to the circuit board 20 through the first connecting member 110, and further electrically connect the fourth chip 12d to the circuit board 20. For example, the grounding of the fourth chip 12d can be achieved through this connection method.

[0209] Of course, in other examples, there may be no connection between the first heat sink 17 and the chip, and the first connecting member 110 and the circuit board 20 may only play a role of heat conduction connection and do not need to achieve electrical connection.

[0210] Alternatively, in some examples, the first connecting member 110 may also be other types of connection structural members. For example, the first connecting member 110 may also be an adhesive layer, a snap connector, a threaded fastener, etc., so that the chip module 10 can be fixed to the circuit board 20 by means of adhesion, snap connection, threaded fastening, etc.

[0211] It should be noted that, in some examples, referring to Figure 6 As shown, the number of the first connecting members 110 fixed on the first heat dissipation member 17 may be multiple. For example, a plurality of first connecting members 110 may be arranged in an array on the first heat dissipation member 17, and the plurality of first connecting members 110 may be arranged at intervals.

[0212] Figure 7 FIG. is a schematic cross-sectional structure diagram of another chip module provided by an embodiment of the present application.

[0213] Alternatively, in some other examples, referring to Figure 7 As shown, the number of the first connecting members 110 may also be one.

[0214] Taking the example that the first heat dissipation member 17 at least covers the first region of the first chip 12a, the assembly relationship among the first chip 12a, the first heat dissipation member 17 and the substrate 11 will be described below.

[0215] In some examples, as shown in Figure 7 the first chip 12a may be disposed on the first surface 11a of the substrate 11.

[0216] On the side of the first chip 12a facing the substrate 11, there is a first electrical connecting member 121a. The connection trace 111d of the substrate 11 may extend to the first surface 11a of the substrate 11. The first electrical connecting member 121a of the first chip 12a and the connection trace 111d may be electrically connected through a welding member 16, so as to realize the electrical connection between the first chip 12a and the substrate 11. The heat of the first chip 12a is transferred to the substrate 11 through the first electrical connecting member 121a, and then heat dissipation is realized through the first heat dissipation member 17. One end end face of the first electrical connecting member 121a connected to the substrate 11 forms a heat conduction region (such as the first region) of the first chip 12a.

[0217] Exemplarily, the first heat sink 17 can be fixed on the second surface 11b of the substrate 11. For example, the second end of the first heat sink 17 is fixed to the second surface 11b of the substrate 11, so that the first chip 12a and the first heat sink 17 are respectively located on the first surface 11a and the second surface 11b of the substrate 11, and the structural design is relatively simple. When preparing the chip module 10, when setting the chip on the second surface 11b, the first heat sink 17 can be set on the second surface 11b as well, which can be fully compatible with the preparation process flow of the existing DSBGA packaged chip module in the related technology, without adding extra processes, and is beneficial to cost saving.

[0218] In the embodiment of the present application, the heat dissipation effect of the chip module 10 is simulated. Figure 8 For Figure 7 the schematic diagram of the junction-to-board thermal resistance model of the first chip in the chip module.

[0219] See Figure 8 As shown, the first electrical connector 121a of the first chip 12a is connected to the connection trace 111d on the first surface 11a of the substrate 11 through the welding part 16. Taking the example that the first heat sink 17 is fixed to the conductive part 21 on the circuit board by welding, there can be a welding layer 22 between the first heat sink 17 and the conductive part 21, and the connection trace 111e on the second surface 11b of the substrate 11 is connected to the conductive part 21 on the circuit board through the first heat sink 17 and the welding layer 22. The forming material of the first heat sink 17 is copper.

[0220] The position of the first chip 12a opposite to the heat conduction area can be used as the heat source S, and the heat can be transferred from the first electrical connector 121a of the first chip 12a to the circuit board in sequence along the thickness direction, forming a constant temperature surface H on the circuit board side.

[0221] Taking the DSBGA packaged chip module in the related technology as the control group, and in the chip module of the control group, the layout position of the solder balls can be the ideal position with the best heat dissipation effect in theory. For example, the solder balls can be arranged below the heat conduction area of the first chip, the first electrical connector of the first chip is connected to the connection trace on the first surface of the substrate through the welding part, and the connection trace on the second surface of the substrate is connected to the conductive part on the circuit board through the solder balls and the welding layer. The solder balls are tin balls. Table 1 shows the forming materials and thermal conductivities of the structural parts in the above model. The chip module 400 of the control group has the same other structural designs as the chip module 10 in the embodiment of the present application.

[0222] Table 1 is the forming materials and thermal conductivities of some structural components in the above model.

[0223] Component Material Thermal Conductivity First Chip Silicon 130 W / (mK) First Electrical Connector / First Heat Sink / Connection Trace / Conductive Component Copper 400 W / (mK) Welding Component / Solder Ball / Welding Layer Sn Alloy 50 W / (mK) Substrate FR4 Resin 0.3 W / (mK)

[0224] Figure 9Schematic diagram of heat conduction simulation of the first chip in a ball grid array chip module in the related art Figure 10 Is Figure 7 Schematic diagram of heat conduction simulation of the first chip in the chip module of

[0225] Combined with Figure 9 And Figure 10 As shown, even compared with the theoretically ideal ball grid array chip module 500, in the chip module 10 of the embodiment of the present application, the first heat dissipation member 17 formed of metallic copper is used to replace the solder balls, so that the vertical projection of the first heat dissipation member 17 at least covers the vertical projection of a part of the heat conduction area of the first chip 12a (such as covering the first area), and the temperature difference is reduced by 35%, having a more significant heat dissipation effect.

[0226] Figure 11 Schematic cross-sectional structure diagram of another chip module provided by the embodiment of the present application.

[0227] In some examples, as shown in Figure 11 In order to further improve the heat dissipation performance, the first heat dissipation member 17 is fixed on the second surface 11b of the substrate 11, and the substrate 11 may further be provided with a second heat dissipation member 112.

[0228] The forming material of the second heat dissipation member 112 may also be a material with a high thermal conductivity coefficient. The forming material of the second heat dissipation member 112 may be the same as the forming material of the first heat dissipation member 17. For the forming material, shape and thermal conductivity coefficient of the second heat dissipation member 112, reference may be made to the first heat dissipation member 17, which will not be elaborated in this example.

[0229] The second heat dissipation member 112 may be located on the side of the first surface 11a facing the second surface 11b. The second heat dissipation member 112 is located between the first surface 11a and the surface of the second encapsulation member 14 facing away from the substrate 11, that is, the second heat dissipation member 112 will not be exposed from the first surface 11a either. The vertical projection of the second heat dissipation member 112 on the substrate 11 may at least partially coincide with the vertical projection of the first heat dissipation member 17 on the substrate 11, that is, the projection of the second heat dissipation member 112 on the substrate 11 along the x direction at least partially coincides with the projection of the first heat dissipation member 17 on the substrate 11 along the x direction. Reducing the thermal resistance on the heat dissipation path from the first chip 12a to the first heat dissipation member 17 is beneficial to further improving the heat dissipation effect.

[0230] It should be noted that the vertical projections of the second heat dissipation member 112 and the first heat dissipation member 17 on the substrate 11 may completely coincide, or the vertical projections of the second heat dissipation member 112 and the first heat dissipation member 17 on the substrate 11 may partially coincide. For example, the vertical projection of the second heat dissipation member 112 on the substrate 11 may at least cover 50% of the vertical projection area of the first heat dissipation member 17 on the substrate 11 to ensure a better heat dissipation effect.

[0231] In a possible implementation, referring to Figure 11 as shown, the second heat sink 112 may be located inside the substrate 11, that is, the second heat sink 112 is located between the first surface 11a and the second surface 11b, and the second heat sink 112 does not protrude from the first surface 11a and the second surface 11b. While improving the heat dissipation effect, the structural design is simplified and easy to implement.

[0232] Figure 12 This is a schematic cross-sectional structure diagram of another chip module provided by an embodiment of the present application.

[0233] In another possible implementation, referring to Figure 12 as shown, one end of the second heat sink 112 may be located inside the substrate 11, and the other end of the second heat sink 112 may extend towards the inside of the second package 14 in the thickness direction. The second end of the first heat sink 17 may be fixed to the other end of the second heat sink 112, so that the first heat sink 17 is fixed on the second surface 11b, which is beneficial to increasing the thickness of the second heat sink 112, further reducing the thermal resistance, and enriching the fixing and assembling method between the first heat sink 17 and the second surface 11b of the substrate 11, having better structural design flexibility.

[0234] Exemplarily, the end face of the other end of the second heat sink 112 may extend to the side of the substrate 11 facing away from the first surface 11a, and the end face of the other end of the second heat sink 112 may be flush with the side of the substrate 11 facing away from the first surface 11a, so that the end face of the other end of the second heat sink 112 is used to form a part of the second surface 11b, and the first heat sink 17 is fixed on the end face of the other end of the second heat sink 112.

[0235] Exemplarily, to realize the fixation between the first heat sink 17 and the second heat sink 112, the chip module 10 may further include a second connecting member 120. The first heat sink 17 may be fixed to the end face of the end of the second heat sink 112 facing away from the first surface 11a through the second connecting member 120.

[0236] Among them, the second connecting member 120 may also be a welding member. For example, the second connecting member 120 may be a solder ball, a solder pad, etc., so that the first heat sink 17 can be fixed to the end face of the second heat sink 112 by welding.

[0237] Alternatively, the second connecting member 120 may also be other types of connection structural members. For example, the second connecting member 120 may also be an adhesive layer, a clamping member, a threaded fastener, etc., so that the first heat sink 17 can be fixed to the end face of the second heat sink 112 by bonding, clamping, threaded fastening, etc.

[0238] Figure 13Another cross-sectional structure schematic diagram of the chip module provided by the embodiment of the present application.

[0239] Alternatively, in some other examples, refer to Figure 13 As shown, the second end of the first heat dissipation member 17 can extend into and be fixed inside the substrate 11, that is, the first heat dissipation member 17 is inserted on the substrate 11. Part of the first heat dissipation member 17 is located inside the substrate 11, and part of the first heat dissipation member 17 is located inside the second encapsulation member 14. Fixing the second end of the first heat dissipation member 17 to extend into the inside of the substrate 11 is beneficial to reducing the number of heat dissipation members arranged on the substrate 11, simplifying the structural design and the forming process, and is conducive to reducing costs while further reducing the thermal resistance and improving the heat dissipation effect.

[0240] Figure 14 Another cross-sectional structure schematic diagram of the chip module provided by the embodiment of the present application.

[0241] Alternatively, in some other examples, refer to Figure 14 As shown, the first chip 12a can be arranged on the second surface 11b of the substrate 11.

[0242] On the side of the first chip 12a facing the substrate 11, there is a second electrical connection member 121c. The connection trace 111d of the substrate 11 can be located on the second surface 11b of the substrate 11. The first chip 12a can be electrically connected to the connection trace 111d of the substrate 11 through the second electrical connection member 121c, and then electrically connected to the conductive member 15 through the connection trace 111d.

[0243] Correspondingly, the second electrical connection member 121c of the first chip 12a can also be electrically connected to the connection trace 111d through the welding member 16.

[0244] The first heat dissipation member 17 can be fixed on the side of the first chip 12a facing away from the substrate 11. The heat generated by the first chip 12a is transferred to the first heat dissipation member 17 to achieve heat dissipation. The side of the first chip 12a facing the first heat dissipation member 17 forms the heat conduction area of the first chip 12a, further shortening the heat dissipation path, reducing the thermal resistance, and improving the heat dissipation efficiency.

[0245] Exemplarily, the first heat dissipation member 17 can be formed by the back gold layer of the first chip 12a itself. Enriching the layout methods of the first chip 12a and the first heat dissipation member 17 improves the layout flexibility.

[0246] Of course, in some other examples, the first heat dissipation member 17 can also be a heat dissipation structural member additionally arranged on the first chip 12a.

[0247] The embodiment of the present application also provides a method for manufacturing a chip module. Figure 15 A flowchart of a method for manufacturing a chip module provided by the embodiment of the present application. Refer toFigure 15 As shown, the above chip module 10 can be prepared by this preparation method.

[0248] This preparation method includes:

[0249] S101: Provide a substrate, a first heat dissipation member, and a plurality of chips.

[0250] Figure 15a It is a schematic diagram of a chip module provided by an embodiment of the present application after some chips are assembled on a substrate.

[0251] Refer to Figure 15a As shown, the substrate 11 has a first surface 11a and a second surface 11b facing away from each other in the thickness direction. The substrate 11 has connecting traces inside, and the connecting traces can extend to the first surface 11a and the second surface 11b of the substrate 11. For example, the connecting trace 111a extends to the first surface 11a of the substrate 11, and the connecting trace 111c is located on the second surface 11b of the substrate 11.

[0252] For the specific structures of the substrate 11, the connecting traces, the chips, and the first heat dissipation member 17, etc., reference can be made to the foregoing, and details will not be elaborated in this example.

[0253] S102: Arrange some of the plurality of chips on the first surface and form a first encapsulation member on the first surface.

[0254] Such as Figure 15a As shown, some chips are assembled on the first surface 11a of the substrate 11. For example, taking the first chip 12a fixed on the first surface 11a of the substrate 11 as an example, the first chip 12a, the second chip 12b, and the third chip 12c are assembled and fixed on the first surface 11a, and the first chip 12a, the second chip 12b, and the third chip 12c are electrically connected to the connecting traces of the substrate 11 correspondingly.

[0255] Among them, the chips can be fixed on the first surface 11a by surface mounted technology (SMT) mounting, or the chips can also be fixed on the first surface 11a by welding, bonding, etc.

[0256] Figure 15b It is a schematic diagram of a chip module provided by an embodiment of the present application after the first encapsulation member is formed on the substrate.

[0257] Refer to Figure 15bAs shown, a first encapsulation member 13 is formed on the first surface 11a of the substrate 11. The first encapsulation member 13 can cover the first surface 11a and at least partially encapsulate the chips located on the first surface 11a within the first encapsulation member 13, so as to achieve plastic encapsulation of the chips on the first surface 11a. Exemplarily, the first chip 12a, the second chip 12b, and the third chip 12c can be encapsulated inside the first encapsulation member 13.

[0258] S103: Arrange another part of the multiple chips on the second surface, and at least the first end of the first heat dissipation member is located on the second surface.

[0259] Figure 15c This is a schematic diagram of a chip module provided by an embodiment of the present application after chips and solder joints are assembled on a substrate.

[0260] See Figure 15c As shown, another part of the chips is assembled on the second surface 11b of the substrate 11. For example, the fourth chip 12d is fixedly assembled on the second surface 11b, and the connection traces between the fourth chip 12d and the substrate 11 are electrically connected correspondingly.

[0261] Among them, the chips can also be fixed on the second surface 11b by means of SMT mounting, soldering, bonding, etc.

[0262] Exemplarily, before or after arranging the chips on the second surface 11b, at least the first end of the first heat dissipation member can also be located on the second surface. See Figure 15c As shown, taking the fixation of the second end of the first heat dissipation member 17 to the second surface 11b of the substrate 11 as an example, before or after arranging the chips on the second surface 11b, the first heat dissipation member 17 can also be fixed on the second surface 11b. And the vertical projection of the first heat dissipation member 17 on the substrate 11 at least partially covers the vertical projection of the heat conduction area of the first chip 12a on the substrate 11.

[0263] S104: Form an encapsulation layer on the second surface.

[0264] Figure 15d This is a schematic diagram of the formation of an encapsulation layer on the second surface of a chip module in an embodiment of the present application.

[0265] See Figure 15d As shown, the encapsulation layer 141 covers the second surface 11b and the encapsulation layer 141 wraps the chips and the first heat dissipation member 17 located on the second surface 11b. Exemplarily, the fourth chip 12d and the first heat dissipation member 17 are encapsulated inside the encapsulation layer 141.

[0266] S105: Thinning the encapsulation layer to form a thin encapsulation layer.

[0267] Exemplarily, the thinning of the encapsulation layer can be achieved by means such as grinding and removal.

[0268] Figure 15e This is a schematic diagram after thinning the encapsulation layer in a chip module according to an embodiment of the present application.

[0269] Part of the encapsulation layer can be removed to achieve the thinning of the encapsulation layer. Refer to Figure 15e As shown, the remaining part of the encapsulation layer forms an encapsulation thin layer 141a, and the encapsulation thin layer 141a is used to form the second encapsulation component. After the encapsulation layer thinning process forms the encapsulation thin layer 141a, the first end of the first heat dissipation component 17 is wrapped inside the encapsulation thin layer 141a. For example, there may be a preset distance h between the end face of the first end of the first heat dissipation component 17 and the side of the encapsulation thin layer 141a facing away from the substrate 11. After thinning, the first heat dissipation component 17 is not exposed on the side of the encapsulation thin layer 141a facing away from the substrate 11. That is, during the process of thinning the encapsulation layer, the depth of grinding and removal (thickness along the x direction) does not reach the position of the first end face of the first heat dissipation component 17, and the first heat dissipation component 17 is not thinned during the thinning of the encapsulation layer, thus avoiding problems such as delamination, cracks, or separation at the junction of the circumferential side wall of the first heat dissipation component 17 and the encapsulation layer during the grinding and thinning process, improving the workability and reliability of grinding the encapsulation layer, improving the yield rate, and also being able to avoid problems such as short circuits.

[0270] S106: Process the encapsulation thin layer to form the second encapsulation component, so that one end face of the first heat dissipation component is recessed in the thickness direction relative to the side of the second encapsulation component facing away from the substrate.

[0271] For example, the encapsulation thin layer can be processed to form the second encapsulation component by means such as grooving on the encapsulation thin layer or specifically removing the part of the encapsulation thin layer opposite to one end of the first heat dissipation component, so that the first end face of the first heat dissipation component is recessed inward relative to the side of the second encapsulation facing away from the substrate, that is, the first end face of the first heat dissipation component is recessed in the thickness direction relative to the side of the second encapsulation component facing away from the substrate towards the first encapsulation component.

[0272] Exemplarily, the above step S106 of processing the encapsulation thin layer to form the second encapsulation component may include: opening a groove on the side of the encapsulation thin layer facing away from the substrate to form the second encapsulation component.

[0273] For example, a groove can be opened on the side of the encapsulation thin layer 141a facing away from the substrate 11 by means of laser grooving to form the second encapsulation component.

[0274] Figure 15f This is a schematic diagram after the second encapsulation component is formed in a chip module provided by an embodiment of the present application.

[0275] Refer to Figure 15fAs shown, on the side of the formed second package 14 facing away from the substrate 11, there is a groove 18. The groove 18 can be located on the side of the first heat sink 17 facing away from the substrate 11, and the groove 18 extends to the first end of the first heat sink 17, so that the end face of the first end of the first heat sink 17 is recessed in the thickness direction relative to the side of the second package 14 facing away from the substrate 11. It is ensured that in the thickness direction, there is still a preset distance h between the end face of the first end of the first heat sink 17 and the side of the second package 14 facing away from the substrate 11.

[0276] To form the conductive components of the chip module to achieve the electrical connection between the chip module and the external circuit board, before step S104 of forming the encapsulation layer on the second surface, the method further includes: forming a plurality of spaced solder joints on the second surface.

[0277] For example, a plurality of solder balls can be formed on the second surface by stencil printing as the plurality of solder joints 15a (refer to Figure 15c shown), and the plurality of solder joints 15a are arranged at intervals. The solder joints 15a can be electrically connected to the connection traces on the second surface 11b, so as to achieve the electrical connection between the chip and the corresponding solder joints.

[0278] Step S104 of forming the encapsulation layer on the second surface includes: making the encapsulation layer wrap the solder joints (refer to Figure 15d shown).

[0279] After step S104 of forming the encapsulation layer on the second surface, the method further includes: thinning the solder joints to form conductive components.

[0280] Among them, the synchronous thinning of the encapsulation layer and the solder joints can be achieved by means of grinding and removal (refer to Figure 15d and Figure 15e shown). The unremoved encapsulation thin layer 141a is used to form the second package 14, and the unremoved part of the solder joints is used to form the conductive components 15, ensuring that the end of the conductive component 15 facing away from the substrate 11 is exposed on the side of the second package 14 facing away from the substrate 11, so that the conductive component 15 is exposed from the second package 14.

[0281] Exemplarily, thinning the solder joints to form conductive components may include:

[0282] S1041: Thinning the solder joints to form transitional solder joints.

[0283] The unremoved part after thinning the solder joints forms the transitional solder joints 15b (refer to Figure 15f shown).

[0284] S1042: Forming a notch structure on the side of the encapsulation thin layer facing away from the substrate.

[0285] For example, a notch structure 19a can be formed on the side of the encapsulation thin layer facing away from the substrate 11 by means such as laser grooving. The notch structure 19a can be arranged to surround the transition solder joint 15b, so that after the second encapsulation member is formed, the side of the second encapsulation member 14 facing away from the substrate 11 has the notch structure 19a (refer to Figure 15f as shown).

[0286] S1043: A first solder structure is arranged on the transition solder joint, and the transition solder joint and the first solder structure are subjected to reflow treatment to form a conductive member.

[0287] Figure 15g The figure is a schematic diagram of a first solder structure and a second solder structure arranged on a transition solder joint in a chip module provided by an embodiment of the present application.

[0288] See Figure 15g as shown, the first solder structure 130 is arranged on the transition solder joint 15b. Among them, the first solder structure 130 can be solder paste, and the first solder structure 130 can also be fixed on the transition solder joint 15b by means such as printing, so that after the transition solder joint 15b and the first solder structure 130 are subjected to reflow treatment, a conductive member 15 is formed (refer to Figure 15i as shown).

[0289] The notch structure 19a can increase the interfacial freedom degree of the transition solder joint 15b and the first solder structure 130, which is beneficial to the reflow forming of the conductive member 15, and is especially beneficial to the forming of a spherical conductive member.

[0290] Of course, in some examples, step S1042 can also be omitted, that is, it is not necessary to form the notch structure 19a on the side of the second encapsulation member facing away from the substrate.

[0291] In some examples, the formed conductive member 15 can partially fill the notch structure 19a. For example, the vertical projection of the conductive member 15 on the substrate 11 partially covers the vertical projection of the notch structure 19a on the substrate 11, so that there can be a gap 19 between the outer wall surface of the conductive member 15 and the second encapsulation member 14 (refer to Figure 15i as shown).

[0292] Or, in some examples, the formed conductive member 15 can also completely fill the notch structure 19a. For example, the vertical projection of the conductive member 15 on the substrate 11 completely covers the vertical projection of the notch structure 19a on the substrate 11, so that the outer wall surface of the conductive member 15 can extend to the second encapsulation member 14.

[0293] It can be understood that controlling the amount of the first solder structure 130 can control the thickness dimension, etc. of the conductive member 15 after reflow, and can make the end of the conductive member 15 facing away from the substrate 11 protrude from the side of the second encapsulation member 14 facing away from the substrate 11.

[0294] In some examples, a part of the first end of the first heat sink 17 can be exposed from the second package 14 through the formed groove 18 (see Figure 15f shown), so that heat can be transferred to the outside of the chip module 10 through the first heat sink 17.

[0295] Alternatively, in some examples, the chip module may further include a first connecting member, and the first connecting member can be fixed to the first heat sink 17, so that the first heat sink 17 can be externally connected to a structural member such as a circuit board through the first connecting member, and heat can be transferred to the outside of the chip module through the first heat sink 17 and the first connecting member. For the specific structure of the first connecting member, refer to the above, and it will not be elaborated in this example.

[0296] After forming the groove on the side of the encapsulation thin layer facing away from the substrate to form the second package, the manufacturing method may further include:

[0297] S107: Set a second solder structure on the first end of the first heat sink.

[0298] See Figure 15g shown, the second solder structure 140 is placed on the first end of the first heat sink 17, and the second solder structure 140 can be located in the groove 18. For example, the groove 18 can be arranged to surround the second solder structure 140. The groove 18 can improve the freedom degree of the interface of the second solder structure 140, which is beneficial to the reflow forming of the first connecting member.

[0299] Figure 15h FIG. is a bottom view schematic diagram of a first heat sink with a first solder structure and a second solder structure provided in an embodiment of the present application.

[0300] Combined with Figure 15h shown, the second solder structure 140 can be fixed on the end face of the first end of the first heat sink 17. Exemplarily, the second solder structure 140 can be solder paste, and the second solder structure 140 can be fixed on the first end face of the first heat sink 17 by printing or other means.

[0301] S108: After reflow processing the second solder structure, form a first connecting member.

[0302] For example, after the solder paste is reflow processed, solder balls can be formed as the first connecting member.

[0303] Figure 15i FIG. is a schematic diagram after reflow of the second solder structure in a chip module provided in an embodiment of the present application. See Figure 15i shown, thus a first connecting member 110 is formed on the first heat sink 17, so that the first heat sink 17 can be assembled and connected to an external circuit board through the first connecting member 110.

[0304] In some examples, the first connecting member 110 formed after reflow can partially fill the groove, such as the vertical projection of the first connecting member 110 on the substrate 11 partially covering the vertical projection of the groove on the substrate 11. Refer to Figure 15i As shown, there is a gap 181 between the first connecting member 110 and the second package 14, and the first end portion of the first heat sink 17 can still be exposed from the side of the second package 14 facing away from the substrate 11.

[0305] Alternatively, in some examples, the formed first connecting member 110 can also fill the entire groove, such as the vertical projection of the first connecting member 110 on the substrate 11 completely covering the vertical projection of the groove on the substrate 11, so that the outer wall surface of the first connecting member 110 extends to the second package 14, and the first heat sink 17 is not exposed from the side of the second package 14 facing away from the substrate 11.

[0306] Correspondingly, by controlling the amount of the second solder structure 140, the control of the thickness dimension of the first connecting member 110 after reflow can be achieved, and one end of the first connecting member 110 facing away from the first heat sink 17 can also protrude from the side of the second package 14 facing away from the substrate 11.

[0307] It should be noted that to simplify the forming process, the notch structure and the groove can be formed synchronously, and the printing forming and reflow treatment of the first solder structure and the second solder structure can also be formed synchronously.

[0308] For example, when opening a groove in the encapsulation thin layer by means of laser grooving or the like, the notch structure can be synchronously opened in the encapsulation thin layer in the same way, so that the side of the formed second package 14 facing away from the substrate 11 has a groove 18 and a notch structure 19a (refer to Figure 15f As shown).

[0309] For example, when setting the first solder structure 130 on the transition solder joint by printing or the like, the second solder structure 140 can also be synchronously set on the first heat sink 17 in the same way (refer to Figure 15g As shown).

[0310] When performing reflow treatment on the first solder structure 130 and the transition solder joint, the reflow treatment of the second solder structure 140 can also be synchronously completed in the same way, and the conductive member 15 and the first connecting member 110 are synchronously formed (refer to Figure 15i As shown).

[0311] Among them, in some examples, the first chip is disposed on the first surface of the substrate, and the first chip has a first electrical connecting member on the side facing the substrate.

[0312] The above step S102 of setting some of the multiple chips on the first surface may include: assembling the first chip on the first surface and electrically connecting the first chip to the substrate through a first electrical connector.

[0313] For example, the first electrical connector may be fixed to and electrically connected to the connection trace of the substrate by welding. In this way, the first chip is assembled on the first surface of the substrate, and the electrical connection between the first chip and the substrate is achieved. The heat of the first chip can be transferred to the substrate through the first electrical connector, and one end face of the first electrical connector connected to the substrate forms the heat conduction area of the first chip.

[0314] Exemplarily, providing the substrate and the first heat sink in the above step S101 may include S1011: fixing the second end of the first heat sink on the second surface. By this method, a chip module 10 with a layout in which the first chip 12a is located on the first surface 11a and the first heat sink 17 is located on the second surface 11b can be obtained (refer to Figure 7 shown).

[0315] Wherein, the second end of the first heat sink may be SMT-mounted on the second surface of the substrate. Alternatively, in some examples, the second end of the first heat sink may also be fixed on the second surface by other means. For example, it may be attached to the second surface by bonding.

[0316] In some examples, the substrate may further have a second heat sink, and the second heat sink may be formed on the substrate while the substrate is being formed, that is, the second heat sink is integrally formed during the formation process of the substrate.

[0317] Alternatively, after the second heat sink and the substrate are separately and independently formed, the second heat sink and the substrate may be assembled together.

[0318] The above step S1011 of fixing the second end of the first heat sink on the second surface may include: making the vertical projection of the first heat sink on the substrate and the vertical projection of the second heat sink on the substrate at least partially overlap, so as to further improve the heat dissipation effect through the second heat sink.

[0319] Exemplarily, the second heat sink may be fixed inside the substrate, that is, the second heat sink is located between the first surface and the second surface, and the first heat sink is assembled on the second surface. The assembly method can refer to step S1011. By this method, a chip module 10 with a layout in which the first chip 12a is located on the first surface 11a, the first heat sink 17 is located on the second surface 11b, and a second heat sink 112 is provided inside the substrate 11 can be obtained (refer to Figure 11 shown).

[0320] Alternatively, in some examples, one end of the second heat sink is located inside the substrate, and the other end of the second heat sink can extend towards the second package along the thickness direction. For example, the end face of the other end of the second heat sink extends to the side of the substrate facing away from the first surface, and the end face of the other end of the second heat sink can form part of the second surface.

[0321] The above step S1011 of fixing the second end of the first heat sink on the second surface may include: forming a second connecting member on the other end of the second heat sink, and fixing the second end of the first heat sink to the other end of the second heat sink through the second connecting member, so as to realize the fixed assembly of the first heat sink on the second surface of the substrate. Through this method, a chip module 10 with a layout in which the first chip 12a is located on the first surface 11a, the first heat sink 17 is located on the second surface 11b, one end of the second heat sink 112 is located inside the substrate 11, and the other end is fixed to the first heat sink can be obtained (refer to Figure 12 shown).

[0322] In some other examples, step S101 of providing a substrate and a first heat sink may include S1012: fixing the second end of the first heat sink inside the substrate. Through this method, a chip module 10 with a layout in which the first chip 12a is located on the first surface 11a and the first heat sink 17 is partially fixed inside the substrate 11 can be obtained (refer to Figure 13 shown).

[0323] Exemplarily, the first heat sink can be formed on the substrate while the substrate is being formed, that is, during the process of substrate formation, a substrate with the first heat sink inserted therein is integrally formed.

[0324] Alternatively, the first heat sink can also be fixed to the substrate by other means. For example, it can be inserted on the substrate by means of bonding, clamping, interference fit, etc.

[0325] In some other examples, the first chip can be disposed on the second surface of the substrate, and the first chip has a second electrical connecting member on the side facing the substrate.

[0326] The above step S103 of disposing another part of the multiple chips on the second surface may include:

[0327] S1031: Dispose the first chip on the second surface, and electrically connect the first chip to the substrate through the second electrical connecting member.

[0328] For example, the second electrical connecting member can also be welded to the connection trace of the substrate by welding to achieve electrical connection. Thus, the first chip is assembled on the second surface of the substrate through the above method, and the electrical connection between the first chip and the substrate is realized.

[0329] S1032: Fix the first heat sink on the side of the first chip facing away from the substrate.

[0330] The heat generated by the first chip can be directly dissipated through the first heat sink, and a heat conduction area is formed on the side of the first chip facing away from the first heat sink.

[0331] Exemplarily, the first heat sink can be a back gold layer on the first chip, and the first heat sink can be fixed on the side of the first chip facing away from the substrate by means such as SMT mounting, bonding, printing, etc. Through the above method, a chip module 10 with a layout where the first chip 12a is located on the second surface 11b and the first heat sink 17 is located on the first chip 12a can be obtained (refer to Figure 14 shown).

[0332] In the description of the embodiments of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "mount", "connect", and "couple" should be understood in a broad sense. For example, it can be a fixed connection, or an indirect connection through an intermediate medium, and can be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific situations. The terms "first", "second", "third", "fourth", etc. (if any) are used to distinguish similar objects and do not necessarily need to be used to describe a specific order or sequence.

[0333] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the embodiments of the present application, and are not intended to limit them; although the embodiments of the present application have been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip module, characterized in that, Comprising: A substrate having a first surface and a second surface facing away from each other in the thickness direction; A first encapsulation member disposed on the first surface; A second encapsulation member disposed on the second surface; A plurality of chips respectively disposed on the first surface and the second surface, and at least part of the chips are wrapped in the first encapsulation member or the second encapsulation member. The plurality of chips include a first chip having a heat conduction area for achieving heat conduction contact; A first heat dissipation member located between the first surface and the side of the second encapsulation member facing away from the substrate, and at least a first end of the first heat dissipation member is located in the second encapsulation member. The vertical projection of the first heat dissipation member on the substrate at least partially covers the vertical projection of the heat conduction area on the substrate; The end surface of the first end of the first heat dissipation member is recessed in the thickness direction with respect to the surface of the second encapsulation member facing away from the substrate, and there is a preset distance between the end surface of the first end and the surface of the second encapsulation member facing away from the substrate.

2. The chip module according to claim 1, wherein The preset distance is 10 μm to 20 μm.

3. The chip module according to claim 1 or 2, characterized in that, There are a plurality of the heat conduction areas, and the plurality of heat conduction areas at least include a first area, and the first area is the area with the largest cross-sectional area among the plurality of heat conduction areas; The vertical projection of the first heat dissipation member on the substrate at least partially covers the vertical projection of the first area on the substrate.

4. The chip module according to claim 3, wherein The vertical projection of the first heat dissipation member on the substrate at least covers 50% of the vertical projection area of the first area on the substrate.

5. The chip module according to any one of claims 1-4, characterized in that, The vertical projection of the first heat dissipation member on the substrate at least covers 50% of the vertical projection area of the first chip on the substrate.

6. The chip module according to claim 5, wherein, The vertical projection of the first heat dissipation member on the substrate completely covers the vertical projection of the first chip on the substrate.

7. The chip module according to any one of claims 1-6, characterized in that, Further comprising: A plurality of spaced conductive members fixed on the second surface, and the conductive members are electrically connected to the chips correspondingly through the substrate; Part of the conductive members are located inside the second encapsulation member, and the end of the conductive member facing away from the substrate is exposed on the surface of the second encapsulation member facing away from the substrate.

8. The chip module according to claim 7, wherein The cross-sectional area of the first heat dissipation member is larger than the cross-sectional area of one of the conductive members.

9. The chip module according to claim 8, wherein, The cross-sectional area of the first heat sink is greater than π*(D / 2) 2 , where the range of the D is 200μm to 300μm.

10. The chip module according to any one of claims 1-9, characterized in that, The thermal conductivity of the first heat dissipation member is greater than 100 W / mK.

11. The chip module according to any one of claims 1-10, characterized in that, The thickness of the first heat dissipation member is greater than 30 μm.

12. The chip module according to any one of claims 1-11, characterized in that, There is a groove on the surface of the second encapsulation member facing away from the substrate, and the groove extends to the first end of the first heat dissipation member to expose part of the first end.

13. The chip module according to any one of claims 1-11, characterized in that, Further comprising: A first connecting member fixed on the first end of the first heat dissipation member; The end of the first connecting member facing away from the first heat dissipation member protrudes from the surface of the second encapsulation member facing away from the substrate.

14. The chip module according to claim 13, wherein There is a gap between the first connecting member and the second encapsulation member.

15. The chip module according to any one of claims 7-9, characterized in that, The end of the conductive member facing away from the substrate protrudes from the surface of the second encapsulation member facing away from the substrate.

16. The chip module according to claim 15, wherein There is a gap between the conductive member and the second encapsulation member.

17. The chip module according to any one of claims 1-16, characterized in that, The first chip is disposed on the first surface, and a first electrical connector is provided on a surface of the first chip facing the substrate. The first chip is electrically connected to the substrate through the first electrical connector; An end face of one end of the first electrical connector connected to the substrate forms the heat conduction region.

18. The chip module according to claim 17, wherein, In the thickness direction, the first heat sink further includes a second end opposite to the first end, and the second end of the first heat sink is fixed on the second surface.

19. The chip module according to claim 18, wherein, The substrate has a second heat sink, and at least a part of a vertical projection of the second heat sink and the first heat sink on the substrate overlaps.

20. The chip module according to claim 19, wherein, The second heat sink is located inside the substrate.

21. The chip module according to claim 19, wherein, One end of the second heat sink is located inside the substrate, and the other end of the second heat sink extends towards the inside of the second package along the thickness direction. The second end of the first heat sink is fixed to the other end of the second heat sink.

22. The chip module according to claim 17, wherein, In the thickness direction, the first heat sink further includes a second end opposite to the first end, and the second end is fixed inside the substrate.

23. The chip module according to any one of claims 1-16, characterized in that, The first chip is disposed on the second surface, and a second electrical connector is provided on a surface of the first chip facing the substrate. The first chip is electrically connected to the substrate through the second electrical connector; The first heat sink is fixed on a surface of the first chip facing away from the substrate, and a surface of the first chip facing the first heat sink forms the heat conduction region.

24. A method for preparing a chip module, characterized in that, Comprising: Providing a substrate, a first heat sink and a plurality of chips, wherein the substrate includes a first surface and a second surface facing away from each other in a thickness direction, the plurality of chips include a first chip, and the first chip has a heat conduction region for realizing heat conduction contact; Setting a part of the plurality of chips on the first surface, forming a first package on the first surface, and at least a part of the chips located on the first surface are wrapped in the first package; Setting another part of the plurality of chips on the second surface, and at least the first end of the first heat sink is located on the second surface. A vertical projection of the first heat sink on the substrate at least partially covers a vertical projection of the heat conduction region of the first chip on the substrate; Forming a packaging layer on the second surface, and the packaging layer wraps the chips and the first heat sink located on the second surface; Thinning the packaging layer to form a thin packaging layer, and the first end of the first heat sink is wrapped inside the thin packaging layer; Processing the thin packaging layer to form a second package, so that an end face of the first end of the first heat sink is recessed in the thickness direction with respect to a surface of the second package facing away from the substrate. At least a part of the chips located on the second surface are wrapped in the second package. The first heat sink is located between the first surface and a surface of the second package facing away from the substrate, and in the thickness direction, there is a preset distance between the end face of the first end of the first heat sink and the surface of the second package facing away from the substrate.

25. The preparation method according to claim 24, characterized in that, Before forming the encapsulation layer on the second surface, the method further includes: forming a plurality of spaced solder joints on the second surface, and the solder joints are correspondingly electrically connected to the chip through the substrate; Forming the encapsulation layer on the second surface further includes: wrapping the encapsulation layer around the solder joints; After forming the encapsulation layer on the second surface, the method further includes: thinning the solder joints to form conductive members, and one end of the conductive members facing away from the substrate is exposed on the side of the second package facing away from the substrate.

26. The preparation method according to claim 25, wherein Thinning the solder joints to form conductive members includes: Thinning the solder joints to form transitional solder joints; Forming a notch structure on the side of the encapsulation thin layer facing away from the substrate, and the notch structure surrounds the transitional solder joints; Providing a first solder structure on the transitional solder joints, and after subjecting the transitional solder joints and the first solder structure to a reflow process, forming the conductive members, and one end of the conductive members facing away from the substrate protrudes from the side of the second package facing away from the substrate.

27. The preparation method according to any one of claims 24-26, characterized in that, Processing the encapsulation thin layer to form the second package includes: Opening a groove on the side of the encapsulation thin layer facing away from the substrate to form the second package, and the groove extends to the first end of the first heat sink, so that part of the first end is exposed.

28. The preparation method according to claim 27, wherein After opening a groove on the side of the encapsulation thin layer facing away from the substrate, the method further includes: Providing a second solder structure on the first end of the first heat sink; After subjecting the second solder structure to a reflow process, forming a first connecting member, and one end of the first connecting member facing away from the first heat sink protrudes from the side of the second package facing away from the substrate.

29. The preparation method according to any one of claims 24-28, characterized in that, On the side of the first chip facing the substrate, there is a first electrical connecting member; Arranging some of the plurality of chips on the first surface includes: arranging the first chip on the first surface, and electrically connecting the first chip to the substrate through the first electrical connecting member, and the end face of the end of the first electrical connecting member connected to the substrate forms the heat conduction area.

30. The preparation method according to claim 29, wherein In the thickness direction, the first heat sink further includes a second end opposite to the first end; Providing the substrate and the first heat sink includes: fixing the second end of the first heat sink on the second surface.

31. The preparation method according to claim 30, wherein, The substrate has a second heat sink; Fixing the second end of the first heat sink on the second surface includes: making at least part of the vertical projection of the first heat sink on the substrate and the vertical projection of the second heat sink on the substrate coincide.

32. The preparation method according to claim 31, characterized in that, One end of the second heat sink is located inside the substrate, and the other end of the second heat sink extends towards the inside of the second package along the thickness direction; Fixing the second end of the first heat sink on the second surface includes: forming a second connecting member on the other end of the second heat sink, and fixing the second end of the first heat sink to the other end of the second heat sink through the second connecting member.

33. The preparation method according to claim 29, wherein In the thickness direction, the first heat sink further includes a second end opposite to the first end; The provided substrate and the first heat sink include: fixing the second end of the first heat sink inside the substrate.

34. The preparation method according to any one of claims 24-28, characterized in that On the surface of the first chip facing the substrate, there is a second electrical connector; The step of disposing another part of the plurality of chips on the second surface includes: Disposing the first chip on the second surface and electrically connecting the first chip to the substrate through the second electrical connector; Fixing the first heat sink on the surface of the first chip facing away from the substrate, and a heat conduction area is formed on the surface of the first chip facing the first heat sink.

35. An electronic device, characterized in that, It includes a housing, a circuit board, and the chip module according to any one of claims 1-34 above. The chip module is disposed on the circuit board, and the chip module is electrically connected to the circuit board. Both the circuit board and the chip module are assembled inside the housing.

Images