Multi-chip packaging structure and power device

Abstract

The invention discloses a multi-chip packaging structure and a power device, and relates to the field of power semiconductor devices.The packaging structure comprises a first DBC substrate and a plurality of second DBC substrates located on the first DBC substrate, and each second DBC substrate is provided with an upper horizontal section, a lower horizontal section and a vertical section connecting the upper horizontal section and the lower horizontal section. And in every two adjacent second DBC substrates, the upper surface of the lower horizontal section of one second DBC substrate is fixed to the lower surface of the chip in a tin soldering mode, and the lower surface of the upper horizontal section of the other second DBC substrate is fixed to the upper surface of the chip in a tin soldering mode. The upper surface of the upper horizontal section of the second DBC substrate at the leftmost end is connected with the first power supply leading-out end of the power device, and the upper surfaces of the upper horizontal sections of the adjacent second DBC substrates are connected to form a conductive path; the upper surface of the first DBC substrate is connected with a second power source leading-out end of the power device, and the lower surface of the lower horizontal section of each second DBC substrate is fixed to the upper surface of the first DBC substrate in a tin soldering mode. The packaging structure is high in packaging reliability and suitable for working at high temperature.

Description

Technical Field

[0001] The present invention relates to the field of power semiconductor devices, and in particular to a multi-chip packaging structure and a power device. Background Art

[0002] Power devices play a crucial role in power electronic systems. For example, automotive power devices need to operate under harsh environmental conditions (working environment: high vibration, multi-dust, strong electromagnetic interference; need to adapt to extreme temperatures from -40°C to 155°C and humidity ranges from 0% to 100%), and high reliability, high performance, and high safety need to be ensured.

[0003] Currently, discrete devices with single power semiconductor device packaging can no longer meet the requirements, while parallel connection of multiple discrete devices will cause problems such as large parasitic parameters, large volume, and difficult heat dissipation. Summary of the Invention

[0004] Embodiments of the present invention provide a multi-chip packaging structure and a power device to overcome the above technical problems.

[0005] To solve the above problems, in a first aspect, embodiments of the present invention disclose a multi-chip packaging structure applied to a power device, including: A first DBC substrate and a plurality of second DBC substrates located above the first DBC substrate; The second DBC substrate includes an upper horizontal section, a lower horizontal section, and a vertical section connecting the right end of the upper horizontal section and the left end of the lower horizontal section; The plurality of second DBC substrates are arranged in sequence from left to right on the first DBC substrate. Among two adjacent second DBC substrates, the upper surface of the lower horizontal section of one second DBC substrate is used to be fixed to the lower surface of the chip by soldering, and the lower surface of the upper horizontal section of the other second DBC substrate is used to be fixed to the upper surface of the chip by soldering; Wherein, the upper surface of the upper horizontal section of the second DBC substrate located at the leftmost end of the first DBC substrate is used to be connected to the first power output terminal of the power device, and the upper surfaces of the upper horizontal sections of adjacent second DBC substrates are connected to form a conduction path; the upper surface of the first DBC substrate is used to be connected to the second power output terminal of the power device, and the lower surfaces of the lower horizontal sections of each second DBC substrate are all fixed to the upper surface of the first DBC substrate by soldering.

[0006] In an embodiment of the present invention, the first power output terminal is a DC+ terminal, and the second power output terminal is a DC- terminal.

[0007] In an embodiment of the present invention, both the first DBC substrate and the second DBC substrate include a first metal layer, an insulating layer, and a second metal layer arranged in sequence from bottom to top, wherein the insulating layer is used to isolate the first metal layer and the second metal layer.

[0008] In one embodiment of the present invention, the gap between the lower horizontal segments of adjacent second DBC substrates is 100 - 200 μm.

[0009] In one embodiment of the present invention, the second metal layers of the upper horizontal segments of adjacent second DBC substrates are connected by bonding wires; or, in adjacent second DBC substrates, the second metal layer of the upper horizontal segment of one of the second DBC substrates has a thinning region, the thinning region is connected to the second metal layer of the vertical segment of this second DBC substrate, and the second metal layer of the upper horizontal segment of the other second DBC substrate extends to the thinning region and matches with the thinning region and is fixed by soldering to achieve coplanar welding interconnection.

[0010] In one embodiment of the present invention, the angle between the vertical segment and the lower horizontal segment of the second DBC substrate is 90 - 120°.

[0011] In one embodiment of the present invention, the heights of the chips in the packaging structure are partially the same or completely different; the soldering thickness between the lower horizontal segments of each second DBC substrate for carrying chips of different heights and the first DBC substrate is different, so that the lower surfaces of the upper horizontal segments of each second DBC substrate are located in the same plane.

[0012] In one embodiment of the present invention, a heat dissipation structure is provided on the lower surface of the lower horizontal segment of the first DBC substrate; a heat dissipation structure is provided on the upper surface of the upper horizontal segment of one or more second DBC substrates.

[0013] In one embodiment of the present invention, the length of the upper horizontal segment of the second DBC substrate at the leftmost end of the first DBC substrate is less than the length of the upper horizontal segments of other second DBC substrates in the packaging structure; the length of the lower horizontal segment of the second DBC substrate at the rightmost end of the first DBC substrate is less than the length of the lower horizontal segments of other second DBC substrates in the packaging structure.

[0014] From a second aspect, the embodiments of the present invention also disclose a power device, including the multi-chip packaging structure of the first aspect of the embodiments of the present invention.

[0015] The embodiments of the present invention have the following advantages: The packaging structure of the present invention makes the connection path between chips more direct and compact, realizes modular integrated design, not only reduces the packaging size, but also reduces the detour path of current during transmission, thereby effectively reducing the stray inductance value and improving the switching performance and working efficiency of the power device in the high-frequency working state.

[0016] On the basis of realizing the parallel connection of multiple cores, the packaging structure of the present invention also eliminates additional power terminals and avoids the parasitic inductance introduced by the power terminals.

[0017] The encapsulation structure of the present invention does not require opening holes, does not damage the DBC substrate, eliminates the use of the PCB, is more suitable for the high-temperature operating temperature of power devices, and ensures the reliability of power devices during high-temperature operation.

[0018] The encapsulation structure of the present invention, through a unique multi-DBC substrate structure, can better shield electromagnetic interference. The adjacent chips are isolated by the DBC substrate, effectively suppressing the electromagnetic interference of mutual interaction. At the same time, the interference to the surrounding electronic components is also greatly reduced, ensuring the stable operation of the entire circuit system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention.

[0020] Figure 1 is a schematic structural diagram of a multi-chip encapsulation structure according to an embodiment of the present invention Figure 1 ; Figure 2 is a schematic structural diagram of the DBC substrate according to an embodiment of the present invention; Figure 3 is a schematic structural diagram of a multi-chip encapsulation structure according to an embodiment of the present invention Figure 2 ; Figure 4 is a schematic diagram of a second DBC substrate structure according to an embodiment of the present invention; Figure 5 is a schematic diagram of another second DBC substrate structure according to an embodiment of the present invention; Figure 6 is a schematic structural diagram of a multi-chip encapsulation structure according to an embodiment of the present invention Figure 3 . DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of the embodiments.

[0022] Hereinafter, terms such as "second" and "first" are only for convenience of description and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "second", "first", etc. may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise stated, "a plurality of" means two or more.

[0023] In the embodiments of the present invention, unless otherwise clearly defined and limited, the term "connection" should be understood in a broad sense, which can be directly connected or indirectly connected through an intermediate medium.

[0024] In the embodiments of the present invention, "and / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the front and rear associated objects.

[0025] Regarding the problem that the parallel connection of multiple discrete devices will cause large parasitic parameters, large volume, difficult heat dissipation, etc.

[0026] In high-power application scenarios, power devices formed by packaging multiple chips in parallel are popular. In the related art, power devices with multiple chips in parallel are generally formed by directly soldering multiple chips on the same PCB substrate. The chips are connected in parallel through bonding wires and connected to power terminals, as Figure 1 shown. However, such power devices generally have problems such as high stray inductance value and high electromagnetic interference, and it is particularly difficult to adapt to the high operating temperature of power devices, resulting in reduced packaging reliability.

[0027] In view of this, the embodiments of the present invention provide a multi-chip packaging structure, which is applied to power devices, as Figure 1 shown, including: a first DBC substrate and a plurality of second DBC substrates located above the first DBC substrate; the second DBC substrate includes an upper horizontal section, a lower horizontal section, and a vertical section connecting the right end of the upper horizontal section and the left end of the lower horizontal section; the plurality of second DBC substrates are arranged in sequence from left to right on the first DBC substrate. Among adjacent two second DBC substrates, the upper surface of the lower horizontal section of one second DBC substrate is used to be fixed to the lower surface of the chip by soldering, and the lower surface of the upper horizontal section of the other second DBC substrate is used to be fixed to the upper surface of the chip by soldering; wherein, the upper surface of the upper horizontal section of the second DBC substrate located at the leftmost end of the first DBC substrate is used to be connected to the first power lead-out end of the power device, and the upper surfaces of the upper horizontal sections of adjacent second DBC substrates are connected to form a conduction path; the upper surface of the first DBC substrate is used to be connected to the second power lead-out end of the power device, and the lower surfaces of the lower horizontal sections of each second DBC substrate are all fixed to the upper surface of the first DBC substrate by soldering.

[0028] The DBC (Direct Bonding Copper) substrate is a composite substrate, as Figure 2As shown, both the first DBC substrate and the second DBC substrate include a first metal layer, an insulating layer, and a second metal layer arranged in sequence from bottom to top. The insulating layer is used to isolate the first metal layer and the second metal layer. Among them, the first metal layer and the second metal layer are generally copper, and the insulating layer can be selected as aluminum oxide ceramic. The DBC substrate has the characteristics of high thermal conductivity, high electrical insulation, high mechanical strength, low expansion, etc. of ceramics, and also has the high electrical conductivity and excellent welding performance of oxygen-free copper, and can etch various patterns like a PCB circuit board. The packaging structure of the present invention is entirely realized by using DBC substrates (i.e., the first DBC substrate and multiple second DBC substrates). Compared with using a PCB substrate for packaging, it is more suitable for the high-temperature operating temperature of power devices and ensures the reliability of power devices during high-temperature operation.

[0029] In the multi-chip packaging structure of the power device proposed by the present invention, the second DBC substrate includes an upper horizontal section, a lower horizontal section, and a vertical section connecting the right end of the upper horizontal section and the left end of the lower horizontal section, and is a Z-shaped structure. Multiple second DBC substrates are located above the first DBC substrate and are arranged in sequence from left to right on the first DBC substrate, as Figure 1 shown. The upper surface of the lower horizontal section of the second DBC substrate at odd positions is fixed to the lower surface of the chip by soldering, and the lower surface of the upper horizontal section of the second DBC substrate at even positions is fixed to the upper surface of the chip by soldering, so that adjacent second DBC substrates alternately connect the upper and lower surfaces of the chip, forming a 3D commutation circuit. Compared with the prior art, the packaging structure of the present invention makes the connection path between chips more direct and compact, realizes modular integrated design, not only reduces the packaging size, but also reduces the detour path of the current during transmission, thereby effectively reducing the stray inductance value and improving the switching performance and working efficiency of the power device in the high-frequency operating state.

[0030] In the multi-chip packaging structure proposed by the present invention, the first power lead-out terminal is a DC+ terminal, and the second power lead-out terminal is a DC- terminal. As Figure 1 shown, the DC+ terminal of the power device is connected to the upper surface of the upper horizontal section of the leftmost second DBC substrate, and the upper horizontal sections of adjacent second DBC substrates are interconnected to form a conductive path to connect to the DC+ terminal; the DC- terminal is directly connected to the upper surface of the first DBC substrate, and the lower surfaces of the lower horizontal sections of each second DBC substrate are fixed to the upper surface of the first DBC substrate by soldering. In this way, not only the parallel connection of multiple cores in this packaging structure is realized, but also compared with the prior art, additional power terminals are eliminated, and the parasitic inductance introduced by the power terminals is avoided. In addition, compared with the problem that the DBC stacked PCB board packaging structure needs to open holes on the PCB board, the packaging structure of the present invention does not need to open holes and does not damage the DBC substrate.

[0031] During the operation of automotive chips, external electromagnetic interference may cause temporary functional failures such as communication disruptions, restarts, and freezes in automotive chips through radiation and conduction, and even cause permanent damage to some hardware. In the multi-chip packaging structure proposed by the present invention, through a unique multi-DBC substrate structure as shown in Figure 1 it can better shield electromagnetic interference. Adjacent chips are isolated by the DBC substrate, effectively suppressing the interacting electromagnetic interference, and at the same time greatly reducing the interference to surrounding electronic components, ensuring the stable operation of the entire circuit system. Among them, the first DBC substrate serves as a common ground plane and can shield high-frequency noise.

[0032] In the multi-chip packaging structure of the power device proposed by the present invention, solder is selected as the conductive material. Based on the high temperature resistance of solder, the connection performance between the chip and the second DBC substrate and between the second DBC substrate and the first DBC substrate can be maintained stably even in a high-temperature environment, which can adapt to the high-temperature working temperature of the power device, improve the reliability of the packaging, and extend the service life of the power device.

[0033] In practical applications, according to the power size and the number of chips of the power device, the sizes of the first DBC substrate and the second DBC substrate and the models and numbers of the chips can be flexibly selected to achieve the best packaging effect. For example, in high-power applications such as automotive chips, the number of the second DBC substrates and the number of chips can be appropriately increased in this packaging structure to meet the working requirements of high current and high voltage; while in a packaging structure with higher requirements for high-frequency performance, a DBC substrate material with a low dielectric constant can be selected to further reduce the stray inductance value and electromagnetic interference.

[0034] Regarding the interconnection of the upper horizontal segments of adjacent second DBC substrates to form a conductive path to connect to the DC+ terminal, there are various connection methods for the upper horizontal segments of adjacent second DBC substrates.

[0035] In an alternative implementation, as shown in Figure 3 the second metal layers of the upper horizontal segments of adjacent second DBC substrates are connected by bonding wires. In this implementation, the bonding wires can be aluminum wires, usually with a diameter of 100-500 μm, and an appropriate wire diameter is selected according to the current magnitude. The connection method of the bonding wires can adopt ultrasonic bonding or thermocompression bonding technology to ensure a firm and reliable connection. Compared with the connection method of bonding wires between chips, in this solution, the second metal layers of the upper horizontal segments of adjacent second DBC substrates are connected by bonding wires, and the bonding points can be set larger and the bonding wires can be set thicker, which not only improves the connection strength between the two but also reduces the requirements for bonding wire equipment.

[0036] In another alternative implementation, as shown in Figure 1As shown, in adjacent second DBC substrates, there is a thinning area in the second metal layer of the upper horizontal section of one of the second DBC substrates. The thinning area is connected to the second metal layer of the vertical section of this second DBC substrate. The second metal layer of the upper horizontal section of the other second DBC substrate extends to this thinning area, matches with this thinning area and is fixed by soldering, realizing coplanar welding interconnection. In this implementation method, the second metal layers of the upper horizontal sections of adjacent second DBC substrates realize coplanar welding interconnection. The coplanar welding interconnection technology can reduce the connection resistance and improve the current-carrying capacity, which is especially suitable for high-current application scenarios. And compared with the way connected by bonding wires, the coplanar welding interconnection not only has higher packaging stability, but also can achieve low stray inductance parameters.

[0037] Optionally, the thickness of the thinning area is usually 30%-70% of the original thickness of the second metal layer, which can ensure the overall flatness after welding. Exemplarily, the thickness of the thinning area is 50% of the original thickness of the second metal layer, that is, 0.15 mm. The length of the thinning area is 2 mm, and the width is the same as the width of the upper horizontal section of the second DBC substrate. The thinning treatment can be achieved by chemical etching or mechanical processing.

[0038] Among them, the solder paste used for coplanar welding interconnection can be the same as that used for chip soldering. The welding temperature is 250 °C and the time is 90 seconds. This connection method can carry a larger current, has a lower connection resistance, and also has a smaller thermal resistance, which is especially suitable for high-current application scenarios.

[0039] In the embodiment of the present invention, the lower horizontal sections of adjacent second DBC substrates cannot be in contact to avoid short circuits. Therefore, the insulating layer of the second DBC substrate must isolate the first metal layer and the second metal layer. In the right end face of the lower horizontal section of the second DBC substrate, the insulating layer is flush with the cross-sections of the first metal layer and the second metal layer, or the insulating layer can protrude slightly. Optionally, the gap between the lower horizontal sections of adjacent second DBC substrates is 100-200 μm. This gap is made by the inventor considering electromagnetic interference, heat dissipation effect and packaging size, and can balance the effects of the three. The design of this gap can effectively prevent short circuits between adjacent second DBC substrates, and at the same time ensure the compactness of the packaging structure. Preferably, the gap between the lower horizontal sections of adjacent second DBC substrates is preferably 150 μm, which can not only ensure the electrical insulation performance, but also maximize the packaging density.

[0040] In an embodiment of the present invention, the second DBC substrate includes an upper horizontal section, a lower horizontal section, and a vertical section connecting the right end of the upper horizontal section and the left end of the lower horizontal section. When the angle between the vertical section and the lower horizontal section of the second DBC substrate is relatively large, the gap between the chip and the vertical section of the second DBC substrate is larger, which helps with heat dissipation and reduces electromagnetic interference, but ultimately results in a larger area of the packaging structure. When the angle between the vertical section and the lower horizontal section of the second DBC substrate is relatively small, not only is there serious electromagnetic interference, but it is also not conducive to the installation of the chip. Therefore, it is preferred that the angle between the vertical section and the lower horizontal section of the second DBC substrate is 90 - 120°, that is, this angle ≥ 90° and ≤ 120°. The structure of the second DBC substrate with an angle of 90° is as shown in Figure 4 shown, and the structure of the second DBC substrate with an angle of 120° is as shown in Figure 5 shown.

[0041] Exemplarily, the angle between the vertical section and the lower horizontal section of the second DBC substrate is 120°. This inclined design can reduce stress concentration and improve the mechanical strength and reliability of the structure.

[0042] For power devices with multi-chip packaging, the multi-chips encapsulated therein generally have various types of chips, such as diode chips, capacitors, power chips, MOSFETs, etc. The heights of these chips are partially the same or completely different. Since the packaging structure is flat and the thickness of the second DBC substrate is also uniform, in order to avoid problems such as reduced device stability and increased cost caused by using metal gaskets, connecting posts, etc. to eliminate the height differences of chips with different heights. An embodiment of the present invention proposes an implementation scheme: the soldering thickness between the lower horizontal section of each second DBC substrate for carrying chips with different heights and the first DBC substrate is different, so that the lower surfaces of the upper horizontal sections of each second DBC substrate are located in the same plane. Among them, as shown in Figure 6 shown, when the angles between the vertical sections and the lower horizontal sections of each second DBC substrate are the same, the lengths of the vertical sections of each second DBC substrate for carrying chips with different heights are different. In this way, by adjusting the soldering thickness between the lower horizontal section of each second DBC substrate for carrying chips with different heights and the first DBC substrate, that is, making the soldering thickness between the lower horizontal section of each second DBC substrate for carrying chips with different heights and the first DBC substrate different, the lower surfaces of the upper horizontal sections of each second DBC substrate can be located in the same plane. In Figure 6 , for chips with different heights, the soldering thicknesses between the lower horizontal section of the second DBC substrate and the first DBC substrate are represented by H and h respectively.

[0043] Among them, when the angles between the vertical segments and the lower horizontal segments of the respective second DBC substrates are the same, the lengths of the vertical segments of the respective second DBC substrates for carrying chips of different heights can be different or the same (not shown in the figure). In this case, by adjusting the soldering thickness between the lower horizontal segments of the respective second DBC substrates carrying chips of different heights and the first DBC substrate, the lower surfaces of the upper horizontal segments of the respective second DBC substrates can be located in the same plane.

[0044] In this embodiment, for a chip with a low height, the soldering thickness between the lower horizontal segment of the second DBC substrate for carrying the chip and the first DBC substrate can be thicker; for a chip with a high height, the soldering thickness between the lower horizontal segment of the second DBC substrate for carrying the chip and the first DBC substrate can be thinner. Since the thickness of the second DBC substrate is uniform, when the soldering thickness between the lower horizontal segment of the second DBC substrate and the first DBC substrate is adjusted according to the chip height so that the lower surfaces of the upper horizontal segments of the respective second DBC substrates are located in the same plane, at the same time, the upper surfaces of the upper horizontal segments of the respective second DBC substrates can also be located in the same plane, which is beneficial to packaging. This embodiment eliminates the height difference of chips of different heights without involving the use of metal gaskets, connection posts, etc., saves costs, ensures the stability of the connection between the chip and the second DBC substrate, and further makes the conductive performance of the power device stable. This embodiment can meet the packaging requirements of chips of different heights, compensate for the height difference by adjusting the soldering layer thickness, ensure the coplanarity of the upper horizontal segments, and facilitate subsequent interconnection.

[0045] Since a large amount of heat will be generated during the operation of a power device (such as an IGBT module), if the heat cannot be dissipated in time, it may cause excessive thermal stress inside the chip package, resulting in package failure and affecting the reliability of the chip. To improve the heat dissipation effect, in the embodiment of the present invention, a heat dissipation structure is provided on the lower surface of the lower horizontal segment of the first DBC substrate; a heat dissipation structure is provided on the upper surface of the upper horizontal segment of one or more second DBC substrates. This embodiment provides a double-sided heat dissipation structure, which can improve the heat dissipation efficiency by 30%-50% and also reduce the electromagnetic noise caused by the temperature gradient. Among them, the heat dissipation structure of the upper horizontal segment can be selectively provided on some or all of the second DBC substrates according to the actual heat dissipation requirements.

[0046] Of course, due to factors such as specific application scenarios and package sizes, in order to improve the heat dissipation effect, a heat dissipation structure can also be provided only on the lower surface of the lower horizontal segment of the first DBC substrate, or only on the upper surface of the upper horizontal segment of one or more second DBC substrates. The present invention does not make any limitations in this regard.

[0047] Among them, in each embodiment, the heat dissipation structure can be selected as heat dissipation fins, a radiator, a liquid cooling system, etc., which are used to improve the heat dissipation efficiency. The material of the heat dissipation structure can be selected from copper, aluminum or other metal materials with good thermal conductivity.

[0048] Further, in the embodiments of the present invention, as Figure 1 and Figure 3 shown, the length of the upper horizontal section of the second DBC substrate located at the leftmost end of the first DBC substrate is less than the length of the upper horizontal sections of the other second DBC substrates in the packaging structure; the length of the lower horizontal section of the second DBC substrate located at the rightmost end of the first DBC substrate is less than the length of the lower horizontal sections of the other second DBC substrates in the packaging structure. Since the upper horizontal section of the second DBC substrate located at the leftmost end of the first DBC substrate and the lower horizontal section of the second DBC substrate located at the rightmost end of the first DBC substrate do not participate in the installation of the chip, their sizes can be designed to be shorter to save the size of the entire packaging structure.

[0049] In an application, the multi-chip packaging structure of the embodiments of the present invention can package 2-20 power chips to form a high-power density power module. After packaging, the entire structure can be potted and protected with epoxy resin or silica gel to improve its mechanical strength and environmental adaptability.

[0050] Based on the same inventive concept, the embodiments of the present invention also disclose a power device, including the multi-chip packaging structure as described in the embodiments of the present invention.

[0051] It should be noted that the embodiments in this specification are all described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0052] The technical solutions provided by the present invention have been introduced in detail above. Specific examples are used in this article to elaborate on the principles and implementation manners of the present invention. The descriptions of the above embodiments are only used to help understand the present invention. The content of this specification should not be construed as a limitation to the present invention. At the same time, for those of ordinary skill in the art, based on the present invention, there will be various changes in the specific implementation manners and application scopes. It is not necessary and impossible to list all the implementation manners here. The obvious changes or variations derived therefrom are still within the protection scope of the present invention.

Claims

1. A multi-chip packaging structure, characterized in that, Applied to power devices, including: A first DBC substrate and a plurality of second DBC substrates located above the first DBC substrate; The second DBC substrate includes an upper horizontal section, a lower horizontal section, and a vertical section connecting the right end of the upper horizontal section and the left end of the lower horizontal section; The plurality of second DBC substrates are arranged in sequence from left to right on the first DBC substrate. Among two adjacent second DBC substrates, the upper surface of the lower horizontal section of one second DBC substrate is used to be fixed to the lower surface of the chip by soldering, and the lower surface of the upper horizontal section of the other second DBC substrate is used to be fixed to the upper surface of the chip by soldering; Wherein, the upper surface of the upper horizontal section of the second DBC substrate located at the leftmost end of the first DBC substrate is used to be connected to the first power supply lead-out terminal of the power device, and the upper surfaces of the upper horizontal sections of adjacent second DBC substrates are connected to form a conduction path; the upper surface of the first DBC substrate is used to be connected to the second power supply lead-out terminal of the power device, and the lower surfaces of the lower horizontal sections of each second DBC substrate are all fixed to the upper surface of the first DBC substrate by soldering.

2. The multi-chip packaging structure according to claim 1, wherein The first power supply lead-out terminal is a DC+ terminal, and the second power supply lead-out terminal is a DC- terminal.

3. The multi-chip package structure according to claim 1, wherein Both the first DBC substrate and the second DBC substrate include a first metal layer, an insulating layer, and a second metal layer arranged in sequence from bottom to top. Among them, the insulating layer is used to isolate the first metal layer and the second metal layer.

4. The multi-chip packaging structure according to any one of claims 1-3, wherein The gap between the lower horizontal sections of adjacent second DBC substrates is 100-200 μm.

5. The multi-chip packaging structure according to claim 3, wherein The second metal layers of the upper horizontal sections of adjacent second DBC substrates are connected by bonding wires; Or, among adjacent second DBC substrates, the second metal layer of the upper horizontal section of one second DBC substrate has a thinning area, the thinning area is connected to the second metal layer of the vertical section of this second DBC substrate, and the second metal layer of the upper horizontal section of the other second DBC substrate extends to the thinning area and is mutually matched with the thinning area and fixed by soldering to achieve coplanar welding interconnection.

6. The multi-chip packaging structure according to claim 1, wherein The included angle between the vertical section and the lower horizontal section of the second DBC substrate is 90-120°.

7. The multi-chip packaging structure according to any one of claims 1-3, wherein The heights of the chips in the packaging structure are partially the same or completely different; The soldering thickness between the lower horizontal sections of each second DBC substrate for carrying chips of different heights and the first DBC substrate is different, so that the lower surfaces of the upper horizontal sections of each second DBC substrate are located on the same plane.

8. The multi-chip packaging structure according to claim 1, wherein The lower surface of the lower horizontal section of the first DBC substrate is provided with a heat dissipation structure; The upper surface of the upper horizontal segment of one or more of the second DBC substrates is provided with a heat dissipation structure.

9. The multi-chip package structure according to claim 1, wherein the length of the upper horizontal segment of the second DBC substrate located at the leftmost end of the first DBC substrate is less than the length of the upper horizontal segments of the other second DBC substrates in the package structure; the length of the lower horizontal segment of the second DBC substrate located at the rightmost end of the first DBC substrate is less than the length of the lower horizontal segments of the other second DBC substrates in the package structure.

10. A power device, characterized in that, It includes the multi-chip package structure according to any one of claims 1-9.

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