Multi-chip packaging structure and power device

Abstract

The present invention discloses a multi-chip packaging structure and a power device, which relates to the field of power semiconductor devices. The packaging structure includes a first DBC substrate and a plurality of second DBC substrates located thereon, wherein the second DBC substrates have an upper horizontal section, a lower horizontal section, and a vertical section connecting the two. The plurality of second DBC substrates are arranged in sequence from left to right. Of the two adjacent second DBC substrates, the upper surface of the lower horizontal section of one is soldered and fixed to the lower surface of the chip, and the lower surface of the upper horizontal section of the other is soldered and fixed to the upper surface of the chip. The upper surface of the upper horizontal section of the leftmost second DBC substrate is connected to the first power supply lead-in terminal of the power device, and the upper surfaces of the upper horizontal sections of the adjacent second DBC substrates are connected to form a conductive path; the upper surface of the first DBC substrate is connected to the second power supply lead-in terminal of the power device, and the lower surfaces of the lower horizontal sections of each second DBC substrate are soldered and fixed to the upper surface of the first DBC substrate. The packaging of the present invention has high reliability and is suitable for working under high temperatures.

Description

Technical Field

[0001] The present invention relates to the field of power semiconductor devices, and in particular to a multi-chip packaging structure and a power device. Background Art

[0002] Power devices play a vital role in power electronics systems. For example, automotive power devices must operate in harsh environmental conditions (including high vibration, dust, strong electromagnetic interference, extreme temperatures ranging from -40°C to 155°C, and humidity ranging from 0% to 100%) while maintaining high reliability, performance, and safety.

[0003] Currently, the discrete devices packaged in a single power semiconductor device can no longer meet the requirements, and connecting multiple discrete devices in parallel will cause problems such as large parasitic parameters, large size, and difficulty in heat dissipation. Summary of the Invention

[0004] Embodiments of the present invention provide a multi-chip packaging structure and a power device to overcome the above technical problems.

[0005] To solve the above problems, from a first aspect, an embodiment of the present invention discloses a multi-chip packaging structure applied to power devices, comprising:

[0006] a first DBC substrate and a plurality of second DBC substrates located on the first DBC substrate;

[0007] The second DBC substrate includes an upper horizontal segment, a lower horizontal segment, and a vertical segment connected to the right end of the upper horizontal segment and the left end of the lower horizontal segment;

[0008] The plurality of second DBC substrates are sequentially arranged from left to right on the first DBC substrate. Among two adjacent second DBC substrates, the upper surface of the lower horizontal section of one second DBC substrate is used to be fixed to the lower surface of the chip by soldering, and the lower surface of the upper horizontal section of the other second DBC substrate is used to be fixed to the upper surface of the chip by soldering;

[0009] Among them, the upper surface of the upper horizontal section of the second DBC substrate located at the leftmost end of the first DBC substrate is used to connect to the first power lead-in terminal of the power device, and the upper surfaces of the upper horizontal sections of adjacent second DBC substrates are connected to form a conductive path; the upper surface of the first DBC substrate is used to connect to the second power lead-in terminal of the power device, and the lower surface of the lower horizontal section of each second DBC substrate is fixed to the upper surface of the first DBC substrate by soldering.

[0010] In one embodiment of the present invention, the first power lead-out terminal is a DC+ terminal, and the second power lead-out terminal is a DC- terminal.

[0011] In one embodiment of the present invention, the first DBC substrate and the second DBC substrate each include a first metal layer, an insulating layer, and a second metal layer sequentially arranged from bottom to top, wherein the insulating layer is used to isolate the first metal layer from the second metal layer.

[0012] In one embodiment of the present invention, the gap between the lower horizontal sections of adjacent second DBC substrates is 100-200 μm.

[0013] In one embodiment of the present invention, the second metal layers of the upper horizontal segments of adjacent second DBC substrates are connected by bonding wires; or, among the adjacent second DBC substrates, the second metal layer of the upper horizontal segment of one of the second DBC substrates has a thinned area, the thinned area is connected to the second metal layer of the vertical segment of the second DBC substrate, and the second metal layer of the upper horizontal segment of the other second DBC substrate extends to the thinned area and matches the thinned area and is fixed by soldering to achieve coplanar welding interconnection.

[0014] In one embodiment of the present invention, the included angle between the vertical section and the lower horizontal section of the second DBC substrate is 90-120°.

[0015] In one embodiment of the present invention, the height portions of the chips in the packaging structure are the same or completely different; the soldering thickness between the lower horizontal segments of each second DBC substrate used to support chips of different heights and the first DBC substrate is different, so that the lower surfaces of the upper horizontal segments of each second DBC substrate are located in the same plane.

[0016] In one embodiment of the present invention, a heat dissipation structure is provided on the lower surface of the lower horizontal section of the first DBC substrate; and a heat dissipation structure is provided on the upper surface of the upper horizontal section of one or more second DBC substrates.

[0017] In one embodiment of the present invention, the length of the upper horizontal segment of the second DBC substrate located at the leftmost end of the first DBC substrate is smaller than the lengths of the upper horizontal segments of other second DBC substrates in the packaging structure; the length of the lower horizontal segment of the second DBC substrate located at the rightmost end of the first DBC substrate is smaller than the lengths of the lower horizontal segments of other second DBC substrates in the packaging structure.

[0018] From a second aspect, an embodiment of the present invention further discloses a power device, including the multi-chip packaging structure of the first aspect of the embodiment of the present invention.

[0019] The embodiments of the present invention include the following advantages:

[0020] The packaging structure of the present invention makes the connection path between chips more direct and compact, realizing modular integrated design, which not only reduces the package size but also reduces the circuitous path of current during transmission, thereby effectively reducing the stray inductance value and improving the switching performance and working efficiency of power devices under high-frequency working conditions.

[0021] The packaging structure of the present invention not only realizes the parallel connection of multiple cores, but also eliminates additional power terminals, thereby avoiding parasitic inductance introduced by the power terminals.

[0022] The packaging structure of the present invention does not require openings, does not damage the DBC substrate, eliminates the use of a PCB, is more adaptable to the high temperature operating temperature of the power device, and ensures the reliability of the power device under high temperature operation.

[0023] The packaging structure of the present invention can better shield electromagnetic interference through its unique multi-DBC substrate structure. Adjacent chips are isolated by the DBC substrate, so that the interactive electromagnetic interference can be effectively suppressed. At the same time, the interference to peripheral electronic components is also greatly reduced, ensuring the stable operation of the entire circuit system. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention.

[0025] Figure 1 This is a schematic diagram of a multi-chip packaging structure according to an embodiment of the present invention. Figure 1 ;

[0026] Figure 2 2 is a schematic structural diagram of a DBC substrate according to an embodiment of the present invention;

[0027] Figure 3 This is a schematic diagram of a multi-chip packaging structure according to an embodiment of the present invention. Figure 2 ;

[0028] Figure 4 is a schematic diagram of a second DBC substrate structure according to an embodiment of the present invention;

[0029] Figure 5 is a schematic diagram of another second DBC substrate structure according to an embodiment of the present invention;

[0030] Figure 6 This is a schematic diagram of a multi-chip packaging structure according to an embodiment of the present invention. Figure 3 . DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0032] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature qualified as "second," "first," etc., may explicitly or implicitly include one or more of such features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0033] In the embodiments of the present invention, unless otherwise clearly specified or limited, the term "connection" should be understood in a broad sense, and may refer to direct connection or indirect connection through an intermediate medium.

[0034] In the embodiments of the present invention, "and / or" describes the association relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0035] Connecting multiple discrete devices in parallel will cause problems such as large parasitic parameters, large size, and difficulty in heat dissipation.

[0036] In high-power applications, power devices packaged with multiple chips in parallel have become popular. In related technologies, multi-chip parallel power devices are generally made by directly soldering multiple chips on the same PCB substrate. The chips are connected in parallel through bonding wires and connected to power terminals, such as Figure 1 However, such power devices generally have problems such as high stray inductance and high electromagnetic interference, and are particularly difficult to adapt to high operating temperatures of power devices, which reduces packaging reliability.

[0037] In view of this, an embodiment of the present invention provides a multi-chip packaging structure, which is applied to power devices, such as Figure 1As shown, it includes: a first DBC substrate and multiple second DBC substrates located on the first DBC substrate; the second DBC substrate includes an upper horizontal section, a lower horizontal section and a vertical section connected to the right end of the upper horizontal section and the left end of the lower horizontal section; the multiple second DBC substrates are arranged in sequence from left to right on the first DBC substrate, and among two adjacent second DBC substrates, the upper surface of the lower horizontal section of one second DBC substrate is used to be fixed to the lower surface of the chip by soldering, and the lower surface of the upper horizontal section of the other second DBC substrate is used to be fixed to the upper surface of the chip by soldering; wherein, the upper surface of the upper horizontal section of the second DBC substrate located at the leftmost end of the first DBC substrate is used to be connected to the first power lead-in terminal of the power device, and the upper surfaces of the upper horizontal sections of adjacent second DBC substrates are connected to form a conductive path; the upper surface of the first DBC substrate is used to be connected to the second power lead-in terminal of the power device, and the lower surface of the lower horizontal section of each second DBC substrate is fixed to the upper surface of the first DBC substrate by soldering.

[0038] DBC (Direct Bonding Copper) substrate is a composite substrate, such as Figure 2 As shown, the first and second DBC substrates each include a first metal layer, an insulating layer, and a second metal layer, arranged sequentially from bottom to top. The insulating layer is used to isolate the first and second metal layers. The first and second metal layers are generally copper, and the insulating layer can be aluminum oxide ceramic. DBC substrates have the high thermal conductivity, high electrical insulation, high mechanical strength, and low expansion characteristics of ceramics, while also possessing the high electrical conductivity and excellent solderability of oxygen-free copper. They can also be etched with various patterns similar to PCB circuit boards. The packaging structure of the present invention is implemented entirely using DBC substrates (i.e., a first DBC substrate and multiple second DBC substrates). Compared to packaging using PCB substrates, this is more adaptable to the high operating temperatures of power devices, ensuring the reliability of power devices under high-temperature operation.

[0039] In the multi-chip package structure of the power device proposed in the present invention, the second DBC substrate includes an upper horizontal section, a lower horizontal section, and a vertical section connected to the right end of the upper horizontal section and the left end of the lower horizontal section, forming a Z-shaped structure. The plurality of second DBC substrates are located above the first DBC substrate and are arranged in sequence from left to right on the first DBC substrate, such as Figure 1As shown, the upper surface of the lower horizontal segment of the odd-numbered second DBC substrate is soldered to the lower surface of the chip, while the lower surface of the upper horizontal segment of the even-numbered second DBC substrate is soldered to the upper surface of the chip. This allows adjacent second DBC substrates to alternately connect the upper and lower surfaces of the chip, forming a 3D commutation circuit. Compared to existing technologies, the packaging structure of the present invention makes the connection paths between chips more direct and compact, achieving a modular integrated design. This not only reduces package size but also reduces circuitous current paths during transmission, effectively reducing stray inductance and improving the switching performance and operating efficiency of power devices under high-frequency operation.

[0040] In the multi-chip package structure proposed by the present invention, the first power supply terminal is a DC+ terminal, and the second power supply terminal is a DC- terminal. Figure 1 As shown, the DC+ terminal of the power device is connected to the upper surface of the upper horizontal segment of the second DBC substrate on the far left. The upper horizontal segments of adjacent second DBC substrates are interconnected to form a conductive path to connect to the DC+ terminal. The DC- terminal is directly connected to the upper surface of the first DBC substrate, and the lower surface of the lower horizontal segment of each second DBC substrate is soldered to the upper surface of the first DBC substrate. This not only enables the parallel connection of multiple cores in this package structure, but also eliminates the need for additional power terminals compared to existing technologies, thus avoiding the parasitic inductance introduced by power terminals. Furthermore, compared to DBC-PCB package structures that require holes in the PCB, the package structure of the present invention does not require holes, thus preventing damage to the DBC substrate.

[0041] During the operation of the automotive chip, external electromagnetic interference may cause temporary functional failures such as communication disruption, error, restart, and freeze of the automotive chip through radiation and conduction, and even cause permanent damage to some hardware. Figure 1 The unique multi-DBC substrate structure shown here provides enhanced electromagnetic interference shielding. Adjacent chips are isolated by the DBC substrate, effectively suppressing any mutual electromagnetic interference. This significantly reduces interference with surrounding electronic components, ensuring stable operation of the entire circuit system. The first DBC substrate acts as a common ground plane, shielding against high-frequency noise.

[0042] In the multi-chip packaging structure of the power device proposed in the present invention, solder is selected as the conductive material. Based on the high temperature resistance of solder, the chip and the second DBC substrate, as well as the second DBC substrate and the first DBC substrate, can maintain stable connection performance even in a high temperature environment. It can adapt to the high temperature operating temperature of the power device, improve the reliability of the package, and extend the service life of the power device.

[0043] In practical applications, the dimensions of the first and second DBC substrates, as well as the type and number of chips, can be flexibly selected based on the power level and number of chips in the power device to achieve the optimal packaging effect. For example, in high-power applications such as automotive chips, the number of second DBC substrates and the number of chips can be appropriately increased to meet the high current and high voltage requirements. In packaging structures requiring high high-frequency performance, DBC substrate materials with low dielectric constants can be selected to further reduce stray inductance and electromagnetic interference.

[0044] As far as the upper horizontal segments of adjacent second DBC substrates are interconnected to form a conductive path to be connected to the DC+ terminal, there may be various ways to connect the upper horizontal segments of adjacent second DBC substrates.

[0045] In an optional implementation, if Figure 3 As shown, the second metal layers of the upper horizontal sections of adjacent second DBC substrates are connected by bonding wires. In this implementation, the bonding wires can be aluminum wires, which are usually 100-500μm in diameter, and the appropriate wire diameter is selected according to the current size. The bonding wires can be connected using ultrasonic bonding or thermocompression bonding technology to ensure a firm and reliable connection. Compared to the method of connecting chips with bonding wires, this solution connects the second metal layers of the upper horizontal sections of adjacent second DBC substrates with bonding wires. The bonding points can be set larger and the bonding wires can be set thicker, which not only improves the connection strength between the two, but also reduces the requirements for bonding wire equipment.

[0046] In another optional implementation, Figure 1 As shown, in adjacent second DBC substrates, the second metal layer of the upper horizontal segment of one second DBC substrate has a thinned region, which connects to the second metal layer of the vertical segment of the second DBC substrate. The second metal layer of the upper horizontal segment of the other second DBC substrate extends to the thinned region, mates with the thinned region, and is secured to the thinned region via soldering, achieving coplanar soldering interconnection. In this implementation, the second metal layers of the upper horizontal segments of adjacent second DBC substrates achieve coplanar soldering interconnection. Coplanar soldering interconnection technology can reduce connection resistance and improve current carrying capacity, making it particularly suitable for high-current applications. Compared to wirebond connections, coplanar soldering interconnection not only provides higher packaging stability but also achieves low stray inductance parameters.

[0047] Optionally, the thickness of the thinned region is typically 30%-70% of the original thickness of the second metal layer, ensuring overall flatness after welding. Exemplarily, the thickness of the thinned region is 50% of the original thickness of the second metal layer, or 0.15 mm. The thinned region is 2 mm long and has a width equal to the width of the upper horizontal section of the second DBC substrate. Thinning can be achieved by chemical etching or mechanical processing.

[0048] Coplanar soldering uses the same solder paste used for chip soldering, with a soldering temperature of 250°C and a soldering time of 90 seconds. This connection method can carry higher currents, has lower connection resistance, and minimizes thermal resistance, making it particularly suitable for high-current applications.

[0049] In an embodiment of the present invention, the lower horizontal sections of adjacent second DBC substrates cannot touch each other to avoid short circuits, so the insulating layer of the second DBC substrate must isolate the first metal layer and the second metal layer, and in the right end face of the lower horizontal section of the second DBC substrate, the insulating layer is flush with the cross-section of the first metal layer and the second metal layer, or the insulating layer can be slightly protruding. Optionally, the gap between the lower horizontal sections of adjacent second DBC substrates is 100-200μm. This gap is made by the inventors to take into account electromagnetic interference, heat dissipation effect and packaging size, and can take into account the effects of the three. The design of this gap can effectively prevent short circuits between adjacent second DBC substrates while ensuring the compactness of the packaging structure. Preferably, the gap between the lower horizontal sections of adjacent second DBC substrates is preferably 150μm, which can not only ensure electrical insulation performance but also maximize packaging density.

[0050] In an embodiment of the present invention, the second DBC substrate includes an upper horizontal segment, a lower horizontal segment, and a vertical segment connected to the right end of the upper horizontal segment and the left end of the lower horizontal segment. When the angle between the vertical segment and the lower horizontal segment of the second DBC substrate is large, the gap between the chip and the vertical segment of the second DBC substrate should be larger, which is helpful for heat dissipation and reducing electromagnetic interference, but will eventually lead to a larger area of ​​the packaging structure. When the angle between the vertical segment and the lower horizontal segment of the second DBC substrate is small, not only is there a high risk of serious electromagnetic interference, but it is also not conducive to the installation of the chip. Therefore, it is preferred that the angle between the vertical segment and the lower horizontal segment of the second DBC substrate is 90~120°, that is, the angle is ≥90° and ≤120°. The second DBC substrate structure of 90° is as follows Figure 4 As shown, the second DBC substrate structure of 120° is as follows Figure 5 shown.

[0051] For example, the included angle between the vertical section and the lower horizontal section of the second DBC substrate is 120°. This inclined design can reduce stress concentration and improve the mechanical strength and reliability of the structure.

[0052] For multi-chip packaged power devices, the multi-chips packaged therein generally include various types of chips, such as diode chips, capacitors, power chips, MOSFETs, etc., and the heights of these chips are partially the same or completely different. Since the packaging structure is flat, the thickness of the second DBC substrate is also uniform. In order to avoid the problem of reduced device stability and increased costs caused by the use of metal gaskets, connecting columns, etc. to eliminate the height difference of chips of different heights. An embodiment of the present invention proposes an implementation plan: the soldering thickness between the lower horizontal section of each second DBC substrate used to carry chips of different heights and the first DBC substrate is different, so that the lower surface of the upper horizontal section of each second DBC substrate is located in the same plane. Among them, if Figure 6 As shown, if the included angles between the vertical segments and the lower horizontal segments of each second DBC substrate are the same, the vertical segments of each second DBC substrate used to carry chips of different heights have different lengths. In this way, by adjusting the soldering thickness between the lower horizontal segments of each second DBC substrate carrying chips of different heights and the first DBC substrate, that is, making the soldering thickness between the lower horizontal segments of each second DBC substrate carrying chips of different heights and the first DBC substrate different, the lower surfaces of the upper horizontal segments of each second DBC substrate can be located in the same plane. Figure 6 In FIG, for chips of different heights, the soldering thickness between the lower horizontal section of the second DBC substrate and the first DBC substrate is represented by H and h, respectively.

[0053] Among them, if the angles between the vertical sections and the lower horizontal sections of each second DBC substrate are the same, the lengths of the vertical sections of each second DBC substrate used to carry chips of different heights can be different or the same (not shown in the figure). In this case, by adjusting the soldering thickness between the lower horizontal sections of each second DBC substrate carrying chips of different heights and the first DBC substrate, the lower surfaces of the upper horizontal sections of each second DBC substrate can be located in the same plane.

[0054] In this embodiment, for chips of lower height, the solder thickness between the lower horizontal section of the second DBC substrate supporting the chip and the first DBC substrate can be thicker; for chips of higher height, the solder thickness between the lower horizontal section of the second DBC substrate supporting the chip and the first DBC substrate can be thinner. Because the thickness of the second DBC substrate is uniform, when the solder thickness between the lower horizontal section of the second DBC substrate and the first DBC substrate is adjusted according to the chip height so that the lower surfaces of the upper horizontal sections of each second DBC substrate are located in the same plane, the upper surfaces of the upper horizontal sections of each second DBC substrate can also be located in the same plane, facilitating packaging. This embodiment eliminates the height difference between chips of different heights without the use of metal gaskets, connecting columns, etc., saving costs, ensuring the stability of the connection between the chip and the second DBC substrate, and thus stabilizing the conductive performance of the power device. This embodiment can meet the packaging requirements of chips of different heights by adjusting the thickness of the solder layer to compensate for the height difference, ensuring the coplanarity of the upper horizontal sections, and facilitating subsequent interconnection.

[0055] Since power devices (such as IGBT modules) generate a large amount of heat during operation, if the heat cannot be dissipated in a timely manner, it may cause excessive thermal stress inside the chip package, leading to package failure and affecting the reliability of the chip. To improve the heat dissipation effect, in an embodiment of the present invention, a heat dissipation structure is provided on the lower surface of the lower horizontal section of the first DBC substrate; and a heat dissipation structure is provided on the upper surface of the upper horizontal section of one or more second DBC substrates. This embodiment provides a double-sided heat dissipation structure, which improves heat dissipation efficiency by 30%-50% and can also reduce electromagnetic noise caused by temperature gradients. The heat dissipation structure of the upper horizontal section can be selectively provided on part or all of the second DBC substrates according to actual heat dissipation requirements.

[0056] Of course, based on specific application scenarios, package size, and other factors, to improve heat dissipation, a heat dissipation structure may be provided only on the lower surface of the lower horizontal section of the first DBC substrate, or only on the upper surface of the upper horizontal section of one or more second DBC substrates. The present invention is not limited to this.

[0057] In various embodiments, the heat dissipation structure may be a heat dissipation fin, a radiator, or a liquid cooling system to improve heat dissipation efficiency. The heat dissipation structure may be made of copper, aluminum, or other metal materials with good thermal conductivity.

[0058] Furthermore, in an embodiment of the present invention, Figure 1 and Figure 3As shown, the upper horizontal section of the second DBC substrate located at the leftmost end of the first DBC substrate is shorter than the upper horizontal sections of the other second DBC substrates in the package structure; and the lower horizontal section of the second DBC substrate located at the rightmost end of the first DBC substrate is shorter than the lower horizontal sections of the other second DBC substrates in the package structure. Since the upper horizontal section of the second DBC substrate located at the leftmost end of the first DBC substrate and the lower horizontal section of the second DBC substrate located at the rightmost end of the first DBC substrate do not participate in chip mounting, their dimensions can be designed to be shorter, saving space in the overall package structure.

[0059] In one application, the multi-chip package structure of the present invention can encapsulate 2-20 power chips to form a high-power density power module. After packaging, the entire structure can be potted with epoxy resin or silicone to improve its mechanical strength and environmental adaptability.

[0060] Based on the same inventive concept, an embodiment of the present invention further discloses a power device, including the multi-chip packaging structure as described in the embodiment of the present invention.

[0061] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0062] The technical solutions provided by the present invention have been described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is intended only to facilitate understanding of the present invention, and the contents of this specification should not be construed as limiting the present invention. Furthermore, those skilled in the art will appreciate that various modifications may be made to the specific implementation methods and scope of application according to the present invention. It is not necessary and impossible to exhaustively enumerate all implementation methods herein, and any obvious variations or modifications derived therefrom remain within the scope of protection of the present invention.

Claims

1. A multi-chip package structure, characterized in that: Applied to power devices, including: a first DBC substrate and a plurality of second DBC substrates located on the first DBC substrate; The second DBC substrate includes an upper horizontal segment, a lower horizontal segment, and a vertical segment connected to the right end of the upper horizontal segment and the left end of the lower horizontal segment; The plurality of second DBC substrates are sequentially arranged from left to right on the first DBC substrate, wherein the upper surface of the lower horizontal section of one of the two adjacent second DBC substrates is used to be fixed to the lower surface of the chip by soldering, and the lower surface of the upper horizontal section of the other second DBC substrate is used to be fixed to the upper surface of the chip by soldering; The upper surface of the upper horizontal segment of the second DBC substrate located at the leftmost end of the first DBC substrate is used to connect to the first power lead of the power device, and the upper surfaces of the upper horizontal segments of adjacent second DBC substrates are connected to form a conductive path; the upper surface of the first DBC substrate is used to connect to the second power lead of the power device, and the lower surface of the lower horizontal segment of each second DBC substrate is fixed to the upper surface of the first DBC substrate by soldering; The first DBC substrate and the second DBC substrate each include a first metal layer, an insulating layer, and a second metal layer arranged in sequence from bottom to top, wherein the insulating layer is used to isolate the first metal layer from the second metal layer.

2. The multi-chip package structure according to claim 1, wherein: The first power supply lead-out terminal is a DC+ terminal, and the second power supply lead-out terminal is a DC- terminal.

3. The multi-chip package structure according to claim 1 or 2, characterized in that: The gap between the lower horizontal sections of adjacent second DBC substrates is 100-200 μm.

4. The multi-chip package structure according to claim 1, wherein: The second metal layers of the upper horizontal segments of adjacent second DBC substrates are connected via bonding wires; Alternatively, in adjacent second DBC substrates, the second metal layer of the upper horizontal segment of one second DBC substrate has a thinned area, and the thinned area is connected to the second metal layer of the vertical segment of the second DBC substrate. The second metal layer of the upper horizontal segment of the other second DBC substrate extends to the thinned area and matches the thinned area and is fixed by soldering to achieve coplanar welding interconnection.

5. The multi-chip package structure according to claim 1, wherein: The included angle between the vertical section and the lower horizontal section of the second DBC substrate is 90-120°.

6. The multi-chip package structure according to claim 1 or 2, characterized in that: The heights of the chips in the package structure are partially the same or completely different; The soldering thickness between the lower horizontal section of each second DBC substrate for carrying chips of different heights and the first DBC substrate is different, so that the lower surfaces of the upper horizontal sections of each second DBC substrate are located in the same plane.

7. The multi-chip package structure according to claim 1, wherein: A heat dissipation structure is provided on the lower surface of the lower horizontal section of the first DBC substrate; A heat dissipation structure is provided on the upper surface of the upper horizontal section of one or more second DBC substrates.

8. The multi-chip package structure according to claim 1, wherein: The length of the upper horizontal section of the second DBC substrate located at the leftmost end of the first DBC substrate is smaller than the lengths of the upper horizontal sections of other second DBC substrates in the packaging structure; The length of the lower horizontal segment of the second DBC substrate located at the rightmost end of the first DBC substrate is smaller than the lengths of the lower horizontal segments of other second DBC substrates in the packaging structure.

9. A power device, characterized in that: The multi-chip package structure comprises the multi-chip package structure according to any one of claims 1 to 8.

Images