Rapid locking system and method for network-building type MMC with super-capacity

Abstract

The invention provides a rapid locking system and method for a network-building type MMC with a super capacitor. The rapid locking system comprises a current transformer, a valve protector, a valve controller and the network-building type MMC with the super capacitor which are connected in sequence. The valve controller comprises a plurality of core boards and a plurality of interface boards; the network-forming type MMC with the super capacitor comprises a plurality of valve sub-modules; the current transformer is used for collecting the bridge arm current value of the network-constructing MMC with the super capacitor; valve protection: determining a control signal indicating whether each valve sub-module is locked or not based on the bridge arm current value and a preset current threshold value; a control signal based on whether each valve sub-module is locked; the core board is used for analyzing the pulse signal to obtain a data frame containing the control signal; and the interface board is used for generating a locking pulse signal and controlling each valve sub-module to be locked if a result obtained by analysis is that each valve sub-module is controlled to be locked. The probability that the valve sub-module cannot detect the locking pulse signal is low, the complexity of code implementation is reduced, and the error-tolerant rate is high.

Description

Technical Field

[0001] The present invention belongs to the technical field of HVDC transmission and power electronics, and particularly relates to a fast blocking system and method for a grid-forming MMC with supercapacitors. Background Art

[0002] To address the technical gap in the active inertia support of cutting-edge technical equipment in the power industry, grid-forming control and protection devices have emerged. Grid-forming control and protection devices mainly include, but are not limited to, control devices such as grid-forming SVG (Static Var Generator) and grid-forming energy storage devices.

[0003] The grid-side grid-forming SVG device with supercapacitors is the latest cutting-edge technology in the field of flexible DC transmission that adopts the topology of "modular multilevel converter + supercapacitor". By applying advanced grid-forming control strategies, it can achieve synchronous operation, instantaneously respond to active and reactive power changes, provide inertia support to the power grid, have the ability to dynamically support active / reactive power during the fault process, establish the grid voltage in the scenario without traditional synchronous machines, and can also operate stably under weak grids.

[0004] The information flow of the bridge arm overcurrent protection of the converter generally adopts Figure 1 the shown architecture (simplified diagram, redundant systems have been omitted). If this architecture is adopted and the communication between different links all uses the data frame format with a frame interval of the control period, then the delay from the bridge arm current acquisition to the blocking of the sub-module IGBT (Insulate-Gate Bipolar Transistor) will reach hundreds of microseconds, which is extremely likely to cause control instability and lead to the damage of the converter valve equipment. Therefore, in the field of flexible DC transmission, the means of data frame interpolation is used to achieve fast blocking. This design can minimize the blocking delay of the bridge arm overcurrent protection as much as possible, but at the same time, there are the disadvantages that the implementation method of the fast blocking of the MMC (Modular Multilevel Converter) valve control is complex and the fault tolerance rate is low. Summary of the Invention

[0005] To overcome the deficiencies of the above-mentioned prior art, on the first aspect, the present invention proposes a fast blocking system for a grid-forming MMC with supercapacitors, including: a current transformer, a valve protection, a valve control, and a grid-forming MMC with supercapacitors connected in sequence; the valve control includes: a plurality of core boards and a plurality of interface boards, and each of the core boards is connected to all of the interface boards; the grid-forming MMC with supercapacitors includes: a plurality of valve sub-modules.

[0006] The current transformer is used to collect the bridge arm current value of the grid-forming MMC with supercapacitors and send the bridge arm current value to the valve protection.

[0007] The valve protection is used to determine a control signal for locking each valve sub-module based on the arm current value and a preset current threshold; and send a pulse signal containing the control signal to the core board based on the control signal for whether each valve sub-module is locked.

[0008] The core board is used to analyze the pulse signal to obtain a data frame containing the control signal, and send the data frame to each interface board.

[0009] The interface board is used to analyze the data frame. If the analysis result is to control the locking of each valve sub-module, a locking pulse signal is generated; and each valve sub-module is controlled to lock based on the locking pulse signal.

[0010] Preferably, the core board is further used to obtain the control period of the grid-forming MMC with supercapacitors, shorten the frame interval of the data frame to 1 / N times of the control period to form a data frame with a reduced frame interval, where N is a positive integer.

[0011] Preferably, the data frame includes: a data frame of a locking signal or a data frame of a non-locking signal.

[0012] Preferably, the valve sub-module includes: a plurality of insulated gate bipolar transistors and capacitors, and the plurality of insulated gate bipolar transistors are bridged and then the capacitors are connected in parallel.

[0013] Preferably, the interface board is further used to generate a locking pulse signal with a specified duration based on the data frame of the locking signal; and send the locking pulse signal with the specified duration to each valve sub-module.

[0014] The valve sub-module is used to control itself to lock when receiving the locking pulse signal with the specified duration.

[0015] Preferably, the valve protection is specifically used to set a current threshold, compare the arm current value with the current threshold to obtain a comparison result; if the comparison result is that the arm current value is greater than the current threshold, it is determined that the control signal is a control signal for locking each valve sub-module; if the comparison result is that the arm current value is less than the current threshold, it is determined that the control signal is a control signal for not locking each valve sub-module.

[0016] Preferably, the interface board is specifically used to determine that the data frame belongs to the data frame of the locking signal and generate a locking pulse signal if the analysis result is to control the locking of each valve sub-module.

[0017] Preferably, the interface board is further configured to send signals to each valve sub-module based on the data frame and the blocking pulse signal; and is expressed by the following formula:

[0018]

[0019] In the above formula: tx_sm_signal represents the signal sent by the interface board to the valve sub-module, pulse_signal represents the blocking pulse signal, frame_signal represents the data frame, lock represents the blocking signal, 1 represents blocking control, and 0 represents non-blocking control.

[0020] In a second aspect, the present invention application also proposes a fast blocking method for a network-forming MMC with supercapacitance, including:

[0021] Using the current transformer of the fast blocking system to collect the arm current value of the network-forming MMC with supercapacitance of the fast blocking system;

[0022] Using the valve protection of the fast blocking system, based on the arm current value and a preset current threshold, determine the control signal for whether each valve sub-module of the fast blocking system is blocked; based on the control signal for whether each valve sub-module is blocked, generate a pulse signal including the control signal;

[0023] Using the core board of the fast blocking system to parse the pulse signal to obtain a data frame including the control signal;

[0024] Using the interface board of the fast blocking system to parse the data frame; if the parsed result is to control each valve sub-module to be blocked, then generate a blocking pulse signal; based on the blocking pulse signal, control each valve sub-module to perform blocking.

[0025] Preferably, after using the core board of the fast blocking system to parse the pulse signal to obtain a data frame including the control signal, it further includes:

[0026] Using the core board to obtain the control period of the network-forming MMC with supercapacitance, and shorten the frame interval of the data frame to 1 / N times of the control period to form a data frame with a reduced frame interval, where N is a positive integer.

[0027] In a third aspect, the present invention application also proposes an electronic device, including: at least one processor and a memory; the memory and the processor are connected by a bus;

[0028] The memory is used to store one or more programs;

[0029] When the one or more programs are executed by the at least one processor, the described fast blocking method of the network-forming MMC with overcapacity is implemented.

[0030] In a fourth aspect, the present invention application also proposes a readable storage medium with an execution program stored thereon. When the execution program is executed, the described fast blocking method of the network-forming MMC with overcapacity is implemented.

[0031] Compared with the closest prior art, the beneficial effects of the present invention application are as follows:

[0032] The fast blocking system and method of the network-forming MMC with overcapacity of the present invention includes: a current transformer, a valve protection, a valve control, and a network-forming MMC with overcapacity connected in sequence; the valve control includes: a plurality of core boards and a plurality of interface boards, and each of the core boards is connected to all of the interface boards; the network-forming MMC with overcapacity includes: a plurality of valve sub-modules; the current transformer is used to collect the arm current value of the network-forming MMC with overcapacity and send the arm current value to the valve protection; the valve protection is used to determine the control signal for whether each valve sub-module is blocked based on the arm current value and a preset current threshold; based on the control signal for whether each valve sub-module is blocked, send a pulse signal containing the control signal to the core board; the core board is used to parse the pulse signal to obtain a data frame containing the control signal and send the data frame to each of the interface boards; the interface board is used to parse the data frame. If the parsed result is to control each valve sub-module to be blocked, a blocking pulse signal is generated; based on the blocking pulse signal, control each valve sub-module to be blocked. Since the control of each valve sub-module to be blocked is based on the blocking pulse signal, the probability that the valve sub-module cannot detect the blocking pulse signal is very low, greatly reducing the complexity of code implementation between the valve sub-module and the valve control and having a relatively high fault tolerance rate. Description of the Drawings

[0033] Figure 1 Simplified architecture diagram of the arm overcurrent protection information flow of the converter in the background technology;

[0034] Figure 2 Architecture diagram of a fast blocking system of a network-forming MMC with overcapacity provided by the present invention application;

[0035] Figure 3 Schematic diagram of the network-forming MMC with overcapacity of a fast blocking system of a network-forming MMC with overcapacity provided by the present invention application;

[0036] Figure 4The valve protection and valve control connection architecture diagram of a fast blocking system for a network-forming MMC with supercapacitors provided for this invention application;

[0037] Figure 5 The signal generation process diagram sent by the valve control interface board of a fast blocking system for a network-forming MMC with supercapacitors provided for this invention application to the sub-modules;

[0038] Figure 6 The schematic diagram of the specific application scenario of a fast blocking system for a network-forming MMC with supercapacitors provided for this invention application;

[0039] Figure 7 The measured delay diagram from the start of sending the blocking pulse signal by the slave interface board to the IGBT blocking in a fast blocking system for a network-forming MMC with supercapacitors provided for this invention application;

[0040] Figure 8 The flowchart of a fast blocking method for a network-forming MMC with supercapacitors provided for this invention application;

[0041] Figure 9 The operation schematic diagram of an electronic device provided for this invention application. Detailed implementation manners

[0042] The following further elaborates on the detailed implementation manners of this invention application in conjunction with the attached drawings.

[0043] Embodiment 1:

[0044] As Figure 2 shown, this invention application proposes a fast blocking system for a network-forming MMC with supercapacitors, which may include: a current transformer, a valve protection, a valve control, and a network-forming MMC with supercapacitors connected in sequence; the valve control includes: a plurality of core boards and a plurality of interface boards, and each of the core boards is connected to all of the interface boards; the network-forming MMC with supercapacitors may include: a plurality of valve sub-modules;

[0045] The current transformer is used to collect the arm current value of the network-forming MMC with supercapacitors and send the arm current value to the valve protection;

[0046] The valve protection is used to determine the control signal for whether each valve sub-module is blocked based on the arm current value and a preset current threshold; and send a pulse signal containing the control signal to the core board based on the control signal for whether each valve sub-module is blocked;

[0047] The core board is used to parse the pulse signal to obtain a data frame containing the control signal and send the data frame to each of the interface boards;

[0048] The interface board is used to parse the data frame. If the parsed result is to control the locking of each valve sub-module, a locking pulse signal is generated; based on the locking pulse signal, each valve sub-module is controlled to lock.

[0049] In this system, the valve control consists of a valve control chassis. The valve control may further include: a valve control host integrated in the valve control chassis; the most important control link within the valve control host, and multiple core boards and multiple interface boards are included in the valve control host; for example: it can be composed of 2 core boards and several interface boards (the number of interface boards depends on the number of valve sub-modules), and the two core boards are in standby with each other to improve the reliability of the valve control. Each interface board can be paired with 12 valve sub-modules. The main functions of the valve control can be completed by the core chips on 2 core boards and several interface boards. When the valve control receives the pulse signal sent by the valve protection, in fact, it is the core board that receives the pulse signal sent by the valve protection. The current transformer can select an optical current transducer (OCT) with a relatively high sampling rate; the optical current transducer collects the arm current value, and the optical current transducer can send the arm current value to the valve protection without using a merging unit. This is mainly because the selected optical current transducer has a relatively high sampling frequency and can directly send the current value data to multiple protection devices without the need for a merging unit device to distribute, reducing the communication link and shortening the communication delay at the hardware level.

[0050] Further, the valve sub-module includes: a plurality of insulated gate bipolar transistors and capacitors, and the plurality of insulated gate bipolar transistors are bridged and then connected in parallel with the capacitors.

[0051] As Figure 3 shown, it is the schematic diagram of a networked MMC with supercapacitors. The networked MMC with supercapacitors further includes: a plurality of arms and a plurality of supercapacitor branches; a plurality of valve sub-modules are respectively included in the plurality of arms, and each supercapacitor branch is also provided with a plurality of branch valve sub-modules, and each valve sub-module has a controller and an IGBT. In the system of the present invention, the valve sub-modules in the arms are controlled, and the plurality of branch valve sub-modules in the supercapacitor branches are not controlled; among them, SM1, SM2....SM N are all valve sub-modules located in the arms, and SM1, SM2....SM M are the branch valve sub-modules of the supercapacitor branch.

[0052] Further, the data frame includes: a data frame with a locking signal or a data frame without a locking signal.

[0053] Further, the interface board is further configured to send signals to each valve sub-module based on the data frame and the blocking pulse signal; and is expressed by the following formula:

[0054]

[0055] In the above formula: tx_sm_signal represents the signal sent by the interface board to the valve sub-module, pulse_signal represents the blocking pulse signal, frame_signal represents the data frame, lock represents the blocking signal, 1 represents blocking control, and 0 represents non-blocking control.

[0056] Further, the valve protection is specifically configured to set a current threshold, compare the arm current value with the current threshold to obtain a comparison result; if the comparison result is that the arm current value is greater than the current threshold, it is determined that the control signal is the control signal for blocking each valve sub-module; if the comparison result is that the arm current value is less than the current threshold, it is determined that the control signal is the control signal for not blocking each valve sub-module.

[0057] As Figure 4 shown: The valve protection adopts a two-out-of-three architecture, which consists of 3 valve protection chassis and 2 valve protection two-out-of-three chassis. The same arm current is sent by the OCT to 3 valve protection chassis respectively, and the 3 valve protection chassis respectively detect the arm overcurrent fault and generate an arm overcurrent signal. Each valve protection two-out-of-three chassis receives the arm overcurrent signals sent by the 3 valve protection chassis. As long as the valve protection two-out-of-three chassis receives 2 or more overcurrent signals of the same arm, it will determine that the arm is overcurrent. The two valve protection two-out-of-three chassis are in standby for each other to improve the reliability of protection. The valve protection determines the overcurrent of the arm current value through the set current threshold. If the valve protection determines that the current values sent by the optical current transformer for 3 consecutive sampling points all exceed the current threshold, it is determined that the arm is overcurrent. During overcurrent, the valve protection sends a pulse signal containing a control signal to the core board. This pulse signal is a pulse signal of a certain frequency for a certain duration, and the frequency is quite different from the bit frequency of the normal data frame to prevent misjudgment. The pulse signal sent by the valve protection can be divided into two pulse signals with different frequencies, and only one frequency of pulse signal can be sent at the same time. The pulse signal with a higher frequency represents blocking, and the pulse signal with a lower frequency represents non-blocking. Using a pulse signal instead of a data frame for sending can further shorten the communication delay; for example: the pulse signal containing a control signal sent by the valve protection can represent non-blocking when the frequency is 1 MHz and represent blocking when the frequency is 5 MHz, but the frequencies are not limited to 5 MHz and 1 MHz.

[0058] Further, the core board is further configured to obtain the control period of the network-forming MMC with supercapacitors, and shorten the frame interval of the data frame to 1 / N times of the control period to form a data frame with a reduced frame interval, where N is a positive integer.

[0059] Further, the interface board is specifically configured to, if the parsed result is to control the locking of each valve sub-module, determine that the data frame belongs to the data frame of the locking signal, and generate a locking pulse signal.

[0060] Further, the interface board is further configured to generate a locking pulse signal with a specified duration based on the data frame of the locking signal; and send the locking pulse signal with the specified duration to each valve sub-module;

[0061] The valve sub-module is configured to control its own locking when receiving the locking pulse signal with the specified duration.

[0062] As described above, when the interface board receives the data frame sent by the core board, it can send a locking pulse signal to the controller of the valve sub-module. When the controller of the valve sub-module receives the locking pulse signal, it immediately drives the IGBT in the valve sub-module to lock; thereby realizing the control of the locking of the valve sub-module.

[0063] As described above, as Figure 5 shown: The data frame is a complete string of data packets used to transmit information in the communication protocol; the idle bit is the part between data frames that does not carry actual data and is used to ensure the frame interval between data frames. t1 is the frame interval, and t2 is the pulse duration of the locking signal. When the core board receives the pulse signal sent by the valve protection, it sends the pulse signal to the interface board through a normal data frame; it should be noted that the frame interval of the data frame sent by the core board to the interface board is not the control period, but is shortened to 1 / N of the control period, ensuring that the frequency of the pulse signal must not be in the same order of magnitude as the original communication data frame bit rate to avoid misjudgment of the valve sub-module and resulting in locking failure; the duty cycle of the pulse signal can be set to 50%, but is not limited to 50%; and this pulse signal can be replaced by other signals that are not misjudged as normal data frames, which can not only ensure the transmission of data in the data frame, but also improve the delay of the locking signal transmission inside the core board as much as possible, and improve the real-time performance of the pulse signal transmission.

[0064] As described above, valve control determines whether to issue a blocking pulse signal by judging whether the frequency of the pulse signal sent by valve protection is within the duration range set by the criterion. The set duration is located in the controller of the valve sub-module, and the duration set in the controller of the valve sub-module should be less than the duration of the blocking pulse signal to prevent the controller of the valve sub-module from failing to detect the blocking pulse signal. Using the blocking pulse signal shortens the blocking delay again. After rapid blocking of the valve sub-module, it should continue to be blocked according to the data frame issued by valve control until the arm overcurrent fault is eliminated. After that, whether the valve sub-module is in the blocked state or the unlocked state depends on whether the arm overcurrent fault has been eliminated.

[0065] In summary, this system reduces the communication link and uses pulse signals to send signals in multiple places. Even in a complex power grid operation environment, this system can work stably, ensuring that the grid-forming MMC with over-capacity can reliably block the IGBT during an overcurrent fault, avoiding equipment damage and system instability problems caused by blocking failure, thereby improving the reliability of the entire power system.

[0066] This system can be applied to MMC converters with different rated voltages and powers. By simply adjusting the frame interval sent from the core board to the interface board and the duration and frequency of the pulse signal, it can adapt to different system requirements. Whether it is a high-voltage AC power transmission system or other types of power systems, rapid blocking can be achieved through appropriate adjustment, with wide applicability. This flexibility enables the present invention to be widely applied in various power grid environments to meet the protection needs in different scenarios.

[0067] Those skilled in the art should know that: in the prior art, in order to avoid interfering with the correctness of normal data frame transmission, valve control needs to judge whether to insert a frame and how to insert a frame according to the relationship between the time of receiving the blocking signal and the data frame transmission stage of the sending valve sub-module. The relatively complex logic increases the code amount and the implementation difficulty. In addition, if the data frame carrying the blocking command between valve control and the valve sub-module fails the verification, the valve sub-module cannot be effectively blocked, reducing the reliability of equipment protection. The system of the present invention reduces the implementation difficulty of rapid blocking and significantly reduces the probability of blocking failure, while improving the real-time performance and reliability of protection by selecting a current acquisition device with a higher sampling rate, reducing the communication link, using pulse signals for communication between valve protection and valve control, shortening the frame interval of the data frame sent from the core board to the interface board, and directly replacing the data frame sent from valve control to the valve sub-module with a blocking pulse signal when the result obtained by parsing is to control the valve sub-module to be blocked.

[0068] For the sake of generality, the following takes a specific application scenario as an example to illustrate the system of the present invention:

[0069] Such as Figure 6As shown in the figure, assume that a grid-connected SVG with an over-capacity configuration and a rated capacity of 50 Mvar is used on the grid side. The modular multilevel converter (MMC) topology with over-capacity is adopted. Among them, the MMC has 6 arms, and each arm is composed of a number of valve sub-modules. Each valve sub-module contains 4 insulated gate bipolar transistors (IGBTs) and 1 capacitor. The valve control is responsible for controlling the opening and closing of the valve sub-modules, communicates with each valve sub-module through optical fibers, and sends data frames to control the state of the IGBTs. The valve protection monitors the current of the arm of the MMC with over-capacity in real time. When an over-current fault is detected, it can issue a blocking signal in a timely manner. The control period of the MMC with over-capacity is 50 us. The device for measuring the arm current is an optical current transformer (OCT), the sampling frequency is 100 kHz, that is, the sampling period is 10 us. The internal delay of the OCT is 10 us. The data frame duration for the OCT to send the arm current value to the valve protection is 4.8 us.

[0070] The valve protection sets the current threshold for judging the arm over-current fault. In the normal operation state, the current of the arm does not exceed the current threshold. The valve protection three-out-of-two chassis sends a pulse signal with a frequency of 1 MHz and a duty cycle of 50% to the valve control. The valve control determines that the valve protection has not issued a blocking signal. When the current of the arm exceeds the current threshold at three consecutive sampling points, the valve protection immediately determines that an arm over-current fault has occurred. The delay between the first sampling point and the third sampling point of the arm over-current is 20 us. After the valve protection detects an over-current fault, the valve protection three-out-of-two chassis sends a pulse signal with a frequency of 5 MHz and a duty cycle of 50% to the valve control system through optical fibers. The valve control determines that the valve protection has issued a blocking signal. The communication frame length received by the valve control from the valve protection is 3.2 us.

[0071] The core board monitors the signal from the valve protection in real time. When a blocking pulse is received continuously for 1 us, it is determined that a blocking signal has been received, and the blocking signal is sent to the interface board in the form of a data frame. The frame interval is 5 us (1 / 10 of the control period), and the frame length is 3.6 us. The maximum delay between the core board determining that a blocking signal has been received and starting to send the data frame carrying the blocking signal is 5 us. After the interface board receives the blocking signal, it immediately inserts a 2 MHz pulse signal with a duration of 5 us into the communication signal sent to the valve sub-module (the normal communication signal is Manchester code with a 50 us frame interval and a 10 Mbps bit rate), that is, generates a blocking pulse signal. The amplitude and frequency of the inserted pulse signal are different from the normal data frame, so that the valve sub-module can accurately detect it. During the insertion of the pulse signal, the valve control pauses sending the normal data frame to ensure that the valve sub-module can focus on detecting the inserted pulse signal.

[0072] The valve sub-module monitors the communication signal from the valve control in real time. When detecting the above-mentioned blocking pulse signal with a duration of 1 us, it immediately triggers the IGBT blocking program, immediately blocks its IGBT, disconnects the current path, and prevents the overcurrent fault from further expanding. After the valve sub-module receives a normal data frame again, it continues to control the turn-on or turn-off of the IGBT according to the instructions in the data frame. The controller of the valve sub-module determines that the delay between the blocking signal and the triggering of IGBT blocking is 1.6 us.

[0073] Based on the above specific applications, it can be obtained that: the theoretical maximum value of the delay between the arm current starting to exceed the current threshold and the IGBT blocking is 50.2 us. Here is a measured result. In one of the fast blocking experiments, it is measured that the delay between the arm current starting to exceed the current threshold and the interface board starting to send the blocking pulse signal is 45.04 us. As Figure 7 shown, the delay between the interface board starting to send the blocking pulse signal and the IGBT blocking is 2.46 us. The sum of the two shows that the delay between the arm current starting to exceed the current threshold and the IGBT blocking is 47.5 us, which is less than the theoretical maximum value, indicating that the system of the present invention can achieve fast blocking.

[0074] Embodiment 2:

[0075] Based on the same inventive concept, as Figure 8 shown, the present invention also provides a fast blocking method for a grid-forming MMC with supercapacitors, including:

[0076] Step S1: Using the current transformer of the fast blocking system, collect the arm current value of the grid-forming MMC with supercapacitors of the fast blocking system;

[0077] Step S2: Using the valve protection of the fast blocking system, based on the arm current value and a preset current threshold, determine the control signal for whether each valve sub-module of the fast blocking system is blocked; based on the control signal for whether each valve sub-module is blocked, generate a pulse signal including the control signal;

[0078] Step S3: Using the core board of the fast blocking system, parse the pulse signal to obtain a data frame including the control signal;

[0079] Step S4: Using the interface board of the fast blocking system, parse the data frame; if the parsed result is to control each valve sub-module to be blocked, generate a blocking pulse signal; based on the blocking pulse signal, control each valve sub-module to perform blocking.

[0080] In step S3, after parsing the pulse signal on the core board adopting the fast locking system to obtain a data frame containing the control signal, the following steps are further included:

[0081] Adopt the core board to obtain the control period of the grid-forming MMC with supercapacitor, and shorten the frame interval of the data frame to 1 / N times of the control period to form a data frame with a reduced frame interval, where N is a positive integer.

[0082] Further, the data frame includes: a data frame of a locking signal or a data frame of a non-locking signal.

[0083] Further, in step S4, the controlling each valve sub-module to perform locking based on the locking pulse signal includes:

[0084] Adopt the interface board to generate a locking pulse signal with a specified duration based on the data frame of the locking signal;

[0085] Adopt the valve sub-module to control itself to lock when receiving the locking pulse signal with the specified duration.

[0086] Further, in step S2, the valve protection of the fast locking system determines the control signal for whether each valve sub-module of the fast locking system locks based on the arm current value and a preset current threshold, including:

[0087] Adopt the valve protection to set the current threshold, compare the arm current value with the current threshold to obtain a comparison result; if the comparison result is that the arm current value is greater than the current threshold, determine the control signal as the control signal for each valve sub-module to lock; if the comparison result is that the arm current value is less than the current threshold, determine the control signal as the control signal for each valve sub-module not to lock.

[0088] Further, in step S4, the interface board of the fast locking system parses the data frame; if the parsed result is to control each valve sub-module to lock, a locking pulse signal is generated, including:

[0089] Adopt the interface board. If the parsed result is to control each valve sub-module to lock, determine that the data frame belongs to the data frame of the locking signal and generate a locking pulse signal.

[0090] Further, the interface board is also used to send signals to each valve sub-module based on the data frame and the locking pulse signal; and is expressed as the following formula:

[0091]

[0092] In the above formula: tx_sm_signal represents the signal sent by the interface board to the valve submodule, pulse_signal represents the locking pulse signal, frame_signal represents the data frame, lock represents the locking signal, 1 represents locking control, and 0 represents non-locking control.

[0093] The method of the present invention can shorten the lockout protection delay of the bridge arm overcurrent fault as much as possible by introducing a pulse signal, and avoid the shortcomings of the previous fast lockout method, which is difficult to implement and has a low fault tolerance, so as to improve the real-time performance and reliability of the protection lockout.

[0094] Embodiment 3:

[0095] like Figure 9 As shown, the present invention also provides an electronic device, which may be a computer device, a single-chip device, an intelligent mobile device, etc. The electronic device in this embodiment may include a processor, a memory, a transceiver component, etc. The memory, the processor, and the transceiver component are connected via a bus; the memory may be used to store an execution program, and an exemplary execution program may include instructions; the processor is used to execute the instructions stored in the memory. The memory may also be used to store data, which may be called and / or modified when the instructions are executed.

[0096] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, which is suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions in a storage medium to implement corresponding method flows or corresponding functions, so as to implement the steps of a fast locking method of a meshed MMC with supercapacitor in the above-mentioned embodiment.

[0097] Embodiment 4:

[0098] Based on the same inventive concept, the present invention also provides a readable storage medium, specifically an electronic device-readable storage medium (Memory). The electronic device-readable storage medium is a memory device in the electronic device and is used to store programs and data. It can be understood that the storage medium here can include both the built-in storage medium in the electronic device and, of course, the extended storage medium supported by the electronic device. The storage medium provides a storage space, and this storage space stores the operating system of the terminal. Moreover, in this storage space, one or more instructions suitable for being loaded and executed by the processor are also stored. These instructions can be one or more executable programs (including program codes). It should be noted that the storage medium here can be a high-speed RAM memory or a non-volatile memory, such as at least one disk memory. By the processor loading and executing one or more instructions stored in the storage medium, the steps of the fast locking method of a network-forming MMC with super capacitance in the above embodiments can be implemented.

[0099] Those skilled in the art should understand that the embodiments of the present invention application can be provided as a method, a system, or a computer program product. Therefore, the present invention application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program codes.

[0100] The present invention application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present invention application. It should be understood that each process and / or block in the flowchart and / or block diagram, and the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for realizing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0101] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and this instruction device realizes the functions in Figure 1 one process or multiple processes and / or blocks Figure 1The functions specified in one or more boxes.

[0102] These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process. Thus, the instructions executed on the computer or other programmable device provide for implementing the steps of the functions specified in Figure 1 one process or more processes and / or boxes Figure 1 the functions specified in one box or more boxes.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention application rather than limit the scope of its protection. Although the present invention application has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: after reading the present invention application, those skilled in the art can still make various changes, modifications or equivalent replacements to the specific implementation manners of the application. However, these changes, modifications or equivalent replacements are all within the scope of protection of the claims pending for approval of the application.

Claims

1. A fast locking system for a network-forming MMC with supercapacitors, characterized in that, Including: A current transformer, valve protection, valve control, and network-constructing MMC with supercapacitance connected in sequence; The valve control includes: a plurality of core boards and a plurality of interface boards, and each of the core boards is connected to all of the interface boards; the network-constructing MMC with supercapacitance includes: a plurality of valve sub-modules; The current transformer is used to collect the arm current value of the network-constructing MMC with supercapacitance and send the arm current value to the valve protection; The valve protection is used to determine the control signal for locking or unlocking each valve sub-module based on the arm current value and a preset current threshold; and send a pulse signal containing the control signal to the core board based on the control signal for locking or unlocking each valve sub-module; The core board is used to parse the pulse signal to obtain a data frame containing the control signal and send the data frame to each of the interface boards; The interface board is used to parse the data frame. If the parsed result is to control the locking of each valve sub-module, a locking pulse signal is generated; and each valve sub-module is controlled to lock based on the locking pulse signal.

2. The system according to claim 1, wherein The core board is further used to obtain the control period of the network-constructing MMC with supercapacitance, shorten the frame interval of the data frame to 1 / N times of the control period to form a data frame with a reduced frame interval, where N is a positive integer.

3. The system according to claim 2, wherein The data frame includes: a data frame with a locking signal or a data frame without a locking signal.

4. The system according to claim 2, wherein The valve sub-module includes: a plurality of insulated gate bipolar transistors and capacitors, and the plurality of insulated gate bipolar transistors are bridged and then connected in parallel with the capacitors.

5. The system according to claim 2, wherein The interface board is further used to generate a locking pulse signal with a specified duration based on the data frame with a locking signal; send the locking pulse signal with the specified duration to each valve sub-module; The valve sub-module is used to control itself to lock when receiving the locking pulse signal with the specified duration.

6. The system according to claim 1, wherein The valve protection is specifically used to set a current threshold, compare the arm current value with the current threshold to obtain a comparison result; if the comparison result is that the arm current value is greater than the current threshold, determine the control signal as the control signal for locking each valve sub-module; if the comparison result is that the arm current value is less than the current threshold, determine the control signal as the control signal for not locking each valve sub-module.

7. The system according to any one of claims 1 to 3, characterized in that, The interface board is specifically used to determine that the data frame belongs to the data frame with a locking signal and generate a locking pulse signal if the parsed result is to control the locking of each valve sub-module.

8. The system according to claim 3, wherein The interface board is further used to send signals to each valve sub-module based on the data frame and the locking pulse signal; and is expressed by the following formula: In the above formula: tx_sm_signal represents the signal sent by the interface board to the valve sub-module, pulse_signal represents the blocking pulse signal, frame_signal represents the data frame, lock represents the blocking signal, 1 represents the blocking control, and 0 represents no blocking control.

9. A fast blocking method for a grid-forming MMC with supercapacitor, applied to the fast blocking system of the grid-forming MMC with supercapacitor as described in any one of claims 1-8 above, characterized in that, The method includes: Using the current transformer of the fast blocking system to collect the arm current value of the network-forming MMC with over-capacitance of the fast blocking system; Using the valve protection of the fast blocking system, based on the arm current value and a preset current threshold, determining the control signal for whether each valve sub-module of the fast blocking system is blocked; generating a pulse signal containing the control signal based on the control signal for whether each valve sub-module is blocked; Using the core board of the fast blocking system to parse the pulse signal to obtain a data frame containing the control signal; Using the interface board of the fast blocking system to parse the data frame; if the parsed result is to control each valve sub-module to be blocked, generating a blocking pulse signal; controlling each valve sub-module to perform blocking based on the blocking pulse signal.

10. The method according to claim 9, wherein After using the core board of the fast blocking system to parse the pulse signal to obtain a data frame containing the control signal, it further includes: Using the core board to obtain the control period of the network-forming MMC with over-capacitance, shortening the frame interval of the data frame to 1 / N times of the control period to form a data frame with a reduced frame interval, where N is a positive integer.

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