Longitudinal differential protection method and system for dual-CPU (Central Processing Unit) protection logic peer-to-peer line

Abstract

The invention relates to the technical field of power system control, and provides a longitudinal differential protection method and system for a line with equivalent double-CPU protection logic, and the method comprises the steps: respectively configuring longitudinal differential protection devices at two sides of the line, and employing a double-CPU protection architecture of a master CPU and a slave CPU; a ping-pong synchronization algorithm is adopted to calculate synchronization errors on the two sides; the sampling rhythms of the master CPU and the slave CPU of the host are fixed; the main CPU of the slave regularly adjusts the sampling time of the CPU according to the synchronization error of the two sides; each slave CPU performs sampling synchronization pulse legality verification to realize sampling synchronization of the four CPUs of the host and the slave at the two sides of the line; and each master CPU obtains synchronous sampling data of the master CPU and the slave CPU at the opposite side through the optical longitudinal module, and constructs a line longitudinal differential protection function of logic peer-to-peer of the master CPU and the slave CPU. According to the invention, protection abnormal action behaviors caused by sampling deviation can be effectively avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of power system control, and in particular to a line pilot differential protection method and system with dual-CPU protection logic equivalence. Background Art

[0002] Line pilot differential protection devices generally adopt a single-CPU or dual-CPU architecture. When using a single-CPU architecture, generally, a dual-AD sampling mode is adopted to improve the reliability of protection actions. However, since the dual-AD is located on the same board, an abnormality in a single board may cause the protection to refuse to operate or malfunction, resulting in poor reliability. Therefore, the single-CPU architecture generally cannot be used on lines with high reliability requirements. When using a dual-CPU architecture, since the two-side devices need to achieve sampling synchronization to perform differential protection calculations, generally, the master CPU on one side will follow the master CPU on the opposite side for sampling adjustment, while the slave CPU generally samples independently. Therefore, the master and slave CPUs of the two-side devices sample asynchronously. Based on the above sampling method, generally only the analog quantity sampling data of the master CPU is transmitted in the optical fiber channel of the line pilot differential protection device. Since both sides of the device can only obtain the synchronous data of the master CPU on the opposite side, generally, the line pilot differential protection device can only adopt the "protection" + "start" mode, that is, the master CPU is used to judge the protection logic, and the slave CPU can only be used to judge the protection start. When the slave CPU meets the start condition, the power supply of the outlet relay is opened, and when the master CPU meets the protection action logic, the protection device can trip. Although the above logic has improved in reliability compared with the single-CPU architecture, it reduces the threshold for the slave CPU to check, and cannot implement the "protection" + "protection" logic architecture, that is, it cannot open the protection outlet according to both the master and slave CPUs meeting the differential protection action threshold. When there is an abnormal sampling of the master CPU and at the same time there is an out-of-zone disturbance, the device has a greater risk of malfunction, and the reliability is difficult to guarantee. In addition, among the various protection functions of the line pilot differential protection device, for other single-ended quantity backup protections except the line pilot differential protection function, since the sampling data of the master and slave CPUs can be obtained, they meet the conditions for dual-CPU protection logic equivalence and can adopt the "protection" + "protection" architecture. However, since the main protection, the line pilot differential protection, can only use the "protection" + "start" architecture, to reduce the complexity of device design, the line pilot current differential protection device generally uses the "protection" + "start" architecture as a whole, resulting in further reduction of the reliability of the device. Summary of the Invention

[0003] The purpose of the present invention is to solve at least one technical problem in the background art, and provide a line pilot differential protection method and system with dual-CPU protection logic equivalence.

[0004] To achieve the above purpose, the present invention provides a line pilot differential protection method with dual-CPU protection logic equivalence, including: Line differential protection devices are respectively configured on both sides of the line, and the line differential protection devices on both sides adopt a dual-CPU protection architecture of a main CPU and a slave CPU. The main CPU and the slave CPU obtain local sampling data through their respective sampling modules, and the main CPU obtains the sampling data of the main CPU and the slave CPU on the opposite side through the optical line module; The line differential protection device on one side of the line is the master device, and the line differential protection device on the other side is the slave device. The master device and the slave device interact analog quantities, digital quantities, and communication characteristic words through the optical fiber channel, and use the ping-pong synchronization algorithm to calculate the synchronization error between the two sides; The sampling beats of the main CPU and the slave CPU of the master device are fixed. The main CPU among them, according to its own sampling beat, sends sampling synchronization pulses to the slave CPU of the master device at time intervals through the sampling synchronization bus; The main CPU of the slave device adjusts the sampling moment of this CPU regularly according to the synchronization error between the two sides to track the sampling beat of the master device, and sends sampling synchronization pulses to the slave CPU of the slave device at time intervals through the sampling synchronization bus; Each slave CPU performs a legality check on the sampling synchronization pulse. When it detects that the sampling synchronization pulse is illegal, it enters the abnormal processing flow of the sampling synchronization pulse. Otherwise, it adjusts the sampling beat according to the sampling synchronization pulse of the main CPU respectively, completes the sampling synchronization of the main CPU and the slave CPU of this machine, and realizes the sampling synchronization of the four CPUs of the master device and the slave device on both sides of the line; Each slave CPU respectively sends the synchronized sampling data to each main CPU through the high-speed data bus, and then sends it to the optical line module through the main CPU for encapsulation. The digital quantities and communication characteristic words are packaged into a frame of complete data and sent to the optical line module of the line differential protection device on the opposite side through the optical fiber channel; Each main CPU obtains the synchronized sampling data of the main CPU and the slave CPU on the opposite side through the optical line module, and constructs a line differential protection function with logical equivalence between the main CPU and the slave CPU.

[0005] According to one aspect of the present invention, both the main CPU and the slave CPU adopt a sampling architecture combining a CPU processor, an FPGA processing chip, and an A / D sampling chip; The CPU processor is used to complete the protection logic processing. The CPU processors of each main CPU use the ping-pong synchronization algorithm to calculate the sampling synchronization error in real time and regularly send synchronization pulses to correct the sampling beat of the FPGA processing chip; The FPGA processing chip adjusts its own sampling beat according to the synchronization pulses regularly sent by the CPU processor, and obtains local sampling data from the A / D sampling chip according to the adjusted sampling beat; The A / D sampling chip completes the analog-to-digital conversion function and provides digital sampling data for the FPGA processing chip; A sampling synchronization pulse bus is provided between the master CPU and the slave CPU. The synchronization pulse sent by the master CPU to the FPGA processing chip is sent to the slave CPU via the synchronization pulse bus for correcting the sampling rhythm of the slave CPU.

[0006] According to one aspect of the present invention, the method for determining the master and slave machines on both sides of the line is as follows: After the pilot differential protection devices on both sides of the line are powered on, they each generate a random code A and B, and send them to the opposite side in each frame of data transmission. After the pilot differential protection devices on both sides receive the random codes of the opposite side devices, they compare the values of A and B, and determine the master and slave machines through the magnitude relationship between the values of A and B; If it is found that the two random codes A and B are the same, a random code is generated again for secondary comparison; when a channel reception interruption occurs in a certain pilot differential protection device, the previous determined state of the master and slave machines is maintained, and after the channel is restored, the master and slave machines are determined again by re-comparing the magnitudes of the two random codes.

[0007] According to one aspect of the present invention, the time interval , where n is the number of sampling points per cycle; T s is the sampling interval; is the reliability coefficient of the master sampling synchronization pulse sending interval.

[0008] According to one aspect of the present invention, the time interval , where n is the number of sampling points per cycle; T s is the sampling interval; is the reliability coefficient of the slave sampling synchronization pulse sending interval.

[0009] According to one aspect of the present invention, it further includes: the master and slave machines perform time t synchronization based on the synchronization error on both sides; ; wherein, is the minimum threshold for the master and slave machines to start synchronizing error adjustment; The maximum value of the single-cycle sampling rhythm adjustment amplitude; f is the frequency corresponding to a single cycle, and in the case of power frequency, f = 50HZ.

[0010] According to one aspect of the present invention, each slave CPU performs a legality check on the sampling synchronization pulse. When it detects that the sampling synchronization pulse is illegal, it enters the sampling synchronization pulse exception handling process. Otherwise, it adjusts the sampling beat according to the sampling synchronization pulse of the master CPU respectively, and completes the sampling synchronization of the local master CPU and slave CPUs as follows: The slave CPU sets the sampling synchronization pulse legality check threshold according to the accumulated deviation upper limit of each sampling synchronization pulse adjustment amount, sampling synchronization pulse transmission execution deviation, CPU crystal oscillator deviation, and FPGA processing chip crystal oscillator deviation ; when the FPGA processing chip detects that the sampling synchronization pulse deviation is not greater than it determines that the sampling synchronization pulse interval is within the legal range, and the slave CPU adjusts the sampling beat with this sampling synchronization pulse to achieve the synchronization of the master CPU and slave CPUs; when the sampling synchronization pulse deviation is greater than it enters the sampling synchronization pulse exception handling process.

[0011] According to one aspect of the present invention, the sampling synchronization pulse exception handling process includes: When the FPGA processing chip detects that the sampling synchronization pulse deviation is greater than it determines that the sampling synchronization pulse interval exceeds the legal range, and then it no longer adjusts the sampling beat following this sampling synchronization pulse, and the FPGA processing chip uses its own beat for timekeeping; during the timekeeping process, if the FPGA processing chip detects that the sampling synchronization pulse deviation is not greater than for N1 consecutive times, it resumes using the sampling synchronization pulse to adjust the sampling beat. During the recovery process, the pilot differential protection device briefly locks the pilot differential protection to avoid misoperation of the differential protection caused by excessive deviation between the synchronization pulse and its own crystal oscillator beat before and after recovery; if the sampling synchronization pulse deviation still does not meet the condition for resuming use after exceeding the timekeeping time, it directly sets the sampling synchronization pulse exception flag and locks the pilot differential protection; When the FPGA detects that the sampling synchronization pulse deviation is greater than for 3 consecutive times, it directly sets the sampling synchronization pulse exception flag and locks the pilot differential protection. Subsequently, if the FPGA processing chip detects that the sampling synchronization pulse deviation is not greater than for N2 consecutive times, it resumes using the sampling synchronization pulse to adjust the sampling beat. During the recovery process, the pilot differential protection device briefly locks the pilot differential protection to avoid misoperation of the differential protection caused by excessive deviation between the synchronization pulse and its own crystal oscillator beat before and after recovery, and then opens the pilot differential protection after the sampling synchronization pulse is stable.

[0012] According to one aspect of the present invention, after the four CPUs of the master and slave devices on both sides of the line are synchronized, the synchronized sampling data of the slave CPUs on each side is sent to the master CPU through a high-speed data bus. The master CPU sends the communication characteristic word, the master CPU sampling data, the slave CPU sampling data, the digital input information, the channel number, and the application layer check code to the FPGA processing chip for data encapsulation according to the optical longitudinal data convention format. Among them, the communication characteristic word includes the master-slave random code, the sampling point number, and the number of the most recently received sampling point. The master CPU sampling data includes the master CPU current sampling value and the master CPU voltage sampling value. The slave CPU sampling data includes the slave CPU current sampling value and the slave CPU voltage sampling value.

[0013] According to one aspect of the present invention, each master CPU obtains the synchronized sampling data of the master and slave CPUs on the opposite side through the optical longitudinal module, and constructs a line pilot differential protection function with logical equivalence between the master and slave CPUs, including: The master CPUs on each side of the line select the synchronized sampling data of the master CPUs on the opposite side to construct the master CPU differential protection action equation, and the slave CPUs on each side of the line select the synchronized sampling data of the slave CPUs on the opposite side to construct the slave CPU differential protection action equation; Both the master and slave devices perform protection logic discrimination through the differential protection action equations of the master and slave CPUs completed by themselves. When both the master CPU and the slave CPU meet the differential protection action logic, the differential protection action trips. If only a certain CPU meets the differential protection action condition, only the master or slave device sends a message.

[0014] To achieve the above object, the present invention also provides a line pilot differential protection system with logical equivalence of dual CPUs, including: The master CPU and slave CPU configuration module. Pilot differential protection devices are configured on both sides of the line, and the pilot differential protection devices on both sides adopt a dual-CPU protection architecture of the master CPU and the slave CPU. The master CPU and the slave CPU obtain local sampling data through their respective sampling modules, and the master CPU obtains the sampling data of the master and slave CPUs on the opposite side through the optical longitudinal module; The master-slave device synchronization error calculation module. The pilot differential protection device on one side of the line is the master device, and the pilot differential protection device on the other side is the slave device. The master and slave devices exchange analog quantities, digital inputs, and communication characteristic word information through the optical fiber channel, and use the ping-pong synchronization algorithm to calculate the synchronization error between the two sides; The master CPU sampling module of the master device. The sampling beats of the master CPU and the slave CPU of the master device are fixed. The master CPU therein sends sampling synchronization pulses to the slave CPU of the master device at time intervals through the sampling synchronization bus according to its own sampling beat ; The slave CPU sampling module of the slave device. The master CPU of the slave device adjusts the sampling beat according to the synchronization error between the two sides Adjust the sampling time of this CPU regularly to track the sampling rhythm of the host, and send sampling synchronization pulses to the slave CPUs of the slave machines at time intervals through the sampling synchronization bus; Send sampling synchronization pulses to the slave CPUs of the slave machines; Master-slave sampling synchronization module. Each slave CPU performs a legality check on the sampling synchronization pulse. When it detects that the sampling synchronization pulse is illegal, it enters the abnormal processing flow of the sampling synchronization pulse. Otherwise, it adjusts the sampling rhythm according to the sampling synchronization pulse of the master CPU respectively, completes the sampling synchronization of the master CPU and slave CPU of this machine, and realizes the sampling synchronization of the four CPUs of the host and slave machines on both sides of the line; Synchronous sampling data processing module. Each slave CPU sends the synchronous sampling data to each master CPU through the high-speed data bus respectively, and then sends it to the optical longitudinal module through the master CPU for encapsulation. Synchronously, the switch quantity and communication characteristic word are packed into a frame of complete data and sent to the optical longitudinal module of the pilot differential protection device on the opposite side through the optical fiber channel; Line pilot differential protection module. Each master CPU and slave CPU obtain the synchronous sampling data of the master CPU and slave CPU on the opposite side through the optical longitudinal module, and construct the line pilot differential protection function with logical equivalence between the master CPU and slave CPU.

[0015] To achieve the above object, the present invention also provides an electronic device, including a processor, a memory, and a computer program stored on the memory and executable on the processor. When the computer program is executed by the processor, it implements the line pilot differential protection method with logical equivalence of dual CPU protection as described above.

[0016] To achieve the above object, the present invention also provides a computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, it implements the line pilot differential protection method with logical equivalence of dual CPU protection as described above.

[0017] According to the solution of the present invention, the present invention solves the problem that the existing line protection device can only use the sampling data of the master CPU for differential protection logic operation by synchronously adjusting the dual CPUs of the pilot differential protection devices on both sides of the line and checking the legality of the sampling synchronization pulse, and provides a practical method for constructing a safe, reliable, and logically equivalent master-slave dual CPU line pilot differential protection, upgrading the existing architecture design of "protection" + "start" to a logical architecture of "protection" + "protection", which can greatly improve the reliability of the line pilot differential protection device.

[0018] In the present invention, the device has a reliable sampling synchronization pulse legality check mechanism and perfect abnormal processing and warning measures, which can ensure the safety of adjusting the sampling rhythm using the sampling synchronization pulse while effectively improving the reliability and stability of the device operation.

[0019] In the present invention, the device adopts a sampling architecture of "CPU processor" + "FPGA processing chip" + "A / D sampling chip", with the sampling link being preposed. The FPGA completes the sampling, and the CPU is only used to correct the sampling beat of the FPGA, which can effectively reduce the CPU load and improve the operation efficiency of the device.

[0020] In the present invention, the sampling synchronization of the master and slave dual CPUs can greatly improve the consistency of the dual-CPU sampling of the line pilot differential protection device, effectively avoiding abnormal protection operation behaviors caused by sampling deviations.

[0021] The present invention is based on the synchronous adjustment of the currents and voltages of the master and slave dual CPUs on both sides of the line. The principle is simple and easy to implement, and it has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematically showing a flowchart of a line pilot differential protection method with dual-CPU protection logic equivalence according to an embodiment of the present invention; Figure 2 Schematically showing a diagram of the master and slave architectures according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] The content of the present invention will now be described with reference to exemplary embodiments. It should be understood that the described embodiments are only for enabling those of ordinary skill in the art to better understand and thus implement the content of the present invention, rather than implying any limitation to the scope of the present invention.

[0024] As used herein, the term "comprising" and its variants are to be construed as open-ended terms meaning "including but not limited to". The term "based on" is to be construed as "at least partially based on". The terms "one embodiment" and "an embodiment" are to be construed as "at least one embodiment".

[0025] Figure 1 Schematically showing a flowchart of a line pilot differential protection method with dual-CPU protection logic equivalence according to an embodiment of the present invention; Figure 2 Schematically showing a diagram of the master and slave architectures according to an embodiment of the present invention. As Figure 1 and Figure 2 shown, in the present embodiment, the line pilot differential protection method with dual-CPU protection logic equivalence includes: Line pilot differential protection devices are respectively configured on both sides of the line, and the line differential protection devices on both sides adopt a dual-CPU protection architecture of a master CPU and a slave CPU. The master CPU and the slave CPU obtain local sampling data through their respective sampling modules, and the master CPU obtains the sampling data of the master CPU and the slave CPU on the opposite side through an optical pilot module; The pilot differential protection device on one side of the line is the master unit, and the pilot differential protection device on the other side is the slave unit. The master unit and the slave unit exchange analog quantities, switch quantities, and communication characteristic word information through an optical fiber channel, and use the ping-pong synchronization algorithm to calculate the synchronization error between the two sides. Calculation; The sampling beats of the main CPU and the slave CPU of the master unit are fixed. Among them, the main CPU, according to its own sampling beat, sends sampling synchronization pulses to the slave CPU of the master unit at time intervals through the sampling synchronization bus. Send sampling synchronization pulses to the slave CPU of the master unit; The main CPU of the slave unit adjusts the sampling moment of this CPU regularly according to the synchronization error between the two sides. To track the sampling beat of the master unit, and send sampling synchronization pulses to the slave CPU of the slave unit at time intervals through the sampling synchronization bus. Send sampling synchronization pulses to the slave CPU of the slave unit; Each slave CPU performs a legality check on the sampling synchronization pulse. When it detects that the sampling synchronization pulse is illegal, it enters the abnormal processing flow of the sampling synchronization pulse. Otherwise, it adjusts the sampling beat according to the sampling synchronization pulse of the main CPU respectively, completes the sampling synchronization of the main CPU and the slave CPU of this machine, and realizes the sampling synchronization of the four CPUs of the master unit and the slave unit on both sides of the line; Each slave CPU sends the synchronous sampling data to each main CPU through the high-speed data bus respectively, and then sends it to the optical longitudinal module through the main CPU for encapsulation (the optical longitudinal module receives and transmits the sampling data, and then performs data encapsulation through the FPGA processing chip), and synchronously packs the switch quantity and the communication characteristic word into a frame of complete data and sends it to the optical longitudinal module of the pilot differential protection device on the opposite side through the optical fiber channel; Each main CPU obtains the synchronous sampling data of the main CPU and the slave CPU on the opposite side through the optical longitudinal module, and constructs the pilot differential protection function of the line with logical equivalence between the main CPU and the slave CPU.

[0026] In this embodiment, the main (pilot differential protection function) and backup (backup such as distance and zero sequence) protection functions of the pilot differential protection device are designed according to the dual-CPU action logic, realizing the "protection" + "protection" logic architecture of the line pilot differential protection device, and improving the reliability of the protection device.

[0027] Furthermore, according to an embodiment of the present invention, both the main CPU and the slave CPU adopt a sampling architecture combining a CPU processor, an FPGA processing chip, and an A / D sampling chip; The CPU processor is used to complete the protection logic processing. The CPU processors of each main CPU use the ping-pong synchronization algorithm to calculate the sampling synchronization error in real time and send synchronization pulses regularly to correct the sampling beat of the FPGA processing chip; The FPGA processing chip adjusts its own sampling rhythm according to the synchronization pulses periodically sent by the CPU processor, and obtains local sampling data from the A / D sampling chip according to the adjusted sampling rhythm. The A / D sampling chip completes the analog-to-digital conversion function and provides digital sampling data for the FPGA processing chip. A sampling synchronization pulse bus is provided between the main CPU and the slave CPU. The synchronization pulse sent by the main CPU to the FPGA processing chip is sent to the slave CPU through the synchronization pulse bus to correct the sampling rhythm of the slave CPU.

[0028] In the above sampling architecture, the sampling link is preposed, and the FPGA processing chip completes the sampling, while the CPU is only used to correct the sampling rhythm of the FPGA, which can effectively reduce the CPU load and improve the operation efficiency of the device.

[0029] Further, in this embodiment, through the encapsulation and decapsulation of the optical longitudinal data by the FPGA processing chip of the main CPU, information transmission is carried out through the optical longitudinal interface of the optical longitudinal module, so as to realize the reliable interaction of information between the two-sided longitudinal differential protection devices.

[0030] Further, according to an embodiment of the present invention, the method for determining the master and slave machines on both sides of the line is as follows: After the longitudinal differential protection devices on both sides of the line are powered on, they each generate a random code A and B and send them to the opposite side in each frame of data transmission. After the longitudinal differential protection devices on both sides receive the random codes of the opposite side devices, they compare the values of A and B, and determine the master and slave machines according to the size relationship between the values of A and B (for example, the larger value is the master machine and the smaller value is the slave machine); If it is found that the two random codes A and B are the same, a random code is generated again for secondary comparison; when the channel reception of a certain longitudinal differential protection device is interrupted, the previous determined state of the master and slave machines is maintained, and after the channel is restored, the master and slave machines are determined again by comparing the sizes of the two random codes again.

[0031] Further, according to an embodiment of the present invention, the above time interval , where n is the number of sampling points per power frequency cycle; T s is the sampling interval; is the reliable coefficient of the master machine sampling synchronization pulse sending interval.

[0032] In this embodiment, since the sampling rhythm of the master machine is fixed, it is only necessary to ensure that the slave CPU has the same sampling rhythm as the main CPU. Therefore the value of can be appropriately relaxed. Generally can take values from 5 to 50. In the case of power frequency 50HZ, that is, n*T S =0.02s, The value generally ranges from 0.1 to 1 s.

[0033] Furthermore, according to an embodiment of the present invention, the above time interval , where n is the number of sampling points per power frequency cycle; T s is the sampling interval; is the reliable coefficient of the slave sampling synchronization pulse transmission interval.

[0034] In this embodiment, since the main CPU and slave CPU of the slave need to adjust sampling according to the synchronization error on both sides of the line , to improve the adjustment accuracy of the sampling rhythm and at the same time consider reducing the impact on the protection algorithm during the sampling rhythm adjustment process, the value of should not be too large, generally S taking a value of 1 to 5. In the case of power frequency 50 Hz, that is, n * T the value generally ranges from 0.02 to 0.1 s.

[0035] Furthermore, according to an embodiment of the present invention, to achieve a smooth adjustment of the synchronization process, the adjustment amplitude of the slave side synchronization error adopts a step-by-step approximation method, and the master and slave perform time t synchronization based on the synchronization error on both sides; ; wherein, is the minimum threshold for the master and slave to start the synchronization error adjustment, generally taking a value not greater than 50 μs; is the maximum value of the single power frequency cycle sampling rhythm adjustment amplitude, generally taking a value of 10 to 15 μs; f is the frequency corresponding to a single power frequency cycle, and in the case of power frequency, f = 50 Hz.

[0036] Furthermore, according to an embodiment of the present invention, each slave CPU performs a legality check on the sampling synchronization pulse. When it detects that the sampling synchronization pulse is illegal, it enters the sampling synchronization pulse exception handling process. Otherwise, it adjusts the sampling rhythm according to the sampling synchronization pulse of the main CPU respectively, and completes the sampling synchronization of the main CPU and slave CPU of the local machine as follows: The slave CPU sets the sampling synchronization pulse legality check threshold according to the sum of the adjustment amount of each sampling synchronization pulse, the execution deviation of the sampling synchronization pulse transmission, the CPU crystal oscillator deviation, and the FPGA processing chip crystal oscillator deviation , generally taking a value of 200 to 300 μs; when the FPGA processing chip detects that the sampling synchronization pulse deviation is not greater than When it is determined that the sampling synchronization pulse interval is within the legal range, the sampling beat is adjusted from the CPU following the sampling synchronization pulse to achieve synchronization between the master CPU and the slave CPU; when the deviation of the sampling synchronization pulse is greater than then it enters the abnormal processing flow of the sampling synchronization pulse. Such a solution can ensure the reliability of the device using the sampling synchronization pulse to adjust the sampling beat.

[0037] Furthermore, according to an embodiment of the present invention, the abnormal processing flow of the sampling synchronization pulse includes: When the FPGA processing chip detects that the deviation of the sampling synchronization pulse is greater than it is determined that the sampling synchronization pulse interval exceeds the legal range, and then the sampling beat is no longer adjusted following the sampling synchronization pulse. The FPGA processing chip uses its own beat to keep time; during the timekeeping process, if the FPGA processing chip detects that the deviation of the sampling synchronization pulse is not greater than for N1 consecutive times (N1 generally does not exceed 5), then the sampling synchronization pulse is restored to adjust the sampling beat. During the restoration process, the pilot differential protection device briefly locks the pilot differential protection to avoid misoperation of the differential protection caused by too large a deviation between the synchronization pulse and its own crystal oscillator beat before and after restoration; if the deviation of the sampling synchronization pulse still does not meet the condition for restoring use after exceeding the timekeeping time, then the abnormal flag of the sampling synchronization pulse is directly set, and the pilot differential protection is locked; When the FPGA detects that the deviation of the sampling synchronization pulse is greater than for 3 consecutive times, then the abnormal flag of the adopted synchronization pulse is directly set, and the pilot differential protection is locked. Subsequently, if the FPGA processing chip detects that the deviation of the sampling synchronization pulse is not greater than for N2 consecutive times (N2 generally does not exceed 10), then the sampling synchronization pulse is restored to adjust the sampling beat. During the restoration process, the pilot differential protection device briefly locks the pilot differential protection to avoid misoperation of the differential protection caused by too large a deviation between the synchronization pulse and its own crystal oscillator beat before and after restoration, and the pilot differential protection is opened after the sampling synchronization pulse is stable.

[0038] Furthermore, according to an embodiment of the present invention, after the four CPUs of the host and slave on both sides of the line are synchronized, the synchronized sampling data of the slave CPUs on each side are sent to the master CPU through the high-speed data bus. The master CPU sends the communication characteristic word, the master CPU sampling data, the slave CPU sampling data, the switch quantity information, the channel number, and the application layer check code to the FPGA processing chip for data encapsulation according to the optical longitudinal data convention format; among them, the communication characteristic word includes contents such as the master-slave random coding, the sampling point number, and the number of the most recently received sampling point; the master CPU sampling data includes the master CPU current sampling value and the master CPU voltage sampling value; the slave CPU sampling data includes the slave CPU current sampling value and the slave CPU voltage sampling value.

[0039] Furthermore, according to an embodiment of the present invention, each master CPU obtains the synchronous sampling data of the opposite master CPU and slave CPUs through the optical longitudinal module, and constructs a line longitudinal differential protection function with logical equivalence between the master CPU and slave CPUs, including: After the master CPU obtains the synchronous sampling data of the opposite master CPU and slave CPUs through the optical longitudinal module, it synchronizes the sampling data to the slave CPU through the sampling synchronization bus; The master CPUs on each side of the line select the synchronous sampling data of the opposite master CPU to construct the master CPU differential protection action equation, and the slave CPUs on each side of the line select the synchronous sampling data of the opposite slave CPU to construct the slave CPU differential protection action equation; Both the master and slave devices perform protection logic discrimination through the differential protection action equations of the master CPU and slave CPU completed by themselves. When both the master CPU and slave CPU meet the differential protection action logic, the differential protection acts to trip. If only a certain CPU meets the differential protection action condition, the master or slave device only sends a message, does not light the trip action light, and does not drive the protection trip output. The backup protection refers to the differential protection action logic, and when the dual CPUs meet the action logic, it drives the output. Then the line differential protection device can achieve the design of logical equivalence of dual CPUs protection, which can effectively improve the reliability of protection actions.

[0040] According to the above solution of the present invention, the present invention solves the problem that the existing line protection device can only use the sampling data of the master CPU for differential protection logic operation through the synchronous adjustment of the dual CPUs of the line longitudinal differential protection device on both sides and the legality verification of the sampling synchronization pulse, provides a practical method for constructing a safe, reliable and logically equivalent master-slave dual-CPU line longitudinal differential protection, upgrades the existing architecture design of "protection" + "start" to the logical architecture of "protection" + "protection", and can greatly improve the reliability of the line longitudinal differential protection device.

[0041] In the present invention, the device has a reliable sampling synchronization pulse legality verification mechanism and perfect abnormal handling and warning measures, which can ensure the safety of using the sampling synchronization pulse for sampling beat adjustment, and can effectively improve the reliability and stability of the device operation.

[0042] In the present invention, the device adopts a sampling architecture of "CPU processor" + "FPGA processing chip" + "A / D sampling chip", preposes the sampling link, and the FPGA completes the sampling, while the CPU is only used to correct the sampling beat of the FPGA, which can effectively reduce the CPU load and improve the operation efficiency of the device.

[0043] In the present invention, the sampling synchronization of the master-slave dual CPUs can greatly improve the consistency of the dual-CPU sampling of the line longitudinal differential protection device, and effectively avoid the abnormal protection action behavior caused by sampling deviation.

[0044] The present invention is based on the synchronous regulation of the current and voltage of the master and slave dual CPUs on both sides of the line. The principle is simple and easy to implement, and it has broad application prospects.

[0045] Furthermore, to achieve the above object, the present invention also provides a line pilot differential protection system with dual-CPU protection logic peer-to-peer, including: Master CPU and slave CPU configuration modules. Pilot differential protection devices are respectively configured on both sides of the line, and the pilot differential protection devices on both sides adopt the dual-CPU protection architecture of the master CPU and the slave CPU. The master CPU and the slave CPU obtain local sampling data through their respective sampling modules, and the master CPU obtains the sampling data of the master CPU and the slave CPU on the opposite side through the optical pilot module; Master-slave machine synchronous error calculation module. The pilot differential protection device on one side of the line is the master machine, and the pilot differential protection device on the other side is the slave machine. The master machine and the slave machine exchange analog quantities, switch quantities, and communication characteristic words through the optical fiber channel, and use the ping-pong synchronization algorithm to calculate the synchronous error between the two sides; Host CPU sampling module. The sampling beats of the master CPU and the slave CPU of the host are fixed. The master CPU therein sends sampling synchronization pulses to the slave CPU of the host at time intervals through the sampling synchronization bus according to its own sampling beat ; Slave CPU sampling module. The master CPU of the slave adjusts the sampling moment of its own CPU regularly according to the synchronous error between the two sides to track the sampling beat of the host, and sends sampling synchronization pulses to the slave CPU of the slave at time intervals through the sampling synchronization bus ; Master-slave machine sampling synchronization module. Each slave CPU performs a legality check on the sampling synchronization pulse. When it detects that the sampling synchronization pulse is illegal, it enters the sampling synchronization pulse exception handling process. Otherwise, it adjusts the sampling beat according to the sampling synchronization pulse of the master CPU respectively, completes the sampling synchronization of the master CPU and the slave CPU of the local machine, and realizes the sampling synchronization of the four CPUs of the host and the slave on both sides of the line; Synchronous sampling data processing module. Each slave CPU respectively sends the synchronous sampling data to each master CPU through the high-speed data bus, and then the master CPU sends it to the optical pilot module for optical pilot data encapsulation. Synchronously, the switch quantity and the communication characteristic word are packed into a frame of complete data and sent to the optical pilot module of the pilot differential protection device on the opposite side through the optical fiber channel; Line pilot differential protection module. Each master CPU obtains the synchronous sampling data of the master CPU and the slave CPU on the opposite side through the optical pilot module, and constructs the line pilot differential protection function with the master CPU and the slave CPU logic peer-to-peer.

[0046] The line pilot differential protection system with dual-CPU protection logic equivalence according to the present invention can implement the above-mentioned line pilot differential protection method with dual-CPU protection logic equivalence. The specific process steps are as described above and will not be elaborated here.

[0047] Furthermore, to achieve the above object, the present invention also provides an electronic device, including a processor, a memory, and a computer program stored on the memory and executable on the processor. When the computer program is executed by the processor, it implements the above-mentioned line pilot differential protection method with dual-CPU protection logic equivalence.

[0048] Furthermore, to achieve the above object, the present invention also provides a computer-readable storage medium with a computer program stored thereon. When the computer program is executed by the processor, it implements the above-mentioned line pilot differential protection method with dual-CPU protection logic equivalence.

[0049] Those of ordinary skill in the art can realize that the modules and algorithm steps described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0050] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the above-described devices and equipment can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated here.

[0051] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division. In actual implementation, there may be other division methods. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection can be through some interfaces. The indirect coupling or communication connection of devices or modules can be in an electrical, mechanical, or other form.

[0052] The modules described as separate components may or may not be physically separated. The components displayed as modules may or may not be physical modules, that is, they can be located in one place or distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the embodiments of the present invention.

[0053] In addition, each functional module in the embodiments of the present invention may be integrated into one processing module, may exist physically alone for each module, or two or more modules may be integrated into one module.

[0054] If the above functions are implemented in the form of software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method for sending / receiving energy-saving signals in various embodiments of the present invention. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, ROM, RAM, magnetic disks, or optical discs that can store program codes.

[0055] The above description is only for the preferred embodiments of the present application and the explanation of the applied technical principles. Those skilled in the art should understand that the scope of the invention involved in the present application is not limited to the technical solution formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the technical solutions formed by mutually replacing the above features with the (but not limited to) technical features with similar functions disclosed in the present application.

[0056] It should be understood that the magnitudes of the sequence numbers of the steps in the content and embodiments of the present invention do not absolutely mean the sequence of execution. The execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

Claims

1. Line pilot differential protection method with dual CPU protection logic peer-to-peer, characterized in that, Including: Pilot differential protection devices are respectively configured on both sides of the line, and the pilot differential protection devices on both sides adopt a dual-CPU protection architecture of a main CPU and a slave CPU. The main CPU and the slave CPU obtain local sampling data through their respective sampling modules, and the main CPU obtains the sampling data of the main CPU and the slave CPU on the opposite side through the optical pilot module; The pilot differential protection device on one side of the line is the master unit, and the pilot differential protection device on the other side is the slave unit. The master unit and the slave unit exchange analog quantities, digital quantities, and communication characteristic word information through an optical fiber channel, and use the ping-pong synchronization algorithm to calculate the synchronization error between the two sides. Calculation; The sampling beats of the main CPU and the slave CPU of the host are fixed. The main CPU among them, according to its own sampling beat, sends sampling synchronization pulses to the slave CPU of the host at time intervals through the sampling synchronization bus ; The slave's main CPU adjusts the sampling time of this CPU at regular intervals according to the synchronization error on both sides to track the sampling rhythm of the master, and sends sampling synchronization pulses to the slave CPU of the slave through the sampling synchronization bus at time intervals of; Each slave CPU performs a legality check on the sampling synchronization pulse. When it detects that the sampling synchronization pulse is illegal, it enters the sampling synchronization pulse exception handling process. Otherwise, it adjusts the sampling beat according to the sampling synchronization pulse of the main CPU respectively, completes the sampling synchronization of the main CPU and the slave CPU of the local machine, and realizes the sampling synchronization of the four CPUs of the main and slave machines on both sides of the line; Each slave CPU respectively sends the synchronous sampling data to each main CPU through the high-speed data bus, and then sends it to the optical pilot module through the main CPU for encapsulation. The switch quantity and communication characteristic word are synchronously packed into a frame of complete data and sent to the optical pilot module of the pilot differential protection device on the opposite side through the optical fiber channel; Each main CPU obtains the synchronous sampling data of the main CPU and the slave CPU on the opposite side through the optical pilot module, and constructs the line pilot differential protection function with logical equivalence between the main CPU and the slave CPU.

2. The line pilot differential protection method with dual CPU protection logic peer-to-peer according to claim 1, characterized in that, Both the main CPU and the slave CPU adopt a sampling architecture combining a CPU processor, an FPGA processing chip, and an A / D sampling chip; The CPU processor is used to complete the protection logic processing. The CPU processors of each main CPU use the ping-pong synchronization algorithm to calculate the sampling synchronization error in real time and regularly send synchronization pulses to correct the sampling beat of the FPGA processing chip; The FPGA processing chip adjusts its own sampling beat according to the synchronization pulse regularly sent by the CPU processor, and obtains local sampling data from the A / D sampling chip according to the adjusted sampling beat; The A / D sampling chip completes the analog-to-digital conversion function and provides digital sampling data for the FPGA processing chip; A sampling synchronization pulse bus is provided between the main CPU and the slave CPU. The synchronization pulse sent by the main CPU to the FPGA processing chip is sent to the slave CPU through the synchronization pulse bus to correct the sampling beat of the slave CPU.

3. The line pilot differential protection method with dual CPU protection logic peer-to-peer according to claim 1, characterized in that, The determination method for the main and slave machines on both sides of the line is as follows: After the pilot differential protection devices on both sides of the line are powered on, they respectively generate a random code A and B, and send them to the opposite side during each frame of data transmission. After the pilot differential protection devices on both sides receive the random codes of the opposite side devices respectively, they compare the values of A and B, and determine the main and slave machines through the magnitude relationship between the values of A and B; If it is found that the two random codes A and B are the same, a random code is generated again for a second comparison; When a channel reception interruption occurs in a certain pilot differential protection device, the previous determination state of the main and slave machines is maintained. After the channel is restored, the main and slave machines are determined again by comparing the magnitudes of the two random codes again.

4. The line pilot differential protection method with dual CPU protection logic peer-to-peer according to claim 1, characterized in that The time interval , where n is the number of weekly wave sampling points; T s is the sampling interval; is the reliable coefficient of the host sampling synchronization pulse transmission interval.

5. The line pilot differential protection method with dual CPU protection logic peer-to-peer according to claim 1, characterized in that The time interval , where n is the number of weekly wave sampling points; T s is the sampling interval; is the reliable coefficient of the slave sampling synchronization pulse transmission interval.

6. The line pilot differential protection method with dual CPU protection logic peer-to-peer as claimed in claim 1, wherein Also including: The master and slave devices synchronize the time t based on the synchronization error on both sides ; ； Among them, is the minimum threshold for the host and slave to start synchronous error adjustment; is the maximum value of the single-cycle sampling beat adjustment amplitude; f is the frequency corresponding to a single cycle. In the case of power frequency, f = 50HZ.

7. The line pilot differential protection method with dual CPU protection logic peer-to-peer according to claim 2, characterized in that, Each of the slave CPUs performs a legality check on the sampling synchronization pulse. When it detects that the sampling synchronization pulse is illegal, it enters the sampling synchronization pulse exception handling process. Otherwise, it adjusts the sampling beat according to the sampling synchronization pulse of the main CPU respectively, and the completion of the sampling synchronization of the main CPU and the slave CPU of the local machine is as follows: The CPU sets the sampling synchronization pulse legality check threshold according to the sum of the adjustment amounts of each sampling synchronization pulse, the execution deviation of the sampling synchronization pulse transmission, the CPU crystal oscillator deviation, and the FPGA processing chip crystal oscillator deviation When the FPGA processing chip detects that the sampling synchronization pulse deviation is not greater than At this time, it is determined that the sampling synchronization pulse interval is within the legal range, and the slave CPU adjusts the sampling beat with this sampling synchronization pulse to achieve synchronization between the master CPU and the slave CPU; when the sampling synchronization pulse deviation is greater than Then, it enters the sampling synchronization pulse exception handling process.

8. The line pilot differential protection method with dual CPU protection logic peer-to-peer according to claim 7, characterized in that, The abnormal processing flow of the sampling synchronization pulse includes: When the FPGA processing chip detects that the sampling synchronization pulse deviation is greater than , it is determined that the sampling synchronization pulse interval exceeds the legal range, and the sampling beat is no longer adjusted following this sampling synchronization pulse. The FPGA processing chip uses its own beat for timekeeping. During the timekeeping process, if the sampling synchronization pulse deviation detected by the FPGA processing chip is not greater than for N1 consecutive times, the sampling beat is restored to be adjusted using the sampling synchronization pulse. During the restoration process, the pilot differential protection device briefly locks the pilot differential protection. If the sampling synchronization pulse deviation still does not meet the condition for restoration after exceeding the timekeeping time, the sampling synchronization pulse abnormal flag is directly set, and the pilot differential protection is locked; When the deviation of the sampling synchronization pulse detected by the FPGA is greater than for three consecutive times, the abnormal flag of the sampling synchronization pulse is directly set, and the pilot differential protection is blocked. Subsequently, if the deviation of the sampling synchronization pulse detected by the FPGA processing chip is not greater than for N2 consecutive times, the sampling synchronization pulse is restored to adjust the sampling beat. During the restoration process, the pilot differential protection device briefly blocks the pilot differential protection and then opens the pilot differential protection after the sampling synchronization pulse is stable.

9. The line pilot differential protection method with dual CPU protection logic peer-to-peer according to claim 2, characterized in that After the four CPUs of the master and slave devices on both sides of the line are synchronized, the synchronized sampling data of the slave CPUs on each side are sent to the master CPU through the high-speed data bus. The master CPU sends the communication characteristic word, the master CPU sampling data, the slave CPU sampling data, the digital input information, the channel number, and the application layer check code to the FPGA processing chip for data encapsulation according to the optical longitudinal data convention format; among them, the communication characteristic word includes the master-slave random code, the sampling point number, and the number of the most recently received sampling point; the master CPU sampling data includes the master CPU current sampling value and the master CPU voltage sampling value; the slave CPU sampling data includes the slave CPU current sampling value and the slave CPU voltage sampling value.

10. The line pilot differential protection method with dual CPU protection logic peer-to-peer according to any one of claims 1-9, characterized in that, Each master CPU obtains the synchronized sampling data of the master and slave CPUs on the opposite side through the optical longitudinal module, and constructs a line pilot differential protection function with logical equivalence between the master and slave CPUs, including: the master CPUs on each side of the line select the synchronized sampling data of the master CPUs on the opposite side to construct the master CPU differential protection action equation, and the slave CPUs on each side of the line select the synchronized sampling data of the slave CPUs on the opposite side to construct the slave CPU differential protection action equation; Both the master and slave devices perform protection logic discrimination through the differential protection action equations of the master and slave CPUs they have completed. When both the master and slave CPUs meet the differential protection action logic, the differential protection acts and trips. If only a certain CPU meets the differential protection action condition, the master or slave device only sends a message.

11. The line pilot differential protection system with dual CPU protection logics being peer-to-peer, characterized in that, It includes: The master and slave CPU configuration module: Pilot differential protection devices are configured on both sides of the line, and the pilot differential protection devices on both sides adopt a dual-CPU protection architecture of the master and slave CPUs. The master and slave CPUs obtain local sampling data through their respective sampling modules, and the master CPU obtains the sampling data of the master and slave CPUs on the opposite side through the optical longitudinal module; Master-slave machine synchronization error calculation module. The pilot differential protection device on one side of the line is the master machine, and the pilot differential protection device on the other side is the slave machine. The master machine and the slave machine exchange analog quantities, switch quantities, and communication characteristic word information through an optical fiber channel, and use the ping-pong synchronization algorithm to calculate the synchronization error between the two sides. Calculation; Host CPU Sampling Module. The sampling beats of the main CPU and the slave CPU of the host are fixed. The main CPU therein, according to its own sampling beat, sends sampling synchronization pulses to the slave CPU of the host through the sampling synchronization bus at time intervals ; Slave CPU Sampling Module. The main CPU of the slave adjusts the sampling time of this CPU at regular intervals according to the synchronization error on both sides to track the sampling rhythm of the master, and sends sampling synchronization pulses to the slave CPUs of the slave through the sampling synchronization bus at time intervals ; The master-slave sampling synchronization module: Each slave CPU performs legality verification on the sampling synchronization pulse. When it detects that the sampling synchronization pulse is illegal, it enters the abnormal processing flow of the sampling synchronization pulse. Otherwise, it adjusts the sampling rhythm according to the sampling synchronization pulse of the master CPU respectively to complete the sampling synchronization of the master and slave CPUs of the local machine, and realizes the sampling synchronization of the four CPUs of the master and slave devices on both sides of the line; The synchronized sampling data processing module: Each slave CPU sends the synchronized sampling data to each master CPU through the high-speed data bus, and then sends it to the optical longitudinal module through the master CPU for encapsulation. At the same time, the digital input and the communication characteristic word are packed into a complete frame of data and sent to the optical longitudinal module of the pilot differential protection device on the opposite side through the optical fiber channel; The line pilot differential protection module: Each master CPU obtains the synchronized sampling data of the master and slave CPUs on the opposite side through the optical longitudinal module, and constructs a line pilot differential protection function with logical equivalence between the master and slave CPUs.

12. An electronic device, characterized in that, It includes a processor, a memory, and a computer program stored on the memory and executable on the processor. When the computer program is executed by the processor, it implements the line pilot differential protection method with logical equivalence of the dual-CPU protection as described in any one of claims 1-10.

13. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium. When the computer program is executed by a processor, it implements the line pilot differential protection method with dual CPU protection logic peer-to-peer as described in any one of claims 1-10.

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