Hybrid power topology circuit, voltage conversion method, power supply chip and electronic equipment

Abstract

The embodiment of the invention provides a hybrid power topology circuit, a voltage conversion method, a power supply chip and electronic equipment. The hybrid power topology circuit comprises a first voltage conversion circuit, a second voltage conversion circuit and an equalization circuit, when the hybrid power topology circuit works in a charge pump mode, the first voltage conversion circuit converts an input voltage into a first output voltage at a first phase; when the hybrid power topology circuit works in a buck mode, the second voltage conversion circuit converts the input voltage into a first output voltage in a second phase, and when the hybrid power topology circuit works in a buck mode, the first voltage conversion circuit converts the input voltage into a second output voltage. The equalization circuit equalizes a first equalization node voltage of the first voltage conversion circuit and a second equalization node voltage of the second voltage conversion circuit. According to the hybrid power topology circuit, the area occupied by the circuit can be reduced, so that the chip area is reduced, and the circuit stability and the circuit conversion efficiency can be improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of integrated circuit technologies, and in particular, to a hybrid power topology circuit, a voltage conversion method, a power supply chip, and an electronic device. Background Art

[0002] A two-phase charge pump structure includes eight power transistors and two flying capacitors, and a three-level buck structure includes four power transistors, an inductor, and a capacitor. These two power topology structures, as power converters applied in fast charging devices, are widely used in consumer electronics fields such as mobile phones, tablets, and computers. In these two power topology structures, the flying capacitors can play a voltage equalization and clamping role, so that the drain-source voltage of the power transistors during normal operation is only half of the input operating voltage. Therefore, low-voltage withstand devices can be selected to reduce the on-resistance and switching losses, thereby improving the fast charging efficiency.

[0003] The traditional fast charging power topology structure is formed by integrating two sets of power topologies on the same silicon chip. During the high-current fast charging stage, the charge pump structure is used to improve the fast charging efficiency. During the dead battery and near-full charge stages of the battery, the three-level buck structure is used for charging. However, since the fast charging power topology structure consists of two discrete sets of power topologies, it will occupy a large amount of chip area. Summary of the Invention

[0004] The present disclosure provides a hybrid power topology circuit, a voltage conversion method, a power supply chip, and an electronic device, which can reduce the area occupied by the circuit, thereby reducing the chip area, and can also improve the circuit stability and the conversion efficiency of the circuit.

[0005] In a first aspect, the present disclosure provides a hybrid power topology circuit, including a first voltage conversion circuit, a second voltage conversion circuit, and an equalization circuit. The first voltage conversion circuit and the second voltage conversion circuit are connected in parallel between a voltage input terminal and the ground. The output terminal of the first voltage conversion circuit and the output terminal of the second voltage conversion circuit are connected to a voltage output terminal. The equalization circuit is connected to a first equalization node of the first voltage conversion circuit and a second equalization node of the second voltage conversion circuit.

[0006] The first voltage conversion circuit is configured to convert an input voltage into a first output voltage in a first phase when the hybrid power topology circuit operates in a charge pump mode; and convert the input voltage into a second output voltage when the hybrid power topology circuit operates in a buck mode.

[0007] The second voltage conversion circuit is configured to convert the input voltage into the first output voltage in a second phase when the hybrid power topology circuit operates in the charge pump mode, and the hybrid power topology circuit in the charge pump mode switches between the first phase and the second phase.

[0008] The balancing circuit is configured to balance a first balancing node voltage and a second balancing node voltage.

[0009] In some embodiments of the present disclosure, the balancing circuit includes a first balancing circuit and a second balancing circuit. The first balancing node includes a first high-level balancing node and a first low-level balancing node. The second balancing node includes a second high-level balancing node and a second low-level balancing node. The first balancing circuit is connected to the first high-level balancing node and the second high-level balancing node, and the second balancing circuit is connected to the first low-level balancing node and the second high-level balancing node.

[0010] The first balancing circuit is configured to balance the first high-level balancing node voltage and the second high-level balancing node voltage in a third phase when the hybrid power topology circuit operates in the buck mode; and balance the first high-level balancing node voltage and the second high-level balancing node voltage during a dead time between the adjacent first phase and second phase when the hybrid power topology circuit operates in the charge pump mode.

[0011] The second balancing circuit is configured to balance the first low-level balancing node voltage and the second high-level balancing node voltage in a fourth phase when the hybrid power topology circuit operates in the buck mode, and the hybrid power topology circuit in the buck mode switches between the third phase and the fourth phase.

[0012] In some embodiments of the present disclosure, the first balancing circuit includes a first balancing transistor and a second balancing transistor. The second balancing circuit includes a third balancing transistor and a fourth balancing transistor. A first end of the first balancing transistor is connected to a first end of the second balancing transistor. A control end of the first balancing transistor is connected to a control end of the second balancing transistor. A second end of the first balancing transistor is connected to the first high-level balancing node, and a second end of the second balancing transistor is connected to the second high-level balancing node.

[0013] A first end of the third balancing transistor is connected to a first end of the fourth balancing transistor. A control end of the third balancing transistor is connected to a control end of the fourth balancing transistor. A second end of the third balancing transistor is connected to the first low-level balancing node, and a second end of the fourth balancing transistor is connected to the second high-level balancing node.

[0014] In some embodiments of the present disclosure, the first voltage conversion circuit includes a mode switching circuit, a first transistor, a second transistor, a third transistor, a fourth transistor, and a first flying capacitor. The first transistor, the second transistor, the third transistor, and the fourth transistor are connected in series between the voltage input terminal and the ground. The connection point of the first transistor and the second transistor is the first high-level equalization node. The connection point of the second transistor and the third transistor is the switching node. The switching node is connected to the voltage output terminal through the mode switching circuit. The connection point of the third transistor and the fourth transistor is the first low-level equalization node. The first flying capacitor is connected across the first high-level equalization node and the first low-level equalization node. The control terminal of the mode switching circuit receives a mode switching signal, and the mode switching signal includes a charge pump mode switching signal and a buck mode switching signal.

[0015] The mode switching circuit is configured to short-circuit the voltage output terminal and the switching node according to the charge pump mode switching signal, and connect an inductor between the voltage output terminal and the switching node according to the buck mode switching signal.

[0016] In some embodiments of the present disclosure, the mode switching circuit includes an inductor and a switch assembly. The inductor and the switch assembly are connected in parallel between the voltage output terminal and the switching node.

[0017] The switch assembly is configured to conduct the voltage output terminal and the switching node according to the charge pump mode switching signal to short-circuit the inductor; and disconnect the voltage output terminal and the switching node according to the buck mode switching signal to connect the inductor.

[0018] In some embodiments of the present disclosure, the switch assembly includes a first switch tube and a second switch tube. The first end of the first switch tube is connected to the first end of the second switch tube. The control terminal of the first switch tube is connected to the control terminal of the second switch tube. The second end of the first switch tube is connected to the switching node. The second end of the second switch tube is connected to the voltage output terminal.

[0019] In some embodiments of the present disclosure, the second voltage conversion circuit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a second flying capacitor. The fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are connected in series between the voltage input terminal and the ground. The connection point of the fifth transistor and the sixth transistor is the second high-level equalization node. The connection point of the sixth transistor and the seventh transistor is connected to the voltage output terminal. The connection point of the seventh transistor and the eighth transistor is the second low-level equalization node. The second flying capacitor is connected across the second high-level equalization node and the second low-level equalization node.

[0020] In some embodiments of the present disclosure, in the first phase, the first transistor, the third transistor, the sixth transistor, and the eighth transistor are in the cut-off state, and the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are in the conducting state.

[0021] In the second phase, the first transistor, the third transistor, the sixth transistor, and the eighth transistor are in the conducting state, and the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are in the cut-off state.

[0022] During the dead time, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are in the cut-off state.

[0023] In some embodiments of the present disclosure, in the buck mode, the eighth transistor is in the conducting state, and the fifth transistor, the sixth transistor, and the seventh transistor are in the cut-off state; in the third phase, the fourth transistor is in the conducting state, and the first flying capacitor and the second flying capacitor are in parallel; in the fourth phase, the first transistor is in the conducting state, and the first flying capacitor and the second flying capacitor are in series.

[0024] In some embodiments of the present disclosure, when the duty cycle of the buck mode driving signal is greater than 0.5, the fourth phase includes a second sub-phase and two first sub-phases, and the second sub-phase is located between the two first sub-phases.

[0025] In the first sub-phase, the second transistor is in the on state, and the third transistor and the fourth transistor are in the off state. In the second sub-phase, the third transistor is in the on state, and the second transistor and the fourth transistor are in the off state. In the third phase, the second transistor is in the on state, and the first transistor and the third transistor are in the off state.

[0026] When the duty cycle of the buck mode driving signal is not greater than 0.5, the third phase includes a fourth sub-phase and two third sub-phases, and the fourth sub-phase is located between the two third sub-phases.

[0027] In the third sub-phase, the third transistor is in the on state, and the first transistor and the second transistor are in the off state. In the fourth sub-phase, the second transistor is in the on state, and the first transistor and the third transistor are in the off state. In the fourth phase, the third transistor is in the on state, and the second transistor and the fourth transistor are in the off state.

[0028] In a second aspect, the present disclosure provides a voltage conversion method applied to a hybrid power topology circuit. The hybrid power topology circuit includes a first voltage conversion circuit, a second voltage conversion circuit, and an equalization circuit. The first voltage conversion circuit and the second voltage conversion circuit are connected in parallel between a voltage input terminal and the ground. An output terminal of the first voltage conversion circuit and an output terminal of the second voltage conversion circuit are connected to a voltage output terminal, and the equalization circuit is connected to a first equalization node of the first voltage conversion circuit and a second equalization node of the second voltage conversion circuit. The voltage conversion method includes:

[0029] When the hybrid power topology circuit operates in the charge pump mode, the input voltage is converted into a first output voltage in the first phase and the second phase. The hybrid power topology circuit in the charge pump mode switches between the first phase and the second phase. When the hybrid power topology circuit operates in the buck mode, the input voltage is converted into a second output voltage; and the voltage of the first equalization node and the voltage of the second equalization node are equalized.

[0030] In some embodiments of the present disclosure, the first equalization node includes a first high-level equalization node and a first low-level equalization node, and the second equalization node includes a second high-level equalization node and a second low-level equalization node. Equalizing the voltage of the first equalization node and the voltage of the second equalization node includes:

[0031] When the hybrid power topology circuit operates in the buck mode, the first high-level balancing node voltage and the second high-level balancing node voltage are balanced in the third phase; the first low-level balancing node voltage and the second high-level balancing node voltage are balanced in the fourth phase; the hybrid power topology circuit in the buck mode switches between the third phase and the fourth phase; when the hybrid power topology circuit operates in the charge pump mode, the first high-level balancing node voltage and the second high-level balancing node voltage are balanced in the dead time between the adjacent first phase and the second phase.

[0032] In a third aspect, the present disclosure provides a power chip, comprising any hybrid power topology circuit provided in the first aspect.

[0033] In a fourth aspect, the present disclosure provides an electronic device, comprising any hybrid power topology circuit provided in the first aspect.

[0034] The technical solution disclosed in the present invention provides a hybrid power topology circuit, including a first voltage conversion circuit, a second voltage conversion circuit and a balancing circuit. In the first aspect, when the hybrid power topology circuit operates in a charge pump mode, the first voltage conversion circuit converts an input voltage into a first output voltage in a first phase, and the second voltage conversion circuit converts the input voltage into the first output voltage in a second phase. When the hybrid power topology circuit operates in a buck mode, the first voltage conversion circuit converts the input voltage into a second output voltage. The charge pump power topology and the buck power topology share the first voltage conversion circuit. Compared with a discrete solution, it has a smaller number of devices, which can reduce the area occupied by the circuit, thereby reducing the chip area.

[0035] On the second hand, in the buck mode, the equalization circuit equalizes the first equalization node voltage of the first voltage conversion circuit and the second equalization node voltage of the second voltage conversion circuit, and the second voltage conversion circuit can be used as a voltage equalization module of the first voltage conversion circuit. By wirelessly setting additional voltage equalization devices, the number of devices can be further reduced, the area occupied by the circuit can be reduced, and thus the chip area can be reduced. At the same time, the voltage equalization of the first voltage conversion circuit does not change with the duty cycle of the driving signal and the switching frequency of the hybrid power topology circuit, which can improve the circuit stability.

[0036] On the third aspect, in the charge pump mode, the balancing circuit balances the first balancing node voltage of the first voltage conversion circuit and the second balancing node voltage of the second voltage conversion circuit, and can balance the amount of charge on the first voltage conversion circuit and the second voltage conversion circuit to reduce the switching loss of the circuit, thereby improving the conversion efficiency of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. It should be understood that the accompanying drawings described below only relate to some embodiments of the present disclosure and do not limit the present disclosure, where:

[0038] Figure 1 FIG. 4 is a circuit schematic diagram of a power converter provided by the prior art.

[0039] Figure 2 FIG. 8 is a structural schematic diagram of a hybrid power topology circuit provided by an embodiment of the present disclosure.

[0040] Figure 3 FIG. 12 is a circuit schematic diagram of a hybrid power topology circuit provided by an embodiment of the present disclosure.

[0041] Figure 4 FIG. 16 is a circuit schematic diagram of a hybrid power topology circuit in a charge pump mode provided by an embodiment of the present disclosure.

[0042] Figure 5 FIG. 20 is a circuit schematic diagram of a hybrid power topology circuit in a buck mode provided by an embodiment of the present disclosure.

[0043] Figure 6 FIG. 24 is a timing diagram of a hybrid power topology circuit in a buck mode provided by an embodiment of the present disclosure.

[0044] Figure 7 FIG. 28 is a timing diagram of a hybrid power topology circuit in a charge pump mode provided by an embodiment of the present disclosure.

[0045] Figure 8 FIG. 32 is a schematic flowchart of a voltage conversion method provided by an embodiment of the present disclosure. Detailed implementation manners

[0046] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of the present disclosure without creative efforts also belong to the scope of protection of the present disclosure.

[0047] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Further will be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0048] References to "embodiments" in this disclosure mean that a particular feature, structure, or characteristic described in connection with the embodiments can be included in at least one embodiment of this application. The phrase "embodiment" appearing in various places in the specification is not necessarily referring to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described in this disclosure can be combined with other embodiments.

[0049] Furthermore, the terms "first", "second", etc. in the description of this disclosure and the claims or in the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order, and may explicitly or implicitly include one or more of such features.

[0050] The term "and / or" in this disclosure is merely a description of the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: the existence of A, the simultaneous existence of A and B, and the existence of B. Additionally, the character " / " in this text generally represents an "or" relationship between the associated objects before and after.

[0051] In the description of this disclosure, unless otherwise specified, the meanings of "a plurality" and "at least two" refer to more than two (including two). Similarly, "multiple groups" and "at least two groups" refer to more than two groups (including two groups).

[0052] To enable those skilled in the art to better understand the solution of this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the accompanying drawings.

[0053] Figure 1 A circuit schematic diagram of a power converter provided for the prior art, as Figure 1 shown in part (a) thereof, the two-phase charge pump structure includes transistors Q1A, Q1B, Q2A, Q2B, Q3A, Q3B, Q4A, Q4B, flying capacitors CFA, CFB, output capacitor Cout, and output resistor Rout.

[0054] Among them, transistor Q1A, transistor Q2A, transistor Q3A, and transistor Q4A are connected in series between the voltage input terminal IN and the ground. The first plate of the flying capacitor CFA is connected to the connection point of transistor Q1A and transistor Q2A, and the second plate of the flying capacitor CFA is connected to the connection point of transistor Q3A and transistor Q4A. The connection point of transistor Q2A and transistor Q3A is connected to the voltage output terminal OUT, and the voltage output terminal OUT is grounded through the output capacitor Cout and the output resistor Rout in sequence.

[0055] Transistor Q1B, transistor Q2B, transistor Q3B, and transistor Q4B are connected in series between the voltage input terminal IN and the ground. The first plate of the flying capacitor CFB is connected to the connection point of transistor Q1B and transistor Q2B, and the second plate of the flying capacitor CFB is connected to the connection point of transistor Q3B and transistor Q4B. The connection point of transistor Q2B and transistor Q3B is connected to the voltage output terminal OUT.

[0056] The flying capacitors CFA and CFB can perform voltage equalization and clamping, so that the drain-source voltage of each transistor during normal operation is half of the input operating voltage. Therefore, low-voltage transistors can be selected as each transistor, which can reduce the on-resistance and switching loss of the transistor, thereby improving the voltage conversion efficiency.

[0057] As Figure 1 shown in part (b) of , the three-phase buck structure includes transistor Q1C, transistor Q2C, transistor Q3C, transistor Q4C, flying capacitor CFC, inductor L, output capacitor Cout, and output resistor Rout. Among them, transistor Q1C, transistor Q2C, transistor Q3C, and transistor Q4C are connected in series between the voltage input terminal IN and the ground. The first plate of the flying capacitor CFC is connected to the connection point of transistor Q1C and transistor Q2C, and the second plate of the flying capacitor CFC is connected to the connection point of transistor Q3C and transistor Q4C. The connection point of transistor Q2C and transistor Q3C is connected to the voltage output terminal OUT, and the voltage output terminal OUT is grounded through the output capacitor Cout and the output resistor Rout in sequence.

[0058] The flying capacitor CFC can perform voltage equalization and clamping, so that the drain-source voltage of each transistor during normal operation is half of the input operating voltage. Therefore, low-voltage transistors can be selected as each transistor, which can reduce the on-resistance and switching loss of the transistor, thereby improving the voltage conversion efficiency.

[0059] Integrating the above three-phase buck power topology and two-phase charge pump power topology on the same silicon chip can form a fast charging power topology. During the high-current fast charging stage, charging is carried out based on the charge pump structure to improve the fast charging efficiency. During the dead battery and near-full charge stages of the battery, charging is carried out based on the three-level buck structure. This fast charging power topology can be used as a power converter for fast charging devices and is widely applied in consumer electronics fields such as mobile phones, tablets, and computers. However, since the fast charging power topology is composed of discrete two-phase charge pump power topology and three-phase buck power topology, it will occupy a large amount of chip area.

[0060] To solve the above technical problems, the present disclosure provides a hybrid power topology circuit, including a first voltage conversion circuit, a second voltage conversion circuit, and an equalization circuit. In the first aspect, when the hybrid power topology circuit operates in the charge pump mode, the first voltage conversion circuit converts the input voltage into a first output voltage in the first phase, and the second voltage conversion circuit converts the input voltage into a first output voltage in the second phase. When the hybrid power topology circuit operates in the buck mode, the first voltage conversion circuit converts the input voltage into a second output voltage. The charge pump power topology and the buck power topology share the first voltage conversion circuit. Compared with the discrete solution, it has a smaller number of devices, can reduce the area occupied by the circuit, and thus reduce the chip area.

[0061] In the second aspect, in the buck mode, the equalization circuit equalizes the first equalization node voltage of the first voltage conversion circuit and the second equalization node voltage of the second voltage conversion circuit. The second voltage conversion circuit can be used as the voltage equalization module of the first voltage conversion circuit without wirelessly setting additional voltage equalizing devices, which can further reduce the number of devices and the area occupied by the circuit, and thus reduce the chip area. At the same time, the voltage equalization of the first voltage conversion circuit does not change with the duty cycle of the driving signal and the switching frequency of the hybrid power topology circuit, which can improve the circuit stability.

[0062] In the third aspect, in the charge pump mode, the equalization circuit equalizes the first equalization node voltage of the first voltage conversion circuit and the second equalization node voltage of the second voltage conversion circuit, which can equalize the charge amounts on the first voltage conversion circuit and the second voltage conversion circuit to reduce the switching loss energy of the circuit, and thus improve the conversion efficiency of the circuit.

[0063] The following describes in detail the technical solutions provided by the present disclosure with several specific embodiments.

[0064] Figure 2 The structural schematic diagram of a hybrid power topology circuit provided by an embodiment of the present disclosure is as Figure 2As shown, the hybrid power topology circuit 100 includes a first voltage conversion circuit 110, a second voltage conversion circuit 120, and an equalization circuit 130. Among them, the first voltage conversion circuit 110 and the second voltage conversion circuit 120 are connected in parallel between the voltage input terminal IN and the ground. The output terminal of the first voltage conversion circuit 110 and the output terminal of the second voltage conversion circuit 120 are connected to the voltage output terminal OUT. The equalization circuit 130 is connected to the first equalization node of the first voltage conversion circuit 110 and the second equalization node of the second voltage conversion circuit 120.

[0065] The first voltage conversion circuit 110 is configured to convert the input voltage Vin into a first output voltage Vout1 in the first phase when the hybrid power topology circuit 100 operates in the charge pump mode, and convert the input voltage Vin into a second output voltage Vout2 when the hybrid power topology circuit 100 operates in the buck mode. The second voltage conversion circuit 120 is configured to convert the input voltage Vin into the first output voltage Vout1 in the second phase when the hybrid power topology circuit 100 operates in the charge pump mode. The hybrid power topology circuit 100 in the charge pump mode switches between the first phase and the second phase. The equalization circuit 130 is configured to equalize the first equalization node voltage and the second equalization node voltage.

[0066] Exemplarily, Figure 3 is a circuit schematic diagram of a hybrid power topology circuit provided by an embodiment of the present disclosure. As Figure 3 shown, the first equalization node includes a first high-level equalization node CTOP1 and a first low-level equalization node CBOT1. The first voltage conversion circuit 110 includes a mode switching circuit 111, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, and a first flying capacitor CFLY1. The control terminal of the first transistor Q1 receives a first driving signal Vdrv1, the control terminal of the second transistor Q2 receives a second driving signal Vdrv2, the control terminal of the third transistor Q3 receives a third driving signal Vdrv3, and the control terminal of the fourth transistor Q4 receives a fourth driving signal Vdrv4.

[0067] The first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are connected in series between the voltage input terminal IN and the ground. The connection point of the first transistor Q1 and the second transistor Q2 is the first high-level equalization node CTOP1. The connection point of the second transistor Q2 and the third transistor Q3 is the switching node SW. The switching node SW is connected to the voltage output terminal OUT through the mode switching circuit 111. The connection point of the third transistor Q3 and the fourth transistor Q4 is the first low-level equalization node CBOT1. The first flying capacitor CFLY1 is connected across the first high-level equalization node CTOP1 and the first low-level equalization node CBOT1. The control terminal of the mode switching circuit 111 receives a mode switching signal.

[0068] Among them, the mode switching signal includes a charge pump mode switching signal and a buck mode switching signal. For example, the charge pump mode switching signal is a high-level signal, and the buck mode switching signal is a low-level signal, or the charge pump mode switching signal is a low-level signal, and the buck mode switching signal is a high-level signal.

[0069] Specifically, the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are all N-type metal oxide semiconductor field effect transistors (N-MOSFETs). The gate of the first transistor Q1 receives the first driving signal Vdrv1, the gate of the second transistor Q2 receives the second driving signal Vdrv2, the gate of the third transistor Q3 receives the third driving signal Vdrv3, and the gate of the fourth transistor Q4 receives the fourth driving signal Vdrv4.

[0070] The drain of the first transistor Q1 is connected to the voltage input terminal IN. The source of the first transistor Q1 is connected to the drain of the second transistor Q2 and the first plate of the first flying capacitor CFLY1 through the first high-level equalization node CTOP1. The source of the second transistor Q2 is connected to the mode switching circuit 111 and the drain of the third transistor Q3 through the switch node SW. The source of the third transistor Q3 is connected to the drain of the fourth transistor Q4 and the second plate of the first flying capacitor CFLY1 through the first low-level equalization node CBOT1. The source of the fourth transistor Q4 is grounded.

[0071] Continue to refer to Figure 3 , the second equalization node includes a second high-level equalization node CTOP2 and a second low-level equalization node CBOT2. The second voltage conversion circuit 120 includes a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, and a second flying capacitor CFLY2. The control terminal of the fifth transistor Q5 receives the fifth driving signal Vdrv5, the control terminal of the sixth transistor Q6 receives the sixth driving signal Vdrv6, the control terminal of the seventh transistor Q7 receives the seventh driving signal Vdrv7, and the control terminal of the eighth transistor Q8 receives the eighth driving signal Vdrv8.

[0072] The fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, and the eighth transistor Q8 are connected in series between the voltage input terminal IN and the ground. The connection point of the fifth transistor Q5 and the sixth transistor Q6 is the second high-level equalization node CTOP2. The connection point of the sixth transistor Q6 and the seventh transistor Q7 is connected to the voltage output terminal OUT. The connection point of the seventh transistor Q7 and the eighth transistor Q8 is the second low-level equalization node CBOT2. The second flying capacitor CFLY2 is connected across the second high-level equalization node CTOP2 and the second low-level equalization node CBOT2.

[0073] Specifically, the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, and the eighth transistor Q8 are all NMOS transistors. The gate of the fifth transistor Q5 receives the fifth driving signal Vdrv5. The gate of the sixth transistor Q6 receives the sixth driving signal Vdrv6. The gate of the seventh transistor Q7 receives the seventh driving signal Vdrv7. The gate of the eighth transistor Q8 receives the eighth driving signal Vdrv8.

[0074] The drain of the fifth transistor Q5 is connected to the voltage input terminal IN. The source of the fifth transistor Q5 is connected to the drain of the sixth transistor Q6 and the first plate of the second flying capacitor CFLY2 through the second high-level equalization node CTOP2. The source of the sixth transistor Q6 and the drain of the seventh transistor Q7 are connected to the voltage output terminal OUT. The source of the seventh transistor Q7 is connected to the drain of the eighth transistor Q8 and the second plate of the second flying capacitor CFLY2 through the second low-level equalization node CBOT2. The source of the eighth transistor Q8 is grounded.

[0075] When the mode switching signal is the charge pump mode switching signal, the mode switching circuit 111 shorts the voltage output terminal OUT and the switch node SW according to the charge pump mode switching signal, so that the hybrid power topology circuit 100 operates in the charge pump mode, as Figure 4 shown, Figure 4 is the circuit schematic diagram of the hybrid power topology circuit in the charge pump mode provided by the embodiment of the present disclosure. At this time, the first driving signal Vdrv1 is multiplexed as the third driving signal Vdrv3, the sixth driving signal Vdrv6, and the eighth driving signal Vdrv8. The second driving signal Vdrv2 is multiplexed as the fourth driving signal VQ4, the fifth driving signal Vdrv5, and the seventh driving signal Vdrv7.

[0076] When the first driving signal VQ1 is a conduction signal and the second driving signal VQ2 is a cut-off signal, the first transistor Q1, the third transistor Q3, the sixth transistor Q6, and the eighth transistor Q8 are in the conduction state, the second transistor Q2, the fourth transistor Q4, the fifth transistor Q5, and the seventh transistor Q7 are in the cut-off state, the first flying capacitor CFLY1 is in the charging state, the second flying capacitor CFLY2 is in the discharging state, and the hybrid power topology circuit 100 operates in the second phase.

[0077] When the first driving signal VQ1 is a cut-off signal and the second driving signal VQ2 is a conduction signal, the first transistor Q1, the third transistor Q3, the sixth transistor Q6, and the eighth transistor Q8 are in the cut-off state, the second transistor Q2, the fourth transistor Q4, the fifth transistor Q5, and the seventh transistor Q7 are in the conduction state, the first flying capacitor CFLY1 is in the discharging state, the second flying capacitor CFLY2 is in the charging state, and the hybrid power topology circuit 100 operates in the first phase.

[0078] In this way, the hybrid power topology circuit 100 in the charge pump mode switches between the first phase and the second phase to continuously reduce the input voltage Vin to the first output voltage Vout1 and output it.

[0079] When the mode switching signal is a buck mode switching signal, the mode switching circuit 111 connects the inductor L in the mode switching circuit 111 between the voltage output terminal OUT and the switch node SW according to the buck mode switching signal, so that the hybrid power topology circuit 100 operates in the buck mode, as Figure 5 shown Figure 5 is a circuit schematic diagram of the hybrid power topology circuit in the buck mode provided by the embodiment of the present disclosure. At this time, the fifth driving signal Vdrv5, the sixth driving signal Vdrv6, and the seventh driving signal Vdrv7 are constantly cut-off signals, the eighth driving signal Vdrv8 is constantly a conduction signal, the fourth driving signal Idrv4 is an inverted phase signal of the first driving signal Vdrv1, the third driving signal Idrv3 is an inverted phase signal of the second driving signal Vdrv2, the fifth transistor Q5, the sixth transistor Q6, and the seventh transistor Q7 are constantly in the cut-off state, and the eighth transistor Q8 is constantly in the conduction state.

[0080] When the first driving signal Vdrv1 is a conduction signal, the fourth driving signal Vdrv4 is a cut-off signal, the first transistor Q1 is in the conduction state, the fourth transistor Q4 is in the cut-off state, the first flying capacitor CFLY1 and the second flying capacitor CFLY2 are in series, and the hybrid power topology circuit 100 operates in the fourth phase. When the first driving signal Vdrv1 is a cut-off signal, the fourth driving signal Vdrv4 is a conduction signal, the first transistor Q1 is in the cut-off state, the fourth transistor Q4 is in the conduction state, the first flying capacitor CFLY1 and the second flying capacitor CFLY2 are in parallel, and the hybrid power topology circuit 100 operates in the third phase.

[0081] Among them, the hybrid power topology circuit 100 in the buck mode switches between the third phase and the fourth phase to continuously reduce the input voltage Vin to the second output voltage Vout2 and output it.

[0082] When the duty cycle D of the buck mode driving signal is greater than 0.5, that is, the duty cycles of the first driving signal Vdrv1, the second driving signal Vdrv2, the third driving signal Vdrv3, and the fourth driving signal Vdrv4 are all greater than 0.5, the fourth phase includes a second sub-phase and two first sub-phases, and the second sub-phase is located between the two first sub-phases, as Figure 6 shown in part (a) of Figure 6 which is the timing diagram of the hybrid power topology circuit in the buck mode provided by the embodiments of the present disclosure.

[0083] When the first transistor Q1 is in the conduction state, when the second driving signal Vdrv2 is a conduction signal, the third driving signal Vdrv3 is a cut-off signal, the second transistor Q2 is in the conduction state, the third transistor Q3 and the fourth transistor Q4 are in the cut-off state, and the hybrid power topology circuit 100 operates in the first sub-phase. At this time, the input voltage Vin magnetizes the inductor L, the inductor current IL increases, and both the first flying capacitor CFLY1 and the second flying capacitor CFLY2 are in the charging state.

[0084] When the third driving signal Vdrv3 is a conduction signal, the second driving signal Vdrv2 is a cut-off signal, the third transistor Q3 is in the conduction state, the second transistor Q2 and the fourth transistor Q4 are in the cut-off state, and the hybrid power topology circuit 100 operates in the second sub-phase. At this time, the input voltage Vin demagnetizes the inductor L through the first flying capacitor CFLY1, the inductor current IL decreases, and the second flying capacitor CFLY2 remains in the charging state.

[0085] When the fourth transistor Q4 is in the on state, the second drive signal Vdrv2 is an on signal, the third drive signal Vdrv3 is an off signal, the second transistor Q2 is in the on state, the third transistor Q3 is in the off state, and the hybrid power topology circuit 100 operates in the third phase. At this time, the ground demagnetizes the inductor L through the first flying capacitor CFLY1, the inductor current IL decreases, and the second flying capacitor CFLY is in the discharging state.

[0086] As Figure 6 shown in part (b) of [], when the duty cycle D of the buck mode drive signal is not greater than 0.5, that is, the duty cycles of the first drive signal Vdrv1, the second drive signal Vdrv2, the third drive signal Vdrv3, and the fourth drive signal Vdrv4 are all not greater than 0.5, the third phase includes a fourth sub-phase and two third sub-phases, and the fourth sub-phase is located between the two third sub-phases.

[0087] When the first transistor Q1 is in the on state, the third drive signal Vdrv3 is an on signal, the second drive signal Vdrv2 is an off signal, the third transistor Q3 is in the on state, the second transistor Q2 and the fourth transistor Q4 are in the off state, and the hybrid power topology circuit 100 operates in the fourth phase. At this time, the input voltage Vin magnetizes the inductor L through the first flying capacitor CFLY1, the inductor current IL increases, and both the first flying capacitor CFLY1 and the second flying capacitor CFLY2 are in the charging state.

[0088] When the fourth transistor Q4 is in the on state, when the third drive signal Vdrv3 is an on signal, the second drive signal Vdrv2 is an off signal, the third transistor Q3 is in the on state, the first transistor Q1 and the second transistor Q2 are in the off state, and the hybrid power topology circuit 100 operates in the third sub-phase. At this time, the ground demagnetizes the inductor L through the first flying capacitor CFLY1, the inductor current IL decreases, and the first flying capacitor CFLY1 is in the discharging state.

[0089] When the second drive signal Vdrv2 is an on signal, the third drive signal Vdrv3 is an off signal, the second transistor Q2 is in the on state, the first transistor Q1 and the third transistor Q3 are in the off state, and the hybrid power topology circuit 100 operates in the fourth sub-phase. At this time, the ground magnetizes the inductor L through the first flying capacitor CFLY1, the inductor current IL rises, and the first flying capacitor CFLY1 and the second flying capacitor CFLY are in the discharging state.

[0090] Thus, in each working cycle of the buck mode, when the duty cycle of the buck mode driving signal is greater than 0.5, the hybrid power topology circuit 100 switches according to the phase sequence of the first sub-phase - the second sub-phase - the first sub-phase - the third phase. When the duty cycle of the buck mode driving signal is not greater than 0.5, the hybrid power topology circuit 100 switches according to the phase sequence of the fourth phase - the third sub-phase - the fourth sub-phase - and the third sub-phase.

[0091] In summary, the first voltage conversion circuit 110 can not only achieve voltage conversion in the buck mode, but also cooperate with the second voltage conversion circuit 120 to achieve voltage conversion in the charge pump mode. That is to say, the first voltage conversion circuit 110 shared by the two-phase charge pump power topology and the three-level buck power topology has a smaller number of devices compared with the discrete solution, which can reduce the area occupied by the circuit and thus reduce the chip area.

[0092] Exemplarily, continue to refer to Figure 3 , the equalization circuit 130 includes a first equalization circuit 131 and a second equalization circuit 132. The first equalization circuit 131 is connected to the first high-level equalization node CTOP1 and the second high-level equalization node CTOP2. The second equalization circuit 132 is connected to the first low-level equalization node CBOT1 and the second high-level equalization node CTOP2. The control end of the first equalization circuit 131 receives the first equalization driving signal Vbal1, and the control end of the second equalization circuit 132 receives the second equalization driving signal Vbal2.

[0093] When the hybrid power topology circuit 100 operates in the buck mode, the fourth driving signal Vdrv4 is multiplexed as the first equalization driving signal Vbal1, and the first driving signal Vdrv1 is multiplexed as the second equalization driving signal Vbal2. In the fourth phase, as Figure 6 shown, the fourth driving signal Vdrv4 is a cut-off signal, and the first driving signal Vdrv1 is a conduction signal. Then the first equalization driving signal Vbal1 is a cut-off signal, and the second equalization driving signal Vbal2 is a conduction signal. The second equalization circuit 132 can conduct the first low-level equalization node CBOT1 and the second high-level equalization node CTOP2 to equalize the voltage of the first low-level equalization node VCBOT1 and the voltage of the second high-level equalization node VCTOP2. After equalization, VCBOT1 = VCTOP2 = 0.5 * Vin.

[0094] Since the first flying capacitor CFLY1 and the second flying capacitor CFLY2 are connected in series, after voltage equalization, the voltage of the second flying capacitor VCFLY2 = VCTOP2 - VCBOT2 = 0.5 * Vin, and the voltage of the first flying capacitor VCFLY1 = VCTOP1 - VCBOT1 = Vin - 0.5 * Vin = 0.5 * Vin, where VCTOP1 is the voltage of the first high - level equalization node.

[0095] As Figure 6 shown, in the third phase, the fourth drive signal Vdrv4 is a conduction signal, and the first drive signal Vdrv1 is a cut - off signal. Then the first equalization drive signal Vbal1 is a conduction signal, and the second equalization drive signal Vbal2 is a cut - off signal. The first equalization circuit 131 can conduct the first high - level equalization node CTOP1 and the second high - level equalization node CTOP2 to equalize the voltage of the first high - level equalization node VCTOP1 and the voltage of the second high - level equalization node VCTOP2. After voltage equalization, VCTOP1 = VCTOP2 = 0.5 * Vin.

[0096] Since the first flying capacitor CFLY1 and the second flying capacitor CFLY2 are connected in parallel, after voltage equalization, the voltage of the first flying capacitor VCFLY1 = VCTOP1 - VCBOT1 = 0.5 * Vin, and the voltage of the second flying capacitor VCFLY2 = VCTOP2 - VCBOT2 = 0.5 * Vin.

[0097] In this way, the second flying capacitor CFLY2 can equalize the voltage of the first flying capacitor CFLY1 without setting an additional voltage - equalizing capacitor, which can reduce the number of devices in the circuit, reduce the area occupied by the circuit, and thus reduce the chip area. In addition, the voltage equalization of the first flying capacitor CFLY1 does not change with the duty cycle of the buck - mode drive signal and the switching frequency of the hybrid power topology circuit 100, which can improve the circuit stability.

[0098] When the hybrid power topology circuit 100 operates in the charge - pump mode, the second equalization drive signal Vbal2 is always a cut - off signal. There is a dead - zone period between the adjacent first phase and the second phase where both the first drive signal Vdrv1 and the second drive signal Vdrv2 are cut - off signals. The duration of the dead - zone period is the dead - zone time. The first equalization drive signal Vbal1 is a conduction signal during the dead - zone time, and the first equalization drive signal Vbal1 in the first phase and the second phase is a cut - off signal. As Figure 7 shown, Figure 7 This is the timing diagram of the hybrid power topology circuit in the charge - pump mode provided by the present disclosure.

[0099] In the first phase, the first equalization drive signal Vbal1 is a cut-off signal. The first transistor Q1 and the third transistor Q3 are in the cut-off state. The second transistor Q2 and the fourth transistor Q4 are in the conducting state. The first flying capacitor CFLY1 is in the discharging state. VCTOP1 = Vout1, and VCBOT1 = 0. At the same time, the fifth transistor Q5 and the seventh transistor Q7 are in the conducting state. The sixth transistor Q6 and the eighth transistor Q8 are in the cut-off state. The second flying capacitor CFLY2 is in the charging state. VCTOP2 = 2*Vout1, and VCBOT2 = Vout1.

[0100] Entering the dead time, the first equalization drive signal Vbal1 is a conducting signal. The first equalization drive signal Vbal1 can conduct the first high-level equalization node CTOP1 and the second high-level equalization node CTOP2. The charges on the drain-source parasitic capacitances of the transistors in the second voltage conversion circuit 120 can flow into the first voltage conversion circuit 110 to equalize the first high-level equalization node voltage VCTOP1 and the second high-level equalization node voltage VCTOP2. After equalization, VCTOP1 = VCTOP2 = 1.5*Vout1, and VCBOT1 = VCBOT2 = 0.5*Vout1, which can reduce the switching losses of the transistors in the second voltage conversion circuit 120.

[0101] Subsequently entering the second phase, the first equalization drive signal Vbal1 is a cut-off signal. The first transistor Q1 and the third transistor Q3 are in the conducting state. The second transistor Q2 and the fourth transistor Q4 are in the cut-off state. The first flying capacitor CFLY1 is in the charging state. VCTOP1 = 2Vout1, and VCBOT1 = Vout1. At the same time, the fifth transistor Q5 and the seventh transistor Q7 are in the cut-off state. The sixth transistor Q6 and the eighth transistor Q8 are in the conducting state. The second flying capacitor CFLY2 is in the discharging state. VCTOP2 = Vout1, and VCBOT2 = 0.

[0102] Entering the dead time again, the first equalization drive signal Vbal1 is a conducting signal. The first equalization drive signal Vbal1 can conduct the first high-level equalization node CTOP1 and the second high-level equalization node CTOP2. The charges on the drain-source parasitic capacitances of the transistors in the first voltage conversion circuit 110 can flow into the second voltage conversion circuit 120 to equalize the first high-level equalization node voltage VCTOP1 and the second high-level equalization node voltage VCTOP2. After equalization, VCTOP1 = VCTOP2 = 1.5*Vout1, and VCBOT1 = VCBOT2 = 0.5*Vout1, which can reduce the switching losses of the transistors in the first voltage conversion circuit 110.

[0103] Thus, when the hybrid power topology circuit operates in the buck mode, the first balancing circuit 131 balances the first high-level balancing node voltage VCTOP1 and the second high-level balancing node voltage VCTOP2 in the third phase, and the second balancing circuit 132 balances the first low-level balancing node voltage VCBOT1 and the second high-level balancing node voltage VCTOP2 in the fourth phase. Without setting additional voltage equalizing devices, the number of devices in the circuit can be reduced, the area occupied by the circuit can be decreased, and thus the chip area can be reduced. In addition, the voltage equalization does not change with the duty cycle of the driving signal and the switching frequency of the hybrid power topology circuit 100, which can improve the circuit stability.

[0104] When the hybrid power topology circuit operates in the charge pump mode, the first balancing circuit 131 balances the first high-level balancing node voltage VCTOP1 and the second high-level balancing node voltage VCTOP2 during the dead time between the adjacent first phase and the second phase, which can reduce the amount of charge on the first voltage conversion circuit 110 and the second voltage conversion circuit 120, so as to reduce the switching loss energy of the circuit, and thus improve the conversion efficiency of the circuit.

[0105] In some embodiments, continue to refer to Figure 3 , the first balancing circuit 131 includes a first balancing transistor M1 and a second balancing transistor M2. The first end of the first balancing transistor M1 is connected to the first end of the second balancing transistor M2, the control end of the first balancing transistor M1 is connected to the control end of the second balancing transistor M2, the second end of the first balancing transistor M1 is connected to the first high-level balancing node CTOP1, and the second end of the second balancing transistor M2 is connected to the second high-level balancing node CTOP2.

[0106] Exemplarily, as Figure 3 shown, the first balancing transistor M1 and the second balancing transistor M2 are NMOS. The source of the first balancing transistor M1 is connected to the source of the second balancing transistor M2. The gates of the first balancing transistor M1 and the second balancing transistor M2 receive the first balancing driving signal Vbal1. The drain of the first balancing transistor M1 is connected to the first high-level balancing node CTOP1, and the drain of the second balancing transistor M2 is connected to the second high-level balancing node CTOP2.

[0107] During the dead time of the charge pump mode, the first balancing driving signal Vbal1 is a conduction signal, and the first balancing transistor M1 and the second balancing transistor M2 are in the conduction state. The first balancing transistor M1 can conduct the first high-level balancing node CTOP1 and the source of the second balancing transistor M2, and the second balancing transistor M2 can conduct the source of the second balancing transistor M2 and the second high-level balancing node CTOP2, so as to conduct the first high-level balancing node CTOP1 and the second high-level balancing node CTOP2, enabling the charge on the voltage conversion circuit with more charge in the first voltage conversion circuit 110 and the second voltage conversion circuit 120 to flow to the other voltage conversion circuit, thus achieving the purpose of voltage equalization.

[0108] In the first phase and the second phase of the charge pump mode, the first equalization driving signal Vbal1 is a cut-off signal, the first equalization transistor M1 and the second equalization transistor M2 are in the cut-off state. The first equalization transistor M1 can disconnect the connection between the first high-level equalization node CTOP1 and the source of the second equalization transistor M2, and the second equalization transistor M2 can disconnect the connection between the source of the second equalization transistor M2 and the second high-level equalization node CTOP2, thereby disconnecting the connection between the first high-level equalization node CTOP1 and the second high-level equalization node CTOP2.

[0109] In the third phase of the buck mode, the first driving signal Vdrv1 is a conduction signal, the first equalization transistor M1 and the second equalization transistor M2 are in the conduction state. The first equalization transistor M1 can conduct the connection between the first high-level equalization node CTOP1 and the source of the second equalization transistor M2, and the second equalization transistor M2 can conduct the connection between the source of the second equalization transistor M2 and the second high-level equalization node CTOP2, thereby conducting the connection between the first high-level equalization node CTOP1 and the second high-level equalization node CTOP2, so that the second flying capacitor CFLY2 discharges and equalizes the voltage of the first flying capacitor CFLY1.

[0110] In the fourth phase of the buck mode, the first equalization driving signal Vbal1 is a cut-off signal, the first equalization transistor M1 and the second equalization transistor M2 are in the cut-off state. The first equalization transistor M1 can disconnect the connection between the first high-level equalization node CTOP1 and the source of the second equalization transistor M2, and the second equalization transistor M2 can disconnect the connection between the source of the second equalization transistor M2 and the second high-level equalization node CTOP2, thereby disconnecting the connection between the first high-level equalization node CTOP1 and the second high-level equalization node CTOP2.

[0111] In some embodiments, referring further to Figure 3 , the second equalization circuit 132 includes a third equalization transistor M3 and a fourth equalization transistor M4. The first end of the third equalization transistor M3 is connected to the first end of the fourth equalization transistor M4, the control end of the third equalization transistor M3 is connected to the control end of the fourth equalization transistor M4, the second end of the third equalization transistor M3 is connected to the first low-level equalization node CBOT1, and the second end of the fourth equalization transistor M4 is connected to the second high-level equalization node CTOP2.

[0112] Exemplarily, as Figure 3 shown, the third equalization transistor M3 and the fourth equalization transistor M4 are NMOS. The source of the third equalization transistor M3 is connected to the source of the fourth equalization transistor M4, the gates of the third equalization transistor M3 and the fourth equalization transistor M4 are connected to the second equalization driving signal Vbal2, the drain of the third equalization transistor M3 is connected to the first low-level equalization node CBOT1, and the drain of the fourth equalization transistor M4 is connected to the second high-level equalization node CTOP2.

[0113] In the charge pump mode, the second equalization drive signal Vbal2 is constantly a cut-off signal, the third equalization transistor M3 and the fourth equalization transistor M4 maintain the cut-off state, the third equalization transistor M3 can continuously disconnect the connection between the first low equalization node CBOT1 and the source of the fourth equalization transistor M4, and the fourth equalization transistor M4 can continuously disconnect the connection between the source of the fourth equalization transistor M4 and the second high equalization node CTOP2, so that the connection between the first low equalization node CBOT1 and the second high equalization node CTOP2 can be continuously disconnected.

[0114] In the third phase of the buck mode, the second equalization drive signal Vbal2 is a cut-off signal, the third equalization transistor M3 and the fourth equalization transistor M4 are in the cut-off state, the third equalization transistor M3 can disconnect the connection between the first low equalization node CBOT1 and the source of the fourth equalization transistor M4, and the fourth equalization transistor M4 can disconnect the connection between the source of the fourth equalization transistor M4 and the second high equalization node CTOP2, so that the connection between the first low equalization node CBOT1 and the second high equalization node CTOP2 can be disconnected.

[0115] In the fourth phase of the buck mode, the second equalization drive signal Vbal2 is a conduction signal, the third equalization transistor M3 and the fourth equalization transistor M4 are in the conduction state, the third equalization transistor M3 conducts the first low equalization node CBOT1 and the source of the fourth equalization transistor M4, and the fourth equalization transistor M4 can conduct the source of the fourth equalization transistor M4 and the second high equalization node CTOP2, so that the first low equalization node CBOT1 and the second high equalization node CTOP2 can be conducted, so that the second flying capacitor CFLY2 charges and equalizes the first flying capacitor voltage CFLY1.

[0116] In some embodiments, continue to refer to Figure 3 , the mode switching circuit 111 includes an inductor L and a switch component 1111, and the inductor L and the switch component 1111 are connected in parallel between the voltage output terminal OUT and the switch node SW.

[0117] Exemplarily, as Figure 3 shown, the switch component 1111 includes a first switch transistor K1 and a second switch transistor K2. The first end of the first switch transistor K1 is connected to the first end of the second switch transistor K2, the control end of the first switch transistor K1 is connected to the control end of the second switch transistor K2, the second end of the first switch transistor K1 is connected to the switch node SW, and the second end of the second switch transistor K2 is connected to the voltage output terminal OUT.

[0118] Specifically, as Figure 3As shown, the first switching transistor K1 and the second switching transistor K2 are NMOS. The source of the first switching transistor K1 is connected to the source of the second switching transistor K2. The gates of the first switching transistor K1 and the second switching transistor K2 are connected to a mode switching signal. The drain of the first switching transistor K1 is connected to a switching node SW, and the drain of the second switching transistor K2 is connected to a voltage output terminal OUT.

[0119] In the charge pump mode, the mode switching signal is a charge pump mode switching signal. The first switching transistor K1 and the second switching transistor K2 are in the conducting state. The first switching transistor K1 can conduct the switching node SW and the source of the second switching transistor K2, and the second switching transistor K2 can conduct the voltage output terminal OUT and the source of the second switching transistor K2. Then, the switching assembly 1111 can, according to the charge pump mode switching signal, conduct the voltage output terminal OUT and the switching node SW to short - circuit the inductor L, so that the voltage output terminal OUT and the switching node SW are short - circuited.

[0120] In the buck mode, the mode switching signal is a buck mode switching signal. The first switching transistor K1 and the second switching transistor K2 are in the cut - off state. The first switching transistor K1 can disconnect the connection between the switching node SW and the source of the second switching transistor K2, and the second switching transistor K2 can disconnect the connection between the voltage output terminal OUT and the source of the second switching transistor K2. Then, the switching assembly 1111 can, according to the buck mode switching signal, disconnect the connection between the voltage output terminal OUT and the switching node SW to connect the inductor L, so that the voltage output terminal OUT is connected to the switching node SW through the inductor L.

[0121] The present disclosure also provides a voltage conversion method, which applies the hybrid power topology circuit 100 provided in any of the above embodiments.

[0122] Figure 8 It is a schematic flowchart of a voltage conversion method provided by an embodiment of the present disclosure. As Figure 8 shown, the specific steps of the voltage conversion method include:

[0123] S101, when the hybrid power topology circuit operates in the charge pump mode, convert the input voltage into a first output voltage in the first phase and the second phase.

[0124] Exemplarily, the hybrid power topology circuit can receive a mode switching signal, where the mode switching signal includes a charge pump mode switching signal and a buck mode switching signal, and switch the operating mode according to the mode switching signal.

[0125] When the mode switching signal is a charge pump mode switching signal, the mode switching circuit shorts the voltage output terminal OUT and the switching node SW to make the hybrid power topology circuit operate in the charge pump mode. As Figure 4As shown. At this time, the first driving signal Vdrv1 is multiplexed as the third driving signal Vdrv3, the sixth driving signal Vdrv6, and the eighth driving signal Vdrv8, and the second driving signal Vdrv2 is multiplexed as the fourth driving signal VQ4, the fifth driving signal Vdrv5, and the seventh driving signal Vdrv7.

[0126] When the mode switching signal is a buck mode switching signal, the mode switching circuit connects an inductor L between the voltage output terminal OUT and the switch node SW, so that the hybrid power topology circuit operates in the buck mode, as Figure 5 shown. At this time, the fifth driving signal Vdrv5, the sixth driving signal Vdrv6, and the seventh driving signal Vdrv7 are constantly cutoff signals, the eighth driving signal Vdrv8 is constantly a conducting signal, the fourth driving signal Idrv4 is an inverted phase signal of the first driving signal Vdrv1, the third driving signal Idrv3 is an inverted phase signal of the second driving signal Vdrv2, the fifth transistor Q5, the sixth transistor Q6, and the seventh transistor Q7 are constantly in a cutoff state, and the eighth transistor Q8 is constantly in a conducting state.

[0127] The hybrid power topology circuit in the charge pump mode switches between the first phase and the second phase. When the first driving signal VQ1 is a conducting signal and the second driving signal VQ2 is a cutoff signal, the first transistor Q1, the third transistor Q3, the sixth transistor Q6, and the eighth transistor Q8 are in a conducting state, the second transistor Q2, the fourth transistor Q4, the fifth transistor Q5, and the seventh transistor Q7 are in a cutoff state, the first flying capacitor CFLY1 is in a charging state, the second flying capacitor CFLY2 is in a discharging state, the hybrid power topology circuit operates in the second phase, and the second voltage conversion circuit operates. At this time, the second voltage conversion circuit can convert the input voltage into the first output voltage.

[0128] When the first driving signal VQ1 is a cutoff signal and the second driving signal VQ2 is a conducting signal, the first transistor Q1, the third transistor Q3, the sixth transistor Q6, and the eighth transistor Q8 are in a cutoff state, the second transistor Q2, the fourth transistor Q4, the fifth transistor Q5, and the seventh transistor Q7 are in a conducting state, the first flying capacitor CFLY1 is in a discharging state, the second flying capacitor CFLY2 is in a charging state, the hybrid power topology circuit operates in the first phase, and the first voltage conversion circuit operates. At this time, the first voltage conversion circuit can convert the input voltage into the first output voltage.

[0129] In this way, by switching the hybrid power topology circuit in the charge pump mode between the first phase and the second phase, the input voltage can be continuously reduced to the first output voltage and output.

[0130] S101’, when the hybrid power topology circuit operates in the buck mode, convert the input voltage into a second output voltage.

[0131] Exemplarily, the hybrid power topology circuit in the buck mode switches between the third phase and the fourth phase. When the first driving signal Vdrv1 is a conduction signal, the fourth driving signal Vdrv4 is a cut-off signal, the first transistor Q1 is in the conduction state, the fourth transistor Q4 is in the cut-off state, the first flying capacitor CFLY1 and the second flying capacitor CFLY2 are in series, and the hybrid power topology circuit operates in the fourth phase.

[0132] When the first driving signal Vdrv1 is a cut-off signal, the fourth driving signal Vdrv4 is a conduction signal, the first transistor Q1 is in the cut-off state, the fourth transistor Q4 is in the conduction state, the first flying capacitor CFLY1 and the second flying capacitor CFLY2 are in parallel, and the hybrid power topology circuit operates in the third phase.

[0133] In this way, by switching the hybrid power topology circuit in the charge pump mode between the third phase and the fourth phase, the input voltage can be continuously reduced to the second output voltage and output.

[0134] S102, balance the first equalization node voltage and the second equalization node voltage.

[0135] Exemplarily, in the third phase, the equalization circuit conducts the first high-level equalization node CTOP1 and the second high-level equalization node CTOP2 to balance the first high-level equalization node voltage VCTOP1 and the second high-level equalization node voltage VCTOP2. After equalizing the voltage, VCTOP1 = VCTOP2 = 0.5 * Vin. Since the first flying capacitor CFLY1 and the second flying capacitor CFLY2 are in parallel, after equalizing the voltage, the first flying capacitor voltage VCFLY1 = VCTOP1 - VCBOT1 = 0.5 * Vin, and the second flying capacitor voltage VCFLY2 = VCTOP2 - VCBOT2 = 0.5 * Vin.

[0136] In the fourth phase, the equalization circuit conducts the first low-level equalization node CBOT1 and the second high-level equalization node CTOP2 to balance the first low-level equalization node voltage VCBOT1 and the second high-level equalization node voltage VCTOP2. After equalizing the voltage, VCBOT1 = VCTOP2 = 0.5 * Vin. Since the first flying capacitor CFLY1 and the second flying capacitor CFLY2 are in series, after equalizing the voltage, the second flying capacitor voltage VCFLY2 = VCTOP2 - VCBOT2 = 0.5 * Vin, and the first flying capacitor voltage VCFLY1 = VCTOP1 - VCBOT1 = Vin - 0.5 * Vin = 0.5 * Vin.

[0137] Thus, when the hybrid power topology circuit operates in the buck mode, the equalization circuit equalizes the first high-level equalization node voltage VCTOP1 and the second high-level equalization node voltage VCTOP2 in the third phase, and equalizes the first low-level equalization node voltage VCBOT1 and the second high-level equalization node voltage VCTOP2 in the fourth phase.

[0138] In the first phase, the first transistor Q1 and the third transistor Q3 are in the cut-off state, the second transistor Q2 and the fourth transistor Q4 are in the conduction state, the first flying capacitor CFLY1 is in the discharge state, VCTOP1 = Vout1, and VCBOT1 = 0. At the same time, the fifth transistor Q5 and the seventh transistor Q7 are in the conduction state, the sixth transistor Q6 and the eighth transistor Q8 are in the cut-off state, the second flying capacitor CFLY2 is in the charging state, VCTOP2 = 2 * Vout1, and VCBOT2 = Vout1.

[0139] Entering the dead time, the first high-level equalization node CTOP1 and the second high-level equalization node CTOP2 can be conducted, and the charges on the drain-source parasitic capacitors of the transistors in the second voltage conversion circuit can flow into the first voltage conversion circuit to equalize the first high-level equalization node voltage VCTOP1 and the second high-level equalization node voltage VCTOP2. After equalization, VCTOP1 = VCTOP2 = 1.5 * Vout1, and VCBOT1 = VCBOT2 = 0.5 * Vout1, which can reduce the switching losses of the transistors in the second voltage conversion circuit.

[0140] Subsequently, entering the second phase, the first transistor Q1 and the third transistor Q3 are in the conduction state, the second transistor Q2 and the fourth transistor Q4 are in the cut-off state, the first flying capacitor CFLY1 is in the charging state, VCTOP1 = 2Vout1, and VCBOT1 = Vout1. At the same time, the fifth transistor Q5 and the seventh transistor Q7 are in the cut-off state, the sixth transistor Q6 and the eighth transistor Q8 are in the conduction state, the second flying capacitor CFLY2 is in the discharge state, VCTOP2 = Vout1, and VCBOT2 = 0.

[0141] Entering the dead time again, the first high-level equalization node CTOP1 and the second high-level equalization node CTOP2 can be conducted, and the charges on the drain-source parasitic capacitors of the transistors in the first voltage conversion circuit can flow into the second voltage conversion circuit to equalize the first high-level equalization node voltage VCTOP1 and the second high-level equalization node voltage VCTOP2. After equalization, VCTOP1 = VCTOP2 = 1.5 * Vout1, and VCBOT1 = VCBOT2 = 0.5 * Vout1, which can reduce the switching losses of the transistors in the first voltage conversion circuit.

[0142] Thus, when the hybrid power topology circuit operates in the charge pump mode, the equalization circuit equalizes the first high-level equalization node voltage VCTOP1 and the second high-level equalization node voltage VCTOP2 during the dead time between adjacent first and second phases, which can reduce the amount of charge on the first voltage conversion circuit and the second voltage conversion circuit, thereby reducing the switching loss energy of the circuit and improving the conversion efficiency of the circuit.

[0143] In the embodiments of the present disclosure, when the hybrid power topology circuit operates in the charge pump mode, the input voltage is converted into a first output voltage in the first and second phases. The hybrid power topology circuit in the charge pump mode switches between the first and second phases. When the hybrid power topology circuit operates in the buck mode, the input voltage is converted into a second output voltage, and the first equalization node voltage and the second equalization node voltage are equalized, which can reduce the switching loss energy of the circuit and improve the conversion efficiency of the circuit.

[0144] The present disclosure also provides a power supply chip, including the hybrid power topology circuit 100 provided in any one of the above embodiments.

[0145] The power supply chip provided in the embodiments of the present disclosure includes the hybrid power topology circuit 100 provided in any one of the above embodiments, and has the same functional modules and beneficial effects as the hybrid power topology circuit 100, which will not be elaborated here.

[0146] The present disclosure also provides an electronic device, including the hybrid power topology circuit 100 provided in any one of the above embodiments.

[0147] Exemplarily, the electronic device may be a charger or a transformer, or other devices capable of realizing voltage conversion. The embodiments of the present disclosure do not make specific limitations thereto.

[0148] The electronic device provided in the embodiments of the present disclosure includes the hybrid power topology circuit 100 provided in any one of the above embodiments, and has the same functional modules and beneficial effects as the hybrid power topology circuit 100, which will not be elaborated here.

[0149] Unless otherwise clearly indicated in the context, the singular forms of the words used in this specification and the appended claims include the plural, and vice versa. Thus, when referring to the singular, the corresponding plural terms are usually included. Similarly, the terms "comprising" and "including" will be interpreted as inclusive rather than exclusive. Likewise, the terms "including" and "or" should be interpreted as inclusive, unless such an interpretation is explicitly prohibited in this specification. Where the term "example" is used in this specification, the "example" is merely exemplary and explanatory, and should not be considered exclusive or extensive.

[0150] The above has described several embodiments of the present disclosure in detail. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims

1. A hybrid power topology circuit, characterized in that, Including: A first voltage conversion circuit, a second voltage conversion circuit, and an equalization circuit; The first voltage conversion circuit and the second voltage conversion circuit are connected in parallel between a voltage input terminal and ground. The output terminal of the first voltage conversion circuit and the output terminal of the second voltage conversion circuit are connected to a voltage output terminal. The equalization circuit is connected to a first equalization node of the first voltage conversion circuit and a second equalization node of the second voltage conversion circuit; The first voltage conversion circuit is configured to convert an input voltage into a first output voltage in a first phase when the hybrid power topology circuit operates in a charge pump mode; and convert the input voltage into a second output voltage when the hybrid power topology circuit operates in a buck mode; The second voltage conversion circuit is configured to convert the input voltage into the first output voltage in a second phase when the hybrid power topology circuit operates in the charge pump mode, and the hybrid power topology circuit in the charge pump mode switches between the first phase and the second phase; The equalization circuit is configured to equalize the voltage of the first equalization node and the voltage of the second equalization node.

2. The hybrid power topology circuit according to claim 1, wherein, The equalization circuit includes a first equalization circuit and a second equalization circuit. The first equalization node includes a first high-level equalization node and a first low-level equalization node. The second equalization node includes a second high-level equalization node and a second low-level equalization node; The first equalization circuit is connected to the first high-level equalization node and the second high-level equalization node. The second equalization circuit is connected to the first low-level equalization node and the second high-level equalization node; The first equalization circuit is configured to equalize the voltage of the first high-level equalization node and the voltage of the second high-level equalization node in a third phase when the hybrid power topology circuit operates in the buck mode; and equalize the voltage of the first high-level equalization node and the voltage of the second high-level equalization node during a dead time between the adjacent first phase and second phase when the hybrid power topology circuit operates in the charge pump mode; The second equalization circuit is configured to equalize the voltage of the first low-level equalization node and the voltage of the second high-level equalization node in a fourth phase when the hybrid power topology circuit operates in the buck mode, and the hybrid power topology circuit in the buck mode switches between the third phase and the fourth phase.

3. The hybrid power topology circuit according to claim 2, wherein The first equalization circuit includes a first equalization transistor and a second equalization transistor. The second equalization circuit includes a third equalization transistor and a fourth equalization transistor; A first end of the first equalization transistor is connected to a first end of the second equalization transistor. A control end of the first equalization transistor is connected to a control end of the second equalization transistor. A second end of the first equalization transistor is connected to the first high-level equalization node. A second end of the second equalization transistor is connected to the second high-level equalization node; The first end of the third equalizing tube is connected to the first end of the fourth equalizing tube, the control end of the third equalizing tube is connected to the control end of the fourth equalizing tube, the second end of the third equalizing tube is connected to the first low-level equalizing node, and the second end of the fourth equalizing tube is connected to the second high-level equalizing node.

4. The hybrid power topology circuit according to claim 2, wherein The first voltage conversion circuit includes a mode switching circuit, a first transistor, a second transistor, a third transistor, a fourth transistor, and a first flying capacitor; The first transistor, the second transistor, the third transistor, and the fourth transistor are connected in series between the voltage input terminal and the ground. The connection point of the first transistor and the second transistor is the first high-level equalizing node. The connection point of the second transistor and the third transistor is the switching node. The switching node is connected to the voltage output terminal through the mode switching circuit. The connection point of the third transistor and the fourth transistor is the first low-level equalizing node. The first flying capacitor is connected across the first high-level equalizing node and the first low-level equalizing node. The control end of the mode switching circuit receives a mode switching signal, and the mode switching signal includes a charge pump mode switching signal and a buck mode switching signal; The mode switching circuit is configured to short-circuit the voltage output terminal and the switching node according to the charge pump mode switching signal, and connect an inductor between the voltage output terminal and the switching node according to the buck mode switching signal.

5. The hybrid power topology circuit according to claim 4, characterized in that, The mode switching circuit includes an inductor and a switch component; The inductor and the switch component are connected in parallel between the voltage output terminal and the switching node; The switch component is configured to conduct the voltage output terminal and the switching node according to the charge pump mode switching signal to short-circuit the inductor; and disconnect the voltage output terminal and the switching node according to the buck mode switching signal to connect the inductor.

6. The hybrid power topology circuit according to claim 5, wherein The switch component includes a first switch tube and a second switch tube; The first end of the first switch tube is connected to the first end of the second switch tube, the control end of the first switch tube is connected to the control end of the second switch tube, the second end of the first switch tube is connected to the switching node, and the second end of the second switch tube is connected to the voltage output terminal.

7. The hybrid power topology circuit according to claim 4, characterized in that, The second voltage conversion circuit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a second flying capacitor; The fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are connected in series between the voltage input terminal and the ground. The connection point of the fifth transistor and the sixth transistor is the second high-level equalizing node. The connection point of the sixth transistor and the seventh transistor is connected to the voltage output terminal. The connection point of the seventh transistor and the eighth transistor is the second low-level equalizing node. The second flying capacitor is connected across the second high-level equalizing node and the second low-level equalizing node.

8. The hybrid power topology circuit according to claim 7, wherein In the first phase, the first transistor, the third transistor, the sixth transistor, and the eighth transistor are in the cut-off state, and the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are in the conducting state; In the second phase, the first transistor, the third transistor, the sixth transistor, and the eighth transistor are in the conducting state, and the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are in the cut-off state; During the dead time, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are in the cut-off state.

9. The hybrid power topology circuit according to claim 7, wherein, In the buck mode, the eighth transistor is in the conducting state, and the fifth transistor, the sixth transistor, and the seventh transistor are in the cut-off state; In the third phase, the fourth transistor is in the conducting state, and the first flying capacitor and the second flying capacitor are in parallel; In the fourth phase, the first transistor is in the conducting state, and the first flying capacitor and the second flying capacitor are in series.

10. The hybrid power topology circuit according to claim 9, wherein When the duty ratio of the buck mode driving signal is greater than 0.5, the fourth phase includes a second sub-phase and two first sub-phases, and the second sub-phase is located between the two first sub-phases; In the first sub-phase, the second transistor is in the conducting state, and the third transistor and the fourth transistor are in the cut-off state. In the second sub-phase, the third transistor is in the conducting state, and the second transistor and the fourth transistor are in the cut-off state; In the third phase, the second transistor is in the conducting state, and the first transistor and the third transistor are in the cut-off state; When the duty ratio of the buck mode driving signal is not greater than 0.5, the third phase includes a fourth sub-phase and two third sub-phases, and the fourth sub-phase is located between the two third sub-phases; In the third sub-phase, the third transistor is in the conducting state, and the first transistor and the second transistor are in the cut-off state. In the fourth sub-phase, the second transistor is in the conducting state, and the first transistor and the third transistor are in the cut-off state; In the fourth phase, the third transistor is in the conducting state, and the second transistor and the fourth transistor are in the cut-off state.

11. A voltage conversion method, characterized in that Applied to a hybrid power topology circuit, the hybrid power topology circuit includes a first voltage conversion circuit, a second voltage conversion circuit, and an equalization circuit. The first voltage conversion circuit and the second voltage conversion circuit are connected in parallel between a voltage input terminal and the ground. The output terminal of the first voltage conversion circuit and the output terminal of the second voltage conversion circuit are connected to a voltage output terminal. The equalization circuit is connected to a first equalization node of the first voltage conversion circuit and a second equalization node of the second voltage conversion circuit; The method includes: When the hybrid power topology circuit operates in the charge pump mode, the input voltage is converted into a first output voltage in the first phase and the second phase; the hybrid power topology circuit in the charge pump mode switches between the first phase and the second phase; When the hybrid power topology circuit operates in the buck mode, the input voltage is converted into a second output voltage; Balance the first equalization node voltage and the second equalization node voltage.

12. The method according to claim 11, wherein The first equalization node includes a first high equalization node and a first low equalization node, and the second equalization node includes a second high equalization node and a second low equalization node; The balancing of the first equalization node voltage and the second equalization node voltage includes: When the hybrid power topology circuit operates in the buck mode, balance the first high equalization node voltage and the second high equalization node voltage in the third phase; Balance the first low equalization node voltage and the second high equalization node voltage in the fourth phase; the hybrid power topology circuit in the buck mode switches between the third phase and the fourth phase; When the hybrid power topology circuit operates in the charge pump mode, balance the first high equalization node voltage and the second high equalization node voltage during the dead time between the adjacent first phase and the second phase.

13. A power supply chip, characterized in that, Comprising the hybrid power topology circuit according to any one of claims 1-10.

14. An electronic device, characterized in that, Comprising the hybrid power topology circuit according to any one of claims 1-10.

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