Circuit for solving operational heat carrier effect

Abstract

The invention discloses a circuit for solving an operational heat carrier effect, and belongs to the technical field of OPA design, the circuit comprises PMOS tubes MP1-MP4, PMOS tubes MP10-MP12, NMOS tubes MN1-MN4, resistors R1 and R2, and NMOS tubes MN5 and MN6, the circuit realizes elimination of the heat carrier effect of an operational amplifier under high power supply voltage, and improves the loop gain of the operational amplifier. According to the operational amplifier, the resistor string, the MN5 transistor and the MN6 transistor are additionally arranged in a traditional cascode framework, and the bias current and the size of the two transistors are properly adjusted, so that the Vds of the MN5 transistor, the MN6 transistor, the MN3 transistor and the MN4 transistor are all smaller than 2V, the hot carrier effect can be eliminated, and meanwhile, the loop gain of the operational amplifier can be slightly improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of OPA design, and particularly relates to a circuit for solving the hot carrier effect of an operational amplifier. Background Art

[0002] In current OPA designs, there is a need for a wide power supply voltage, such as a design requirement from 1.8V to 5.5V. At the same time, a cascode structure is adopted in the design. In this architecture, the hot carrier effect is likely to occur under a wide power supply voltage, which is reflected in the STB simulation in that the phase margin starts from 0. Many engineers think that it is a problem of the simulation tool when this situation occurs, thus ignoring this problem. Summary of the Invention

[0003] The purpose of the present invention is to provide a circuit for solving the hot carrier effect of an operational amplifier, whose phase starts from 0 and the loop gain will decrease. The present invention solves the hot carrier effect of these transistors. The difference before and after modification can be seen through the stb simulation, and the problems raised in the above background art can be solved.

[0004] To achieve the above purpose, the present invention provides the following technical solution: A circuit for solving the hot carrier effect of an operational amplifier, the circuit includes PMOS transistors MP1~MP4, PMOS transistors MP10~MP12, NMOS transistors MN1~MN4, resistors R1, R2 and NMOS transistors MN5, MN6. The circuit realizes the elimination of the hot carrier effect of the operational amplifier under a high power supply voltage and improves the loop gain of the operational amplifier;

[0005] Among them, the drain terminal of MP1 is connected to the source terminal of MP3, the gate terminal of MP1 is connected to the drain terminal of MP3, the drain terminal of MN5 and the gate terminal of MP2; the gate terminal of MP3 is connected to the voltage VBP2; the source terminal of MN5 is connected to the drain terminal of MN3, the gate terminal of MN5 is connected to the gate terminal of MN6; the source terminal of MN3 is connected to the drain terminal of MN1 and the drain terminal of MP10, the gate terminal of MN3 is connected to the voltage VBN1; the gate terminal of MN1 is connected to the voltage VBN2;

[0006] One end of the resistor R1 is connected to VDD, and the other end is connected to the resistor R2. A voltage VBX is formed at the point where the resistor R2 is connected; one end of the resistor R2 is connected to GND, and the other end is connected to the resistor R1;

[0007] The drain terminal of MP2 is connected to the source terminal of MP4; the drain terminal of MP4 is connected to the drain terminal of MN6, and the gate terminal of MP4 is connected to voltage VBP2; the source terminal of MN6 is connected to the drain terminal of MN4, and the gate terminal of MN6 is also connected to voltage VBX; the source terminal of MN4 is connected to the drain terminals of MN2 and MP11, and the gate terminal of MN4 is connected to voltage VBN1; the gate terminal of MN2 is connected to voltage VBN2; the drain terminal of MP12 is connected to the source terminals of MP10 and MP11, and the gate terminal of MP12 is connected to the gate terminal of MP1; the drain terminal of MP10 is connected to the drain terminal of MN1 and the source terminal of MN3, and the gate terminal of MP10 is connected to input voltage VIP; the drain terminal of MP11 is connected to the drain terminals of MN2 and MN4, and the gate terminal of MP11 is connected to input voltage VIN.

[0008] Preferably, the source terminals of the PMOS transistors MP1, MP2, and MP12 are connected to power supply VDD.

[0009] Preferably, the source terminals of the NMOS transistors MN1 and MN2 are connected to GND.

[0010] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0011] In the present invention, by adding a resistor string and two transistors MN5 and MN6 inside the traditional cascode architecture, and appropriately adjusting the bias currents and sizes of the two transistors, the Vds of MN5, MN6, MN3, and MN4 are all less than 2V, thereby eliminating the hot carrier effect and slightly increasing the loop gain of the operational amplifier at the same time. Description of the Drawings

[0012] Figure 1 It is the circuit diagram of the traditional cascode architecture.

[0013] Figure 2 It is the circuit diagram of the cascode architecture of a circuit for solving the hot carrier effect of an operational amplifier according to the present invention.

[0014] Figure 3 It is the simulation Bode plot of the traditional cascode architecture OPA.

[0015] Figure 4 It is the simulation Bode plot of the cascode architecture OPA of a circuit for solving the hot carrier effect of an operational amplifier according to the present invention. Detailed Embodiments

[0016] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0017] To increase the gain of the operational amplifier, a cascode structure is usually used. Figure 1 It is a classic cascode architecture, with each path consisting of two PMOS and NMOS transistors. The output point is between the PMOS and NMOS transistors. If this architecture operates at a high supply voltage, such as 3.6V, and the Vout voltage reaches 2.9V, then for transistor MN4, Vds4 = Vout - Vs4, where Vs4 is approximately 0.4V, and Vds4 is approximately 2.5V. At this time, Vds > 2V, and the hot carrier effect of MN4 transistor appears, and the phase diagram of the stb simulation will start from 0. Figure 3 It is the Bode plot simulation result of the OPA. It can be seen that the phase starts from 0. In this case, the loop gain of the OPA will also decrease. The hot carrier effect will cause the threshold voltage of the transistor to change and the transconductance (Gm) to decrease. If the transistor is in this state for a long time, it will exacerbate device aging, resulting in reduced reliability.

[0018] Among them, Figure 1 The connection relationship of the circuit elements in it is described as follows:

[0019] The source terminal of MP1 is connected to the power supply VDD, the drain terminal of MP1 is connected to the source terminal of MP3, and the gate terminal of MP1 is connected to the drain terminal of MP3 and the drain terminal of MN3;

[0020] The source terminal of MP3 is connected to the drain terminal of MP1, the drain terminal of MP3 is connected to the gate terminal of MP1 and the drain terminal of MN3, and the gate terminal of MP3 is connected to the voltage VBP2;

[0021] The drain terminal of MN3 is connected to the drain terminal of MP3 and the gate terminal of MP1, the source terminal of MN3 is connected to the drain terminal of MN1 and the drain terminal of MP10, and the gate terminal of MN3 is connected to the VBN1 voltage;

[0022] The drain terminal of MN1 is connected to the source terminal of MN3 and the drain terminal of MP10, the source terminal of MN1 is grounded, and the gate terminal of MN1 is connected to the VBN2 voltage;

[0023] The source terminal of MP2 is connected to the power supply VDD, the drain terminal of MP2 is connected to the source terminal of MP4, and the gate terminal of MP2 is connected to the gate terminal of MP1;

[0024] The source terminal of MP4 is connected to the drain terminal of MP2, the drain terminal of MP4 is connected to the drain terminal of MN4, and the gate terminal of MP4 is connected to the voltage VBP2;

[0025] The drain terminal of MN4 is connected to the drain terminal of MP4, the source terminal of MN4 is connected to the drain terminal of MN2 and the drain terminal of MP11, and the gate terminal of MN4 is connected to the VBN1 voltage;

[0026] The drain terminal of MN2 is connected to the source terminal of MN4 and the drain terminal of MP11. The source terminal of MN2 is grounded, and the gate terminal of MN2 is connected to the voltage VBN2.

[0027] The source terminal of MP12 is connected to the voltage VDD. The drain terminal of MP12 is connected to the source terminals of MP10 and MP11, and the gate terminal of MP12 is connected to the gate terminal of MP1.

[0028] The source terminal of MP10 is connected to the drain terminal of MP12 and the source terminals of MP11. The drain terminal of MP10 is connected to the drain terminal of MN1 and the source terminal of MN3, and the gate terminal of MP10 is connected to the input voltage VIP.

[0029] The source terminal of MP11 is connected to the drain terminal of MP12 and the source terminals of MP10. The drain terminal of MP11 is connected to the drain terminal of MN2 and the source terminal of MN4, and the gate terminal of MP11 is connected to the input voltage VIN.

[0030] As Figure 2 shown, a circuit for solving the hot carrier effect in an operational amplifier of the present invention adds a resistor string and two transistors MN5 and MN6 in the cascode structure, and appropriately adjusts the bias currents and sizes of the two transistors, so that the Vds of MN5, MN6, MN3, and MN4 are all less than 2V, thereby eliminating the hot carrier effect. As Figure 4 shown, it can also be seen from the simulation that the result of the Bode plot is normal. In this architecture, when the operational amplifier operates at a low power supply voltage, MN5 and MN6 will enter the linear region, but it will not affect the overall performance of the operational amplifier. At a high power supply voltage, in addition to eliminating the hot carrier effect, MN5 and MN6 can also slightly increase the loop gain of the operational amplifier.

[0031] Among them, Figure 2 is the cascode architecture circuit diagram of the method for solving the hot carrier effect in an operational amplifier, and the connection relationship of its circuit elements is described as follows:

[0032] The source terminal of MP1 is connected to the power supply VDD. The drain terminal of MP1 is connected to the source terminal of MP3, and the gate terminal of MP1 is connected to the drain terminal of MP3 and the drain terminal of MN5.

[0033] The source terminal of MP3 is connected to the drain terminal of MP1. The drain terminal of MP3 is connected to the gate terminal of MP1 and the drain terminal of MN5, and the gate terminal of MP3 is connected to the voltage VBP2.

[0034] The drain terminal of MN5 is also connected to the gate terminal of MP1 and the drain terminal of MP3. The source terminal of MN5 is connected to the drain terminal of MN3, and the gate terminal of MN5 is connected to the gate terminal of MN6.

[0035] The drain terminal of MN3 is connected to the source terminal of MN5. The source terminal of MN3 is connected to the drain terminal of MN1 and the drain terminal of MP10, and the gate terminal of MN3 is connected to the voltage VBN1.

[0036] The drain terminal of MN1 is connected to the source terminal of MN3 and the drain terminal of MP10. The source terminal of MN1 is grounded, and the gate terminal of MN1 is connected to the VBN2 voltage.

[0037] One end of R1 is connected to VDD, and the other end is connected to R2. The point where R2 is connected is named VBX.

[0038] One end of R2 is connected to GND, and the other end is connected to R1. The point where R1 is connected is named VBX.

[0039] The source terminal of MP2 is connected to the power supply VDD. The drain terminal of MP2 is connected to the source terminal of MP4, and the gate terminal of MP2 is connected to the gate terminal of MP1.

[0040] The source terminal of MP4 is connected to the drain terminal of MP2. The drain terminal of MP4 is connected to the drain terminal of MN6, and the gate terminal of MP4 is connected to the voltage VBP2.

[0041] The drain terminal of MN6 is connected to the drain terminal of MP4. The source terminal of MN6 is connected to the drain terminal of MN4, and the gate terminal of MN6 is connected to the voltage VBX.

[0042] The drain terminal of MN4 is connected to the drain terminal of MP6. The source terminal of MN4 is connected to the drain terminal of MN2 and the drain terminal of MP11, and the gate terminal of MN4 is connected to the VBN1 voltage.

[0043] The drain terminal of MN2 is connected to the source terminal of MN4 and the drain terminal of MP11. The source terminal of MN2 is grounded, and the gate terminal of MN2 is connected to the VBN2 voltage.

[0044] The source terminal of MP12 is connected to the VDD voltage. The drain terminal of MP12 is connected to the source terminals of MP10 and MP11, and the gate terminal of MP12 is connected to the gate terminal of MP1.

[0045] The source terminal of MP10 is connected to the drain terminal of MP12 and the source terminals of MP11. The drain terminal of MP10 is connected to the drain terminal of MN1 and the source terminal of MN3, and the gate terminal of MP10 is connected to the input voltage VIP.

[0046] The source terminal of MP11 is connected to the drain terminal of MP12 and the source terminals of MP10. The drain terminal of MP11 is connected to the drain terminal of MN2 and the source terminal of MN4, and the gate terminal of MP11 is connected to the input voltage VIN.

[0047] In the present invention, by adding a resistor string (R1 and R2) and two transistors MN5 and MN6 within the traditional cascode architecture, and appropriately adjusting the bias currents and sizes of the two transistors, the Vds of MN5, MN6, MN3, and MN4 are all less than 2V, thereby eliminating the hot carrier effect and slightly increasing the loop gain of the operational amplifier at the same time.

[0048] Although the preferred embodiments of the present invention have been described, additional changes and modifications can be made by those skilled in the art once they learn the basic creative concept. Therefore, the appended claims are intended to be interpreted to include the preferred embodiments as well as all changes and modifications falling within the scope of the present invention.

[0049] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A circuit for solving the hot-carrier effect of transport and heat release, characterized in that The circuit includes PMOS transistors MP1 to MP4, PMOS transistors MP10 to MP12, NMOS transistors MN1 to MN4, resistors R1, R2, and NMOS transistors MN5, MN6. This circuit achieves the elimination of the hot carrier effect under a high power supply voltage and improves the loop gain of the operational amplifier. Among them, the drain terminal of MP1 is connected to the source terminal of MP3, the gate terminal of MP1 is connected to the drain terminal of MP3, the drain terminal of MN5, and the gate terminal of MP2; the gate terminal of MP3 is connected to the voltage VBP2; the source terminal of MN5 is connected to the drain terminal of MN3, and the gate terminal of MN5 is connected to the gate terminal of MN6; the source terminal of MN3 is connected to the drain terminal of MN1 and the drain terminal of MP10, and the gate terminal of MN3 is connected to the voltage VBN1; the gate terminal of MN1 is connected to the voltage VBN2. One end of the resistor R1 is connected to VDD, and the other end is connected to the resistor R2. A voltage VBX is formed at the point where the resistor R2 is connected; one end of the resistor R2 is connected to GND, and the other end is connected to the resistor R1. The drain terminal of MP2 is connected to the source terminal of MP4; the drain terminal of MP4 is connected to the drain terminal of MN6, the gate terminal of MP4 is connected to the voltage VBP2; the source terminal of MN6 is connected to the drain terminal of MN4, and the gate terminal of MN6 is also connected to the voltage VBX; the source terminal of MN4 is connected to the drain terminal of MN2 and the drain terminal of MP11, the gate terminal of MN4 is connected to the voltage VBN1; the gate terminal of MN2 is connected to the voltage VBN2; the drain terminal of MP12 is connected to the source terminals of MP10 and MP11, and the gate terminal of MP12 is connected to the gate terminal of MP1; the drain terminal of MP10 is connected to the drain terminal of MN1 and the source terminal of MN3, and the gate terminal of MP10 is connected to the input voltage VIP; the drain terminal of MP11 is connected to the drain terminal of MN2 and the source terminal of MN4, and the gate terminal of MP11 is connected to the input voltage VIN.

2. The circuit for solving the hot carrier effect of heat generation and transport according to claim 1, characterized in that The source terminals of the PMOS transistors MP1, MP2, and MP12 are connected to the power supply VDD.

3. The circuit for solving the hot carrier effect of heat generation and transport according to claim 1, characterized in that The source terminals of the NMOS transistors MN1 and MN2 are connected to GND.

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