Ultra-high-speed ultra-short-distance serial receiver, receiving method and equipment

Abstract

The invention relates to the technical field of data transmission, and provides an ultra-high-speed ultra-short-distance serial receiver, a receiving method and equipment, and the receiver comprises an analog front-end circuit which carries out the impedance matching, AC coupling and linear equalization processing of received high-speed ultra-short-distance serial data; the static comparator is used for alternately sampling the edge phase information and the data center information of the equalized high-speed extremely-short-distance serial data under the control of the multi-phase clock so as to obtain high-speed serial sampling data; the deserializer deserializes the high-speed serial sampling data into multiple paths of parallel low-speed data; the clock generation circuit is used for generating a high-precision and low-jitter four-phase clock signal for half-rate sampling of the static comparator; and the clock recovery loop is used for tracking and correcting the relative sampling positions of the multi-channel parallel low-speed data and the multi-phase clock. Through the technical scheme, while a wired transmission signal is received, a certain equalization capability is provided, the integrity of a high-speed signal is recovered, and the power consumption of the circuit is saved.

Description

Technical Field

[0001] This application relates to the field of data transmission technologies, and in particular, to an ultra-high-speed and extremely short-distance serial receiver, a receiving method, and a device.

Background Art

[0002] With the progress of modern communication technologies and the substantial increase in data throughput requirements, the small chiplet technology based on the SerDes transmission method and the new Die to Die interconnection method have developed rapidly. The short-distance wired channel communication between chips has put forward new requirements for the serial interface transceiver architecture. The rapid increase in data transmission rate will lead to the deterioration of signal quality and the continuous deterioration of the path signal-to-noise ratio, seriously affecting the working range and signal transmission rate of the SerDes system. At the same time, the multi-channel parallel transmission method means that the power consumption of the interface chip has become a huge challenge. Therefore, most of the SerDes solutions for extremely short-distance channel transmission adopt an analog hybrid architecture to meet the equalization requirements, improve the bit error rate index, and save power consumption and area overhead to the greatest extent.

[0003] Currently, for short-distance wired channel transmission, mainstream high-speed SerDes receivers mostly adopt a quarter-rate or half-rate sampling analog hybrid architecture based on multi-phase clock generation to improve the data transmission rate. The main equalization scheme is to provide corresponding high-frequency equalization capabilities by one or more stages of CTLE in the analog front end. Therefore, achieving high-jitter, high-precision multi-phase clock generation and high-signal-to-noise ratio signal quality in the receiver has gradually become an index that analog hybrid architecture SerDes continuously pursues.

Summary of the Invention

[0004] Embodiments of this application provide an ultra-high-speed and extremely short-distance serial receiver, a receiving method, and a device, aiming to solve the technical problems existing in the related technologies.

[0005] In a first aspect, embodiments of this application provide an ultra-high-speed and extremely short-distance serial receiver, including:

[0006] An analog front-end circuit, configured to perform impedance matching, AC coupling, and linear equalization processing on the received ultra-high-speed and extremely short-distance serial data to obtain the processed ultra-high-speed and extremely short-distance serial data;

[0007] A static comparator, connected to the analog front-end circuit, configured to alternately sample the edge phase information and data center information of the processed ultra-high-speed and extremely short-distance serial data under the control of a multi-phase clock to obtain high-speed serial sampled data;

[0008] A deserialization circuit, connected to the static comparator, configured to deserialize the high-speed serial sampled data into multiple paths of parallel low-speed data;

[0009] A clock generation circuit, connected to the static comparator, for generating a high-precision, low-jitter multi-phase clock and outputting the multi-phase clock to the static comparator;

[0010] A clock recovery circuit, connected between the output end of the deserialization circuit and the clock generation circuit, for correcting the relative positions of the multi-channel parallel low-speed data and the multi-phase clock to track the optimal sampling point.

[0011] In one embodiment, optionally, the analog front-end circuit includes:

[0012] An impedance matching unit, including a programmable adjustable resistor array, for performing channel impedance matching on the high-speed very short-range serial data;

[0013] An AC coupling unit, connected to the impedance matching unit, including a high-pass filter composed of a capacitor and a variable resistor, for performing DC filtering and common-mode parameter adjustment on the high-speed very short-range serial data;

[0014] A linear equalization unit, connected to the AC coupling unit, for performing high-frequency amplification on the high-speed very short-range serial data to compensate for the high-frequency signal attenuation generated by the channel.

[0015] In one embodiment, optionally, the linear equalization unit includes a continuous-time linear equalizer, and the continuous-time linear equalizer includes:

[0016] A source negative feedback resistor array, for controlling the switching of the switching transistors according to a control word to adjust the resistance value incorporated into the circuit;

[0017] A source negative feedback capacitor array, connected in parallel with the source negative feedback resistor array, for controlling the switching of the switching transistors according to a control word to adjust the capacitance value incorporated into the circuit, so as to adjust the position of the zero-pole pair by adjusting the resistance value and the capacitance value;

[0018] An adjustable load resistor, for coping with PVT variations and adjusting the bandwidth in a small range;

[0019] A current-mode digital-to-analog converter, connected between two grounded terminals of the continuous-time linear equalizer, for adjusting the tail current, adjusting the transconductance of the circuit, and maintaining the consistency of the output swing when the adjustable load resistor is adjusted.

[0020] In one embodiment, optionally, the source negative feedback resistor array includes multiple parallel-connected resistor strings;

[0021] Each resistor string includes a switching transistor and a first resistor and a second resistor respectively connected to the input end and the output end of the switching transistor, wherein the resistance values of the first resistor and the second resistor are the same, and the resistance values of the resistors in different resistor strings are the same or different.

[0022] In one embodiment, optionally, the source negative feedback capacitor array includes multiple parallel-connected capacitor strings;

[0023] Each capacitor string includes a first capacitor and a second capacitor connected in series, and a switch group connected between the first capacitor and the second capacitor. Among them, the switch group includes a first MOS group, a second MOS group, and a switching transistor;

[0024] Among them, the first MOS group and the second MOS group are connected in parallel, and the switching transistor is connected between the first MOS group and the second MOS group;

[0025] The first MOS group and the second MOS group include a PMOS transistor and an NMOS transistor connected in series.

[0026] In one embodiment, optionally, the clock recovery circuit includes:

[0027] A Bang-Bang phase detector for performing phase discrimination on the edge phase information and data center information in the low-speed data to determine the phase relationship;

[0028] A voting accumulator connected to the Bang-Bang phase detector for performing voting accumulation summation according to the phase relationship to determine the phase lead information and the phase lag information;

[0029] A low-pass filter connected to the voting accumulator for filtering;

[0030] A phase difference detector connected to the low-pass filter for accumulating the rising signal and the falling signal through PI control logic, and outputting a control codeword of current-mode PI, and outputting a multi-phase clock with low jitter by adjusting the corresponding current weights.

[0031] In one embodiment, optionally, the static comparator includes a master-slave flip-flop using CML logic.

[0032] In one embodiment, optionally, the deserialiser includes: two inverters, a latch, and a master-slave flip-flop cascaded by transmission gates, for performing differential sampling and delay alignment on the high-speed serial sampled data, decomposing the high-speed serial sampled data into two paths of parallel data output in alignment, and at the same time reducing the data rate to half of the original.

[0033] In a second aspect, an embodiment of the present application provides a method for receiving ultra-high-speed and extremely short-distance serial data, which is used for the ultra-high-speed and extremely short-distance serial receiver described in any one of the embodiments of the first aspect. The method includes:

[0034] Perform impedance matching, AC coupling, and linear equalization processing on the received high-speed very short-range serial data to obtain the processed high-speed very short-range serial data;

[0035] Under the control of a multi-phase clock, alternately sample the edge phase information and data center information of the processed high-speed very short-range serial data respectively to obtain high-speed serial sampled data;

[0036] Deserialize the high-speed serial sampled data into multiple paths of parallel low-speed data;

[0037] Generate and output a multi-phase clock with high precision and low jitter;

[0038] Correct the relative positions of the multiple paths of parallel low-speed data and the multi-phase clock to track the optimal sampling point.

[0039] In a third aspect, a chip device is provided, including the ultra-high-speed very short-range serial receiver according to any one of the embodiments of the first aspect.

[0040] In the solutions implemented by the above ultra-high-speed very short-range serial receiver, receiving method, and device, the received high-speed very short-range serial data is subjected to impedance matching, AC coupling, and linear equalization processing through an analog front-end circuit to obtain the processed high-speed very short-range serial data; a static comparator, connected to the analog front-end circuit, is used to alternately sample the edge phase information and data center information of the processed high-speed very short-range serial data respectively under the control of a multi-phase clock to obtain high-speed serial sampled data; a deserialization circuit, connected to the static comparator, is used to deserialize the high-speed serial sampled data into multiple paths of parallel low-speed data; a clock generation circuit, connected to the static comparator, is used to generate a multi-phase clock with high precision and low jitter and output the multi-phase clock to the static comparator; a clock recovery circuit, connected between the output end of the deserialization circuit and the clock generation circuit, is used to correct the relative positions of the multiple paths of parallel low-speed data and the multi-phase clock to track the optimal sampling point. In this way, problems such as high-frequency attenuation, inter-symbol interference, and signal reception in short-distance wired transmission of electrical signals are solved. Compared with traditional receiver solutions, the receiver solution of the present invention has an accurate multi-phase clock generation and recovery loop while providing a certain equalization ability, saving power while increasing the data rate.

Description of the Drawings

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0042] Figure 1 Shows a schematic block diagram of an ultra-high-speed very short-range serial receiver according to an embodiment of the present application.

[0043] Figure 2 Shows a schematic block diagram of an analog front-end circuit in an ultra-high-speed very short-range serial receiver according to an embodiment of the present application.

[0044] Figure 3 Shows a schematic structural diagram of a continuous-time linear equalizer in an ultra-high-speed very short-range serial receiver according to an embodiment of the present application.

[0045] Figure 4 Shows a schematic structural diagram of a source negative feedback resistor array in an ultra-high-speed very short-range serial receiver according to an embodiment of the present application.

[0046] Figure 5 Shows a schematic structural diagram of a source negative feedback capacitor array in an ultra-high-speed very short-range serial receiver according to an embodiment of the present application.

[0047] Figure 6 Shows a schematic diagram of a CML type master-slave trigger static comparator in an ultra-high-speed very short-range serial receiver according to an embodiment of the present application.

[0048] Figure 7 Shows a schematic diagram of a CML to CMOS logic operational amplifier in an ultra-high-speed very short-range serial receiver according to an embodiment of the present application.

[0049] Figure 8 Shows a schematic diagram of a latch-based 1TO 2 deserialiser in an ultra-high-speed very short-range serial receiver according to an embodiment of the present application.

[0050] Figure 9 Shows a schematic diagram of a master-slave flip-flop based on a transmission gate structure in an ultra-high-speed very short-range serial receiver according to an embodiment of the present application.

[0051] Figure 10 Shows a schematic structural diagram of a flip-flop-based frequency division by two structure in an ultra-high-speed very short-range serial receiver according to an embodiment of the present application.

[0052] Figure 11 Shows a schematic diagram of a clock generation circuit and a clock recovery circuit in an ultra-high-speed very short-range serial receiver according to an embodiment of the present application.

[0053] Figure 12 Shows a schematic diagram of a current-mode phase interpolator (PI) in an ultra-high-speed very short-range serial receiver according to an embodiment of the present application.

[0054] Figure 13Shows a schematic diagram of the overall structure of a ultra-high speed very short range serial receiver according to an embodiment of the present application.

[0055] Figure 14 Shows a flowchart of a method for receiving ultra-high speed very short range serial data according to an embodiment of the present application.

Detailed implementation manners

[0056] For a better understanding of the technical solutions of the present application, the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0057] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0058] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "the" and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0059] To solve the technical problems such as high-frequency attenuation, inter-symbol interference, and signal reception in the short-distance wired transmission of electrical signals in the related art, the present application proposes a ultra-high speed very short range serial receiver, receiving method, and device.

[0060] The following will describe in detail some embodiments of the present application with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0061] Please refer to Figure 1 , Figure 1 Shows a schematic block diagram of a ultra-high speed very short range serial receiver according to an embodiment of the present application. The ultra-high speed very short range serial receiver is used to solve the technical problems such as high-frequency attenuation, inter-symbol interference, and signal reception in the short-distance wired transmission of electrical signals in the related art.

[0062] As Figure 1 shown, a ultra-high speed very short range serial receiver 10 according to an embodiment of the present application includes:

[0063] An analog front-end circuit 11, configured to perform impedance matching, AC coupling, and linear equalization processing on the received high-speed very short range serial data to obtain processed high-speed very short range serial data;

[0064] As Figure 2 shown, in one embodiment, optionally, the analog front-end circuit 11 includes:

[0065] An impedance matching unit 21, including a programmably adjustable resistor array, is used for channel impedance matching of the high-speed very short-distance serial data;

[0066] An AC coupling unit 22, connected to the impedance matching unit 21, includes a high-pass filter composed of a capacitor and a variable resistor, and is used for DC filtering and common-mode parameter adjustment of the high-speed very short-distance serial data;

[0067] A linear equalization unit 23, connected to the AC coupling unit 22, is used for high-frequency amplification of the high-speed very short-distance serial data to compensate for high-frequency signal attenuation generated by the channel.

[0068] In this embodiment, the analog front-end part is mainly divided into three parts. Among them, the impedance matching part uses a programmably adjustable resistor array to achieve channel impedance matching with the highest precision and reduce transmission signal reflection. The AC coupling part is mainly composed of a high-pass filter composed of a capacitor and a variable resistor, which can isolate DC and pass AC while being able to adjust the corner frequency and the system common mode. The CTLE part uses a programmable source-level negative feedback resistor and capacitor architecture, and at the same time, the tail current source and the load resistor array are increased with adjustable arrays to cope with the channel environment and PVT variations to the greatest extent.

[0069] As Figure 3 shown, in one embodiment, optionally, the linear equalization unit 23 includes a continuous-time linear equalizer CTLE, and the continuous-time linear equalizer includes:

[0070] A source negative feedback resistor array, used to control the switching of the switching transistors according to a control word to adjust the resistance value incorporated into the circuit;

[0071] A source negative feedback capacitor array, connected in parallel with the source negative feedback resistor array, is used to control the switching of the switching transistors according to a control word to adjust the capacitance value incorporated into the circuit, so as to adjust the position of the zero-pole pair by adjusting the resistance value and the capacitance value;

[0072] An adjustable load resistor, used to cope with PVT variations and adjust the bandwidth in a small range;

[0073] A current-mode digital-to-analog converter, connected between the two grounded terminals of the continuous-time linear equalizer, is used to adjust the tail current, adjust the transconductance of the circuit, and maintain the consistency of the output swing when the adjustable load resistor is adjusted.

[0074] In this embodiment, the present invention uses a first-order CTLE to provide overall equalization for the receiver. As the receiving part of the analog front end, the frequency response of the CTLE is characterized by a high-pass characteristic. It amplifies the high-frequency components of the input signal that has experienced high-frequency attenuation through a low-pass channel, thereby improving the signal quality. However, due to the attenuation in its low-frequency part, it will cause a reduction in the overall swing. In addition, since it also amplifies high-frequency noise indiscriminately, it will deteriorate the signal-to-noise ratio. Therefore, its linearity and noise characteristics directly affect the signal-to-noise ratio of the receiver signal. The present invention adopts a CTLE architecture based on a source-level negative feedback architecture as shown in Figure 3 At the same time, the negative feedback resistor RL and the capacitor CL are set as a register control array to adjust the position of the formed zero-pole pair to cope with the changing channel environment. At the same time, the load resistor RD is also set as a gradient-adjustable array to cope with PVT variations and adjust the bandwidth. To ensure the stability of the overall signal output swing, the tail current is injected by means of a current digital-to-analog converter (IDAC, i.e., Current Digital-Analog Converter), realizing the gradient adjustment of the tail current and ensuring the consistency of the output signal swing IR. At the same time, to meet the design requirements of high-speed signals, the present invention adopts an additional series peaking bandwidth expansion method. A characteristic series inductor is added at the output to divide the load capacitance to expand the bandwidth. The derivation of the transfer function of this design is summarized as the following formula:

[0075]

[0076] As shown in Figure 4 In one embodiment, optionally, the source negative feedback resistor array includes a plurality of parallel-connected resistor strings;

[0077] Each resistor string includes a switching transistor and a first resistor and a second resistor respectively connected to the input end and the output end of the switching transistor. Among them, the resistance values of the first resistor and the second resistor are the same, and the resistance values of the resistors in different resistor strings are the same or different.

[0078] In this embodiment, the source negative feedback resistor array is a weight-adjustable negative feedback resistor array. By controlling the word to turn on the switching transistor, the resistance value incorporated into the circuit is changed.

[0079] As shown in Figure 5 In one embodiment, optionally, the source negative feedback capacitor array includes a plurality of parallel-connected capacitor strings;

[0080] Each capacitor string includes a first capacitor, a second capacitor connected in series, and a switch group connected between the first capacitor and the second capacitor. Among them, the switch group includes a first MOS group, a second MOS group, and a switching transistor;

[0081] Among them, the first MOS group and the second MOS group are connected in parallel, and the switching transistor is connected between the first MOS group and the second MOS group;

[0082] The first MOS group and the second MOS group include a PMOS transistor and an NMOS transistor connected in series.

[0083] In this embodiment, the source negative feedback capacitor array includes four capacitor branches, which are controlled by a binary code, and the capacitance values increase in binary weighted manner. Except for the switching transistor, the other four MOS transistors in each branch are used to set the DC operating voltage at the source and drain of the switching transistor. The function of the PMOS transistor is to pull up the DC voltage at the source and drain to 900 mV when the switching transistor is turned off, increasing the reverse bias voltage of the source-drain PN junction, thereby reducing the parasitic capacitance from the source-drain to the substrate, and thus reducing the influence of the parasitic capacitance on the control accuracy of the capacitor array. The function of the NMOS transistor is to pull down the DC operating voltage at the source and drain to ground when the switching transistor is turned on, so as to ensure that the switching transistor is fully turned on. The on-resistance of the PMOS transistor for pulling up needs to be small enough to ensure that the RC cut-off frequency is low enough to ensure that the capacitor array can be effectively turned off. At the same time, the size of the NMOS pull-down transistor needs to be small enough to prevent it from introducing additional parasitic capacitance at the source-drain node of the switching transistor.

[0084] The static comparator 12 is connected to the analog front-end circuit 11 and is used to alternately sample the edge phase information and the data center information of the processed high-speed very short-range serial data under the control of a multi-phase clock to obtain high-speed serial sampled data;

[0085] In one embodiment, optionally, the static comparator includes a master-slave flip-flop using CML logic.

[0086] To achieve high-speed design, the present invention adopts a half-rate architecture sampling design based on a four-phase clock, and samples the edge phase information and the data center information of the data respectively. The static sampling module used is as Figure 6The master-slave flip-flop structure with cross-coupled positive feedback shown. When the clock signal VCLK_N is at a high level, the master differential pair M1, M2 in the master flip-flop and the cross-coupled positive feedback pair M9, M10 in the slave flip-flop are turned on. The current forms a voltage drop across the load resistors R1, R2 and generates a voltage difference, tracking and amplifying the input differential data VIN_P and VIN_N. When the clock signal VCLK_P is at a high level, the cross-coupled positive feedback pair M3, M4 in the master flip-flop and the master differential pair M7, M10 in the slave flip-flop are turned on. While latching the signal in the tracking stage, due to the additional gain provided by the positive feedback, the signal can be further amplified to amplify the input signal to a sufficient decision level. The static comparator based on CML logic always has one path in the on state, so it sacrifices some power consumption, but ensures a large bandwidth and amplification speed.

[0087] Based on the sampling signal output by the static comparator, since the comparison part uses CML decision logic, for the CMOS deserialization module composed of flip-flops, an additional level conversion module is required to convert the 500mV CML differential comparator output swing signal into a 1V CMOS level. The level conversion circuit adopted in the present invention is as Figure 7 shown, based on the architecture of a two-stage operational amplifier. During the design process, due to the large swing of the input signal, the gain requirement for the overall structure is low, and at the same time, the two poles of the two-stage operational amplifier have a large gap, so no additional phase compensation design is required. However, since it is a level conversion of the output signal sampled by a high-speed comparator, this design has certain requirements for the unity gain bandwidth product.

[0088] The deserialization unit 13 is connected to the static comparator 12 and is used to deserialize the high-speed serial sampled data into multiple paths of parallel low-speed data;

[0089] In one embodiment, optionally, the deserialization unit includes: two inverters, a latch, and a master-slave flip-flop cascaded by transmission gates, which are used to perform differential sampling and delay alignment on the high-speed serial sampled data, decompose one path of the high-speed serial sampled data into two paths of aligned parallel data output, and at the same time reduce the data rate to half of the original.

[0090] In a specific embodiment, the deserialization unit can adopt a 4:64 deserialization unit, mainly based on the 1TO 2 deserialization module controlled by a divided-frequency differential clock as shown in Figure 8 shown. Using two inverters and a master-slave flip-flop cascaded by transmission gates and a latch as shown in Figure 9 shown to perform differential sampling and delay alignment on the signal, decompose one path of serial data into two paths of aligned parallel data output, and at the same time reduce the data rate to half of the original.

[0091] In a specific embodiment, the deserialization part is as follows Figure 10 The input clock is divided by two with a fine-tuned clock beat as shown, and a flip-flop structure with two latches connected end to end is used to divide the input clock by two. After adding an inverter drive, it has high practicality.

[0092] A clock generation circuit 14, connected to the static comparator 12, for outputting a control codeword of a multi-phase clock to the static comparator;

[0093] A clock recovery circuit 15, connected between the output end of the deserialization circuit 13 and the clock generation circuit 14, for correcting the relative positions of the multi-channel parallel low-speed data and the multi-phase clock to output a multi-phase clock with low jitter.

[0094] In one embodiment, optionally, the clock recovery circuit 15 includes:

[0095] A Bang-Bang phase detector, for performing phase discrimination on the edge phase information and data center information in the low-speed data to determine the phase relationship;

[0096] A voting accumulator, connected to the Bang-Bang phase detector, for performing voting accumulation summation according to the phase relationship to determine the phase lead information and phase lag information;

[0097] A low-pass filter, connected to the voting accumulator, for filtering;

[0098] A phase difference detector, connected to the low-pass filter, for accumulating the rising signal and the falling signal through PI control logic and outputting a control codeword of current-type PI. By adjusting the corresponding current weights, a multi-phase clock with low jitter is output.

[0099] In a specific embodiment, the clock generation circuit 14 and the clock recovery circuit 15 are as Figure 11As shown, the sampling method of the present invention is half-rate sampling, which requires sampling both the edge phase information and the data information of the data, and performing deserialization and speed reduction processing on the obtained data. In order to achieve the accuracy of the sampling position and the generation of the half-rate sampling method, therefore, a multi-phase clock with relatively accurate phase accuracy needs to be generated in the receiver, and the relative position of the clock and the data needs to be corrected, that is, a high jitter tolerance clock and data recovery circuit. In the present invention, the four-phase clock generation method mainly uses a symmetric current PI interpolation based on a digital control codeword to generate an accurate four-phase clock. The sampled and deserialized data and the edge information are sent to a Bang-Bang phase detector to identify the phase, and then the phase lead and lag information are obtained after maximum decision logic accumulation and summation. A digital low-pass filter is added to eliminate the output jitter. The phase interpolator controller accumulates the UP / DN signals to give the control codeword of the current-type PI, and adjusts the corresponding current weights to interpolate and synthesize a low-jitter and accurate four-phase clock through PI.

[0100] The phase interpolator controls the phase value of the synthesized signal by changing the amplitude ratio of the interpolation signal. It realizes the conversion from digital control code to continuous phase, so it has very high requirements for the linearity of the conversion. In the present invention, a design based on current-type switches is adopted, the input differential pair is increased to four groups to improve the overall linearity, and at the same time, the phase is changed by the current switch synthesis method. The entire PI structure is as Figure 12 shown. After receiving the input four-phase clock, the quadrant of the selected phase is determined under the control of the coarse adjustment codeword MUX_P0, MUX_N0, MUX_P1, and MUX_N1. On this basis, the number of incorporated switches of the minimum weight current array s0 to Sn is controlled by the digital codeword, so as to adjust the current weights of different branches, and then continue to interpolate and synthesize an accurate phase within the phase quadrant. At the same time, a filter capacitor is added at the output to filter out high-order harmonics and improve the PI linearity.

[0101] In summary, in a specific embodiment, the ultra-high-speed and ultra-short-range serial receiver can adopt as Figure 13The structure shown. To restore the integrity of the signal transmitted through the wired channel, the receiver mainly solves problems such as high-frequency attenuation of the signal transmitted through the low-pass channel, deserialization and speed reduction of high-speed serial data, and signal quality of high signal-to-noise ratio. Therefore, the receiver part mainly consists of an equalization module with high-pass characteristics, an alternating sampling module for high-speed serial data, a multi-stage parallel-to-serial module, and a multi-phase clock generation and recovery module with high jitter tolerance. Based on the traditional SerDes receiver architecture, the present invention designs various key functional modules based on the half-rate sampling mode to receive high-speed serial signals for extremely short-distance transmission. Among them, the analog front-end part mainly consists of impedance matching, AC coupling, and an adjustable continuous-time linear equalizer (CTLE, i.e., Continuous Time Linear Equalizer), which forms an impedance match with the channel, can isolate DC signals, establish an adjustable common-mode signal, and provide a certain degree of equalization to cope with the high-frequency attenuation of the channel; the sampling part is implemented by a current-mode (CML, i.e., Current Mode Logic) master-slave flip-flop type static comparator for alternating sampling; the 4:64 channel serial-to-parallel module (DEMUX, i.e., Demultiplexer) is composed of a multi-stage cascade of 1T0 2 deserializers based on trigger-type frequency division control; the multi-phase clock generation and clock recovery circuit mainly consists of a digital clock and data recovery (CDR, i.e., Clock and Data Recovery) tracking loop with two symmetric current-mode phase interpolators (PI, i.e., Phase Interpolator) with high jitter tolerance, which interpolates to generate a four-phase clock with high phase accuracy and drives it to each module to work after step-by-step transmission and level mode conversion.

[0102] Through the above technical solution of the present invention, in this way, problems such as high-frequency attenuation, inter-symbol interference, and signal reception in short-distance wired transmission of electrical signals are solved. Compared with the traditional receiver solution, the receiver solution of the present invention has an accurate multi-phase clock generation and recovery loop while providing a certain degree of equalization ability, saving power while increasing the data rate.

[0103] Figure 14 The flowchart of the method for receiving ultra-high-speed extremely short-distance serial data according to an embodiment of the present application is shown.

[0104] As Figure 14 shown, in the second aspect, the embodiment of the present application provides a method for receiving ultra-high-speed extremely short-distance serial data, including:

[0105] Step S1401, perform impedance matching, AC coupling, and linear equalization processing on the received high-speed extremely short-distance serial data to obtain the processed high-speed extremely short-distance serial data;

[0106] Step S1402: Under the control of a multi-phase clock, alternately sample the edge phase information and data center information of the processed high-speed very short-distance serial data to obtain high-speed serial sampled data;

[0107] Step S1403: Deserialize the high-speed serial sampled data into multiple paths of parallel low-speed data;

[0108] Step S1404: Generate and output a multi-phase clock with high precision and low jitter;

[0109] Step S1405: Correct the relative positions of the multiple paths of parallel low-speed data and the multi-phase clock to output a multi-phase clock with low jitter.

[0110] In a third aspect, a chip device is provided, including the parallel CRC error detection device according to any one of the embodiments in the first aspect.

[0111] It should be understood that the term "and / or" used herein is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0112] It should be understood that although terms such as first and second may be used to describe the setting units in the embodiments of the present application, these setting units should not be limited to these terms. These terms are only used to distinguish the setting units from each other. For example, without departing from the scope of the embodiments of the present application, the first setting unit may also be referred to as the second setting unit, and similarly, the second setting unit may also be referred to as the first setting unit.

[0113] Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to determining" or "in response to detecting". Similarly, depending on the context, the phrase "if determined" or "if detected (stated condition or event)" may be interpreted as "when determined" or "in response to determining" or "when detected (stated condition or event)" or "in response to detecting (stated condition or event)".

[0114] In several embodiments provided in this application, it should be understood that the disclosed systems, systems, and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections between each other can be through some interfaces. The indirect couplings or communication connections of systems or units can be in electrical, mechanical, or other forms.

[0115] In addition, in each embodiment of this application, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of a combination of hardware and software functional units.

[0116] Those of ordinary skill in the art can understand that all or part of the processes of implementing the above method embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above method embodiments. Among them, any reference to a memory, storage, database, or other medium used in each embodiment provided in this application can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0117] The above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A super-high-speed and ultra-short-distance serial receiver, characterized in that, Comprising: An analog front-end circuit for impedance matching, AC coupling, and linear equalization processing of received high-speed very short-range serial data to obtain processed high-speed very short-range serial data; A static comparator connected to the analog front-end circuit for alternately sampling the edge phase information and data center information of the processed high-speed very short-range serial data under the control of a multi-phase clock to obtain high-speed serial sampled data; A deserialization circuit connected to the static comparator for deserializing the high-speed serial sampled data into multiple paths of parallel low-speed data; A clock generation circuit connected to the static comparator for generating a high-precision, low-jitter multi-phase clock and outputting the multi-phase clock to the static comparator; A clock recovery circuit connected between the output end of the deserialization circuit and the clock generation circuit for correcting the relative positions of the multiple paths of parallel low-speed data and the multi-phase clock to track the optimal sampling point.

2. The ultra-high speed and extremely short-distance serial receiver according to claim 1, characterized in that, The analog front-end circuit includes: An impedance matching unit including a programmable adjustable resistor array for channel impedance matching of the high-speed very short-range serial data; An AC coupling unit connected to the impedance matching unit, including a high-pass filter composed of a capacitor and a variable resistor, for DC filtering and common-mode parameter adjustment of the high-speed very short-range serial data; A linear equalization unit connected to the AC coupling unit for high-frequency amplification of the high-speed very short-range serial data to compensate for high-frequency signal attenuation generated by the channel.

3. The ultra-high speed and extremely short-distance serial receiver according to claim 2, characterized in that, The linear equalization unit includes a continuous-time linear equalizer, and the continuous-time linear equalizer includes: A source negative feedback resistor array for controlling the switching of a switching transistor according to a control word to adjust the resistance value incorporated into the circuit; A source negative feedback capacitor array connected in parallel with the source negative feedback resistor array for controlling the switching of a switching transistor according to a control word to adjust the capacitance value incorporated into the circuit to adjust the position of the zero-pole pair by adjusting the resistance value and capacitance value; An adjustable load resistor for coping with PVT variations and slightly adjusting the bandwidth; A current-mode digital-to-analog converter connected between two ground terminals of the continuous-time linear equalizer for adjusting the tail current, adjusting the transconductance of the circuit, and maintaining the consistency of the output swing when the adjustable load resistor is adjusted.

4. The ultra-high speed and ultra-short distance serial receiver according to claim 3, characterized in that, The source negative feedback resistor array includes multiple paths of parallel-connected resistor strings; Each resistor string includes a switching transistor and a first resistor and a second resistor respectively connected to the input end and output end of the switching transistor. Among them, the resistance values of the first resistor and the second resistor are the same, and the resistance values of the resistors in different resistor strings are the same or different.

5. The ultra-high speed and ultra-short distance serial receiver according to claim 3, characterized in that, The source negative feedback capacitor array includes multiple paths of parallel-connected capacitor strings; Each capacitor string includes a first capacitor, a second capacitor connected in series, and a switch group connected between the first capacitor and the second capacitor. Among them, the switch group includes a first MOS group, a second MOS group, and a switching transistor; Wherein, the first MOS group and the second MOS group are connected in parallel, and the switching transistor is connected between the first MOS group and the second MOS group; The first MOS group and the second MOS group include a PMOS transistor and an NMOS transistor connected in series.

6. The ultra-high speed and ultra-short distance serial receiver according to claim 1, wherein The clock recovery circuit includes: a Bang-Bang phase detector for performing phase discrimination on the edge phase information and data center information in the low-speed data to determine the phase relationship; a voting accumulator connected to the Bang-Bang phase detector for performing voting accumulation summation according to the phase relationship to determine the phase lead information and phase lag information; a low-pass filter connected to the voting accumulator for filtering; a phase difference detector connected to the low-pass filter for accumulating the rising signal and the falling signal through PI control logic, outputting the control codeword of the current-mode PI, and outputting a multi-phase clock with low jitter by adjusting the corresponding current weights.

7. The ultra-high speed and extremely short distance serial receiver according to claim 1, characterized in that, The static comparator includes a master-slave flip-flop using CML logic.

8. The ultra-high speed and ultra-short distance serial receiver according to claim 1, characterized in that, The deserialiser includes: two inverters, a latch, and a master-slave flip-flop cascaded by transmission gates, for performing differential sampling and delay alignment on the high-speed serial sampled data, decomposing the high-speed serial sampled data into two paths of aligned parallel data output, and at the same time reducing the data rate to half of the original.

9. A receiving method for ultra-high-speed and extremely short-distance serial data, characterized in that, For the ultra-high-speed very short-reach serial receiver according to any one of claims 1 to 8, the method includes: performing impedance matching, AC coupling, and linear equalization processing on the received ultra-high-speed very short-reach serial data to obtain the processed ultra-high-speed very short-reach serial data; alternately sampling the edge phase information and data center information of the processed ultra-high-speed very short-reach serial data respectively under the control of a multi-phase clock to obtain high-speed serial sampled data; deserializing the high-speed serial sampled data into multiple paths of parallel low-speed data; generating and outputting a multi-phase clock with high precision and low jitter; correcting the relative positions of the multiple paths of parallel low-speed data and the multi-phase clock to track the optimal sampling point.

10. A chip device, characterized in that, including: the ultra-high-speed very short-reach serial receiver according to any one of claims 1 to 8.

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