Cascaded dual loop phase locked loop (PLL) for reduced phase noise and improved tuning range

Abstract

A cascaded phase-locked loop (PLL) architecture including a voltage-controlled oscillator (VCO) can operate in the millimeter wave and terahertz range. The architecture may include a low jitter type II radio frequency PLL as a first stage and a broadband high frequency dual path PLL as a second stage. By using the radio frequency output of the first stage as a reference, the second stage attenuates the VCO phase noise, resulting in reduced total jitter. Further, the first stage may include an AC coupled charge pump to ensure robust phase noise performance over a wide VCO control voltage range, and a VCO tuning range design may be provided to achieve a wide tuning range without sacrificing jitter performance.

Description

Cross Reference to Related Applications

[0001] This patent application claims priority to U.S. Provisional Patent Application No. 63 / 637,898, filed April 24, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to phase-locked loops (PLLs). In particular, embodiments of the present disclosure relate to cascaded PLLs operating in the millimeter wave (mmWave) and terahertz (THz) ranges. BACKGROUND

[0003] PLLs can be used in various application scenarios. For example, PLLs can be integrated in wired transceiver integrated circuits (ICs) to provide a clean clock for synchronous high-speed data transmission. In addition, PLLs can also be integrated in mmWave transceiver circuits to provide a local oscillator (carrier) signal with very low phase noise. The function of a PLL is to generate an output signal whose frequency is exactly N times the reference frequency generated by a crystal oscillator, where N is an integer. A PLL is usually constructed as a loop including a voltage-controlled oscillator (VCO), a phase detector, and a low-pass filter to help with frequency locking.

[0004] Locking the phase of a signal to a reference signal with a PLL can reduce phase noise. However, conventional charge pump (CP) designs for PLLs suffer from performance limitations caused by charge sharing and channel length modulation issues. Figure 1 An example of a conventional CP architecture is described. As shown in Figure 1 , the transconductance (Gm) of the CP remains relatively small to minimize noise. However, to better match, this requires M1 and M2 to have increased channel length. As a result, the mismatch current due to charge sharing from large parasitic capacitance (C par ) can reach the same level as the bias current of M1 and M2, especially when considering narrow charging pulses. In addition, the different turn-on / off transition times of the P and NMOS switches further exacerbate the mismatch current problem. These problems result in worsened phase noise due to the deviation of the sampling point in the phase detector from the maximum slope and the injection of additional charging current noise. That is, Figure 1 , V DMY ≠ V LF , the large parasitic capacitance (C par ) causes charge sharing (CS), and due to channel length modulation (CLM) effects, I UP ≠ I DNresulting in a deteriorated phase noise.

[0005] Furthermore, conventional voltage controlled oscillators (VCOs) of integrated phase-locked loops (PLLs) operating in the millimeter-wave and terahertz range face problems of phase noise deterioration and jitter. SUMMARY

[0006] In an example embodiment, the present disclosure provides a cascaded phase-locked loop (PLL) system. The cascaded PLL system includes a first stage comprising a type-II loop, wherein the first stage is configured to operate at a first operating frequency; and a second stage comprising a dual-path loop, wherein the second stage is configured to operate at a second operating frequency; wherein a ratio of the second operating frequency to the first operating frequency is an integer greater than 2.

[0007] In a further example embodiment, the type-II loop includes a voltage controlled oscillator, a phase detector, a charge pump, a second order loop filter, and a frequency divider.

[0008] In a further example embodiment, the dual-path loop includes a proportional path and an integral path.

[0009] In a further example embodiment, the proportional path includes a passive loop filter, and wherein the integral path includes a charge pump and a loop filter.

[0010] In a further example embodiment, the first stage includes a first voltage controlled oscillator having a first tuning range; wherein the second stage includes a second voltage controlled oscillator having a second tuning range; and wherein the second tuning range completely covers and is wider than the first tuning range.

[0011] In a further example embodiment, wherein the first stage includes an AC-coupled charge pump and a loop filter, wherein the AC-coupled charge pump is configured to isolate an output of the AC-coupled charge pump from the loop filter.

[0012] In a further example embodiment, the AC-coupled charge pump includes: an output; and an AC-coupled capacitor configured to isolate the output from the loop filter.

[0013] In a further example embodiment, the AC-coupled charge pump further includes: a level alignment loop disposed between the AC-coupled capacitor and the loop filter, the level alignment loop including a unity gain amplifier configured to align a direct current voltage level of the loop filter with a corresponding plate of the AC-coupled capacitor.

[0014] In further example embodiments, the AC-coupled charge pump further comprises: a dummy charge pump disposed between the output and the AC-coupling capacitor and configured to maintain a preset voltage level.

[0015] In further example embodiments, the preset voltage level corresponds to VDD / 2.

[0016] In further example embodiments, wherein the first stage comprises a first voltage controlled oscillator having a first tuning range, wherein a quality factor of an inductor-capacitor tank in the first voltage controlled oscillator is optimized for the first tuning range.

[0017] In further example embodiments, the first stage further comprises a frequency locked loop.

[0018] In further example embodiments, the first stage comprises: a first phase detector configured to receive a reference signal; an AC-coupled charge pump coupled to the first phase detector; a first loop filter coupled to the AC-coupled charge pump; a first voltage controlled oscillator coupled to the loop filter; and a first buffer coupled to the first voltage controlled oscillator and the first phase detector.

[0019] In further example embodiments, the second stage comprises: a reference buffer coupled to the first voltage controlled oscillator; a second phase detector coupled to the reference buffer; a second voltage controlled oscillator coupled to the second phase detector via a first path and a second path, wherein the first path comprises a passive loop filter and the second path comprises a charge pump and a loop filter; and a second buffer coupled to the second voltage controlled oscillator and the second phase detector.

[0020] In another example embodiment, the present disclosure provides an AC-coupled charge pump. The AC-coupled charge pump comprises: an output; an AC-coupling capacitor configured to isolate the output from a loop filter; and a level alignment loop disposed between the AC-coupling capacitor and the loop filter, the level alignment loop comprising a unity gain amplifier configured to align a direct current voltage level of the loop filter with a corresponding plate of the AC-coupling capacitor.

[0021] In further example embodiments, the AC-coupled charge pump further comprises: a dummy charge pump disposed between the output and the AC-coupling capacitor and configured to maintain a preset voltage level.

[0022] In further example embodiments, the preset voltage level corresponds to VDD / 2.

[0023] In another example embodiment, the present disclosure provides an AC-coupled charge pump. The AC-coupled charge pump includes an output, an AC-coupled capacitor configured to isolate the output from a loop filter, and a dummy charge pump disposed between the output and the AC-coupled capacitor, the dummy charge pump configured to hold a preset voltage level.

[0024] In a further example embodiment, the AC-coupled charge pump further includes a level alignment loop disposed between the AC-coupled capacitor and the loop filter, the level alignment loop including a unity gain amplifier configured to align a DC voltage level of the loop filter with a corresponding plate of the AC-coupled capacitor.

[0025] In a further example embodiment, the preset voltage level corresponds to VDD / 2. SUMMARY

[0026] Figure 1 An example of a conventional charge pump (CP) architecture is shown;

[0027] Figure 2A An example of the overall structure of a cascaded PLL according to example embodiments of the present disclosure is shown;

[0028] Figure 2B An example of the detailed architecture of a cascaded PLL according to example embodiments of the present disclosure is shown;

[0029] Figure 3 An example of an AC-coupled charge pump (ACCP) according to example embodiments of the present disclosure is shown;

[0030] Figure 4 An example simulation of CP output node voltage and charging current waveforms for an ACCP and a conventional CP according to example embodiments of the present disclosure is shown;

[0031] Figure 5 An example of a tuning range design scheme for two VCOs according to example embodiments of the present disclosure is shown;

[0032] Figure 6 An example implementation of a class-C VCO (part (a)), a VCO inductor (part (b)), and a VCO buffer (part (c)) of example embodiments of the present disclosure is shown;

[0033] Figure 7 An example of measured phase noise and integrated jitter of a cascaded PLL according to example implementations of the present disclosure is shown, the cascaded PLL including a first stage 7-GHz PLL and a second stage 28-GHz quadrature phase-locked loop (QPLL); and

[0034] Figure 8 An example comparison of measured phase noise of ACCP and conventional CP is shown. DETAILED DESCRIPTION

[0035] Exemplary embodiments of the present disclosure provide a cascaded PLL architecture that includes an AC-coupled charge pump (ACCP) in order to achieve reduced phase noise. Phase noise reduction is advantageous, for example, for providing accurate timing and signal stability in high-speed communication systems, as well as for enhancing signal quality, particularly for high-frequency wireless and radar systems that require clean, stable signals without undesired phase fluctuations.

[0036] In exemplary embodiments, a cascaded integrated phase-locked loop (PLL) architecture is provided for addressing phase noise degradation in a voltage-controlled oscillator (VCO) of an integrated phase-locked loop (PLL) operating in the millimeter wave (mmWave) and terahertz range. The PLL architecture includes a first stage (i.e., a low-jitter Type-II radio frequency PLL) and a second stage (i.e., a wideband high-frequency dual-path PLL). The Type-II PLL is characterized by a loop structure that includes a voltage-controlled oscillator (VCO), a phase detector, a charge pump, a second-order loop filter, and a frequency divider. The transfer function of the Type-II PLL contains two poles at the origin, which are contributed by the integral capacitors in the VCO and the second-order loop filter. By using the first-stage radio frequency output as a reference, the second stage attenuates the VCO phase noise, resulting in reduced total jitter. The ACCP ensures robust phase noise performance over a wide VCO control voltage range. Additionally, a VCO tuning range design scheme is provided to achieve a wide tuning range without sacrificing jitter performance. According to the provided PLL architecture, improvements in jitter performance as well as frequency tuning range of mmWave and terahertz PLLs can be achieved.

[0037] Figure 2AAn example of the overall structure of a cascaded PLL according to example embodiments of the present disclosure is shown. In the first stage 100, a radio frequency (RF) type II phase-locked loop (PLL) is employed to generate an output at Freq1 with low jitter and low spurs. In the first stage, "low jitter PLL" 100, a reference signal ("Ref") 102 is input to a phase detector (PD) 103 for phase detection. The output of the PD 103 is provided to an ACCP and loop filter (LF) ("ACCP + LF") 105. The ACCP addresses the issue of mismatch current and reduces the phase noise contribution. The frequency of the first VCO 109 is controlled by the output of the ACCP + LF 105, and the first VCO 109 outputs the result to a buffer 107, which further feeds the signal back to the PD 103. The VCO 109 also outputs a signal at the first frequency ("Freq1") to the second stage 101 (with jitter lower than 60 fs and spurs lower than -70 dBc). The frequency tuning range of the first VCO 109 is optimized so that the VCO can provide the best phase noise performance, e.g., achieving a phase noise-power figure of merit better than -190 dB.

[0038] The first stage PLL 100 is able to achieve low jitter through two factors. First, the VCO 109 in the first stage PLL operates in a low frequency range (e.g., lower than 10 GHz), which is much lower compared to the second stage millimeter wave (mmWave) or terahertz VCO. As a result, the inductor-capacitor tank (LC tank) in the first VCO 109 exhibits a significantly improved quality factor, which is mainly due to the improvement in the switchable capacitor bank. Second, as mentioned above, the ACCP addresses the issue of mismatch current and thus reduces the phase noise contribution from the mismatch current. The overall loop maintains a robust bandwidth over a wide range of VCO control voltage variations.

[0039] The first stage PLL 100 is also able to achieve low spur performance, which is mainly due to being a type II architecture, where the large integration capacitor in the ACCP + LF 105 along with the subsequent low pass filter helps to reduce the VCO control voltage variation due to charge pump.

[0040] Second-stage PLL 101 operates at a second frequency ("Freq2") that is higher than first frequency Freq1. Second frequency Freq2 can be N times the frequency of the first stage, where N is any integer greater than 2. The signal output by first-stage PLL 100 (at Freq1) is input to second-stage PLL 101 at reference buffer (RFBUF) 111. RFBUF 111 isolates coupling between the VCO and PD, which enhances drive capability. The output of RFBUF 111 is provided to PD 113 for phase detection. The output of PD 113 is provided to passive loop filter (Passive LF) 115 and charge pump (CP) + LF 117. Passive LF 115 is configured to filter the PD output and generate a stable voltage signal for controlling the VCO, and CP + LF 117 is configured to enhance the gain of the integrating path (CP converts the voltage signal from the PD into charge and discharge current signals, and LF then converts the charge and discharge currents back into the voltage domain). The two signals output from the passive LF 115 and the CP+LF 117 are provided to the second VCO 121 for frequency tuning to obtain an output signal at Freq 2. The output signal of the VCO 121 at Freq 2 is provided to a buffer (BUF) 119, which isolates the coupling between the VCO and the PD to enhance the driving capability, and the output of the BUF 119 is fed back to the PD 113 to form a closed loop to achieve phase locking.

[0041] Second-stage PLL 101 utilizes a dual-path architecture consisting of a passive proportional path and an integral path. This implementation offers two advantages. First, the passive proportional path exhibits lower in-band phase noise compared to active implementations. Second, the integral path is solely responsible for capturing frequency errors. Therefore, a small charge pump gain is sufficient for this function, enabling the use of small, area-efficient integrated capacitors for the loop filter in passive LF 115 and CP+LF 117. Because the frequency error is captured entirely by the integral path, the phase detector (PD) gain can be significantly increased, which helps achieve a large PLL loop bandwidth, effectively attenuating the phase noise contribution from second-stage VCO 121. Therefore, although second-stage VCO 121 operates at a high frequency and exhibits significantly greater phase noise than first-stage VCO 109, the overall PLL jitter performance remains unaffected due to the wide bandwidth of second-stage PLL 101.

[0042] Figure 2BAn example of a detailed architecture of a cascaded PLL according to example embodiments of the present disclosure is shown. The first stage PLL includes a phase-locked loop (PLL) and an additional frequency-locked loop (FLL) that assists in the initial frequency locking process. In the phase-locked loop (PLL), a pulse generator (Pul. Gen.) 201 generates sampling pulses and charge pump pulses derived from a reference signal ("Ref") 200 for controlling a first phase detector ("PD") 203 and an AC coupled charge pump (ACCP) 205, respectively. In the frequency-locked loop (FLL), the output from a voltage controlled oscillator (VCO) 209 is AC coupled to a resistive feedback amplifier 211. By using a differential to single-ended converter (D2S) 213, the output of the AC coupled amplifier is converted to a single-ended signal to feed into a subsequent multi-modulus divider (MMD) 215. The MMD 215 operates digitally and takes a single-ended input. It is used to adjust the multiplication ratio between the VCO frequency and the reference frequency. A phase and frequency detector (PFD) with dead zone (DZ), denoted as "PFD+DZ" 217, is used to facilitate wide range frequency error detection between the reference signal (Ref.) and the output of the MMD 215.

[0043] The output from the PFD+DZ 217 in the FLL is fed to the FLL CP (FLL charge pump) 218 to charge the loop filter. The PLL and FLL interact through a dual-branch loop filter 219. This dual-branch loop filter 219 enables separate optimization of the stabilization resistors for the PLL and FLL, respectively. Since the phase detector of the PFD (part of PFD+DZ 217) for the FLL is significantly smaller than the phase detector 203 for the PLL, employing a larger stabilization resistor for the FLL and a smaller stabilization resistor for the PLL can enhance the phase margin and phase noise performance of both loops.

[0044] The output of the first stage is amplified by a buffer 225 and used as a reference signal for a second stage PLL ("PLL2"). The center frequency of the second stage PLL is N times the center frequency of the first stage PLL, where N is an integer typically in the range of 2 to 10. For example, if the frequency of the first stage PLL is configured to be 7 GHz, the frequency of the second stage PLL can be designed to be 14 GHz, 21 GHz, 28 GHz, or even higher, depending on the specific requirements and system constraints.

[0045] While the first stage output frequency falls within a few GHz, the second stage is designed to support a wide bandwidth up to tens of MHz or even beyond 100 MHz, even when a passive scaling path is used. To address the frequency error between the reference signal and the VCO, an integral path is incorporated. The integral path includes an integral charge pump (I-CP) 237 that charges a capacitor C I1 , CI2 、R I The CRC loop filter is charged and discharged. The I-CP 237 and CRC combination provides high open-loop gain at low frequencies, enabling the capture of frequency errors. By tracking these frequency errors through the integral path, the gain of the proportional path can be maximized, allowing for a wide loop bandwidth. This configuration ensures that the second stage maintains a robust and wide loop bandwidth even in the presence of significant initial frequency errors. In the feedback path, an inverter-based buffer with a peaking inductor is used to generate sufficiently large swings in the feedback signal. This large swing enhances the loop bandwidth, helping to improve overall performance.

[0046] For measurement purposes, the phase noise of the first-stage PLL and the second-stage PLL were characterized separately. In the first stage, an output buffer (OBUF) 223 is used to boost the signal strength at the VCO output and bring it off-chip for measurement. In the second stage, the signal from the second-stage VCO 229, the overall output of the cascaded PLLs, is first buffered by a buffer (Buf) 231, then divided by 4 using a divide-by-4 module ("DIV4") 233, and finally routed to the off-chip measurement interface via another output buffer (Buf) 235. The divide-by-4 module DIV4 233 reduces the output frequency, simplifying the output signal distribution and reducing signal loss during the distribution process. The output of VCO 229 is also provided to VCO 227 and fed back into two paths. VCO buffer 227 is designed with a resistive feedback topology and integrates a shunt inductor to widen its operating bandwidth. This buffer isolates the proportional and integral paths from the VCO, thereby protecting the VCO's phase noise and spurious performance.

[0047] Figure 3 An example of an ACCP according to an exemplary embodiment of the present disclosure is shown. The drain nodes of M1 and M2 are directly connected without using separate P and NMOS switches. Instead, switches SW1 to SW3 are implemented using transmission gates to eliminate switching time differences. The ACCP includes a coupling capacitor (C AC ) to V CPO (VCO output voltage) and V LF (loop filter voltage) isolated. and means Figure 2B The charging pulse (PUL CP ) positive and negative phases. When the charging pulse PUL CP When turned off, the rail-to-rail amplifier (RRAMP) 301 in unity-gain feedback configuration switches V ACO (VCO output voltage) is aligned with VLF, while the dummy charge pump (CP) maintains VCPO Close to VDD / 2 (ie, close to half of the power supply voltage). CP When turned on, capacitor C AC and loop filter 303 form a much lower impedance path, allowing the charging current to flow into the loop filter without interfering with V CP0 By aligning the voltage across SW1 to be equal and maintaining V CP0 Close to VDD / 2, the charge sharing and channel length modulation problems can be effectively alleviated. Figure 3 In the feedback control, V ACO =V LF ,and Figure 3 V in CPO =V DMY And they are all close to VDD / 2 (established with the help of dummy fill SSCP), thus alleviating the offset charging current caused by charge sharing and channel length modulation, and increasing the SSPD gain and reducing the current noise of the conventional charge pump (CP), thereby improving the phase noise.

[0048] Figure 4 Example simulations of the CP output node voltage and charging current waveforms for the ACCP and a conventional CP are shown. According to the exemplary implementation, this post-layout simulation was performed to verify the performance of the ACCP. In the simulation setup, the differential inputs of the ACCP and the conventional CP were set to be identical. Therefore, ideally, the CP should not generate any output charging current. By sweeping the differential output loop filter voltage, Figure 4 The simulation waveform in Figure 2 shows that V CPO is kept constant at 0.47V, while V ACO Precisely with 0.8V V LF In contrast, when SW1 is turned on, the conventional source-switched charge pump (SSCP) outputs V CPO is immediately pulled to V LF The simulated output currents in parts (C) and (D) show that compared with the conventional SSCP, when V LF When set to 0.2 and 0.8V, AC-SSCP effectively suppresses the offset current. Figure 4 As shown in part (A), the ACCP output node voltage is always close to VDD / 2 and is not affected by V LF Influence; Figure 4 In part (B), when charging starts, the output voltage of the conventional CP needs to first reach V LF ; Figure 4 In part (C), when V LFAt extreme voltage values ​​(often caused by a large deviation between the oscillator's starting frequency and the final locked frequency), the ACCP's output current offset remains minimal; in comparison, Figure 4 In the part (D), V LF At extreme voltage values, traditional CPs experience large current imbalance.

[0049] When cascading two loops, tuning range misalignment may occur between the first and second stage PLLs, which may result in a reduced overall tuning range. To address this issue, exemplary embodiments of the present disclosure further provide a tuning range design scheme for the first and second VCOs to ensure sufficient tuning range without degrading overall phase noise performance.

[0050] Figure 5 FIG. 2 shows an example of a tuning range design scheme for two VCOs (VCO1 and VCO2) according to an exemplary embodiment of the present disclosure. Figure 5 As shown, VCO1 has a tuning range of approximately 20% or less for better phase noise performance; VCO2's tuning range fully covers that of VCO1, with additional margin to accommodate PVT variations. Although increasing the tuning range of both VCO1 and VCO2 could enhance the overall tuning range, this approach would degrade the quality factor of the switchable capacitor bank and result in higher jitter. Because the wideband of the second-stage PLL can adequately attenuate VCO2's phase noise, tuning range optimization can be performed as described below.

[0051] First, the frequency tuning range of the first-stage VCO is established to meet the target application requirements. This is achieved through an appropriate implementation of the inductor-capacitor resonant tank. The inductor value is chosen based on a trade-off between power consumption and phase noise: smaller inductor values ​​improve phase noise but increase overall power consumption. After selecting the inductor, the capacitor bank tuning range is determined to support the desired frequency tuning range with additional margin to accommodate PVT variations. Subsequently, the tuning range of the second-stage VCO is determined. This tuning range should be wide enough to fully cover the tuning range of the first-stage, ensuring that the tuning range of the first-stage VCO is not wasted. Although a wide tuning range can degrade phase noise, the cascaded architecture allows the wide bandwidth of the second-stage PLL to control the degraded phase noise of the VCO. This design ensures a wide overall PLL tuning range and low overall phase noise, which is primarily determined by the first-stage PLL.

[0052] Figure 6 FIG2 shows an exemplary implementation of a Class C VCO (part (a)), a VCO inductor (part (b)), and a VCO buffer (part (c)) of an exemplary embodiment of the present disclosure. Figure 6As shown in part (a) of the diagram, a Class C topology is used for the first-stage PLL to achieve better phase noise. The noise injection window of the active MOSFET device in each cycle is narrower than that of a Class B VCO. The bias level can be optimized to achieve better phase noise. When the first-stage VCO operates in the GHz band, the inductor quality factor is important to maintain good phase noise.

[0053] Figure 6 The inductor for the VCO shown in part (b) of FIG5 is designed to have a compact area and a short signal return path. The active devices (-gm core, negative transconductance core) that are usually placed outside the inductor are integrated within the inductor area. This integration helps minimize the parasitic resistance associated with the interconnect metal and reduce the overall VCO chip area. In addition, the power wiring (shown as vertical gray lines starting from VSS and VDD to the active devices (-gm core)) is routed directly under the inductor at the center. This wiring method achieves symmetrical and direct power distribution. The power wiring provides a clear return path for the oscillating signal to return to VDD and VSS, ensuring the shortest possible return path. In addition, because the power wiring is located at the AC ground of the inductor, its impact on the quality factor of the inductor can be ignored.

[0054] VCO buffer such as Figure 6 As shown in part (c) of . The VCO differential output is fed into INP and INN, driving the input transistors M1, M2, M9 and M12. After being amplified by the buffer, the signal is output from ON and OP and enters the next stage. The VCO buffer is designed to achieve high output swing and wide bandwidth through three key technologies. First, the cascaded P / NMOS transistors (M5-M8) isolate the input and output nodes of the buffer, effectively decoupling the VCO from the phase detector and minimizing the spurious signals caused by feedback. Secondly, two pairs of -gm transistors (M3-M4 and M10-M11) are incorporated to enhance the bandwidth, enabling the buffer to effectively handle high-frequency signals. Finally, the gate node of the P / NMOS-gm pair is connected to the low-resistance source node of the cascaded devices on opposite sides of the differential topology, allowing the buffer to accommodate significant parasitic capacitance without degrading bandwidth performance.

[0055] Figure 7 An example of measured phase noise and integrated jitter of a cascaded PLL comprising a first stage 7-GHz PLL and a second stage 28-GHz quadrature phase-locked loop (QPLL) according to an exemplary implementation of the present disclosure is shown. The cascaded PLL comprises a 7 GHz first stage PLL cascaded with a second stage 28 GHz QPLL. With a 250-MHz reference, Figure 7Figure 3 shows the measured phase noise of the free-running (FR) 7-GHz VCO, 28-GHz VCO div-4, 7-GHz PLL, and 28-GHz PLL div-4 outputs. Integrating from 1kHz to 30MHz, the 7-GHz and 28-GHz PLLs achieve integrated rms jitter of 54.43 and 56.8 fs, respectively. The first-stage PLL phase noise (PN) curve is smooth and lacks PN peaking, demonstrating sufficient loop bandwidth. Only when the offset frequency reaches 100MHz does the 28-GHz PLL PN curve converge with the 28-GHz FR VCO, validating the wide loop bandwidth provided by the second-stage dual-path (DP) PLL.

[0056] Figure 8 An example comparison of the measured phase noise of ACCP and traditional CP is shown. LF ACCP performance at VDD CP When V is equal to 1.1V, adjust the 7-GHz VCO capacitor bank control code until V LF The on-chip switch can be turned on to enable ACCP, or turned off to short the AC coupling capacitor and disconnect the main SSCP and pseudo SSCP, which then becomes a traditional SSCP topology. Figure 8 As shown, when V LF When V is equal to 0.45V, ACCP and conventional CP show almost the same performance. However, conventional CP has a significantly reduced loop bandwidth due to the reduced phase detection (PD) gain, and LF The PN is degraded when the voltage is equal to 0.16 and 0.92 V. For ACCP, the PN distribution and jitter only show a change of 6.95 fs from 57.28 to 64.23 femtoseconds (fs).

[0057] It should be understood that the various machine-implemented processes and steps described herein may be performed by one or more corresponding processors executing processor-executable instructions stored on one or more tangible, non-transitory computer-readable media (such as random access memory (RAM), read-only memory (ROM), programmable read-only memory (PROM), and / or other electronic storage mechanisms. For example, the operations performed by the various components discussed herein may be implemented according to instructions stored on one or more corresponding computing devices and / or applications installed on such devices.

[0058] All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.

[0059] The use of the terms "the" and "at least one" and similar referents in the context of describing the application (especially in the context of the following claims) are to be interpreted in accordance with their ordinary meanings in the art unless otherwise indicated otherwise or clearly contradicted by context. The use of the term "at least one" followed by a list of one or more items (for example, "at least one of A and B") is to be interpreted as meaning one item from the list A or B or any combination of items from the list A and B, unless otherwise indicated or clearly contradicted by context. The terms "comprising," "having," "including," and "containing" are to be construed as open-ended terms (i.e., meaning "including, but not limited to,") unless otherwise noted. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated in the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended merely to better illuminate the application and does not pose a limitation on the scope of the application unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the application.

[0060] Preferred embodiments of this application are described herein, including the best mode known to the inventors of practicing the application. Variations of these preferred embodiments as they occur to those of ordinary skill in the art are not to be excluded unless otherwise noted. The inventors expect expert artisans to employ such variations as appropriate, and the inventors intend the application to be practiced otherwise than is specifically described herein. Accordingly, the application includes all modifications and equivalents of the subject matter recited in the claims appended hereto as permitted by applicable law. Moreover, any combination of the elements described above can be claimed as a preferred embodiment of the application, unless otherwise indicated or clearly contradicted by context.

Claims

1. A cascaded phase-locked loop (PLL) system comprising: a first stage comprising a type-II loop, wherein the first stage is configured to operate at a first operating frequency; and a second stage comprising a dual-path loop, wherein the second stage is configured to operate at a second operating frequency; wherein a ratio of the second operating frequency to the first operating frequency is an integer greater than 2.

2. The cascaded PLL system of claim 1, wherein the type-II loop comprises a voltage controlled oscillator, a phase detector, a charge pump, a second order loop filter, and a frequency divider.

3. The cascaded PLL system of claim 1, wherein the dual-path loop comprises a proportional path and an integral path.

4. The cascaded PLL system of claim 3, wherein the proportional path comprises a passive loop filter, and the integral path comprises a charge pump and a loop filter.

5. The cascaded PLL system of claim 1, wherein the first stage comprises a first voltage controlled oscillator having a first tuning range; wherein the second stage comprises a second voltage controlled oscillator having a second tuning range; and wherein the second tuning range completely covers and is wider than the first tuning range.

6. The cascaded PLL system of claim 1, wherein the first stage comprises an AC coupled charge pump and a loop filter, wherein the AC coupled charge pump is configured to isolate an output of the AC coupled charge pump from the loop filter.

7. The cascaded PLL system of claim 6, wherein the AC coupled charge pump comprises: an output; and an AC coupling capacitor configured to isolate the output from the loop filter.

8. The cascaded PLL system of claim 7, wherein the AC coupled charge pump further comprises: a level alignment loop disposed between the AC coupling capacitor and the loop filter, the level alignment loop comprising a unity gain amplifier configured to align a DC voltage level of the loop filter with a corresponding plate of the AC coupling capacitor.

9. The cascaded PLL system of claim 7, wherein the AC coupled charge pump further comprises: a dummy charge pump disposed between the output and the AC coupling capacitor and configured to maintain a preset voltage level.

10. The cascaded PLL system of claim 9, wherein the preset voltage level corresponds to VDD / 2.

11. The cascaded PLL system of claim 1, wherein the first stage comprises a first voltage controlled oscillator having a first tuning range, wherein a quality factor of an inductor capacitor tank in the first voltage controlled oscillator is optimized for the first tuning range.

12. The cascaded PLL system of claim 1, wherein the first stage further comprises a frequency locked loop.

13. The cascaded PLL system of claim 1, wherein the first stage comprises: a first phase detector configured to receive a reference signal; an AC coupled charge pump coupled to the first phase detector; and a first voltage controlled oscillator coupled to the AC coupled charge pump. a first loop filter coupled to the AC-coupled charge pump; a first voltage controlled oscillator coupled to the loop filter; and a first buffer coupled to the first voltage controlled oscillator and the first phase detector.

14. The cascaded PLL system of claim 13, wherein the second stage comprises: a reference buffer coupled to the first voltage controlled oscillator; a second phase detector coupled to the reference buffer; a second voltage controlled oscillator coupled to the second phase detector via a first path and a second path, wherein the first path comprises a passive loop filter and the second path comprises a charge pump and a loop filter; and a second buffer coupled to the second voltage controlled oscillator and the second phase detector.

15. An AC-coupled charge pump, comprising: an output; an AC-coupling capacitor configured to isolate the output from a loop filter; and a level alignment loop disposed between the AC-coupling capacitor and the loop filter, the level alignment loop comprising a unity gain amplifier configured to align a DC voltage level of the loop filter with a corresponding plate of the AC-coupling capacitor.

16. The AC-coupled charge pump of claim 15, further comprising: a dummy charge pump disposed between the output and the AC-coupling capacitor and configured to maintain a preset voltage level.

17. The AC-coupled charge pump of claim 16, wherein the preset voltage level corresponds to VDD / 2.

18. An AC-coupled charge pump, comprising: an output; an AC-coupling capacitor configured to isolate the output from a loop filter; and a dummy charge pump disposed between the output and the AC-coupling capacitor and configured to maintain a preset voltage level.

19. The AC-coupled charge pump of claim 18, further comprising: a level alignment loop disposed between the AC-coupling capacitor and the loop filter, the level alignment loop comprising a unity gain amplifier configured to align a DC voltage level of the loop filter with a corresponding plate of the AC-coupling capacitor.

20. The AC-coupled charge pump of claim 18, wherein the preset voltage level corresponds to VDD / 2.

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