An ASK 100% modulation communication system and method applied to passive NFC tags

Abstract

The application discloses an ASK 100% modulation communication system and method applied to a passive NFC tag. The application generates a recovered clock signal by introducing a high-precision digital control oscillator circuit, uses a carrier clock signal for timing control in a signal receiving process of the NFC tag, and switches to the recovered clock signal for timing control in a signal sending process, so that the passive NFC tag has a stable clock source during clock loss of ASK 100% modulation, and the normal work of a digital circuit can be ensured. Meanwhile, the application also introduces a digital clock calibration circuit, has relatively small area and power consumption under the premise of ensuring calibration frequency, and is more suitable for the development trend and requirement of low power consumption and low cost of the passive NFC tag. The application realizes the communication of the passive NFC tag with a PCD by using ASK 100% for load modulation, greatly improves the anti-interference ability of a signal, can optimize the requirement for a minimum antenna coupling coefficient k, optimizes the geometric alignment requirement of an antenna, and improves the long-distance communication ability of the tag.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to an ASK100% modulation communication system and method for passive NFC tags. Background Technology

[0002] NFC is a contactless information transmission technology widely used in finance, identity verification, and logistics warehousing. With the rapid development of modern socio-economic activities and technological advancements, data exchange between readers and transponders faces significant challenges. They need to communicate at high speed, accurately, and securely in environments filled with electromagnetic noise. Electromagnetic interference in such environments severely threatens the accuracy and stability of data transmission. Communication errors or data loss can not only lead to economic losses but also damage the brand reputation and customer loyalty of financial institutions. Therefore, in such scenarios, improving the anti-interference performance of chips and ensuring accurate communication is extremely necessary.

[0003] Conventional passive NFC transponders to readers employ passive modulation, which relies on a carrier signal. Passive NFC tags return signals via load modulation. The load modulation circuit selects whether to connect a resistor based on the 0 or 1 of the load modulation signal, thus affecting the amplitude of the carrier wave on the antenna. Information is transmitted through this amplitude difference. During this process, a stable clock input must be ensured to maintain the normal operation of the tag's internal digital circuitry.

[0004] Non-ASK 100% load modulation of tags has advantages such as ease of implementation and good continuity. However, its disadvantages include a more complex ASK demodulation circuit at the receiver, limited signal anti-interference capability, and increased demodulation difficulty for the reader due to insignificant amplitude differences during long-distance transmission, potentially leading to communication failure. Conversely, under ASK 100% modulation communication, the transponder cannot receive a stable clock signal input, thus failing to maintain the normal operation of the tag's internal digital circuitry and maintain the output of the response signal. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide an ASK100% modulation communication system and method for passive NFC tags.

[0006] The first aspect of this invention provides an ASK100% modulation communication system for passive NFC tags, comprising:

[0007] A clock extraction circuit is used to extract a carrier clock from a carrier signal and use the carrier clock to maintain the working timing of the NFC tag during signal reception.

[0008] The ASK demodulation circuit is used to acquire the binary encoded signal from the reader transmitted in the radio frequency field.

[0009] A decoding module is used to decode the binary encoded signal transmitted by the ASK demodulation circuit to obtain instruction data;

[0010] The response control module is used to generate a binary original code signal for responding to the reader based on the instruction data obtained by the decoding module;

[0011] A numerically controlled oscillator circuit is used to generate a recovery clock signal, and the recovery clock signal is used to maintain the working timing of the NFC tag when transmitting signals;

[0012] A digital clock calibration circuit, wherein the digital clock calibration circuit is used to calibrate the recovered clock signal;

[0013] The encoding module is used to encode the binary original code signal to generate a baseband signal;

[0014] A subcarrier modulation module is used to perform subcarrier modulation on the baseband signal to generate a subcarrier modulated signal;

[0015] A load modulation circuit is used to modulate the amplitude of the carrier signal by 100% according to the subcarrier modulation signal, and generate a response signal to be sent to the reader.

[0016] Furthermore, the numerically controlled oscillator circuit includes:

[0017] A current mirror circuit is used to adjust the charging and discharging current of the oscillator capacitor to control the rate of voltage change of the oscillator capacitor, thereby adjusting the frequency of the recovered clock signal.

[0018] A comparator circuit is used to compare the difference between the voltage of the oscillator capacitor and the reference voltage, and to control the charging or discharging of the oscillator capacitor to generate a square wave signal.

[0019] The frequency divider circuit is used to reduce the frequency of the square wave signal output by the comparator circuit to obtain a recovery clock signal with a 50% duty cycle.

[0020] Furthermore, the current mirror circuit includes multiple current mirror branches; each current mirror branch consists of a PMOS transistor and an NMOS transistor; the base of the NMOS transistor is connected to a digital clock calibration circuit, and the digital clock calibration circuit outputs control words with different control bits to control the on / off state of the NMOS transistor in each current mirror branch, so as to adjust the charging and discharging current of the oscillator capacitor.

[0021] Furthermore, the digital clock calibration circuit includes:

[0022] A first counter is used to count the number of periods of a carrier signal;

[0023] The second counter is used to count the number of cycles of the recovery clock signal output by the numerically controlled oscillator circuit;

[0024] The judgment module is used to judge the quantitative relationship between the number of cycles counted by the first counter and the second counter, so as to generate a fast / slow judgment signal;

[0025] A calibration module is used to adjust the control word output to the numerically controlled oscillator circuit according to the speed judgment signal, so as to calibrate the recovered clock signal.

[0026] Furthermore, the second counter has a counting upper limit; when the second counter reaches the counting upper limit, the control word setting currently output to the numerically controlled oscillator circuit is saved, and it is determined that the recovery clock signal has completed calibration.

[0027] Furthermore, the quantitative relationship judgment performed by the judgment module is as follows: whether the number of cycles counted by the first counter is four times the number of cycles counted by the second counter; the target frequency of the recovered clock signal is a four-quarter frequency divider of the carrier signal clock period;

[0028] When the number of cycles counted by the first counter is greater than four times the number of cycles counted by the second counter, the judgment module outputs a slow judgment signal; the slow judgment signal indicates that the frequency of the recovered clock signal is lower than the target frequency.

[0029] When the number of cycles counted by the first counter is less than four times the number of cycles counted by the second counter, the judgment module outputs a fast judgment signal; the fast judgment signal indicates that the frequency of the recovered clock signal is higher than the target frequency.

[0030] When the number of cycles counted by the first counter is equal to four times the number of cycles counted by the second counter, and the second counter has not reached its upper limit, the judgment module determines that the current counting time is insufficient to distinguish the frequency of the recovery clock signal, does not output a speed judgment signal, and the two counters continue to work.

[0031] Furthermore, when the calibration module receives a slow judgment signal, it sets the control word currently output to the numerically controlled oscillator circuit to 1;

[0032] When the calibration module receives the fast judgment signal, it sets the control word currently output to the numerically controlled oscillator circuit to 0.

[0033] When the calibration module receives the calibration completion signal, it maintains the current control word set to 1, saves the current control word setting output to the CNC oscillator circuit, determines that the recovery clock signal has completed calibration, ends the calibration process in advance, and no further calibration is performed for subsequent control words.

[0034] The second aspect of the present invention discloses an ASK100% modulation communication method for passive NFC tags, which is applied to the ASK100% modulation communication system for passive NFC tags described in the first aspect, and includes a signal receiving process and a signal transmitting process.

[0035] The signal reception process specifically includes:

[0036] A clock extraction circuit is used to extract a carrier clock from the carrier signal, and the carrier clock is used to maintain the working timing of the NFC tag when receiving signals.

[0037] The ASK demodulation circuit is used to obtain the binary encoded signal from the reader transmitted in the radio frequency field;

[0038] The decoding module is used to decode the binary encoded signal transmitted by the ASK demodulation circuit to obtain instruction data;

[0039] The response control module generates a binary original code signal to respond to the reader based on the instruction data obtained from the decoding module;

[0040] The signal transmission process specifically includes:

[0041] A numerically controlled oscillator circuit is used to generate a recovery clock signal, and the recovery clock signal is used to maintain the working timing of the NFC tag when transmitting signals.

[0042] The recovered clock signal is calibrated using a digital clock calibration circuit;

[0043] The binary original code signal is encoded using an encoding module to generate a baseband signal;

[0044] The baseband signal is modulated using a subcarrier modulation module to generate a subcarrier modulated signal.

[0045] The load modulation circuit modulates the amplitude of the carrier signal by 100% according to the subcarrier modulation signal, and generates a response signal to be sent to the reader.

[0046] Furthermore, the recovery clock signal is generated through the following steps:

[0047] The current mirror circuit uses a control word with different control bits output by the digital clock calibration circuit to control the on / off state of the NMOS transistor in each current mirror branch, thereby adjusting the charging and discharging current of the oscillator capacitor.

[0048] A comparator circuit is used to compare the difference between the voltage of the oscillator capacitor and the reference voltage, and to control the charging or discharging of the oscillator capacitor to generate a square wave signal.

[0049] The square wave signal output by the comparator circuit is down-clocked using a frequency divider circuit to obtain a recovery clock signal with a 1 / 2 duty cycle.

[0050] Furthermore, the recovered clock signal is calibrated through the following steps:

[0051] The first counter is used to count the number of periods of the carrier signal;

[0052] The second counter is used to count the number of cycles of the recovered clock signal output by the numerically controlled oscillator circuit;

[0053] The judgment module is used to determine the quantitative relationship between the number of cycles counted by the first counter and the second counter, so as to generate a fast / slow judgment signal.

[0054] The calibration module adjusts the control word output to the numerically controlled oscillator circuit according to the speed judgment signal to achieve calibration of the recovered clock signal.

[0055] The embodiments of this invention have the following beneficial effects: By introducing a high-precision numerically controlled oscillator circuit to generate a recovery clock signal, this invention uses a carrier clock signal for timing control during the signal reception process of the NFC tag, and switches to the recovery clock signal for timing control during the signal transmission process. This achieves a stable clock source for the passive NFC tag during the clock loss period of ASK100% modulation, ensuring the normal operation of the digital circuit. Simultaneously, this invention also introduces a digital clock calibration circuit, which, while ensuring the calibration frequency, has a relatively small area and power consumption, making it more suitable for the development trend and requirements of low power consumption and low cost for passive NFC tags. This invention enables passive NFC tags to use ASK100% load modulation for PCD communication, which not only greatly improves the signal's anti-interference capability, but also reduces the demodulation difficulty at the receiver, simplifies the structure of the ASK demodulation circuit, optimizes the minimum antenna coupling coefficient k required to maintain normal communication, optimizes the antenna's geometric alignment requirements, and improves the tag's long-distance communication capability.

[0056] Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description or may be learned by practice of the invention. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 A comparison of antenna waveforms with and without ASK100% load modulation and ASK100% modulation.

[0059] Figure 2 This is a schematic diagram of an ASK100% modulation communication system applied to passive NFC tags according to the present invention.

[0060] Figure 3 This is a schematic diagram of the ASK100% modulation communication process applied to passive NFC tags.

[0061] Figure 4 This is a schematic diagram of the circuit structure of the numerically controlled oscillator of the present invention.

[0062] Figure 5 This is a schematic diagram of the overall operation of the numerically controlled oscillator circuit and the digital clock calibration circuit of the present invention.

[0063] Figure 6 This is a schematic diagram illustrating the working effect of the digital calibration circuit of the present invention.

[0064] Figure 7 This is a schematic diagram of the AMS simulation results of the NFC tag and reader performing ASK100% modulation communication according to the present invention.

[0065] Figure 8 This is a schematic diagram of the AMS simulation results of the NFC tag response signal of the present invention. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0067] Antenna waveforms of non-ASK100% load modulation and ASK100% modulation, for example Figure 1 As shown. Figure 1The left side of the image shows the antenna waveform without 100% load modulation using ASK. As can be seen from the antenna waveform, the carrier without 100% load modulation is always present, resulting in good signal continuity. However, the disadvantage is that the amplitude difference of the waveform is small, leading to a higher bit error rate. This, in turn, makes the ASK demodulation circuit at the receiver more complex, limits the signal's anti-interference capability, and increases the demodulation difficulty of the reader due to the insignificant amplitude difference during long-distance transmission, potentially causing communication failure. Figure 1 The right side of the image shows the antenna waveform with 100% ASK modulation. As can be seen from the antenna waveform, the carrier signal with 100% ASK modulation is only output when the level is high and disappears completely when the level is low. The amplitude difference of the waveform is large, which can significantly enhance the anti-interference capability of communication. At the same time, it can optimize the communication distance to a certain extent, simplify the ASK demodulation circuit at the receiving end, and optimize the communication performance.

[0068] In practice, passive NFC tags act as transponders, and their load modulation process relies on a carrier signal, which is a passive modulation method. After the tag's receiving antenna receives the electromagnetic waves transmitted by the reader, it analyzes the information carried by the electromagnetic waves and converts it into a binary signal for demodulation by the digital circuitry. The information carried by the electromagnetic waves may include operation instructions and data from the host computer. The tag's internal digital circuitry then returns a response signal to the reader based on the instruction content. Specifically, depending on the instruction, the original code content of the response data may be generated in different ways. Some instructions have fixed response content, in which case the digital circuitry directly generates the corresponding response data (such as ATQA) and performs encoding and modulation. Some instructions require calculations to obtain the required response code from the received binary data; while others require retrieval from the storage unit. For example, in a read instruction, data is read from the EEPROM storage unit and sent to the digital circuitry, which then encodes and modulates the read code. It is evident that the tag's internal digital circuitry plays a crucial role in the tag's response process, and the clock source controlling the timing of the digital circuitry is the carrier clock carried by the carrier signal.

[0069] However, during ASK100% modulation communication, the carrier signal is completely shut off when the modulation signal is low, causing the tag's RF front-end to be unable to continue parsing and unable to provide a stable and accurate clock signal for the digital circuit's clock extraction circuit. Unable to maintain the clock signal output, the digital circuit timing will stagnate at the moment of clock loss. After waiting for a period of time, the reader will determine a communication error and terminate communication with the transponder. Because the communication between the reader and transponder is half-duplex, the reader continuously receives signals from the transponder during the transmission and reception process without performing any actions. Therefore, it is impossible to require the reader to restart the carrier clock while waiting for the modulation signal to pass the low level, resulting in a modulation communication interruption.

[0070] To solve this problem, such as Figure 2 As shown, the first embodiment of the present invention provides an ASK100% modulation communication system for passive NFC tags, comprising:

[0071] A clock extraction circuit is used to extract a carrier clock from a carrier signal and use the carrier clock to maintain the working timing of the NFC tag during signal reception.

[0072] The ASK demodulation circuit is used to acquire the binary encoded signal from the reader transmitted in the radio frequency field.

[0073] A decoding module is used to decode the binary encoded signal transmitted by the ASK demodulation circuit to obtain instruction data;

[0074] The response control module is used to generate a binary original code signal for responding to the reader based on the instruction data obtained by the decoding module;

[0075] A numerically controlled oscillator circuit is used to generate a recovery clock signal, and the recovery clock signal is used to maintain the working timing of the NFC tag when transmitting signals;

[0076] A digital clock calibration circuit, wherein the digital clock calibration circuit is used to calibrate the recovered clock signal;

[0077] The encoding module is used to encode the binary original code signal to generate a baseband signal;

[0078] A subcarrier modulation module is used to perform subcarrier modulation on the baseband signal to generate a subcarrier modulated signal;

[0079] A load modulation circuit is used to modulate the amplitude of the carrier signal by 100% according to the subcarrier modulation signal, and generate a response signal to be sent to the reader.

[0080] In this embodiment of the invention, by introducing a high-precision recovery clock circuit based on a numerically controlled oscillator circuit, the problem of clock loss when passive NFC tags use ASK100% modulation communication is solved. The carrier clock signal is used for timing control in the signal receiving process of the NFC tag, while the recovery clock signal is switched to be used for timing control in the signal sending process. This enables the passive NFC tag to have a stable clock source during the clock loss period of ASK100% modulation, which can ensure the normal operation of digital circuits and thus realize ASK100% modulation communication of passive NFC tags.

[0081] The tag circuit design of this invention is compatible with the ISO / IEC 14443-A protocol. After enabling ASK100% modulation configuration, the digitally controlled oscillator circuit and digital clock calibration circuit begin calibration. When the tag completes the parsing of the received signal and is ready to return an acknowledgment signal to the reader, the recovery clock circuit is switched to maintain the operation of the digital timing circuit instead of the carrier clock. The implementation effect of this invention is as follows: Figure 3 As shown. Under normal operating conditions, the tag will output corresponding information after receiving an instruction. The original code of the information output by the tag through the demodulation module is first passed to the encoding module, where Manchester encoding is performed. Then, a subcarrier modulation signal is loaded, and finally, the subcarrier modulation signal is output to the analog load modulation circuit. The load modulation circuit modulates the amplitude by connecting or disconnecting the resistor in the circuit according to the high or low level of the subcarrier modulation signal.

[0082] The design of the numerically controlled oscillator circuit and the digital clock calibration circuit of this invention is described in detail below.

[0083] like Figure 4 As shown, the numerically controlled oscillator circuit of the present invention includes:

[0084] The current mirror circuit is used to adjust the charging and discharging current of the oscillator capacitor to control the rate of voltage change of the oscillator capacitor, thereby adjusting the frequency of the recovery clock signal.

[0085] A comparator circuit is used to compare the difference between the voltage of the oscillator capacitor and the reference voltage, and to control the charging or discharging of the oscillator capacitor to generate a square wave signal.

[0086] A frequency divider circuit is used to reduce the frequency of the square wave signal output by the comparator circuit to obtain a recovery clock signal with a 50% duty cycle.

[0087] In this embodiment of the invention, a digitally controlled oscillator (DCO) circuit is used to provide a clock source, which provides a stable and high-precision recovery clock signal to the tag's digital circuitry when the ASK100% communication clock is lost. In this embodiment, the recovery clock signal is adjusted using control words. Different control words (FCW) output by the digital clock calibration circuit adjust the magnitude of the charging and discharging current, thereby affecting the charging and discharging speed of the capacitor and controlling the frequency change of the output clock.

[0088] As a specific embodiment, the current mirror circuit in the numerically controlled oscillator circuit includes multiple current mirror branches; each current mirror branch consists of a PMOS transistor and an NMOS transistor; the base of the NMOS transistor is connected to a digital clock calibration circuit, and the digital clock calibration circuit outputs control words with different control bits to control the on / off state of the NMOS transistor in each current mirror branch, thereby adjusting the charging and discharging current of the oscillator capacitor. The current mirror circuit in this embodiment contains 12 branches, and further increasing the number of current mirror branches can improve the resolution of its output recovered clock signal frequency. This embodiment does not limit the specific number of current mirror branches. In this embodiment, the base of the NMOS transistor in each current mirror branch is connected to the control terminal ENI of the digital clock calibration circuit. <x>By controlling ENI <x>The high and low levels of the signal control enable the switching on and off of the NMOS switches in each current mirror branch, thereby controlling the charging current I of the capacitor at node A. osc The speed at which the voltage at the positive plate of the capacitor reaches a preset value is changed, i.e., the time t is changed, which in turn changes the frequency of the output square wave, as shown in the formula below:

[0089]

[0090] In the formula, t represents time, Iref is the reference current, i represents the branch number, Vc(t) represents the voltage from capacitor A to signal ground, W1 / L1 represents the aspect ratio of the PMOS transistor corresponding to the reference current, W2 / L2 represents the aspect ratio of PMOS transistor MP1 corresponding to current mirror branch 1, and the branch current of current mirror branch 1 is k times Iref, where k = (W2 / L2) / (W1 / L1). The aspect ratio of PMOS transistor MP2 in current mirror branch 2 is twice that of MP1, and the branch current is 2k times Iref. The same applies to MP3-MP12, with the corresponding current mirror branch current being twice that of the former. ENI <0> ~ENI <11> Take "1" (high level) or "0" (low level).

[0091] In this embodiment of the invention, as the control word number increases, the current controlled by the corresponding current mirror branch increases exponentially, thereby achieving higher precision control of capacitor charging and discharging current.

[0092] In the comparator circuit, the inputs to the positive and negative terminals of the comparator are the reference voltage Vref and the voltage (Vch) of capacitor A at node A, respectively. Initially, Vch is 0, and the comparator output is the power supply voltage. Due to the current mirror charging capacitor A at node A, as Vch continues to rise, it eventually exceeds the reference voltage Vref by a certain value, reaching the comparator's accuracy. At this point, the output voltage VOUT is grounded, and a signal is transmitted through the loop to control the NMOS switch OUT_B to conduct, discharging the current in the branch. At this time, Vch drops back to 0, and the output returns to the power supply voltage. During this process, the charging and discharging of the capacitor generates a square wave of the corresponding frequency.

[0093] Since the duty cycle of the square wave is not the ideal 50%, and this imperfect duty cycle affects the calibration accuracy of the digital calibration circuit, the clock signal output by the comparator will also pass through a frequency divider circuit. The frequency divider circuit is a D flip-flop, which reduces the frequency of the square wave signal to obtain a recovered clock signal with the ideal 50% duty cycle.

[0094] like Figure 5 As shown, the digital clock calibration circuit in this embodiment of the invention includes:

[0095] The first counter is used to count the number of periods of the carrier signal;

[0096] The second counter is used to count the number of cycles of the recovery clock signal output by the numerically controlled oscillator circuit.

[0097] The judgment module is used to judge the quantitative relationship between the number of cycles counted by the first counter and the second counter, so as to generate a fast / slow judgment signal;

[0098] The calibration module is used to adjust the control word output to the numerically controlled oscillator circuit based on the speed judgment signal in order to calibrate the recovery clock signal.

[0099] In this embodiment of the invention, the digital clock calibration circuit uses a binary search approach to calibrate the recovered clock signal, performing calibration bit by bit from the most significant bit to the least significant bit. By comparing the number of input clock cycles and the number of reference clock cycles within a certain time period, it determines whether the frequency of the CNC ring oscillator output clock corresponding to the current control word is fast or slow. Since the input clock and the reference clock are asynchronous, the input clock needs to be synchronized to the reference clock by acquiring rising edge pulses. The number of rising edge pulses is used to replace the number of input clock cycles, and the core counting work is completed within the reference clock domain.

[0100] In this embodiment of the invention, a carrier clock is used as a reference clock, and the target frequency for recovering the clock signal is a quarter of the carrier clock frequency. Therefore, the ideal frequency for recovering the clock signal is when the target frequency is one-quarter of the carrier clock frequency. In this embodiment of the invention, a counter is used to count the clock frequency, so the value of the corresponding second counter (counter2) should satisfy the following condition with respect to the first counter (counter1): counter1 = counter2 * 4.

[0101] The quantitative relationship judgment performed by the judgment module is as follows: whether the number of cycles counted by the first counter is four times the number of cycles counted by the second counter; the target frequency of the recovered clock signal is four times the frequency of the carrier signal clock period;

[0102] When the number of cycles counted by the first counter is more than four times the number of cycles counted by the second counter, the judgment module outputs a slow judgment signal; the slow judgment signal indicates that the frequency of the recovery clock signal is lower than the target frequency.

[0103] When the number of cycles counted by the first counter is less than four times the number of cycles counted by the second counter, the judgment module outputs a fast judgment signal; the fast judgment signal indicates that the frequency of the recovered clock signal is higher than the target frequency.

[0104] When the number of cycles counted by the first counter is equal to four times the number of cycles counted by the second counter, and the second counter has not reached its upper limit, the judgment module determines that the current counting time is insufficient to distinguish the speed of the recovery clock signal, and does not output a speed judgment signal, and the two counters continue to work.

[0105] When the calibration module receives a slow judgment signal, it sets the control word currently output to the numerically controlled oscillator circuit to 1.

[0106] When the calibration module receives the fast judgment signal, it sets the control word currently output to the numerically controlled oscillator circuit to 0.

[0107] When the calibration module receives the calibration completion signal, it maintains the current control word set to 1, saves the current control word setting output to the CNC oscillator circuit, determines that the recovery clock signal has completed calibration, ends the calibration process in advance, and no further calibration is performed for subsequent control words.

[0108] Calibration process as follows Figure 6 As shown. At the start of calibration, the most significant bit of the control word is calibrated first. The input clock is synchronized within the reference clock domain to obtain a rising edge pulse. Upon receiving the rising edge pulse signal, the first and second counters simultaneously begin counting. Each time the second counter increments, i.e., upon receiving a rising edge pulse, it indicates that another recovery clock signal input clk_dco has elapsed. At this point, the relationship between the counts of the first and second counters is assessed. If the ideal relationship between the reference clock frequency and the target clock frequency is met, it indicates that the elapsed counting time is insufficient to identify the frequency difference between the input clock and the reference clock, and counting continues until the relationship is no longer met. Based on the magnitude of the relationship, it is determined whether the input clock frequency, i.e., the recovery clock signal output by the DCO, is faster or slower than the target clock frequency. If it is too fast, the current control word is set to 0, and calibration proceeds to the next control word. If it is too slow, the current control word remains set to 1, and calibration proceeds to the next control word. This process is repeated until all control words have been calibrated.

[0109] If the ideal quantitative relationship is maintained for an extended period, and the second counter reaches its maximum count value (MAX), it indicates that the set counting duration is insufficient to distinguish the frequency difference between the input clock and the reference clock. The maximum count value (MAX) of the second counter is designed based on the required frequency accuracy. Therefore, in this case, the DCO output frequency corresponding to the control word is considered equal to the target required clock frequency, or the accuracy is within the set range. The control word is then kept at 1, and the calibration process ends; no further calibration of other control words is performed.

[0110] After calibration is complete, save the corresponding control word configuration and wait for the NFC tag to enter the message response process.

[0111] The DCO clock recovery circuit completes calibration before the tag sends an acknowledgment message. During the calibration process, the carrier clock is present, so the tag is in normal reception mode. Figure 2 As shown, under normal operating conditions, the tag will output corresponding information after receiving an instruction. The original code of the tag's output information is first passed to the encoding module, where Manchester encoding is performed. Then, a subcarrier signal is loaded, and finally, the subcarrier signal is output to the analog load modulation circuit. The load modulation circuit selects to connect or disconnect the resistor in the circuit according to the 0 and 1 of the signal to achieve amplitude modulation.

[0112] In ASK100% modulation, the carrier circuit is selected or disconnected to achieve a 100% amplitude difference in the antenna output waveform between the high and low signal bits. The carrier is off when the load modulation signal is low. At this time, the DCO clock source takes over from the carrier clock to maintain the normal operation of the digital circuit until the load modulation signal is high, at which point it outputs the load modulation signal normally. This cycle repeats to complete the transmission of a full response message. When the tag completes the transmission of all response messages and enters the information reception process, the clock source is switched back to the original carrier clock. Before the next transmission, the clock source is switched back to the DCO output clock to maintain the tag's normal operation.

[0113] In this embodiment of the invention, the clock frequency of the carrier signal is 13.56MHz, the target frequency of the recovered clock signal is 3.39MHz, and the clock frequency of the subcarrier modulation signal is 848kHz.

[0114] Figure 7 , 8 This is the AMS simulation result of communication between a tag chip with ASK100% modulation designed based on this scheme and the reader. It can be seen that the antenna carrier achieves 100% ASK modulation transmission by having a carrier amplitude of 0 at the low signal bit of the subcarrier modulation signal. Below are the tag's encoded signal and the reader's shaped output. Except for the phase difference due to propagation, the signal waveforms are completely identical. That is, the encoded signal output by the reader after demodulation and shaping is consistent with the signal transmitted by the tag, indicating successful reception and correct communication.

[0115] This invention introduces a high-precision DCO clock recovery circuit to provide a stable clock source for the tag during the loss of the ASK100% modulation clock, ensuring the normal operation of the digital circuitry and enabling passive NFC to use ASK100% load modulation for communication with the reader. The extreme amplitude difference not only helps improve the anti-interference capability of NFC tags and optimizes the situation where signal attenuation leads to receiver identification failure in long-distance communication, but also greatly reduces the demodulation difficulty at the receiver and simplifies the design of the ASK demodulation circuit.

[0116] The second embodiment of the present invention discloses an ASK100% modulation communication method applied to passive NFC tags, including a signal receiving process and a signal transmitting process;

[0117] The signal reception process specifically includes:

[0118] A clock extraction circuit is used to extract a carrier clock from the carrier signal, and the carrier clock is used to maintain the working timing of the NFC tag when receiving signals.

[0119] The ASK demodulation circuit is used to obtain the binary encoded signal from the reader transmitted in the radio frequency field;

[0120] The decoding module is used to decode the binary encoded signal transmitted by the ASK demodulation circuit to obtain instruction data;

[0121] The response control module generates a binary original code signal to respond to the reader based on the instruction data obtained from the decoding module;

[0122] The signal transmission process specifically includes:

[0123] A numerically controlled oscillator circuit is used to generate a recovery clock signal, and the recovery clock signal is used to maintain the working timing of the NFC tag when transmitting signals.

[0124] The recovered clock signal is calibrated using a digital clock calibration circuit;

[0125] The binary original code signal is encoded using an encoding module to generate a baseband signal;

[0126] The baseband signal is modulated using a subcarrier modulation module to generate a subcarrier modulated signal.

[0127] The load modulation circuit modulates the amplitude of the carrier signal by 100% according to the subcarrier modulation signal, and generates a response signal to be sent to the reader.

[0128] Specifically, in some embodiments, the recovery clock signal is generated through the following steps:

[0129] The current mirror circuit uses a control word with different control bits output by the digital clock calibration circuit to control the on / off state of the NMOS transistor in each current mirror branch, thereby adjusting the charging and discharging current of the oscillator capacitor.

[0130] A comparator circuit is used to compare the difference between the voltage of the oscillator capacitor and the reference voltage, and to control the charging or discharging of the oscillator capacitor to generate a square wave signal.

[0131] The square wave signal output by the comparator circuit is down-clocked using a frequency divider circuit to obtain a recovery clock signal with a 1 / 2 duty cycle.

[0132] In some embodiments, the restored clock signal is calibrated through the following steps:

[0133] The first counter is used to count the number of periods of the carrier signal;

[0134] The second counter is used to count the number of cycles of the recovered clock signal output by the numerically controlled oscillator circuit;

[0135] The judgment module is used to determine the quantitative relationship between the number of cycles counted by the first counter and the second counter, so as to generate a fast / slow judgment signal.

[0136] The calibration module adjusts the control word output to the numerically controlled oscillator circuit according to the speed judgment signal to achieve calibration of the recovered clock signal.

[0137] The content of the system in the first embodiment of the present invention is applicable to the method embodiment. The specific functions implemented in the method embodiment are the same as those in the above system embodiment, and the beneficial effects achieved are also the same as those achieved by the above system.

[0138] It should be noted that the user information (including but not limited to user system information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the embodiments of the present invention are all information and data authorized by the user or fully authorized by all parties. Furthermore, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0139] Those skilled in the art will understand that modules in the systems of the embodiments of the present invention can be adaptively modified and placed in one or more systems different from those embodiments. Modules, units, or components in the embodiments of the present invention can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the corresponding claims, abstract, and drawings) and all processes or units of any method or system so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the corresponding claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0140] Through the above description of the embodiments, those skilled in the art will understand that, for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above.

[0141] Furthermore, the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. In particular, for embodiments such as apparatus and systems, since they are basically similar to the method embodiments, the relevant parts can be referred to the description of the method embodiments. The apparatus, system, and other embodiments described above are merely illustrative, and the modules, units, etc., described as separate components may or may not be physically separate, that is, they may be located in one place or distributed in multiple places, such as nodes in a system network. Specifically, some or all of the modules and units can be selected according to actual needs to achieve the purpose of the above-described embodiment solutions. Those skilled in the art can understand and implement this without creative effort.

[0142] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0143] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0144] Furthermore, the terms "first," "second," etc., used in the embodiments of this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance, or implicitly specifying the number of technical features indicated in this embodiment. Therefore, features defined with terms such as "first" and "second" in the embodiments of this invention can explicitly or implicitly indicate that the embodiment includes at least one of those features. In the description of this invention, the word "multiple" means at least two or more, such as two, three, four, etc., unless otherwise explicitly specified in the embodiments.

[0145] In embodiments of the present invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of the present invention may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0146] Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention. Other embodiments of the present invention will readily conceive of by considering the specification and practicing the invention. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of the invention are indicated by the following claims.< / x> < / x>

Claims

1. An ASK 100% modulation communication system applied to a passive NFC tag, characterized in that, The application relates to a NFC tag, which comprises: a clock extraction circuit for extracting a carrier clock from a carrier signal, using the carrier clock to maintain the working timing of the NFC tag when receiving a signal; an ASK demodulation circuit for obtaining a binary coded signal from a reader transmitted by a radio frequency field; a decoding module for decoding the binary coded signal transmitted by the ASK demodulation circuit to obtain instruction data; a response control module for generating a binary original code signal for responding to the reader according to the instruction data obtained by the decoding module; a digital controlled oscillator circuit for generating a recovery clock signal, using the recovery clock signal to maintain the working timing of the NFC tag when transmitting a signal; a digital clock calibration circuit for calibrating the recovery clock signal; an encoding module for encoding the binary original code signal to generate a baseband signal; a sub-carrier modulation module for sub-carrier modulating the baseband signal to generate a sub-carrier modulated signal; a load modulation circuit for modulating the amplitude of the carrier signal according to the sub-carrier modulated signal to generate a response signal transmitted to the reader.

2. An ASK 100% modulation communication system applied to a passive NFC tag according to claim 1, characterized in that, The digital controlled oscillator circuit comprises: a current mirror circuit for adjusting the charging and discharging current of an oscillator capacitor to control the voltage variation speed of the oscillator capacitor, thereby adjusting the frequency of the recovery clock signal; a comparator circuit for comparing the difference between the voltage of the oscillator capacitor and a reference voltage to control the charging or discharging of the oscillator capacitor to form a square wave signal; a half frequency division circuit for reducing the frequency of the square wave signal output by the comparator circuit to obtain a 1 / 2 duty cycle recovery clock signal.

3. An ASK 100% modulation communication system applied to a passive NFC tag according to claim 2, characterized in that, The current mirror circuit comprises a plurality of current mirror branches; each current mirror branch is composed of a PMOS tube and an NMOS tube; the base of the NMOS tube is connected to the digital clock calibration circuit, and the control word with different control bits output by the digital clock calibration circuit is used to control the on-off of the NMOS tube in each current mirror branch, so as to adjust the charging and discharging current of the oscillator capacitor.

4. An ASK 100% modulation communication system applied to a passive NFC tag according to claim 1, characterized in that, The digital clock calibration circuit comprises: a first counter for counting the number of periods of the carrier clock signal; a second counter for counting the number of periods of the recovery clock signal output by the digital controlled oscillator circuit; a judging module for judging the number relationship between the number of periods counted by the first counter and the second counter to generate a fast-slow judging signal; a calibration module for adjusting the control word output to the digital controlled oscillator circuit according to the fast-slow judging signal to realize the calibration of the recovery clock signal.

5. An ASK 100% modulation communication system applied to a passive NFC tag according to claim 4, characterized in that, The second counter has a counting upper limit; when the second counter reaches the counting upper limit, the current control word output to the digital controlled oscillator circuit is saved, and it is judged whether the calibration of the recovery clock signal is completed.

6. An ASK 100% modulation communication system applied to a passive NFC tag according to claim 4, characterized in that, The number relationship judgment performed by the judgment module is whether the number of cycles counted by the first counter is four times the number of cycles counted by the second counter; and the target frequency of the recovered clock signal is one fourth of the period of the carrier clock signal. When the number of cycles counted by the first counter is greater than four times the number of cycles counted by the second counter, the judgment module outputs a slow judgment signal; the slow judgment signal indicates that the frequency of the recovered clock signal is lower than the target frequency. When the number of cycles counted by the first counter is less than four times the number of cycles counted by the second counter, the judgment module outputs a fast judgment signal; the fast judgment signal indicates that the frequency of the recovered clock signal is higher than the target frequency. When the number of cycles counted by the first counter is equal to four times the number of cycles counted by the second counter, and the second counter has not reached the upper limit, the judgment module judges that the current counting time is insufficient to distinguish the speed of the recovered clock signal, and does not output a fast / slow judgment signal, and the two counters continue to work.

7. An ASK 100% modulation communication system applied to a passive NFC tag according to claim 6, characterized in that, When the calibration module receives a slow judgment signal, the current control word output to the digitally controlled oscillator circuit is set to 1; When the calibration module receives a fast judgment signal, the current control word output to the digitally controlled oscillator circuit is set to 0; When the calibration module receives a calibration completion signal, the current control word is maintained at 1, the current control word output to the digitally controlled oscillator circuit is saved, it is judged that the calibration of the recovered clock signal is completed, the calibration process is ended in advance, and subsequent control words are no longer calibrated.

8. An ASK 100% modulation communication method applied to a passive NFC tag, applied to an ASK 100% modulation communication system applied to a passive NFC tag according to any one of claims 1 to 7, characterized in that, The signal receiving process and the signal sending process are included. The signal receiving process specifically includes: a clock extraction circuit is used to extract a carrier clock from a carrier signal, and the carrier clock is used to maintain the working timing of the NFC tag during signal receiving; an ASK demodulation circuit is used to obtain a binary coded signal from the reader transmitted by the radio frequency field; a decoding module is used to decode the binary coded signal transmitted by the ASK demodulation circuit to obtain instruction data; a response control module is used to generate a binary original code signal for responding to the reader according to the instruction data obtained by the decoding module; The signal sending process specifically includes: a digitally controlled oscillator circuit is used to generate a recovered clock signal, and the recovered clock signal is used to maintain the working timing of the NFC tag during signal sending; a digital clock calibration circuit is used to calibrate the recovered clock signal; an encoding module is used to encode the binary original code signal to generate a baseband signal; a sub-carrier modulation module is used to sub-carrier modulate the baseband signal to generate a sub-carrier modulated signal; a load modulation circuit is used to modulate the amplitude of the carrier signal by 100% amplitude according to the sub-carrier modulated signal to generate a response signal sent to the reader.

9. The ASK 100% modulation communication method for passive NFC tags according to claim 8, characterized in that, The recovered clock signal is generated by the following steps: a current mirror circuit is used to control the on-off of the NMOS transistor in each current mirror branch according to the control word output by the digital clock calibration circuit with different control bits, so as to adjust the charging and discharging current of the oscillator capacitor; The comparator circuit is used to compare the difference between the voltage of the oscillator capacitor and the reference voltage, and control the charging or discharging of the oscillator capacitor to form a square wave signal; The frequency of the square wave signal output by the comparator circuit is reduced by the frequency division circuit to obtain a 50% duty cycle recovery clock signal.

10. The ASK 100% modulation communication method for passive NFC tags according to claim 9, characterized in that, The recovery clock signal is calibrated by the following steps: The number of periods of the carrier signal is counted by a first counter; The number of periods of the recovery clock signal output by the digital controlled oscillator circuit is counted by a second counter; The number of periods counted by the first counter and the second counter is judged by a judging module to generate a fast / slow judgment signal; The calibration module adjusts the control word output to the digital controlled oscillator circuit according to the fast / slow judgment signal to realize the calibration of the recovery clock signal.

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