PWM (Pulse Width Modulation) dimming control circuit of LED and LED driving chip

Abstract

The embodiment of the invention provides a PWM dimming control circuit of an LED and an LED driving chip, the control circuit comprises a cathode voltage processing module, a switch control module and a logic driving module, the cathode voltage processing module is configured to input a cathode voltage of an LED device and a preset reference voltage into an error amplifier to obtain an output voltage of the error amplifier, and the output voltage of the error amplifier is used for outputting the output voltage of the error amplifier; when the PWM1 is at a low level, the voltage of the negative electrode is sampled and held, and when the PWM2 is at a low level, the output voltage of the error amplifier is sampled and held; the switch control module is configured to obtain a turn-off indication signal of a power tube of the power supply circuit according to the output voltage of the error amplifier based on a peak current control mode, and generate a turn-on indication signal of the power tube based on the second pulse width modulation signal; and the logic driving module is configured to generate a switch control signal of the power tube based on the turn-off indication signal and the turn-on indication signal. The problems that according to an existing PWM dimming scheme driven by a Boost LED, dimming is not stable, and use of a user is affected are solved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of integrated circuit technologies, and more particularly, to a PWM dimming control circuit for an LED and an LED driver chip. Background Art

[0002] Due to the characteristic of the Boost output high voltage in the DC boost circuit and the convenience of integrating a current leak in the Boost controller, the Boost LED driver has been widely used in daily life. When current flows through an LED lamp bead, a voltage drop of about 3V will be generated. In daily applications, when dozens of lamp beads are connected in series to form an LED lamp string, the voltage drop on the LED lamp string will reach more than 30V. At this time, a high voltage needs to be provided to the positive pole of the lamp string, and Boost can easily output a high voltage for the LED lamp string to use. Usually, the driving method of the LED lamp string is constant current driving, that is, a constant current needs to flow through the lamp string to generate the required luminous brightness. When the current leak works normally, it will pull down a current. When the current leak is connected to the negative pole of the LED lamp string, the pull-down current generated by the current leak will flow through the LED lamp string to make it emit light. In summary, using a Boost controller with an integrated current leak as the driver of the LED lamp is a convenient circuit solution.

[0003] For Boost LED drivers, the current mainstream LED dimming methods include DC dimming, PWM dimming, and MIX dimming. DC dimming has problems with poor current accuracy at low currents. MIX dimming integrates DC dimming and PWM dimming and requires an additional digital control circuit. PWM dimming has high dimming accuracy at both low and high currents, and its control circuit is simple, which is a convenient and easy-to-use dimming solution, so it is more widely used.

[0004] The basic principle of PWM dimming is to control the average value of the current by adjusting the width (duty cycle) of the pulse, so as to achieve the purpose of adjusting the brightness of the light. When the inventor applied the existing PWM dimming scheme for Boost LED drivers, it was found that when the current leak was turned off and then turned on, the brightness of the LED lamp string was relatively low, and it needed to go through a process of slowly increasing the brightness before it could reach the target brightness, which affected the user experience. In addition, when the duty cycle of PWM was extremely small, the current leak could not work properly, and thus the on and off of the LED lamp string could not be controlled normally, affecting normal use. In summary, the existing PWM dimming scheme for Boost LED drivers has unstable dimming control and will affect user use. Summary of the Invention

[0005] The embodiments described in this document provide a PWM dimming control circuit for an LED and an LED driver chip, aiming to solve the problem that the existing PWM dimming scheme for Boost LED drivers has unstable dimming, which will affect user experience.

[0006] According to a first aspect of the present disclosure, there is provided a PWM dimming control circuit for an LED. The control circuit is used to perform dimming control on an LED device connected between the output voltage and current leakage of a power supply circuit. The control circuit includes: a negative voltage processing module, a switch control module, and a logic driving module. Among them, the negative voltage processing module is coupled to the negative electrode of the LED device and is configured to input the negative voltage of the LED device and a preset reference voltage into an error amplifier to obtain an output voltage of the error amplifier, and sample and hold the negative voltage when a first pulse width modulation signal is at a low level, and sample and hold the output voltage of the error amplifier when a second pulse width modulation signal is at a low level. The first pulse width modulation signal is a signal for controlling the current leakage switch; the switch control module is configured to obtain a turn-off indication signal for a power tube of the power supply circuit based on a peak current control mode according to the output voltage of the error amplifier, and generate a turn-on indication signal for the power tube based on the second pulse width modulation signal; the logic driving module is configured to generate a switch control signal for the power tube based on the turn-off indication signal and the turn-on indication signal.

[0007] Optionally, the negative voltage processing module includes: a first sampling unit, the error amplifier, and a second sampling unit. Among them, the first sampling unit is configured to input the negative voltage to the negative input terminal of the error amplifier when the first pulse width modulation signal is at a high level, and when the first pulse width modulation signal is at a low level, disconnect the negative voltage from the error amplifier and at the same time sample and hold the negative voltage, and input the negative sampled voltage to the negative input terminal of the error amplifier; the positive input terminal of the error amplifier is coupled to the preset reference voltage, and the output terminal of the error amplifier is coupled to the second sampling unit to output the output voltage of the error amplifier; the second sampling unit is configured to input the output voltage of the error amplifier to the switch control module when the second pulse width modulation signal is at a high level, and when the second pulse width modulation signal is at a low level, disconnect the output voltage of the error amplifier from the switch control module and at the same time sample and hold the output voltage of the error amplifier, and input the sampled output voltage of the error amplifier to the switch control module.

[0008] Optionally, the negative voltage processing module further includes: a clamping unit configured to clamp the output voltage of the error amplifier to be equal to the sampled output voltage of the error amplifier when the second pulse width modulation signal is at a low level.

[0009] Optionally, the first sampling unit includes: a first transistor and a first capacitor. The control electrode of the first transistor is coupled to the first pulse width modulation signal. The first electrode of the first transistor is respectively coupled to one end of the first capacitor and the negative input terminal of the error amplifier. The second electrode of the first transistor is coupled to the negative voltage. The other end of the first capacitor is coupled to the ground terminal.

[0010] Optionally, the second sampling unit includes: a second transistor, a second capacitor, and a first resistor. The control electrode of the second transistor is coupled to the second pulse width modulation signal. The first electrode of the second transistor is respectively coupled to one end of the first resistor and the switch control module. The second electrode of the second transistor is coupled to the output terminal of the error amplifier. The other end of the first resistor is coupled to one end of the second capacitor. The other end of the second capacitor is coupled to the ground terminal.

[0011] Optionally, the clamping unit includes: a third transistor and an operational amplifier. The control electrode of the third transistor is coupled to the inverted signal of the second pulse width modulation signal. The first electrode of the third transistor is respectively coupled to the output terminal of the error amplifier and the second sampling unit. The second electrode of the third transistor is respectively coupled to the negative input terminal and the output terminal of the operational amplifier. The positive input terminal of the operational amplifier is coupled to the sampling voltage output by the error amplifier.

[0012] Optionally, the switch control module includes a comparator and an oscillator. The positive input terminal of the comparator is coupled to the sum of the inductor current sampling voltage and the ramp compensation voltage of the power supply circuit. The negative input terminal of the comparator is coupled to the negative voltage processing module. The output terminal of the comparator is coupled to the logic drive module to output a turn-off indication signal. The input terminal of the oscillator is coupled to the second pulse width modulation signal. The output terminal of the oscillator is coupled to the logic drive module to output the turn-on indication signal.

[0013] Optionally, the logic drive module includes a flip-flop and a driver. The set input terminal of the flip-flop is coupled to the turn-on indication signal. The reset input terminal of the flip-flop is coupled to the turn-off indication signal. The output terminal of the flip-flop is coupled to the input terminal of the driver. The output terminal of the driver outputs the switch control signal.

[0014] Optionally, the first pulse width modulation signal and the second pulse width modulation signal have the same period. When the high-level width of the first pulse width modulation signal is greater than or equal to a first preset multiple of the period of the turn-on indication signal, the second pulse width modulation signal is the same as the first pulse width modulation signal; when the high-level width of the first pulse width modulation signal is less than the first preset multiple of the period of the turn-on indication signal, the high-level width of the second pulse width modulation signal is equal to the first preset multiple of the period of the turn-on indication signal.

[0015] According to a second aspect of the present disclosure, there is provided an LED driving chip, which at least includes the PWM dimming control circuit of the LED and a current leakage as described in any one of the above first aspects. Wherein, the current leakage is coupled to the negative electrode of the LED device and is configured to control the turn-on and turn-off of the current leakage by the first pulse width modulation signal, and control the lighting and extinguishing of the LED device through the turn-on and turn-off of the current leakage.

[0016] In the PWM dimming control circuit of the LED according to the embodiment of the present disclosure, the negative electrode voltage processing module samples and holds the negative electrode voltage of the LED device when the first pulse width modulation signal is at a low level, and samples and holds the output voltage of the error amplifier when the second pulse width modulation signal is at a low level, so as to maintain the stability of the loop under PWM dimming, enable the control loop to quickly enter a stable state when the PWM1 signal changes from low to high, and then enable the LED device to quickly reach the target brightness, avoiding the problem in the prior art that when the LED string is turned on (i.e., when the PWM1 signal changes from low to high), the brightness is relatively low and it takes a process of slow increase in brightness to reach the target brightness. Description of the Drawings

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be understood that the following described drawings only relate to some embodiments of the present disclosure and do not limit the present disclosure, where:

[0018] Figure 1 It shows a waveform schematic diagram of the output voltage of the error amplifier in a control loop corresponding to an existing Boost LED driver;

[0019] Figure 2 It shows a schematic block diagram of a PWM dimming control circuit of an LED according to an embodiment of the present disclosure;

[0020] Figure 3 It shows an exemplary circuit diagram of a negative electrode voltage processing module according to an embodiment of the present disclosure;

[0021] Figure 4Shows an exemplary circuit diagram of another negative electrode voltage processing module according to an embodiment of the present disclosure;

[0022] Figure 5 Shows an exemplary circuit diagram of a switching control module and a logic driving module according to an embodiment of the present disclosure;

[0023] Figure 6 、 7 Shows a waveform schematic diagram of key signals corresponding to PWM1 with different duty cycles according to an embodiment of the present disclosure;

[0024] Figure 8 Shows an exemplary circuit diagram of a current leakage according to an embodiment of the present disclosure;

[0025] The elements in the drawings are schematic and not drawn to scale. Detailed Embodiments

[0026] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of the present disclosure without creative efforts shall also fall within the scope of protection of the present disclosure.

[0027] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the subject matter of the present disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that these parts are directly joined together or joined through one or more intermediate components.

[0028] In all embodiments of the present disclosure, since the source and drain of a metal-oxide-semiconductor (MOS) transistor are symmetric, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled intermediate terminal (gate or gate terminal) of the MOS transistor is referred to as the control electrode, and the remaining two terminals of the MOS transistor are respectively referred to as the first electrode and the second electrode. Additionally, terms such as "first" and "second" are only used to distinguish one component (or a part of a component) from another component (or another part of a component).

[0029] As Figure 1As shown, it is a schematic waveform diagram of the output voltage Vcomp of the error amplifier in the control loop corresponding to the existing PWM dimming scheme for Boost LED drivers. The inventor found that when the PWM is low and the current leakage is turned off, Vcomp will discharge to a lower value. When the PWM is high and the current leakage is turned on next time, Vcomp needs to be established upward from a lower value, which will cause insufficient energy to be provided to the output voltage of Boost quickly, and thus the target current cannot be provided for the LED string, resulting in the inability of the string to quickly reach the target brightness. In addition, when the duty cycle of the PWM signal is extremely small, insufficient energy can be provided to the output voltage to turn on the current leakage, and thus the driving current cannot be provided for the LED string, affecting normal use.

[0030] To solve the problems that in the existing PWM dimming scheme for Boost LED drivers, when the LED string is turned on, the brightness is relatively low and it needs to go through a process of slow brightness increase to reach the target brightness, which affects the user experience; and when the duty cycle of the PWM is very small, the current leakage cannot work properly, and thus the on / off of the LED string cannot be normally controlled, affecting normal use, a new PWM dimming control circuit applicable to Boost LED drivers is proposed. The PWM dimming control circuit of the LED in the embodiment of the present disclosure is based on peak current mode control, and maintains the stable operation of the loop under PWM dimming by sampling and holding the negative voltage of the LED device and the output voltage of the error amplifier. The PWM dimming control circuit of the LED in the present disclosure will be described in detail below.

[0031] Figure 2 A schematic block diagram of a PWM dimming control circuit 100 for an LED in an embodiment of the present disclosure is shown. The PWM dimming control circuit 100 for an LED in an embodiment of the present disclosure is applicable to applications of Boost driving LEDs, and is used for dimming control of an LED device 300 connected between the output voltage Vout of a power supply circuit (Boost) and a current leakage 200. As Figure 2 shown, the LED device may be an LED string, and the control circuit 100 includes: a negative voltage processing module 110, a switch control module 120, and a logic driving module 130.

[0032] Among them, the negative voltage processing module 110 is coupled to the negative electrode of the LED device 300 and is configured to input the negative electrode voltage VFB of the LED device 300 and a preset reference voltage Vref into an error amplifier EA to obtain an error amplifier output voltage Vcomp. When the first pulse width modulation signal PWM1 is at a low level, the negative electrode voltage VFB is sampled and held. When the second pulse width modulation signal PWM2 is at a low level, the output voltage Vcomp of the error amplifier EA is sampled and held. The negative electrode voltage VFB of the LED device 300 (i.e., the feedback voltage of Vout) and the preset reference voltage Vref are input into the error amplifier EA to enter the Boost voltage control loop to adjust VFB to make it equal to Vref. The purpose of making VFB equal to Vref is to ensure that the current leakage 200 has sufficient voltage margin when the current leakage 200 is turned on, ensuring that the current leakage 200 can normally generate a pull-down current ILED. The first pulse width modulation signal PWM1 is a signal for controlling the switch of the current leakage 200. When the first pulse width modulation signal PWM1 is at a high level, the current leakage 200 is turned on, and the current leakage 200 generates a pull-down current ILED, and the LED device 300 is lit. The negative electrode voltage VFB of the LED device 300 drops from a high value when there is no current to equal the reference voltage Vref set in the Boost control loop; when the first pulse width modulation signal PWM1 is at a low level, the current leakage 200 is turned off, ILED drops to zero, and the LED device 300 goes out. Since the current of the LED device 300 drops to zero, the forward conduction voltage VF of the LED device 300 rapidly decreases, while Vout remains unchanged, so the VFB voltage will rapidly rise until the next high level of PWM1 arrives. During the period when the first pulse width modulation signal PWM1 is at a high level, the LED device 300 operates at full brightness; during the period when the first pulse width modulation signal PWM1 is at a low level, the LED device 300 goes out. By adjusting the duty cycle of the first pulse width modulation signal PWM1, the average current of the LED device 300 can be adjusted, thereby changing the actual light-emitting brightness of the LED device 300. Generally, the frequency of the first pulse width modulation signal PWM1 is in the range of 100 Hz to 25 KHz, and this frequency range exceeds the frequency that the human eye can respond to. Therefore, under the "filtering" effect of the human eye, the human eye perceives the average brightness of the LED device 300. When the first pulse width modulation signal PWM1 is at a low level, if the negative electrode voltage VFB of the LED device 300 and the output voltage Vcomp of the error amplifier EA are not sampled, there will be Figure 1In the case of the prior art, in the embodiments of the present disclosure, when the first pulse width modulation signal PWM1 is at a low level, the negative voltage VFB is sampled and held. When the first pulse width modulation signal PWM1 changes from a high level to a low level, the connection between VFB and the error amplifier EA is disconnected, and at the same time, the voltage of VFB at the last moment when the first pulse width modulation signal PWM1 is at a high level is sampled and held during the period when the first pulse width modulation signal PWM1 is at a low level, so that the input of the error amplifier EA can be maintained at the voltage when the first pulse width modulation signal PWM1 is at a high level. Similarly, when the second pulse width modulation signal PWM2 is at a low level, the output voltage Vcomp of the error amplifier EA is sampled and held ( Figure 2 where Vcomp_SH is the sampled voltage of the error amplifier output), so that the output voltage Vcomp of the error amplifier EA can be maintained at the voltage when the second pulse width modulation signal PWM2 is at a high level, and the situation where the Vcomp voltage drops significantly as in Figure 1 will not occur. In this way, when PWM1 changes from a low level to a high level again, a steady-state voltage required during the high-level period can be provided, which is beneficial to the transient response when the PWM1 signal changes from low to high. In addition, it should be noted that in this embodiment, the first pulse width modulation signal PWM1 is equal to the second pulse width modulation signal PWM2, that is, they are signals with the same period and equal high-level widths.

[0033] The switch control module 120 is configured to obtain the turn-off indication signal Reset of the power transistor Mp of the power supply circuit based on the peak current control mode according to the output voltage Vcomp of the error amplifier, and generate the turn-on indication signal Vclk of the power transistor Mp based on the second pulse width modulation signal PWM2. The voltage loop control method in the embodiments of the present disclosure is based on the peak current control mode. After obtaining the output voltage Vcomp of the error amplifier EA, it is necessary to compare it with the sum of the inductor current sampling voltage Vsense and the ramp compensation voltage Vslope, and output the turn-off indication signal Reset to control the turn-off of the power transistor Mp of Boost, so as to control the peak value of the inductor current, further control the energy transmitted to the output end, and adjust Vout to an appropriate value so that Vout minus the voltage drop of the LED device 300 (i.e., VFB) is equal to the preset reference Vref. The turn-on indication signal Vclk is a signal with a fixed clock frequency generated by the second pulse width modulation signal PWM2 through the oscillator OSC, and is used to turn on the power transistor Mp period by period.

[0034] The logic driving module 130 is configured to generate a switching control signal VG for the power transistor based on the turn-off indication signal Reset and the turn-on indication signal Vclk. When the turn-off indication signal Reset is a valid signal, the switching control signal VG generated by the logic driving module 130 turns off the power transistor Mp. When the turn-off indication signal Reset is an invalid signal, the switching control signal VG generated by the logic module is controlled by the turn-on indication signal Vclk to control the periodic turn-on of Mp.

[0035] As can be seen from the above description, in the PWM dimming control circuit of the LED in the embodiment of the present disclosure, the negative voltage processing module samples and holds the negative voltage VFB when the first pulse width modulation signal PWM1 is at a low level, and samples and holds the output voltage Vcomp of the error amplifier EA when the second pulse width modulation signal PWM2 is at a low level, so as to maintain the stability of the loop under PWM dimming, enable the control loop to quickly enter a stable state when the PWM1 signal changes from low to high, and further enable the LED device 300 to quickly reach the target brightness, avoiding the problem in the prior art that when the LED string is turned on (i.e., when the PWM1 signal changes from low to high), the brightness is relatively low and it takes a process of slow increase in brightness to reach the target brightness.

[0036] Further, as Figure 3 shown, the negative voltage processing module 110 includes: a first sampling unit 111, the error amplifier EA, and a second sampling unit 112.

[0037] Among them, the first sampling unit 111 is configured to input the negative voltage VFB to the negative input terminal of the error amplifier EA when the first pulse width modulation signal PWM1 is at a high level, and when the first pulse width modulation signal PWM1 is at a low level, sample and hold the negative voltage VFB while disconnecting the negative voltage VFB from the error amplifier EA, and input the negative sampled voltage VFB_SH to the negative input terminal of the error amplifier EA; the positive input terminal of the error amplifier EA is coupled to the preset reference voltage Vref, and the output terminal of the error amplifier EA is coupled to the second sampling unit 112 to output the error amplifier output voltage Vcomp. Further, as Figure 3 shown, the first sampling unit 111 includes: a first transistor M1 and a first capacitor C1. Among them, the control electrode of the first transistor M1 is coupled to the first pulse width modulation signal PWM1, the first pole of the first transistor M1 is respectively coupled to one end of the first capacitor C1 and the negative input terminal of the error amplifier EA, and the second pole of the first transistor M1 is coupled to the negative voltage VFB; the other end of the first capacitor C1 is coupled to the ground terminal.

[0038] The second sampling unit 112 is configured to input the error amplifier output voltage Vcomp to the switch control module 120 when the second pulse width modulation signal PWM2 is at a high level, and to sample and hold the error amplifier output voltage Vcomp while disconnecting the error amplifier output voltage Vcomp from the switch control module 120 when the second pulse width modulation signal PWM2 is at a low level, and input the error amplifier output sampled voltage Vcomp_SH to the switch control module 120. Further, as Figure 3 shown, the second sampling unit 112 includes: a second transistor M2, a second capacitor C2, and a first resistor R1. The control electrode of the second transistor M2 is coupled to the second pulse width modulation signal PWM2. The first electrode of the second transistor M2 is respectively coupled to one end of the first resistor R1 and the switch control module 120. The second electrode of the second transistor M2 is coupled to the output terminal of the error amplifier EA. The other end of the first resistor R1 is coupled to one end of the second capacitor C2, and the other end of the second capacitor C2 is coupled to the ground terminal.

[0039] Combined with Figure 2-3 , the working principle of the negative voltage processing module 110 is described as follows: when PWM1 and PWM2 are at high levels, M1 and M2 are turned on, VFB is connected to the negative input terminal of EA, and Vref and VFB pass through EA to obtain Vcomp, and Vcomp is input to the switch control module 120; when PWM1 and PWM2 are at low levels, M1 and M2 are turned off, and the capacitor C1 will sample the feedback voltage VFB at the last moment when PWM1 is at a high level and hold it during the period when PWM1 is at a low level. The voltage on it is VFB_SH. Sampling and holding VFB can filter out unnecessary VFB information, that is, the voltage value of VFB during the period when PWM1 is at a low level. The really useful information is the voltage value of VFB during the period when PWM1 is at a high level; similarly, after M2 is disconnected, the output of the error amplifier EA is disconnected from the RC compensation network (the compensation network composed of R1 and C2), and the output voltage Vcomp of the error amplifier EA at the last moment when PWM2 is at a high level is sampled and held. In this way, during the period when PWM2 is at a low level, the output voltage Vcomp of the error amplifier EA can be maintained at the voltage Vcomp_SH on the RC compensation network, and at the beginning moment of the next PWM2 high level, a steady-state voltage close to that required during the PWM2 high level is provided, which is beneficial to the transient response when PWM2 (or PWM1, the time when PWM1 and PWM2 change from low to high is the same) changes from low to high.

[0040] Further, as Figure 4 shown, another circuit structure of the negative voltage processing module 110 is also provided. Compared with Figure 3 Figure 4The negative voltage processing module 110 therein adds a clamping unit 113. The clamping unit 113 is configured to clamp the output voltage Vcomp of the error amplifier to be equal to the sampled output voltage Vcomp_SH of the error amplifier when the second pulse width modulation signal PWM2 is at a low level. Specifically, as Figure 4 shown, the clamping unit 113 includes: a third transistor M3 and an operational amplifier OP1. Among them, the control electrode of the third transistor M3 is coupled to the inverted signal PWM2_n of the second pulse width modulation signal PWM2. The first electrode of the third transistor M3 is respectively coupled to the output terminal of the error amplifier EA and the second sampling unit 112. The second electrode of the third transistor M3 is respectively coupled to the negative input terminal of the operational amplifier OP1 and the output terminal of the operational amplifier OP1. The positive input terminal of the operational amplifier OP1 is coupled to the sampled output voltage Vcomp_SH of the error amplifier. Combining Figure 4 , the working principle of the newly added clamping unit 113 is described. PWM1 is the same as PWM2. When PWM2 is at a high level, that is, when PWM1 is at a high level, the inverted signal PWM2_n of PWM2 is at a low level, and M3 is turned off. At this time, the working principle of the negative voltage processing module 100 is the same as that in Figure 3 . When PWM2 is at a low level, the inverted signal PWM2_n of PWM2 is at a high level, and M3 is turned on. The output voltage Vcomp of EA is clamped to be equal to the voltage Vcomp_SH on the RC compensation network. The purpose of this is to prevent the voltage on the parasitic capacitance at the output terminal of EA from impacting the voltage on the RC compensation network when PWM1 changes from low to high, so that the voltage maintained on the RC compensation network deviates more from the steady-state value. It should be noted that Figure 4 the clamping unit 113 in the circuit structure of the negative voltage processing module 110 in

[0041] has a more obvious effect when the capacitance value of the parasitic capacitance at the output terminal of EA is relatively large. Figure 5As shown, the switch control module 120 includes a comparator comp and an oscillator OSC. Among them, the positive input terminal of the comparator comp is coupled to the sum "Vslope + Vsense" of the inductor current sampling voltage Vsense and the slope compensation voltage Vslope of the power supply circuit. The negative input terminal of the comparator comp is coupled to Vcomp or Vcomp_SH output from the output terminal of the negative voltage processing module 110. The output terminal of the comparator comp is coupled to the logic drive module 130 to output a turn-off indication signal Reset. The input terminal of the oscillator OSC is coupled to the second pulse width modulation signal PWM2, and the output terminal of the oscillator OSC is coupled to the logic drive module 130 to output the turn-on indication signal Vclk. Specifically, when "Vslope + Vsense" is equal to or greater than Vcomp / Vcomp_SH, it indicates that the inductor current has reached the peak value and the Mp transistor needs to be turned off. At this time, the turn-off indication signal Reset is at a high level. When "Vslope + Vsense" is less than Vcomp / Vcomp_SH, it indicates that the inductor current has not reached the peak value and the Mp transistor does not need to be turned off. At this time, the turn-off indication signal Reset is at a low level. Figure 5 Among them, the OSC generates a turn-on indication signal Vclk with a fixed clock frequency for periodically turning on the power transistor Mp.

[0042] Further, as Figure 5 shown, the logic drive module 130 includes: a flip-flop DFF and a driver Driver. Among them, the set input terminal S of the flip-flop DFF is coupled to the turn-on indication signal Vclk, the reset input terminal R of the flip-flop DFF is coupled to the turn-off indication signal Reset, and the output terminal Q of the flip-flop DFF is coupled to the input terminal of the driver Driver. The output terminal of the driver Driver outputs the switch control signal VG. Specifically, when Reset is at a high level, VG controls Mp to turn off. When Reset is at a low level, VG is determined by Vclk, that is, at this time, Vclk controls Mp to be periodically turned on.

[0043] Further, in the foregoing embodiments, PWM1 and PWM2 are the same signal. However, considering that when the duty cycle of the first pulse width modulation signal PWM1 is extremely small, current leakage 200 may malfunction, and thus the on / off of the LED string cannot be normally controlled, affecting normal use. The embodiments of the present disclosure further design and adjust the first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2. Specifically, the periods of the first pulse width modulation signal PWM1 and the second pulse width modulation signal PWM2 remain the same, and the moments of changing from low level to high level are consistent, but the times of changing from high level to low level are different. The first case is: when the high-level width of the first pulse width modulation signal PWM1 is greater than or equal to a first preset multiple of the period of the start indication signal Vclk, the second pulse width modulation signal PWM2 is the same as the first pulse width modulation signal PWM1; the second case is: when the high-level width of the first pulse width modulation signal PWM1 is less than the first preset multiple of the period of the start indication signal Vclk, the high-level width of the second pulse width modulation signal PWM2 is equal to the first preset multiple of the period of the start indication signal Vclk. The first preset multiple can be adaptively adjusted according to actual requirements. For example, the first preset multiple can be 3, 4, 5, etc. After the above design in the embodiments of the present disclosure, in the second case, the control signals of M2, M3 and M1 are different. M2 and M3 are controlled by PWM2 different from PWM1 to extend the modulation time of EA within each PWM1 period when the duty cycle of PWM1 is extremely small or the high-level width of PWM1 is extremely narrow (such as 500 ns), which can accelerate the convergence of the control loop. At the same time, the input signal of OSC also becomes controlled by PWM2 different from PWM1. Such a design can enable Boost to have enough switching actions within each PWM1 period to provide sufficient energy for the output capacitor Cout. If PWM2 and PWM1 are still controlled in the same way, when the high-level width of PWM1 is very narrow, due to the limited on-time of Mp, the output capacitor Cout of Boost cannot be charged within multiple PWM1 periods, and the output voltage Vout will drop, resulting in the feedback voltage VFB not being adjustable to be equal to the Vref voltage, which will affect the normal operation of the current leakage 200.

[0044] Further, in the embodiments of the present disclosure, with the first preset multiple being 5, waveform diagrams of key signals corresponding to the case where the high-level width T1 of the first pulse width modulation signal PWM1 is greater than 5 times the period of the start indication signal Vclk and the case where the high-level width T1 of the first pulse width modulation signal PWM1 is less than 5 times the period of the start indication signal Vclk are given, as shown in Figure 6 and 7As shown, it can be seen that whether the duty cycle of PWM1 is small or large, it can ensure the normal operation of the current leakage 200, provide the driving current ILED for the LED device 300, that is, ensure the normal lighting and extinguishing of the LED device 300.

[0045] An embodiment of the present disclosure also provides an LED driving chip, which at least includes the PWM dimming control circuit of the LED described in the above embodiment and the current leakage. Wherein, the current leakage is coupled to the negative electrode of the LED device and is configured to control the opening and closing of the current leakage by a first pulse width modulation signal, and control the lighting and extinguishing of the LED device by the opening and closing of the current leakage. In addition, Figure 2 In practical applications, Mp and Rsense in can be integrated into the LED driving chip or integrated into the main power circuit together with L1, D1, etc. in Figure 1 In.

[0046] Furthermore, as Figure 8 shown, an exemplary circuit diagram of a current leakage 200 is given. Among them, the current leakage includes a fourth transistor M4, a second resistor R2, and a second operational amplifier OP2. The control electrode of the fourth transistor M4 is coupled to the output terminal of the second operational amplifier OP2. The first electrode of the fourth transistor M4 is respectively coupled to one end of the second resistor R2 and the negative input terminal of the second operational amplifier. The second electrode of the fourth transistor M4 is coupled to the negative electrode of the LED device; the other end of the second resistor R2 is coupled to the ground terminal, and the positive input terminal of the second operational amplifier OP2 is coupled to the reference voltage DIM_REF, and DIM_REF is determined according to the ILED current required by the lamp string and the resistance value of R2. The current leakage 200 is controlled by PWM1 to switch. When PWM1 is at a high level, the current leakage 200 is turned on to provide ILED for the LED device. When PWM1 is at a low level, the current leakage 200 is turned off. To turn on the current leakage, it is necessary to ensure that there is enough voltage margin at the drain terminal (the second electrode) of M4, so as to ensure that the current leakage 200 can normally pull down the current.

[0047] In summary, the PWM dimming control circuit of the LED and the LED driving chip in the embodiments of the present disclosure provide a PWM dimming strategy applicable to Boost LED driving, provide a new solution for PWM dimming, can enable the LED device to quickly reach the target brightness, and at the same time solve the problem that the current leakage cannot work normally in the case of extremely small PWM duty cycle applications. This solution has engineering significance and value.

[0048] Unless the context clearly indicates otherwise, the singular forms of words used in this specification and the appended claims include the plural, and vice versa. Thus, when referring to the singular, it generally includes the plural of the corresponding term. Similarly, the phrases "comprising" and "including" will be interpreted as inclusive rather than exclusive. Likewise, the term "including" and "or" shall be interpreted as inclusive, unless such interpretation is expressly prohibited herein. Where the term "exemplary" is used herein, particularly when it follows a list of terms, "exemplary" is merely illustrative and explanatory and should not be considered exclusive or exhaustive.

[0049] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that the various aspects of the present disclosure may be implemented alone or in combination with one or more other aspects. It should also be understood that the description herein and the specific examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

[0050] The foregoing has described in detail several embodiments of the present disclosure, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The scope of protection of the present disclosure is defined by the appended claims.

Claims

1. A PWM dimming control circuit for an LED, the control circuit being used for dimming control of an LED device connected between the output voltage and the current drain of a power supply circuit, characterized in that, The control circuit includes: a negative voltage processing module, a switch control module, and a logic driving module. Among them, the negative voltage processing module is coupled to the negative electrode of the LED device, and is configured to input the negative electrode voltage of the LED device and a preset reference voltage into an error amplifier to obtain an error amplifier output voltage, and sample and hold the negative electrode voltage when the first pulse width modulation signal is at a low level, and sample and hold the output voltage of the error amplifier when the second pulse width modulation signal is at a low level. The first pulse width modulation signal is a signal for controlling the current leakage switch. The switch control module is configured to obtain a turn-off indication signal of the power tube of the power supply circuit based on the peak current control mode according to the error amplifier output voltage, and generate a turn-on indication signal of the power tube based on the second pulse width modulation signal. The logic driving module is configured to generate a switch control signal of the power tube based on the turn-off indication signal and the turn-on indication signal.

2. The PWM dimming control circuit of the LED according to claim 1, wherein The negative voltage processing module includes: a first sampling unit, the error amplifier, and a second sampling unit. Among them, the first sampling unit is configured to input the negative electrode voltage to the negative input terminal of the error amplifier when the first pulse width modulation signal is at a high level, and when the first pulse width modulation signal is at a low level, sample and hold the negative electrode voltage while disconnecting the negative electrode voltage from the error amplifier, and input the negative electrode sampled voltage to the negative input terminal of the error amplifier. The positive input terminal of the error amplifier is coupled to the preset reference voltage, and the output terminal of the error amplifier is coupled to the second sampling unit to output the error amplifier output voltage. The second sampling unit is configured to input the error amplifier output voltage to the switch control module when the second pulse width modulation signal is at a high level, and when the second pulse width modulation signal is at a low level, sample and hold the error amplifier output voltage while disconnecting the error amplifier output voltage from the switch control module, and input the error amplifier output sampled voltage to the switch control module.

3. The PWM dimming control circuit of the LED according to claim 2, characterized in that, The negative voltage processing module further includes: a clamping unit, which is configured to clamp the error amplifier output voltage to be equal to the error amplifier output sampled voltage when the second pulse width modulation signal is at a low level.

4. The PWM dimming control circuit of the LED according to claim 2 or 3, characterized in that, The first sampling unit includes: a first transistor and a first capacitor. Among them, the control electrode of the first transistor is coupled to the first pulse width modulation signal, the first pole of the first transistor is respectively coupled to one end of the first capacitor and the negative input terminal of the error amplifier, and the second pole of the first transistor is coupled to the negative electrode voltage. The other end of the first capacitor is coupled to the ground terminal.

5. The PWM dimming control circuit of the LED according to claim 2 or 3, characterized in that, The second sampling unit includes: a second transistor, a second capacitor, and a first resistor. Among them, the control electrode of the second transistor is coupled to the second pulse width modulation signal, the first pole of the second transistor is respectively coupled to one end of the first resistor and the switch control module, and the second pole of the second transistor is coupled to the output terminal of the error amplifier. The other end of the first resistor is coupled to one end of the second capacitor, and the other end of the second capacitor is coupled to the ground terminal.

6. The PWM dimming control circuit of the LED according to claim 3, characterized in that, The clamping unit includes: a third transistor and an operational amplifier. Wherein, the control electrode of the third transistor is coupled to the inverted signal of the second pulse width modulation signal, the first electrode of the third transistor is respectively coupled to the output terminal of the error amplifier and the second sampling unit, and the second electrode of the third transistor is respectively coupled to the negative input terminal of the operational amplifier and the output terminal of the operational amplifier. The positive input terminal of the operational amplifier is coupled to the sampling voltage output by the error amplifier.

7. The PWM dimming control circuit of the LED according to claim 1, wherein The switch control module includes: a comparator and an oscillator. Wherein, the positive input terminal of the comparator is coupled to the sum of the inductor current sampling voltage of the power supply circuit and the ramp compensation voltage, the negative input terminal of the comparator is coupled to the negative voltage processing module, and the output terminal of the comparator is coupled to the logic driving module to output a turn-off indication signal. The input terminal of the oscillator is coupled to the second pulse width modulation signal, and the output terminal of the oscillator is coupled to the logic driving module to output the turn-on indication signal.

8. The PWM dimming control circuit of the LED according to claim 1, wherein The logic driving module includes: a flip-flop and a driver. Wherein, the set input terminal of the flip-flop is coupled to the turn-on indication signal, the reset input terminal of the flip-flop is coupled to the turn-off indication signal, and the output terminal of the flip-flop is coupled to the input terminal of the driver. The output terminal of the driver outputs the switch control signal.

9. The PWM dimming control circuit of the LED according to claim 6, characterized in that, The first pulse width modulation signal and the second pulse width modulation signal have the same period. When the high-level width of the first pulse width modulation signal is greater than or equal to a first preset multiple of the period of the turn-on indication signal, the second pulse width modulation signal is the same as the first pulse width modulation signal; when the high-level width of the first pulse width modulation signal is less than the first preset multiple of the period of the turn-on indication signal, the high-level width of the second pulse width modulation signal is equal to the first preset multiple of the period of the turn-on indication signal.

10. An LED driving chip, characterized in that, The chip at least includes the PWM dimming control circuit and the current leak of the LED described in any one of claims 1 to 9 above. Wherein, the current leak is coupled to the negative electrode of the LED device, and is configured to control the turn-on and turn-off of the current leak by the first pulse width modulation signal, and control the lighting and extinguishing of the LED device by the turn-on and turn-off of the current leak.

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