Preparation method of semiconductor structure and semiconductor structure
By using hydrophobic self-assembly single-molecular film layer technology in semiconductor structures, the problem of parasitic transistor formation is solved, and the device performance is improved, ensuring that the channel layer is only deposited on the conductive layer, avoiding the influence of parasitic transistors.
Patent Information
- Application Number
- CN202410017471.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-05
- Publication Date
- 2025-07-08
AI Technical Summary
In the prior art, the deposition of metal oxide semiconductor material on the surface of each layer of dielectric layer causes the interconnection of the metal oxide semiconductor material on the surface of the dielectric layer between the upper and lower transistors through the metal oxide semiconductor material on the surface of the dielectric layer to form a parasitic transistor, affecting device performance.
During the preparation of the semiconductor structure, by forming a stacked structure and depositing a self-assembled single-molecular film layer with hydrophobic functional groups in the gate trench, ensuring that the channel layer is only selectively deposited on the surface of the conductive layer without depositing on the surface of the dielectric layer, thereby avoiding the formation of parasitic transistors.
The formation of parasitic transistors is effectively avoided and the device performance is improved. Especially by using selective deposition technology of self-assembled single-molecular film layers, ensuring that the channel layer is only deposited on the conductive layer, improving the overall performance of the device.
Smart Images
Figure CN120282443A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and particularly to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art
[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking day by day, and the types and quantities of devices included in a single chip are increasing accordingly. As a result, any minor difference in the process production may affect the device performance.
[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's Law came out, the industry has proposed various semiconductor structure designs and process optimizations to meet the requirements of current products.
[0004] In related technologies, metal oxide semiconductor materials are usually used as the channel materials of devices. However, metal oxide semiconductor materials will also be deposited on the surfaces of each dielectric layer, which will cause the upper and lower two transistors to be interconnected through the metal oxide semiconductor materials on the surface of the dielectric layer, thereby forming parasitic transistors, and the parasitic transistors will cause the performance of the devices to decline. Summary of the Invention
[0005] Based on this, it is necessary to provide a method for manufacturing a semiconductor structure and a semiconductor structure to solve the problem of device performance degradation in related technologies.
[0006] In a first aspect, the present invention provides a method for manufacturing a semiconductor structure, including:
[0007] Providing a substrate;
[0008] Forming a stacked structure on the substrate, the stacked structure including dielectric layers and conductive layers alternately stacked in a first direction;
[0009] Forming a gate trench in the stacked structure, the gate trench penetrating the stacked structure along the first direction to expose each dielectric layer and each conductive layer;
[0010] Depositing a first self-assembled monolayer on the exposed surfaces of the dielectric layers in the gate trench; the first self-assembled monolayer has hydrophobic functional groups to make the exposed surfaces of the dielectric layers hydrophobic;
[0011] Selectively depositing a channel layer on the exposed surfaces of the conductive layers in the gate trench.
[0012] The method for preparing the above semiconductor structure includes forming a stacked structure on the substrate, where the stacked structure includes a dielectric layer and a conductive layer alternately stacked in sequence along a first direction; forming a gate trench in the stacked structure, where the gate trench penetrates the stacked structure along the first direction to expose each layer of the dielectric layer and each layer of the conductive layer; depositing a first self-assembled monolayer on the exposed surfaces of each layer of the dielectric layer in the gate trench; the first self-assembled monolayer has a hydrophobic functional group so that the exposed surfaces of each layer of the dielectric layer are hydrophobic; selectively depositing a channel layer on the exposed surfaces of each layer of the conductive layer in the gate trench. Since the first self-assembled monolayer has a hydrophobic functional group, the exposed surfaces of each layer of the dielectric layer are hydrophobic. Therefore, when depositing the channel layer, the channel layer will only be selectively deposited on the surface of the conductive layer and will not be deposited on the surface of the hydrophobic dielectric layer, thereby avoiding the formation of parasitic transistors and improving the device performance.
[0013] In one embodiment, depositing the first self-assembled monolayer on the exposed surfaces of each layer of the dielectric layer in the gate trench includes:
[0014] Selectively depositing a second self-assembled monolayer on the exposed surfaces of each layer of the conductive layer in the gate trench;
[0015] Selectively depositing the first self-assembled monolayer on the exposed surfaces of each layer of the dielectric layer in the gate trench, where the removal conditions of the first self-assembled monolayer are different from those of the second self-assembled monolayer;
[0016] Selectively removing the second self-assembled monolayer to obtain the first self-assembled monolayer on the exposed surfaces of each layer of the dielectric layer.
[0017] In one embodiment, the first self-assembled monolayer has a first decomposition temperature, the second self-assembled monolayer has a second decomposition temperature, and the first decomposition temperature is higher than the second decomposition temperature; selectively removing the second self-assembled monolayer includes:
[0018] Selectively removing the second self-assembled monolayer within a preset temperature range, where the preset temperature range is greater than the second decomposition temperature and less than the first decomposition temperature.
[0019] In one embodiment, the second decomposition temperature is 200°C to 300°C, and the first decomposition temperature is 400°C to 550°C.
[0020] In one embodiment, forming a gate trench in the stacked structure, the gate trench exposing the surfaces of the dielectric layers and the surfaces of the conductive layers of each layer, includes:
[0021] Etch away a part of the stacked structure along the first direction to form a first trench in the stacked structure;
[0022] Perform lateral etching on the basis of the first trench along the second direction and the third direction to remove a part of the conductive layer located between the dielectric layers of each layer to form a second trench, the first trench and the second trench together constituting the gate trench, the first direction, the second direction and the third direction intersecting pairwise.
[0023] In one embodiment, the method further includes:
[0024] Remove the first self-assembled monolayer;
[0025] Deposit a gate dielectric layer on the inner walls of the first trench and the inner walls of the second trench;
[0026] Fill a gate conductive layer in the first trench and the second trench.
[0027] In one embodiment, forming a stacked structure on the substrate, the stacked structure including dielectric layers and conductive layers stacked in sequence along a first direction, includes:
[0028] Form an initial stacked structure on the substrate, the initial stacked structure including dielectric material layers and conductive material layers alternately stacked in sequence along the first direction;
[0029] Etch away a part of the initial stacked structure along the first direction to form the stacked structure; the stacked structure includes dielectric layers and conductive layers alternately stacked in sequence along the first direction; wherein, each conductive layer includes a main body portion extending along a third direction and a plurality of branch portions located on both sides of the main body portion and spaced apart along the third direction, a first end of each branch portion being connected to the main body portion, and a second end of each branch portion being disposed away from the main body portion.
[0030] In one embodiment, after forming the stacked structure on the substrate and before forming a gate trench in the stacked structure, the method further includes:
[0031] Remove a part of the dielectric layer in contact with the surface of the branch portion to expose a part of the surface of the branch portion;
[0032] Form a continuously distributed capacitive dielectric layer on the exposed surfaces of the branch portions of each layer;
[0033] A capacitive electrode layer is formed on the surface of the capacitive dielectric layer.
[0034] In one embodiment, the material of the first self-assembled monolayer includes n-octadecyltrimethoxysilane, the material of the second self-assembled monolayer includes n-octadecylphosphoric acid, and the material of the channel layer includes a metal oxide semiconductor material.
[0035] In one embodiment, removing the first self-assembled monolayer includes:
[0036] Removing the first self-assembled monolayer using an organic solvent.
[0037] In a second aspect, the present invention also provides a semiconductor structure, which is prepared by using the preparation method of the semiconductor structure in any one of the above embodiments. The semiconductor structure includes:
[0038] A substrate;
[0039] A stacked structure, located on the substrate; the stacked structure includes a dielectric layer and a conductive layer alternately stacked in a first direction;
[0040] A gate trench, penetrating the stacked structure in the first direction to expose each layer of the dielectric layer and each layer of the conductive layer;
[0041] A channel layer, located on the surface of each layer of the conductive layer exposed by the gate trench.
[0042] In the above semiconductor structure, the channel layer is selectively deposited only on the surface of the conductive layer, and will not be deposited on the surface of the dielectric layer, thereby avoiding the formation of parasitic transistors and improving the device performance.
[0043] In one embodiment, the gate trench includes a first trench and a second trench; the first trench penetrates the stacked structure in the first direction; the second trench is located between adjacent dielectric layers and on opposite sides of the first trench in a second direction and a third direction. The second trench is correspondingly arranged with the conductive layer and is connected to the first trench; the first direction, the second direction and the third direction intersect pairwise; the semiconductor structure further includes:
[0044] A gate dielectric layer, located on the inner walls of the first trench and the second trench;
[0045] A gate conductive layer, located in the first trench and the second trench and on the surface of the gate dielectric layer.
[0046] In one embodiment, each of the conductive layers includes a main body portion extending in a third direction and a plurality of branch portions located on both sides of the main body portion and spaced apart along the third direction. A first end of each of the branch portions is connected to the main body portion, and a second end of each of the branch portions is disposed away from the main body portion.
[0047] In one embodiment, the semiconductor structure further includes:
[0048] A capacitive dielectric layer, located between adjacent branch portions and on the exposed surfaces of the branch portions of each layer;
[0049] A capacitive electrode layer, located on the surface of the capacitive dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0050] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0051] Figure 1 FIG. is a flowchart of a method for manufacturing a semiconductor structure provided in an embodiment;
[0052] Figure 2 FIG. is a flowchart of step S20 in the method for manufacturing a semiconductor structure provided in an embodiment;
[0053] Figure 3 FIG. is a top view structural schematic diagram of step S201 in the method for manufacturing a semiconductor structure provided in an embodiment;
[0054] Figure 4 FIG. is a cross-sectional structural schematic diagram of the structure obtained in step S201 provided in an embodiment, where (a) is a schematic diagram along the Figure 3 direction of AA' in, (b) is a schematic diagram along the Figure 3 direction of BB' in, (c) is a schematic diagram along the Figure 3 direction of CC' in, (d) is a schematic diagram along the Figure 3 direction of DD' in;
[0055] Figure 5 FIG. is a top view structural schematic diagram of step S202 in the method for manufacturing a semiconductor structure provided in an embodiment;
[0056] Figure 6 FIG. is a cross-sectional structural schematic diagram of the structure obtained in step S202 provided in an embodiment, where (a) is a schematic diagram along the Figure 5 direction of AA' in, (b) is a schematic diagram along theFigure 5 Schematic diagram in the BB' direction. Diagram (c) is along Figure 5 Schematic diagram in the CC' direction. Diagram (d) is along Figure 5 Schematic diagram in the DD' direction;
[0057] Figure 7 is a flowchart of the steps for preparing a capacitor in the method for preparing a semiconductor structure provided in an embodiment;
[0058] Figure 8 is a schematic cross-sectional structure diagram of the structure obtained after preparing a capacitor in an embodiment, where diagram (a) is along Figure 5 the AA' direction, diagram (b) is along Figure 5 the BB' direction, diagram (c) is along Figure 5 the CC' direction, diagram (d) is along Figure 5 the DD' direction;
[0059] Figure 9 is a schematic top view structure diagram of step S30 in the method for preparing a semiconductor structure provided in an embodiment;
[0060] Figure 10 is a schematic cross-sectional structure diagram of the structure obtained in step S301 in an embodiment, where diagram (a) is along Figure 9 the AA' direction, diagram (b) is along Figure 9 the BB' direction, diagram (c) is along Figure 9 the CC' direction, diagram (d) is along Figure 9 the DD' direction;
[0061] Figure 11 is a schematic cross-sectional structure diagram of the structure obtained in step S302 in an embodiment, where diagram (a) is along Figure 9 the AA' direction, diagram (b) is along Figure 9 the BB' direction, diagram (c) is along Figure 9 the CC' direction, diagram (d) is along Figure 9 the DD' direction;
[0062] Figure 12 is a flowchart of the steps of step S40 in the method for preparing a semiconductor structure provided in an embodiment;
[0063] Figure 13 is a schematic cross-sectional structure diagram of the structure obtained in step S401 in an embodiment, where diagram (a) is along Figure 9 the AA' direction, diagram (b) is along Figure 9 the BB' direction, diagram (c) is alongFigure 9 Schematic diagram in the CC' direction, and (d) is the schematic diagram along Figure 9 the DD' direction in;
[0064] Figure 14 is the cross-sectional structure schematic diagram of the structure obtained in step S402 provided in an embodiment, where (a) is the schematic diagram along Figure 9 the AA' direction in, (b) is the schematic diagram along Figure 9 the BB' direction in, (c) is the schematic diagram along Figure 9 the CC' direction in, and (d) is the schematic diagram along Figure 9 the DD' direction in;
[0065] Figure 15 is the cross-sectional structure schematic diagram of the structure obtained in step S403 provided in an embodiment, where (a) is the schematic diagram along Figure 9 the AA' direction in, (b) is the schematic diagram along Figure 9 the BB' direction in, (c) is the schematic diagram along Figure 9 the CC' direction in, and (d) is the schematic diagram along Figure 9 the DD' direction in;
[0066] Figure 16 is the cross-sectional structure schematic diagram of the structure obtained in step S40 in the preparation method of the semiconductor structure provided in an embodiment, where (a) is the schematic diagram along Figure 9 the AA' direction in, (b) is the schematic diagram along Figure 9 the BB' direction in, (c) is the schematic diagram along Figure 9 the CC' direction in, and (d) is the schematic diagram along Figure 9 the DD' direction in;
[0067] Figure 17 is the step flow chart for forming the gate dielectric layer and the gate conductive layer in the preparation method of the semiconductor structure provided in an embodiment;
[0068] Figure 18 is the cross-sectional structure schematic diagram of the structure obtained in step S60 in the preparation method of the semiconductor structure provided in an embodiment, where (a) is the schematic diagram along Figure 9 the AA' direction in, (b) is the schematic diagram along Figure 9 the BB' direction in, (c) is the schematic diagram along Figure 9 the CC' direction in, and (d) is the schematic diagram along Figure 9 the DD' direction in;
[0069] Figure 19 is the top view structure schematic diagram of step S80 in the preparation method of the semiconductor structure provided in an embodiment;
[0070] Figure 20 Schematic cross-sectional structure diagram of the structure obtained in step S80 in the method for preparing a semiconductor structure provided in an embodiment, where (a) is a schematic diagram along the Figure 19 AA' direction in, (b) is a schematic diagram along the Figure 19 BB' direction in, (c) is a schematic diagram along the Figure 19 CC' direction in, and (d) is a schematic diagram along the Figure 19 DD' direction in.
[0071] Explanation of reference numerals: 10 - substrate, 11 - gate trench, 101 - first trench, 102 - second trench, 111 - first self-assembled monolayer, 112 - second self-assembled monolayer, 113 - channel layer, 114 - gate dielectric layer, 115 - gate conductive layer, 20 - dielectric layer, 21 - dielectric material layer, 201 - filling layer, 30 - conductive layer, 31 - conductive material layer, 301 - main body, 302 - branch, 303 - first end, 40 - covering layer, 401 - covering dielectric layer, 501 - capacitor dielectric layer, 502 - capacitor electrode layer, 503 - filling dielectric layer. Detailed implementation manners
[0072] For ease of understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application is thorough and comprehensive.
[0073] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the specification of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.
[0074] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be referred to as a second element, component, region, layer or portion; for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0075] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. Additionally, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.
[0076] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / including" etc. specify the presence of the stated features, wholes, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.
[0077] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of preferred embodiments (and intermediate structures) of the invention, so that variations in the shapes shown can be expected due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular typically has rounded or curved features and / or an implantation concentration gradient at its edges, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the invention.
[0078] Please refer to Figure 1 , the present invention provides a method for fabricating a semiconductor structure, comprising the following steps:
[0079] S10: Provide a substrate;
[0080] S20: Form a stacked structure on the substrate, the stacked structure comprising a dielectric layer and a conductive layer alternately stacked in a first direction;
[0081] S30: Form a gate trench in the stacked structure, the gate trench penetrating the stacked structure in the first direction to expose each dielectric layer and each conductive layer;
[0082] S40: Deposit a first self-assembled monolayer on the exposed surfaces of the dielectric layers in the gate trench; the first self-assembled monolayer has a hydrophobic functional group so that the exposed surfaces of the dielectric layers are hydrophobic;
[0083] S50: Selectively deposit a channel layer on the exposed surfaces of the conductive layers in the gate trench.
[0084] In the above method for fabricating a semiconductor structure, a stacked structure is formed on the substrate, the stacked structure comprising a dielectric layer and a conductive layer alternately stacked in a first direction; a gate trench is formed in the stacked structure, the gate trench penetrating the stacked structure in the first direction to expose each dielectric layer and each conductive layer; a first self-assembled monolayer is deposited on the exposed surfaces of the dielectric layers in the gate trench; the first self-assembled monolayer has a hydrophobic functional group so that the exposed surfaces of the dielectric layers are hydrophobic; a channel layer is selectively deposited on the exposed surfaces of the conductive layers in the gate trench. Since the first self-assembled monolayer has a hydrophobic functional group, the exposed surfaces of the dielectric layers are hydrophobic, so when depositing the channel layer, the channel layer will only be selectively deposited on the surface of the conductive layer and will not be deposited on the hydrophobic surface of the dielectric layer, thereby avoiding the formation of parasitic transistors and improving the device performance.
[0085] Among them, the top view of the semiconductor structure obtained after steps S10 - S50 can be referred to Figure 9 , and the cross-sectional view can be referred to Figure 16 . Of course, Figure 9 and Figure 16 The ones shown give an example of the semiconductor structure prepared by using the preparation method of the semiconductor structure of the present invention. There can be other suitable examples of the semiconductor structure prepared by using the preparation method of the semiconductor structure of the present invention, and the present invention does not make any restrictions here.
[0086] In addition, for the convenience of understanding this solution, the first direction involved in the present invention can be the direction perpendicular to the thickness of the substrate, the second direction can be the extension direction of the AA' cut line or the BB' cut line in the top view, and the third direction can be the extension direction of the CC' cut line or the DD' cut line in the top view. Of course, in other suitable application scenarios, the first direction, the second direction, and the third direction can also have other definitions, which are not restricted here.
[0087] As Figures 3 - 4 shown, in step S10, a substrate 10 is provided.
[0088] Among them, the material of the substrate 10 can be common substrate materials, which can be silicon-containing substrates, glass, flexible substrates, etc.
[0089] For example, the substrate 10 can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (germanosilicon), silicon carbide (SiC), carbon germanosilicon (germanosilicon C), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, and also includes multilayer structures composed of these semiconductors, etc., or is silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked germanosilicon on insulator (S-germanosilicon OI), germanosilicon on insulator (germanosilicon OI) and germanium on insulator (GeOI), or can also be double-sided polished wafers (DSP), and can also be a ceramic substrate such as alumina, a quartz or glass substrate, etc. This embodiment does not make any restrictions here.
[0090] As Figures 5 - 6 shown, in step S20, a stacked structure is formed on the substrate 10, and the stacked structure includes a dielectric layer 20 and a conductive layer 30 that are alternately stacked in sequence along the first direction.
[0091] In one embodiment, as Figure 2 shown, the above step S20 includes:
[0092] S201: Form an initial stacked structure on the substrate 10. The initial stacked structure includes a dielectric material layer 21 and a conductive material layer 31 stacked alternately in sequence along a first direction, as Figures 3 - 4 shown.
[0093] S202: Etch and remove a part of the initial stacked structure along the first direction to form a stacked structure. The stacked structure includes a dielectric layer 20 and a conductive layer 30 stacked alternately in sequence along the first direction, as Figures 5 - 6 shown.
[0094] Among them, each conductive layer 30 includes a main body portion 301 extending along a third direction and a plurality of branch portions 302 located on both sides of the main body portion 301 and arranged at intervals along the third direction. The first end portion 303 of each branch portion 302 is connected to the main body portion 301, and the second end portion of each branch portion 302 is arranged away from the main body portion 301.
[0095] Among them, the material of the dielectric layer 20 may include any suitable dielectric material, such as an oxide material or a nitride material. Further, the oxide material may include at least one of silicon oxide, silicon oxynitride, silicon carbon oxide, and silicon carbon oxynitride; the nitride material may include silicon nitride, etc.
[0096] The material of the conductive layer 30 may include metal materials such as tungsten, copper, gold, titanium, silver, aluminum, etc., may also include a multi-layer metal composed of the above-mentioned metal materials, and may also include a metal alloy, etc. This embodiment does not limit here.
[0097] In one embodiment, as Figure 7 shown, after step S20 and before step S30, the method for preparing a semiconductor structure further includes:
[0098] S21: Remove a part of the dielectric layer 20 in contact with the surface of the branch portion 302 to expose a part of the surface of the branch portion 302.
[0099] S22: Form a continuously distributed capacitor dielectric layer 501 on the exposed surface of each layer of branch portion 302;
[0100] S23: Form a capacitor electrode layer 502 on the surface of the capacitor dielectric layer 501.
[0101] As Figure 8 shown, among them, the material of the capacitor dielectric layer 501 may include a dielectric material, such as a high-K material, and the material of the capacitor electrode layer 502 may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or conductive nitrides such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), etc. or a combination thereof.
[0102] Optionally, in steps S20 - S23, some steps of forming the cover layer 40, the filling layer 201, the cover dielectric layer 401, and the filling dielectric layer 503 are also interspersed, such as Figure 8 As shown, these material layers are all for protecting and supporting the stacked structure. Among them, the material of the cover layer 40 can be different from that of the dielectric layer 20, while the materials of the filling layer 201, the cover dielectric layer 401, and the filling dielectric layer 503 can be the same as that of the dielectric layer 20. For example, the materials of the dielectric layer 20, the filling layer 201, the cover dielectric layer 401, and the filling dielectric layer 503 can all be silicon dioxide, while the material of the cover layer 40 can be silicon nitride.
[0103] Such as Figure 11 As shown, in step S30, a gate trench 11 is formed in the stacked structure. The gate trench 11 penetrates the stacked structure along the first direction to expose each dielectric layer 20 and each conductive layer 30.
[0104] In one embodiment, the above step S30 includes:
[0105] S301: Etch and remove a part of the stacked structure along the first direction to form a first trench 101 in the stacked structure, as Figure 10 shown.
[0106] S302: Perform lateral etching based on the first trench 101 along the second direction and the third direction to remove part of the conductive layer 30 located between each dielectric layer 20 to form a second trench 102. The first trench 101 and the second trench 102 together form the gate trench 11; wherein, the first direction, the second direction, and the third direction intersect pairwise, as Figure 11 shown.
[0107] Among them, the wet etching or vapor etching method can be used to selectively remove part of the conductive layer 30 along the second direction and the third direction based on the first trench 101, thereby forming the second trench 102.
[0108] Such as Figure 15 As shown, in step S40, a first self - assembled monolayer film layer 111 is deposited on the exposed surfaces of each dielectric layer 20 in the gate trench 11; the first self - assembled monolayer film layer 111 has a hydrophobic functional group to make the exposed surfaces of each dielectric layer 20 hydrophobic.
[0109] In one embodiment, as Figure 12 shown, the above step S40 includes:
[0110] S401: Selectively deposit a second self - assembled monolayer film layer 112 on the exposed surfaces of each conductive layer 30 in the gate trench 11, as Figure 13 shown.
[0111] Among them, the second self-assembled monolayer 112 can be formed by an area-selective atomic layer deposition (AS-ALD) process. Area-selective atomic layer deposition is a bottom-up deposition process. A common method to achieve AS-ALD is to use a self-assembled monolayer (SAM) as an inhibitor to preferentially block the atomic layer deposition process on a surface material. A self-assembled monolayer is an organic molecule composed of a head group, an alkyl backbone, and a tail functional group. Among them, the head group binds to the substrate surface, the alkyl backbone participates in the self-assembly process through van der Waals interactions, and the tail functional group determines the final surface properties after SAM functionalization. Through the deposition method of AS-ALD, the second self-assembled monolayer 112 can be deposited only on the surface of the conductive layer 30, and will not be deposited on the surface of the dielectric layer 20.
[0112] Optionally, the material of the second self-assembled monolayer 112 may include n-octadecylphosphonic acid (ODPA). Alternatively, the material of the second self-assembled monolayer 112 may also include other self-assembled monolayer materials that can be selectively deposited on the surface of the conductive layer 30, which is not limited in this embodiment.
[0113] S402: Selectively deposit the first self-assembled monolayer 111 on the exposed surfaces of the dielectric layers 20 in the gate trench 11. The removal conditions of the first self-assembled monolayer 111 are different from those of the second self-assembled monolayer 112, as Figure 14 shown.
[0114] Among them, since the surface of the conductive layer 30 has been selectively deposited with the second self-assembled monolayer 112, the first self-assembled monolayer 111 will only be deposited on the surface of the dielectric layer 20, thus achieving selective deposition.
[0115] Optionally, the material of the first self-assembled monolayer 111 may include n-octadecyltrimethoxysilane (OTMS).
[0116] S403: Selectively remove the second self-assembled monolayer 112 to obtain the first self-assembled monolayer 111 located on the exposed surfaces of the dielectric layers 20, as Figure 15 shown.
[0117] Among them, since the removal conditions of the first self-assembled monolayer 111 are different from those of the second self-assembled monolayer 112, the second self-assembled monolayer 112 can be selectively removed while the first self-assembled monolayer 111 is retained.
[0118] Optionally, the removal conditions may include different decomposition temperatures or different removal solutions, etc., and selective removal can be achieved according to specific removal conditions. For example, the first self-assembled monolayer 111 may have a different decomposition temperature from the second self-assembled monolayer 112; or, the first self-assembled monolayer 111 may have a different removal solution from the second self-assembled monolayer 112.
[0119] In one embodiment, the first self-assembled monolayer 111 has a first decomposition temperature, and the second self-assembled monolayer 112 has a second decomposition temperature, and the first decomposition temperature is higher than the second decomposition temperature. The above step S403 includes:
[0120] Selectively removing the second self-assembled monolayer 112 within a preset temperature range, where the preset temperature range is greater than the second decomposition temperature and less than the first decomposition temperature.
[0121] In this embodiment, within the preset temperature range, the second self-assembled monolayer 112 will decompose, while the first self-assembled monolayer 111 will not decompose, thereby enabling selective removal of the second self-assembled monolayer 112.
[0122] In one embodiment, the second decomposition temperature is 200°C to 300°C, and the first decomposition temperature is 400°C to 550°C.
[0123] In one embodiment, the material of the first self-assembled monolayer 111 is n-octadecyltrimethoxysilane, and the material of the second self-assembled monolayer 112 is n-octadecylphosphoric acid.
[0124] As Figure 16 shown, in step S50, a channel layer 113 is selectively deposited on the surface of each conductive layer 30 exposed in the gate trench 11.
[0125] Among them, the material of the channel layer 113 may include a metal oxide semiconductor material, for example, it may be indium gallium zinc oxide (IGZO). When the metal oxide semiconductor material is IGZO, the leakage current of the transistor is small (the leakage current is not greater than or equal to 10A - 15A), thereby ensuring the low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide semiconductor material can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium - zinc - oxide), IZOx and other materials, as long as the leakage current of the transistor can meet the requirements, and it can be specifically adjusted according to the actual situation. The material of the gate dielectric layer 201602 may include a suitable dielectric material, for example, it may include a high - K dielectric material. The material of the word - line conductive layer 30603 may include ITO, polysilicon, a metal material or other suitable conductive materials.
[0126] Since the first self - assembled monolayer 111 has hydrophobic functional groups, the exposed surfaces of the dielectric layers 20 are hydrophobic. Therefore, when depositing the channel layer 113, the channel layer 113 will only be selectively deposited on the surface of the conductive layer 30, rather than on the surface of the hydrophobic dielectric layer 20, thereby being able to avoid the formation of parasitic transistors and improving the device performance.
[0127] In one embodiment, after step S50, as Figure 17 shown, the method further includes:
[0128] S60: Remove the first self - assembled monolayer 111;
[0129] As Figure 18 shown, the first self - assembled monolayer 111 can be removed by decomposing the first self - assembled monolayer 111 at a suitable temperature, or by dissolving the first self - assembled monolayer 111 with a suitable removing solution and other methods.
[0130] In one embodiment, an organic solvent is used to remove the first self - assembled monolayer 111. For example, the organic solvent may include anhydrous ether.
[0131] S70: Deposit a gate dielectric layer 201 on the inner walls of the first trench 101 and the second trench 102, as Figures 19 - 20 shown.
[0132] Among them, the gate dielectric layer 201 may include a suitable dielectric material, for example, it may include a high-K dielectric material.
[0133] S80: Fill the first trench 101 and the second trench 102 with a gate conductive layer 115, as Figures 19 - 20 shown.
[0134] Among them, the material of the gate conductive layer 115 may include ITO, polysilicon, a metal material, or other suitable conductive materials.
[0135] In addition, it should be noted that in the present invention, in order to more clearly show the morphology of the main body portion 301 and the branch portion 302 included in the conductive layer 30, all top views are illustrated with the conductive layer 30 as the main structure. Some irrelevant structures (such as the covering layer 40, the filling layer 201, the covering dielectric layer 401, etc.) are omitted in the top view. This is because these structures do not affect the core technical points of the present invention, and these structures are all shown in the cross-sectional view.
[0136] In another embodiment, please continue to refer to Figures 1 to 18 , the present invention also provides a semiconductor structure, which includes: a substrate 10; a stacked structure located on the substrate 10; the stacked structure includes a dielectric layer 20 and a conductive layer 30 alternately stacked in sequence along a first direction; a gate trench 11 that penetrates the stacked structure along the first direction to expose each dielectric layer 20 and each conductive layer 30; and a channel layer 113 located on the surfaces of the conductive layers 30 exposed by the gate trench 11.
[0137] In the above semiconductor structure, the channel layer 113 is only selectively deposited on the surface of the conductive layer 30, and will not be deposited on the surface of the dielectric layer 20, thereby being able to avoid forming parasitic transistors and improving the device performance.
[0138] It should be noted that the semiconductor structure in this embodiment can be prepared by using the preparation method of the semiconductor structure as described in Figures 1 to 20 .
[0139] In one embodiment, the material of the substrate 10 can be common substrate materials, such as silicon-containing substrates, glass, flexible substrates, etc. For example, the substrate 10 can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (germanium silicide), silicon carbide (SiC), silicon germanium carbide (germanium silicide C), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, and also includes multi-layer structures composed of these semiconductors, etc., or is silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanide on insulator (S-silicon germanide OI), silicon germanide on insulator (silicon germanide OI), and germanium on insulator (GeOI), or can also be double-sided polished wafers (DSP), and can also be a ceramic substrate such as alumina, a quartz or glass substrate, etc. This embodiment is not limited herein.
[0140] In one embodiment, the material of the dielectric layer 20 can include any suitable dielectric material, such as an oxide material or a nitride material. Further, the oxide material can include at least one of silicon oxide, silicon oxynitride, silicon carbon oxide, and silicon carbon oxynitride; the nitride material can include silicon nitride, etc. The material of the conductive layer 30 can include metal materials such as tungsten, copper, gold, titanium, silver, aluminum, etc., can also include multi-layer metals composed of the above-mentioned metals, and can also include metal alloys, etc. This embodiment is not limited herein.
[0141] In one embodiment, the material of the channel layer 113 may include a metal oxide semiconductor material, such as indium gallium zinc oxide (IGZO). When the metal oxide semiconductor material is IGZO, the leakage current of the transistor is small (the leakage current is not greater than or equal to 10A - 15A), thereby ensuring a low refresh rate of the dynamic memory. It should be noted that the material of the metal oxide semiconductor material can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium - zinc - oxide), IZOx and other materials, as long as the leakage current of the transistor can meet the requirements, and it can be adjusted according to the actual situation. The material of the gate dielectric layer 201602 may include a suitable dielectric material, such as a high - K dielectric material. The material of the word - line conductive layer 30603 may include ITO, polysilicon, a metal material or other suitable conductive materials.
[0142] In one embodiment, please refer to Figure 11 , the gate trench 11 may include a first trench 101 and a second trench 102; the first trench 101 penetrates the stacked structure along a first direction; the second trench 102 is located between adjacent dielectric layers 20, and is located on opposite sides of the first trench 101 along a second direction and a third direction. The second trench 102 is correspondingly arranged with the conductive layer 30 and is connected to the first trench 101; the first direction, the second direction and the third direction intersect pairwise.
[0143] In one embodiment, please combine Figures 1 to 19 , refer to Figure 20 , the semiconductor structure may further include: a gate dielectric layer 114, the gate dielectric layer 114 is located on the inner walls of the first trench 101 and the second trench 102; a gate conductive layer 115, the gate conductive layer 115 is located in the first trench 101 and the second trench 102 and is located on the surface of the gate dielectric layer 101.
[0144] In one embodiment, the gate dielectric layer 201 may include a suitable dielectric material, such as a high - K dielectric material. The material of the gate conductive layer 115 may include ITO, polysilicon, a metal material or other suitable conductive materials.
[0145] In one embodiment, as Figure 5 shown, each layer of the conductive layer 30 may include a main body portion 301 extending in the third direction and a plurality of branch portions 302 located on both sides of the main body portion 301 and arranged at intervals in the third direction. The first end portions of the branch portions 302 are connected to the main body portion 301, and the second end portions of the branch portions 302 are arranged away from the main body portion 301.
[0146] In one embodiment, please refer to Figures 1 to 19 and Figure 20 . The semiconductor structure may further include: a capacitive dielectric layer 501, which is located between adjacent branch portions 302 and on the exposed surfaces of the branch portions 302 of each layer; and a capacitive electrode layer 502, which is located on the surface of the capacitive dielectric layer 501.
[0147] In one embodiment, the material of the capacitive dielectric layer 501 may include a dielectric material, such as a high-K material. The material of the capacitive electrode layer 502 may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or conductive nitrides such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), etc., or a combination thereof.
[0148] In one embodiment, please refer to Figures 1 to 14 and Figure 15 . The semiconductor structure may further include a first self-assembled monolayer 111, which is located on the surfaces of the dielectric layers 20 of each layer exposed in the gate trench 11.
[0149] In one embodiment, the first self-assembled monolayer 111 has a hydrophobic functional group, so that the exposed surfaces of the dielectric layers 20 of each layer are hydrophobic. Specifically, the material of the first self-assembled monolayer 111 may include n-octadecyltrimethoxysilane.
[0150] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.
[0151] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.
Claims
1. A method for preparing a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming a stacked structure on the substrate, the stacked structure including dielectric layers and conductive layers alternately stacked in sequence along a first direction; Forming a gate trench in the stacked structure, the gate trench penetrating the stacked structure along the first direction to expose each layer of the dielectric layer and each layer of the conductive layer; Depositing a first self-assembled monolayer on the exposed surfaces of each layer of the dielectric layer within the gate trench; The first self-assembled monolayer has hydrophobic functional groups, such that the exposed surfaces of each layer of the dielectric layer are hydrophobic; Selectively depositing a channel layer on the exposed surfaces of each layer of the conductive layer within the gate trench.
2. The method for preparing a semiconductor structure according to claim 1, wherein The depositing a first self-assembled monolayer on the exposed surfaces of each layer of the dielectric layer within the gate trench includes: Selectively depositing a second self-assembled monolayer on the exposed surfaces of each layer of the conductive layer within the gate trench; Selectively depositing the first self-assembled monolayer on the exposed surfaces of each layer of the dielectric layer within the gate trench, the removal conditions of the first self-assembled monolayer being different from those of the second self-assembled monolayer; Selectively removing the second self-assembled monolayer to obtain the first self-assembled monolayer located on the exposed surfaces of each layer of the dielectric layer.
3. The manufacturing method of the semiconductor structure according to claim 2, wherein, The first self-assembled monolayer has a first decomposition temperature, and the second self-assembled monolayer has a second decomposition temperature, the first decomposition temperature being higher than the second decomposition temperature; The selectively removing the second self-assembled monolayer includes: Selectively removing the second self-assembled monolayer within a preset temperature range, the preset temperature range being greater than the second decomposition temperature and less than the first decomposition temperature.
4. The method for manufacturing a semiconductor structure according to claim 3, wherein, The second decomposition temperature is 200°C to 300°C, and the first decomposition temperature is 400°C to 550°C.
5. The method for manufacturing a semiconductor structure according to claim 1, wherein, The forming a gate trench in the stacked structure, the gate trench exposing the surfaces of each layer of the dielectric layer and the surfaces of each layer of the conductive layer, includes: Etching away a part of the stacked structure along the first direction to form a first trench within the stacked structure; Performing lateral etching based on the first trench along a second direction and a third direction to remove a part of the conductive layer located between each layer of the dielectric layer to form a second trench, the first trench and the second trench jointly constituting the gate trench, the first direction, the second direction and the third direction intersecting pairwise.
6. The manufacturing method of the semiconductor structure according to claim 4, wherein The method further includes: Removing the first self-assembled monolayer; Depositing a gate dielectric layer on the inner walls of the first trench and the inner walls of the second trench; Filling a gate conductive layer within the first trench and within the second trench.
7. The method for manufacturing a semiconductor structure according to claim 1, wherein, The forming a stacked structure on the substrate, the stacked structure including dielectric layers and conductive layers stacked in sequence along a first direction, includes: Forming an initial stacked structure on the substrate, the initial stacked structure including dielectric material layers and conductive material layers alternately stacked in sequence along the first direction; Etch and remove a part of the initial stacked structure along the first direction to form the stacked structure; the stacked structure includes a dielectric layer and a conductive layer alternately stacked along the first direction; wherein, each conductive layer includes a main body portion extending along the third direction and a plurality of branch portions located on both sides of the main body portion and spaced apart along the third direction, a first end portion of each branch portion is connected to the main body portion, and a second end portion of each branch portion is disposed away from the main body portion.
8. The method for preparing a semiconductor structure according to claim 7, characterized in that, After forming the stacked structure on the substrate and before forming the gate trench in the stacked structure, the method further includes: Remove a part of the dielectric layer in contact with the surface of the branch portion to expose a part of the surface of the branch portion; Form a continuously distributed capacitive dielectric layer on the exposed surface of each layer of the branch portion; Form a capacitive electrode layer on the surface of the capacitive dielectric layer.
9. The method for preparing a semiconductor structure according to claim 1, wherein, The material of the first self-assembled monolayer includes n-octadecyltrimethoxysilane, the material of the second self-assembled monolayer includes n-octadecylphosphoric acid, and the material of the channel layer includes a metal oxide semiconductor material.
10. The method for manufacturing a semiconductor structure according to claim 9, wherein, The removing of the first self-assembled monolayer includes: Removing the first self-assembled monolayer with an organic solvent.
11. A semiconductor structure, characterized in that, The semiconductor structure is prepared by using the preparation method of the semiconductor structure according to any one of claims 1-10, and the semiconductor structure includes: Substrate; Stacked structure, located on the substrate; the stacked structure includes a dielectric layer and a conductive layer alternately stacked along the first direction; Gate trench, penetrating the stacked structure along the first direction to expose each layer of the dielectric layer and each layer of the conductive layer; Channel layer, located on the surface of each layer of the conductive layer exposed by the gate trench.
12. The semiconductor structure according to claim 11, wherein, The gate trench includes a first trench and a second trench; the first trench penetrates the stacked structure along the first direction; the second trench is located between adjacent dielectric layers and on opposite sides of the first trench along the second direction and the third direction, the second trench is correspondingly arranged with the conductive layer and is communicated with the first trench; The first direction, the second direction and the third direction intersect pairwise; The semiconductor structure further includes: Gate dielectric layer, located on the inner walls of the first trench and the second trench; Gate conductive layer, located in the first trench and the second trench and on the surface of the gate dielectric layer.
13. The semiconductor structure according to claim 11, wherein, Each conductive layer includes a main body portion extending along the third direction and a plurality of branch portions located on both sides of the main body portion and spaced apart along the third direction, a first end portion of each branch portion is connected to the main body portion, and a second end portion of each branch portion is disposed away from the main body portion.
14. The semiconductor structure according to claim 13, wherein The semiconductor structure further includes: Capacitive dielectric layer, located between adjacent branch portions and on the exposed surface of each layer of the branch portion; Capacitive electrode layer, located on the surface of the capacitive dielectric layer.