Semiconductor memory device

Abstract

A semiconductor memory device includes: a substrate including an active region defined by an element isolation film; a gate electrode within the substrate and extending in a first direction; a buffer film on the substrate and extending in a second direction intersecting the first direction; a direct contact extending through the buffer film and contacting a portion of the active region; a conductive pattern on the direct contact and buffer film and extending in a second direction; and a capacitor structure on the substrate and contacting another portion of the active region. The buffer film includes a lower buffer film and an upper buffer film on the lower buffer film, the upper buffer film including a first upper insulating film, a third upper insulating film, and a second upper insulating film, the third upper insulating film including carbon.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor memory devices. Background Art

[0002] As semiconductor devices become more highly integrated, individual circuit patterns are becoming smaller and smaller to implement a greater number of semiconductor devices in the same area. For example, as the integration degree of semiconductor devices increases, the design rules of components of semiconductor devices are reduced.

[0003] In large-scale semiconductor devices, the processes of forming multiple gate electrodes, multiple contacts connected to the gate electrodes, and multiple conductive patterns become more and more complex and difficult. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor memory device with higher reliability.

[0005] According to an embodiment of the present disclosure, there is provided a semiconductor memory device including: a substrate including an active region defined by an element isolation film; a gate electrode disposed in the substrate and extending in a first direction; a buffer film disposed on the substrate and extending in a second direction intersecting the first direction; a direct contact extending through the buffer film and contacting a part of the active region; a conductive pattern disposed on the direct contact and the buffer film and extending in the second direction; and a capacitor structure disposed on the substrate and contacting another part of the active region. The buffer film includes a lower buffer film and an upper buffer film disposed on the lower buffer film, and the upper buffer film includes a first upper insulating film, a third upper insulating film, and a second upper insulating film sequentially stacked in a third direction intersecting the first direction and the second direction, and the third upper insulating film contains carbon (C).

[0006] According to another embodiment of the present disclosure, a semiconductor memory device is provided. The semiconductor memory device includes: a substrate including an active region defined by an element isolation film; a gate electrode disposed in the substrate and extending in a first direction; a lower buffer film disposed on the substrate and extending in a second direction intersecting the first direction; an upper buffer film disposed on the lower buffer film and extending in the second direction; a direct contact extending through the lower buffer film and the upper buffer film and contacting a part of the active region; a conductive pattern disposed on the direct contact and the upper buffer film and extending in the second direction; and a capacitor structure disposed on the substrate and contacting another part of the active region. The width of the lower buffer film in the first direction is greater than the width of the upper buffer film in the first direction. The lower buffer film includes a first lower insulating film, a second lower insulating film disposed on the first lower insulating film, and a third lower insulating film disposed between the first lower insulating film and the second lower insulating film. The upper buffer film includes a first upper insulating film, a second upper insulating film disposed on the first upper insulating film, and a third upper insulating film disposed between the first upper insulating film and the second upper insulating film. Each of the third lower insulating film and the third upper insulating film includes a silicon carbonitride film (SiCN).

[0007] According to still another embodiment of the present disclosure, a semiconductor memory device is provided. The semiconductor memory device includes: a substrate including an active region defined by an element isolation film; a gate electrode disposed in the substrate and extending in a first direction; a lower buffer film disposed on the substrate and extending in a second direction intersecting the first direction; an upper buffer film disposed on the lower buffer film and extending in the second direction; a direct contact extending through the lower buffer film and the upper buffer film and contacting a part of the active region; a conductive pattern disposed on the direct contact and the upper buffer film and extending in the second direction; a bit line spacer disposed along sidewalls of the conductive pattern and sidewalls of the upper buffer film and disposed on the sidewalls of the conductive pattern and the sidewalls of the upper buffer film; a buried contact disposed on the substrate and contacting another part of the active region; a landing pad electrically connected to the buried contact; and a capacitor structure electrically connected to the landing pad. The upper buffer film includes a first upper insulating film, a third upper insulating film, and a second upper insulating film stacked in a third direction intersecting the first direction and the second direction in sequence. The first upper insulating film includes a silicon oxide film, the second upper insulating film includes a silicon nitride film, and the third upper insulating film includes a silicon carbonitride film (SiCN). The thickness of the third upper insulating film is 1 nm or less. The width of the lower buffer film in the first direction is greater than the width of the upper buffer film in the first direction. At least a part of the lower buffer film overlaps with the bit line spacer in the third direction.

[0008] Details of other embodiments are included in the detailed description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a top view of a semiconductor memory device according to some embodiments of the present disclosure.

[0010] Figure 2 is Figure 1 an enlarged view of region P in

[0011] Figure 3 is Figure 2 a cross-sectional view taken along line A-A in

[0012] Figure 4 is Figure 2 a cross-sectional view taken along line B-B in

[0013] Figure 5 is Figure 2 a cross-sectional view taken along line C-C in

[0014] Figure 6 is Figure 3 an enlarged view of region Q in

[0015] Figures 7 to 12 illustrates a semiconductor memory device according to some embodiments of the present disclosure.

[0016] Figures 13 to 19 illustrates an intermediate structure corresponding to an intermediate step of a method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] It should be understood that when a first component is described as being in contact with a second component, the first component is in direct contact with the second component, and no additional component is inserted therebetween.

[0018] In the drawings of a semiconductor memory device according to some embodiments, a DRAM (Dynamic Random Access Memory) is shown by way of example. However, the embodiments of the present disclosure are not necessarily limited thereto. Hereinafter, reference will be made to Figures 1 to 6 describe a semiconductor memory device according to some embodiments of the present disclosure.

[0019] Figure 1 is a top view of a semiconductor memory device according to some embodiments of the present disclosure.

[0020] Reference Figure 1, A semiconductor memory device according to some embodiments includes a cell region CAR. The cell region CAR includes a plurality of memory cells. Each of the plurality of cell regions CAR constitutes a unit cell block. The cell regions CAR are spaced apart from each other in a first direction D1 and a second direction D2, and a core region COR is provided between the cell regions CAR. The core region COR is a region that provides read amplifiers and write drivers. A peripheral circuit region POR is provided on one side of the cell region CAR. The peripheral circuit region POR includes a row decoder, a column decoder, and the like. Although the peripheral circuit region POR is shown as being provided on one side of the cell region CAR, the peripheral circuit region POR can also be provided on other sides of the cell region CAR.

[0021] Figure 2 is Figure 1 An enlarged view of region P in. Figure 3 is along Figure 2 A cross-sectional view taken along line A-A in. Figure 4 is along Figure 2 A cross-sectional view taken along line B-B in. Figure 5 is along Figure 2 A cross-sectional view taken along line C-C in. Figure 6 is Figure 3 An enlarged view of region Q in.

[0022] Refer to Figures 2 to 6 , In some embodiments, a substrate 100 is provided. The substrate 100 can be, for example, a silicon single crystal substrate or a silicon-on-insulator (SOI) substrate. The substrate 100 can also include, but is not necessarily limited to, silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide.

[0023] An element isolation film 105 is provided within the substrate 100. Element isolation trenches are formed within the substrate 100. The element isolation film 105 is provided within the element isolation trenches.

[0024] Furthermore, the element isolation film 105 includes a first liner film, a buried insulating film, and a second liner film. The first liner film conformally covers the inner walls and bottom surface of the element isolation trenches. The buried insulating film fills the element isolation trenches. The second liner film is interposed between the first liner film and the buried insulating film.

[0025] The first liner film is a silicon oxide film. The second liner film is a silicon nitride film. The buried insulating film is a silicon oxide film.

[0026] The element isolation film 105 defines a plurality of active regions ACT. As the design rule of the semiconductor memory device decreases, the plurality of active regions ACT form stripes extending along a diagonal or an oblique line, as Figure 2 shown. For example, the plurality of active regions ACT extend in a fourth direction D4.

[0027] A plurality of active regions ACT are parallel to each other in a first direction D1. An end of one active region ACT among the plurality of active regions ACT is adjacent to the center of an adjacent other active region ACT. In the present disclosure, the first direction D1, the second direction D2, the third direction D3, and the fourth direction D4 intersect each other. The first direction D1, the second direction D2, and the third direction D3 are substantially perpendicular to each other. The fourth direction D4, the first direction D1, and the second direction D2 form the same plane. That is, the fourth direction D4 is an arbitrary direction between the first direction D1 and the second direction D2.

[0028] A semiconductor memory device according to some embodiments includes various contact arrangements formed on a plurality of active regions ACT. The various contact arrangements include, for example, a direct contact DC, a buried contact BC, and a landing pad LP.

[0029] For example, the direct contact DC electrically connects the plurality of active regions ACT to the bit line BL. The buried contact BC connects the plurality of active regions ACT to the capacitor lower electrode 191. Due to this arrangement structure, the contact area between the buried contact BC and the active region ACT is small. Therefore, the landing pad LP is introduced to increase its contact area with the active region ACT while increasing its contact area with the capacitor lower electrode 191.

[0030] The landing pad LP is disposed between the active region ACT and the buried contact BC, and between the buried contact BC and the capacitor lower electrode 191. In a semiconductor memory device according to some embodiments, the landing pad LP is disposed between the buried contact BC and the capacitor lower electrode 191. By introducing the landing pad LP to increase the contact area, the contact resistance between the active region ACT and the capacitor lower electrode 191 is reduced.

[0031] The word line WL is buried in the substrate 100. The word line WL extends across a plurality of active regions ACT. The word line WL extends in the first direction D1. The word lines WL are spaced apart from each other in the second direction D2. The word line WL is buried in the substrate 100. In addition, a doped region is formed in the active region ACT and between the word lines WL. The doped region is doped with an N-type impurity.

[0032] A semiconductor memory device according to some embodiments includes a plurality of word line structures 110. Each of the plurality of word line structures 110 may be embedded in the substrate 100 and extend in the first direction D1. The plurality of word line structures 110 are spaced apart from each other in the second direction D2.

[0033] Each of the plurality of word line structures 110 includes a gate insulating film 111, a gate electrode 112, and gate capping films 113 and 114. According to some embodiments, the gate electrode 112 of the word line structure 110 corresponds to the word line WL of the semiconductor memory device. Each of the plurality of word line structures 110 is disposed in a gate trench 110t formed in a substrate 100.

[0034] The gate insulating film 111 extends along the inner wall and bottom surface of the gate trench 110t. The gate insulating film 111 extends along the contour of at least a portion of the gate trench 110t. The gate insulating film 111 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, or a high-k material having a higher dielectric constant than silicon oxide. The high-k material includes, for example, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. However, the embodiments of the present disclosure are not necessarily limited thereto.

[0035] The gate electrode 112 is disposed on the gate insulating film 111. The gate electrode 112 fills a portion of the gate trench 110t. The gate capping films 113 and 114 are disposed on the gate electrode 112. The gate capping films 113 and 114 fill the remaining portion of the gate trench 110t after the gate electrode 112 is formed therein.

[0036] In some embodiments, the gate capping films 113 and 114 include a gate capping conductive film 113 and a gate capping insulating film 114. The gate capping conductive film 113 and the gate capping insulating film 114 are stacked in sequence. For example, the gate capping insulating film 114 is disposed on the gate capping conductive film 113. The gate capping conductive film 113 includes, for example, polysilicon or polysilicon germanium. However, the embodiments of the present disclosure are not necessarily limited thereto. The gate capping insulating film 114 includes at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or a combination thereof.

[0037] The gate electrode 112 includes at least one of a metal, a metal alloy, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride, or a conductive metal oxide. The gate electrode 112 includes, for example, at least one of TiN, TaC, TaN, TiSiN, TaSiN, TaTiN, TiAlN, TaAlN, WN, Ru, TiAl, TiAlC-N, TiAlC, TiC, TaCN, W, Al, Cu, Co, Ti, Ta, Ni, Pt, Ni-Pt, Nb, NbN, NbC, Mo, MoN, MoC, WC, Rh, Pd, Ir, Ag, Au, Zn, V, RuTiN, TiSi, TaSi, NiSi, CoSi, IrOx, RuOx, or a combination thereof. However, embodiments of the present disclosure are not necessarily limited thereto.

[0038] The buffer film 120 is disposed on the substrate 100. The buffer film 120 extends in the second direction D2. The buffer film 120 includes a lower buffer film 121 and an upper buffer film 122 stacked in sequence in the third direction D3. For example, the upper buffer film 122 is disposed on the lower buffer film 121. The lower buffer film 121 is interposed between the substrate 100 and the upper buffer film 122. The buffer film 120 will be described in detail below with reference to Figure 6 The buffer film 120 will be described in detail.

[0039] The bit line BL is disposed on the substrate 100. The bit line BL is disposed on the buffer film 120. The bit line BL intersects the word line WL. The bit line BL extends in the second direction D2. The bit lines BL are spaced apart from each other in the first direction D1. The bit line BL corresponds to the conductive pattern 130.

[0040] The conductive pattern 130 includes a first electrode 131 and a second electrode 132 stacked in sequence in the third direction D3. For example, the second electrode 132 is disposed on the first electrode 131. The first electrode 131 is in direct contact with the direct contact DC. In addition, the first electrode 131 is in contact with the buffer film 120. For example, the conductive pattern 130 contacts the buffer film 120. For example, the conductive pattern 130 contacts the upper buffer film 122. For example, the first electrode 131 of the conductive pattern 130 contacts the upper surface 122US of the upper buffer film 122.

[0041] The first electrode 131 includes TiSiN. The second electrode 132 includes tungsten (W). However, embodiments of the present disclosure are not necessarily limited thereto.

[0042] The bit line capping pattern 140 is disposed on the conductive pattern 130. The bit line capping pattern 140 includes a first capping pattern 141 and a second capping pattern 142 stacked in sequence. For example, the second capping pattern 142 is disposed on the first capping pattern 141. Each of the first capping pattern 141 and the second capping pattern 142 is a silicon nitride film.

[0043] The bit line spacer 150 is disposed on sidewalls of the conductive pattern 130 and sidewalls of the bit line capping pattern 140. In Figure 3 , the bit line spacer 150 is disposed on the substrate 100 and the element isolation film 105 in a region where the conductive pattern 130 is formed to directly contact the DC. However, in a region where it does not form a direct contact with the DC, the bit line spacer 150 is disposed on the buffer film 120. For example, in a region where it does not form a direct contact with the DC, the bit line spacer 150 is disposed on the lower buffer film 121.

[0044] The bit line spacer 150 contacts the upper surface of the lower buffer film 121. The bit line spacer 150 overlaps at least a portion of the lower buffer film 121 in the third direction D3. In addition, at least a portion of the bit line spacer 150 contacts the sidewall of the upper buffer film 122. At least a portion of the bit line spacer 150 overlaps the upper buffer film 122 in the first direction D1.

[0045] The bit line spacer 150 may include a single layer or multiple layers. When the bit line spacer 150 has a single layer, the bit line spacer 150 is at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiON), or a silicon oxycarbonitride film (SiOCN). As Figure 6 shown, when the bit line spacer 150 is formed as multiple layers, the bit line spacer 150 includes a first spacer 151 and a second spacer 152. The second spacer 152 is disposed on the first spacer 151. Each of the first spacer 151 and the second spacer 152 includes at least one of, for example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiON), a silicon oxycarbonitride film (SiOCN), air, or a combination thereof. However, embodiments of the present disclosure are not necessarily limited thereto.

[0046] The bit line BL is electrically connected to the doped region of the active region ACT through the direct contact DC. The direct contact DC is made of, for example, polysilicon doped with impurities.

[0047] The direct contact DC extends through the buffer film 120 and is connected to the active region ACT. The direct contact DC extends through both the upper buffer film 122 and the lower buffer film 121. The upper surface DC_US of the direct contact DC is coplanar with the upper surface 122US of the upper buffer film 122.

[0048] The buried contact BC is disposed between a pair of adjacent bit lines BL. The buried contacts BC are spaced apart from each other. The buried contact BC includes at least one of polysilicon doped with impurities, a conductive silicide compound, a conductive metal nitride, or a metal. The buried contact BC has an island shape spaced apart from each other in a plan view. The buried contact BC extends through the buffer film 120 and contacts the doped region of the active region ACT. For example, the buried contact BC extends through the lower buffer film 121 of the buffer film 120 and contacts the doped region of the active region ACT.

[0049] The landing pad LP is formed on the buried contact BC. The landing pad LP is electrically connected to the buried contact BC. The landing pad LP overlaps a part of the upper surface of the bit line BL. For example, the landing pad LP includes at least one of a doped semiconductor material, a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a metal, or a metal alloy.

[0050] The fence pattern 170 is disposed on the substrate 100 and the element isolation film 105. The fence pattern 170 is disposed on the word line structure 110. In addition, the fence pattern 170 overlaps the word line structure 110 formed in the substrate 100. The fence pattern 170 is disposed between the conductive patterns 130 extending in the second direction D2. For example, the fence pattern 170 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0051] The pad isolation insulating film 180 is formed adjacent to the landing pad LP and on the conductive pattern 130. For example, the pad isolation insulating film 180 is disposed on the bit line covering pattern 140. The pad isolation insulating film 180 defines the area of the landing pad LP that constitutes a plurality of isolation regions. In addition, the pad isolation insulating film 180 does not cover the upper surface of the landing pad LP.

[0052] The pad isolation insulating film 180 includes an insulating material and electrically isolates the plurality of landing pads LP from each other. For example, the pad isolation insulating film 180 includes at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon carbon oxynitride film.

[0053] The etch stop film 185 is disposed on the pad isolation insulating film 180 and the landing pad LP. The etch stop film 185 includes at least one of a silicon nitride film, a silicon carbon nitride film, a silicon boron nitride film (SiBN), a silicon oxynitride film, or a silicon carbon oxide film.

[0054] The capacitor structure 190 is disposed on the landing pad LP. The capacitor structure 190 is electrically connected to the landing pad LP. A part of the capacitor structure 190 is disposed within the etch stop film 185. The capacitor structure 190 includes a capacitor lower electrode 191, a capacitor dielectric film 192, and a capacitor upper electrode 193.

[0055] The capacitor lower electrode 191 is disposed on the landing pad LP. The capacitor lower electrode 191 is shown as having a columnar shape. However, embodiments of the present disclosure are not necessarily limited thereto. In some embodiments, the capacitor lower electrode 191 has a cylindrical shape. The capacitor dielectric film 192 is formed on the capacitor lower electrode 191. The capacitor dielectric film 192 is formed along the contour of the capacitor lower electrode 191. The capacitor upper electrode 193 is formed on the capacitor dielectric film 192. The capacitor upper electrode 193 surrounds the outer wall of the capacitor lower electrode 191.

[0056] In an embodiment, the capacitor dielectric film 192 vertically overlaps with the capacitor upper electrode 193. In an embodiment, different from that shown, the capacitor dielectric film 192 includes a portion that vertically overlaps with the capacitor upper electrode 193 and a portion that does not vertically overlap with the capacitor upper electrode 193. For example, the portion of the capacitor dielectric film 192 that does not vertically overlap with the capacitor upper electrode 193 is the portion not covered by the capacitor upper electrode 193.

[0057] Each of the capacitor lower electrode 191 and the capacitor upper electrode 193 includes, for example, a doped semiconductor material, a conductive metal nitride (such as titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride, etc.), a metal (such as ruthenium, iridium, titanium, or tantalum, etc.), or a conductive metal oxide (such as iridium oxide or niobium oxide, etc.). However, embodiments of the present disclosure are not necessarily limited thereto.

[0058] The capacitor dielectric film 192 includes, for example, one of silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant (high-k) material, or a combination thereof. However, embodiments of the present disclosure are not necessarily limited thereto. In a semiconductor memory device according to some embodiments, the capacitor dielectric film 192 includes a stacked film structure in which a zirconia film, an alumina film, and a zirconia film are stacked in sequence. In a semiconductor memory device according to some embodiments, the capacitor dielectric film 192 includes a dielectric film containing hafnium (Hf). In a semiconductor memory device according to some embodiments, the capacitor dielectric film 192 has a stacked structure of a ferroelectric material film and a paraelectric material film.

[0059] Hereinafter, with reference to Figure 6 the buffer film 120 according to some embodiments of the present disclosure will be described in more detail.

[0060] With reference to Figure 6 in some embodiments, the buffer film 120 includes a lower buffer film 121 and an upper buffer film 122. The lower buffer film 121 and the upper buffer film 122 are stacked in sequence in the third direction D3. For example, the upper buffer film 122 is disposed on the lower buffer film 121.

[0061] In some embodiments, a first width W1 of the lower buffer film 121 in a first direction D1 is greater than a second width W2 of the upper buffer film 122 in the first direction D1. This is because when forming the conductive pattern 130, the upper buffer film 122 is patterned like the conductive pattern 130, while when forming the conductive pattern 130, the lower buffer film 121 is not patterned like the conductive pattern 130. Accordingly, the first width W1 is greater than the second width W2.

[0062] For example, the first width W1 is the minimum width of the lower buffer film 121 in the first direction D1. The second width W2 is the maximum width of the upper buffer film 122 in the first direction D1. However, embodiments of the present disclosure are not necessarily limited thereto.

[0063] The lower buffer film 121 includes a first lower insulating film 121a and a second lower insulating film 121b. The first lower insulating film 121a and the second lower insulating film 121b are sequentially stacked in a third direction D3. For example, the second lower insulating film 121b is disposed on the first lower insulating film 121a.

[0064] The first lower insulating film 121a is disposed on the substrate 100 and the element isolation film 105. A part of the lower surface of the first lower insulating film 121a contacts the substrate 100, and another part of the lower surface of the first lower insulating layer 121a contacts the element isolation film 105. Sidewalls of the first lower insulating film 121a contact the buried contact BC. In Figure 5 this, sidewalls of the first lower insulating film 121a contact the gate pattern 170.

[0065] The second lower insulating film 121b is interposed between the first lower insulating film 121a and the upper buffer film 122. The lower surface of the second lower insulating film 121b contacts the first lower insulating film 121a. The upper surface of the second lower insulating film 121b contacts the upper buffer film 122. For example, the upper surface of the second lower insulating film 121b contacts the first upper insulating film 122a. Sidewalls of the second lower insulating film 121b contact the buried contact BC. In Figure 5 this, sidewalls of the second lower insulating film 121b contact the gate pattern 170.

[0066] In some embodiments, each of the first lower insulating film 121a and the second lower insulating film 121b includes an insulating material. In an embodiment, the first lower insulating film 121a is a silicon oxide film. The second lower insulating film 121b is a silicon nitride film. However, embodiments of the present disclosure are not necessarily limited thereto.

[0067] In some embodiments, the first lower insulating film 121a has a first thickness th1 in the third direction D3. The second lower insulating film 121b has a second thickness th2 in the third direction D3. The first thickness th1 is greater than the second thickness th2. In an embodiment, the first thickness th1 is about 3 nm and the second thickness th2 is about 2 nm. However, the embodiments of the present disclosure are not necessarily limited thereto.

[0068] The upper buffer film 122 includes a first upper insulating film 122a, a second upper insulating film 122b, and a third upper insulating film 122c. The first upper insulating film 122a, the third upper insulating film 122c, and the second upper insulating film 122b are stacked in sequence in the third direction D3. For example, the second upper insulating film 122b is disposed on the first upper insulating film 122a. The third upper insulating film 122c is interposed between the first upper insulating film 122a and the second upper insulating film 122b. For example, the first upper insulating film 122a is disposed at the lowest height of the upper buffer film 122. The second upper insulating film 122b is disposed at the highest height of the upper buffer film 122. The third upper insulating film 122c is disposed at the intermediate height of the upper buffer film 122.

[0069] The first upper insulating film 122a is disposed on the lower buffer film 121. The lower surface of the first upper insulating film 122a contacts the lower buffer film 121. The sidewall of the first upper insulating film 122a contacts the bit line spacer 150. For example, the sidewall of the first upper insulating film 122a contacts the first spacer 151.

[0070] The second upper insulating film 122b is disposed on the first upper insulating film 122a. The second upper insulating film 122b is interposed between the first upper insulating film 121a and the conductive pattern 130. The lower surface of the second upper insulating film 122b contacts the third upper insulating film 122c. The upper surface of the second upper insulating film 122b contacts the conductive pattern 130. For example, the upper surface of the second upper insulating film 122b contacts the first electrode 131. The sidewall of the second upper insulating film 122b contacts the first spacer 151.

[0071] The third upper insulating film 122c is disposed on the first upper insulating film 122a. The lower surface of the third upper insulating film 122c contacts the first upper insulating film 122a. The upper surface of the third upper insulating film 122c contacts the second upper insulating film 122b.

[0072] In some embodiments, each of the first upper insulating film 122a, the second upper insulating film 122b, and the third upper insulating film 122c includes an insulating material. In an embodiment, the first upper insulating film 122a is a silicon oxide film. The second upper insulating film 122b is a silicon nitride film. The third upper insulating film 122c is a silicon carbonitride film (SiCN). For example, the third upper insulating film 122c contains carbon (C). However, the embodiments of the present disclosure are not necessarily limited thereto.

[0073] In some embodiments, the first upper insulating film 122a has a third thickness th3 in the third direction D3. The second upper insulating film 122b has a fourth thickness th4 in the third direction D3. The third upper insulating film 122c has a fifth thickness th5 in the third direction D3. The third thickness th3 is equal to the fourth thickness th4. The fifth thickness th5 is less than each of the third thickness th3 and the fourth thickness th4.

[0074] In an embodiment, each of the third thickness th3 and the fourth thickness th4 is about 3 nm. The fifth thickness th5 is 1 nm or less. However, embodiments of the present disclosure are not necessarily limited thereto.

[0075] In some embodiments, since the upper buffer film 122 includes the third upper insulating film 122c, the buffer film 120 can be prevented from collapsing when performing a process of forming a direct contact DC and subsequent processes. Further, since the thickness of the third upper insulating film 122c is less than 1 nm, an etchant is effectively prevented from penetrating the third upper insulating film 122c in a subsequent process.

[0076] Hereinafter, Figures 7 to 12 a semiconductor memory device according to some further embodiments of the present disclosure will be described. For ease of description, repeated descriptions of components described using Figures 2 to 6 may be outlined or omitted.

[0077] Figures 7 to 12 A semiconductor memory device according to some embodiments of the present disclosure is illustrated. For reference, Figures 7 to 12 is Figure 3 an enlarged view of region Q of

[0078] Referring to Figure 7 , in an embodiment, the sidewall of the upper buffer film 122 is inclined. For example, the sidewall of the first upper insulating film 122a of the upper buffer film 122 is inclined. For example, the width of the first upper insulating film 122a in the first direction D1 gradually decreases as the distance from the lower buffer film 121 increases.

[0079] For example, each of the width of the second upper insulating film 122b and the width of the third upper insulating film 122c is constant as the distance from the lower buffer film 121 increases. However, embodiments of the present disclosure are not necessarily limited thereto. In some embodiments, the width of each of the third upper insulating film 122c and the second upper insulating film 122b decreases as the distance from the lower buffer film 121 increases. This may be because the first upper insulating film 122a is etched less during the process of patterning the conductive pattern 130.

[0080] The second width W2 of the upper buffer film 122 in the first direction D1 is the width of the lower surface of the first upper insulating film 122a in the first direction D1. The width of the lower surface of the first upper insulating film 122a in the first direction D1 is the maximum width of the upper buffer film 122 in the first direction D1. The width of the lower surface of the first upper insulating film 122a in the first direction D1 is less than the first width W1 of the lower buffer film 121 in the first direction D1.

[0081] Reference Figure 8 In an embodiment, the third thickness th3 of the first upper insulating film 122a is greater than the fourth thickness th4 of the second upper insulating film 122b. The fourth thickness th4 of the second upper insulating film 122b is equal to the second thickness th2 of the second lower insulating film 121b. The third thickness th3 of the first upper insulating film 122a is equal to the first thickness th1 of the first lower insulating film 121a.

[0082] For example, each of the third thickness th3 of the first upper insulating film 122a and the first thickness th1 of the first lower insulating film 121a is about 3 nm. Each of the fourth thickness th4 of the second upper insulating film 122b and the second thickness th2 of the second lower insulating film 121b is about 2 nm. However, the embodiments of the present disclosure are not necessarily limited thereto.

[0083] Reference Figure 9 In an embodiment, the third thickness th3 of the first upper insulating film 122a is less than the fourth thickness th4 of the second upper insulating film 122b. The fourth thickness th4 of the second upper insulating film 122b is greater than the second thickness th2 of the second lower insulating film 121b. The third thickness th3 of the first upper insulating film 122a is equal to the first thickness th1 of the first lower insulating film 121a.

[0084] For example, each of the third thickness th3 of the first upper insulating film 122a and the first thickness th1 of the first lower insulating film 121a is about 3 nm. The fourth thickness th4 of the second upper insulating film 122b is about 4 nm. The second thickness th2 of the second lower insulating film 121b is about 2 nm. However, the embodiments of the present disclosure are not necessarily limited thereto.

[0085] For example, reference Figure 6 、 Figure 8 and Figure 9 In an embodiment, the fourth thickness th4 of the second upper insulating film 122b is in the range of 2 nm to 4 nm (including 2 nm and 4 nm). However, the embodiments of the present disclosure are not necessarily limited thereto.

[0086] Reference Figure 10, in an embodiment, the upper buffer film 122 further includes a fourth upper insulating film 122d. For example, the upper buffer film 122 includes a first upper insulating film 121a, a second upper insulating film 122b, a third upper insulating film 122c, and a fourth upper insulating film 1220d.

[0087] The first upper insulating film 122a, the fourth upper insulating film 122d, the third upper insulating film 1220c, and the second upper insulating film 122b are sequentially stacked in a third direction D3. For example, the fourth upper insulating film 122d is disposed on the first upper insulating film 122a. The third upper insulating film 122c is disposed on the fourth upper insulating film 122d. The second upper insulating film 122b is disposed on the third upper insulating film 122c. For example, the fourth upper insulating film 122d is interposed between the first upper insulating film 122a and the third upper insulating film 1220c. The third upper insulating film 122c is interposed between the fourth upper insulating film 1220d and the second upper insulating film 122b.

[0088] In some embodiments, the fourth upper insulating film 122d includes a silicon oxynitride film (SiON). Before the third upper insulating film 122c is formed on the first upper insulating film 122a, nitrogen (N) may react with the silicon oxide in the first upper insulating film 122a. The silicon oxide and nitrogen (N) react with each other to produce silicon oxynitride. However, the embodiments of the present disclosure are not necessarily limited thereto.

[0089] In some embodiments, the fourth upper insulating film 122d is formed between the third upper insulating film 122a and the second upper insulating film 122b.

[0090] Reference Figure 11 , in an embodiment, the lower buffer film 121 further includes a third lower insulating film 121c.

[0091] The first lower insulating film 121a, the third lower insulating film 121c, and the second lower insulating film 121b are sequentially stacked in a third direction D3. For example, the second lower insulating film 121b is disposed on the first lower insulating film 121a. The third lower insulating film 121c is interposed between the first lower insulating film 121a and the second lower insulating film 121b. For example, the first lower insulating film 121a is disposed at the lowest height of the lower buffer film 121. The second lower insulating film 121b is disposed at the highest flat height of the lower buffer film 121. The third lower insulating film 121c is disposed at the intermediate height of the lower buffer film 121.

[0092] The third lower insulating film 121c is disposed on the first lower insulating film 121a. The lower surface of the third lower insulating film 121c is in contact with the first lower insulating film 121a. The upper surface of the third lower insulating film 121c is in contact with the second lower insulating film 121b. The third lower insulating film 121c is a silicon carbonitride film (SiCN). For example, the third lower insulating film 121c contains carbon (C).

[0093] In some embodiments, the third lower insulating film 121c has a sixth thickness th6 in the third direction D3. The sixth thickness th6 of the third lower insulating film 121c is equal to the fifth thickness th5 of the third upper insulating film 122c. For example, the sixth thickness th6 of the third lower insulating film 121c is 1 nm or less.

[0094] In some embodiments, since the lower buffer film 121 includes the third lower insulating film 121c, the buffer film 120 can be prevented from collapsing when performing the process of forming the direct contact DC and subsequent processes. In addition, since the thickness of the third lower insulating film 121c is less than 1 nm, it is effectively prevented that the etchant penetrates through the third lower insulating film 121c in subsequent processes.

[0095] Reference Figure 12 In an embodiment, the lower buffer film 121 further includes a fourth lower insulating film 121d. For example, the lower buffer film 121 includes a first lower insulating film 121a, a second lower insulating film 121b, a third lower insulating film 121c, and a fourth lower insulating film 121d.

[0096] The first lower insulating film 121a, the fourth lower insulating film 121d, the third lower insulating film 121c, and the second lower insulating film 121b are sequentially stacked in the third direction D3. For example, the fourth lower insulating film 121d is disposed on the first lower insulating film 121a. The third lower insulating film 121c is disposed on the fourth lower insulating film 121d. The second lower insulating film 121b is disposed on the third lower insulating film 121c. For example, the fourth lower insulating film 121d is interposed between the first lower insulating film 121a and the third lower insulating film 121c. The third lower insulating film 121c is interposed between the fourth lower insulating film 121d and the second lower insulating film 121b.

[0097] In some embodiments, the fourth lower insulating film 121d is a silicon oxynitride film (SiON). Before the third lower insulating film 121c is formed on the first lower insulating film 121a, nitrogen (N) may react with the silicon oxide in the first lower insulating film 121a. The silicon oxide and nitrogen N react with each other to produce silicon oxynitride. However, the embodiments of the present disclosure are not necessarily limited thereto.

[0098] In some embodiments, the fourth lower insulating film 121d is formed between the third lower insulating film 121c and the second lower insulating film 121b.

[0099] Hereinafter, reference Figures 13 to 19 is made to describe a method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure.

[0100] Figures 13 to 19 An intermediate structure corresponding to an intermediate step of a method for manufacturing a semiconductor memory device according to some embodiments of the present disclosure is illustrated.

[0101] Reference Figure 13 , in an embodiment, a substrate 100 is provided. An element isolation film 105 is formed in the substrate 100. The element isolation film 105 defines an active region ACT. Word lines WL are formed in the substrate 100. Gate trenches ( Figure 4 110t in Figure 4 ) are formed in the substrate 100. The gate trenches extend in a first direction D1. A gate insulating film ( Figure 4 111 in Figure 4 ), a gate electrode (

[0102] 112 in

[0103] ) and gate capping films (

[0104] 113 and 114 in

[0105] ) are formed in the gate trenches. An ion implantation process is performed on the entire surface of the substrate 100. The ion implantation process forms doped regions in the active region ACT.

[0106] A pre-buffer film 120P is formed on the substrate 100. The pre-buffer film 120P is formed along the upper surface of the substrate 100 and the upper surface of the element isolation film 105. The pre-buffer film 120P includes a pre-lower buffer film 121P and a pre-upper buffer film 122P. The pre-lower buffer film 121P is formed first, and then the pre-upper buffer film 122P is formed.

[0107] The pre-lower buffer film 121P includes a pre-first lower insulating film 121aP and a pre-second lower insulating film 121bP. The pre-upper buffer film 122P includes a pre-first upper insulating film 122aP, a pre-third upper insulating film 1220cP, and a pre-second upper insulating film 122bP.

[0108] For example, providing a hexachloro disilane (HCD) precursor, providing ethylene gas, heating, and providing ammonia gas are defined as one cycle, and a pre-third upper insulating film 122cP is formed by repeating two or more cycles.

[0109] Reference Figure 14 , in an embodiment, a mask film MASK is formed on the buffer film 120. The mask film MASK has an opening formed therein, and the opening substantially defines the position of direct contact DC. The mask film MASK is at least one of a photoresist film, an amorphous carbon layer (ACL), a spin-on hard mask (SOH), a spin-on carbon (SOC) film, a silicon oxide film, or a silicon nitride film.

[0110] Reference Figure 15 , in an embodiment, a trench t is formed using the mask film MASK as an etching mask. For example, the trench t extends through a portion of the pre-buffer film 120P. In addition, portions of the element isolation film 105 and the substrate 100 are removed.

[0111] Reference Figure 16 , in an embodiment, a pre-direct contact PDC is formed. The pre-direct contact PDC fills the trench t. The pre-direct contact PDC covers the entire upper surface of the mask film MASK. The pre-direct contact PDC is a polysilicon film doped with impurities.

[0112] Reference Figure 17 , in an embodiment, a CMP process is performed to partially remove the pre-direct contact PDC and form the direct contact DC. The pre-buffer film 120P is exposed by the CMP process. Thus, the upper surface of the pre-buffer film 120P is coplanar with the upper surface of the direct contact DC.

[0113] Reference Figure 18 , in an embodiment, a pre-first electrode 131P, a pre-second electrode 132P, a pre-first covering pattern 141P, and a pre-second covering pattern 142P are formed in sequence. The pre-first electrode 131P, the pre-second electrode 132P, the pre-first covering pattern 141P, and the pre-second covering pattern 142P are formed on the pre-buffer film 120P and the direct contact DC. The pre-first electrode 131P and the pre-second electrode 132P constitute a pre-conductive pattern 130P. The pre-first covering pattern 141P and the pre-second covering pattern 142P constitute a pre-bit line covering pattern 140P.

[0114] The pre-first electrode 131P is a TiSiN film. The pre-second electrode 132P is a tungsten (W) film. Each of the pre-first covering pattern 141P and the pre-second covering pattern 142P is a silicon nitride film.

[0115] Reference Figure 19, in an embodiment, the pre-first electrode 131P, the pre-second electrode 132P, the pre-first capping pattern 141P, and the pre-second capping pattern 142P are patterned to form a conductive pattern 130 and a bit line capping pattern 140. For example, a portion of the pre-buffer film 120P is patterned. The pre-upper buffer film 122P and the pre-lower buffer film 121P are patterned simultaneously. The pre-upper buffer film 122P is patterned to form an upper buffer film 122. The pre-lower buffer film 121P is patterned to form a lower buffer film 121.

[0116] The lower buffer film 121 includes a first lower insulating film 121a and a second lower insulating film 121b. The upper buffer film 122 includes a first upper insulating film 122a, a second upper insulating film 122b, and a third upper insulating film 122c. Since the upper buffer film 122 includes the third upper insulating film 122c, the upper buffer film 122 can be prevented from collapsing in subsequent processes. Therefore, a semiconductor memory device with improved reliability can be manufactured.

[0117] Although embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above embodiments and can be implemented in various different forms. Those skilled in the art can understand that the embodiments of the present disclosure can be practiced in other specific forms without changing the technical spirit or basic characteristics of the present disclosure. Therefore, it should be understood that the above embodiments are not restrictive in all aspects but illustrative.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A substrate, the substrate including an active region defined by an element isolation film; A gate electrode, the gate electrode disposed within the substrate and extending in a first direction; A buffer film, the buffer film disposed on the substrate and extending in a second direction intersecting the first direction; A direct contact, the direct contact extending through the buffer film and contacting a portion of the active region; A conductive pattern, the conductive pattern disposed on the direct contact and the buffer film and extending in the second direction; And A capacitor structure, the capacitor structure disposed on the substrate and contacting another portion of the active region, Wherein, the buffer film includes a lower buffer film and an upper buffer film disposed on the lower buffer film, Wherein, the upper buffer film includes a first upper insulating film, a third upper insulating film, and a second upper insulating film stacked in a third direction intersecting the first direction and the second direction, Wherein, the third upper insulating film contains carbon.

2. The semiconductor memory device according to claim 1, wherein The upper surface of the upper buffer film contacts the conductive pattern.

3. The semiconductor memory device according to claim 1, wherein, The upper surface of the upper buffer film is coplanar with the upper surface of the direct contact.

4. The semiconductor memory device according to claim 1, Among them, The first upper insulating film includes a silicon oxide film, Wherein, the second upper insulating film includes a silicon nitride film.

5. The semiconductor memory device according to claim 1, wherein, The third upper insulating film has a thickness of 1 nm or less in the third direction.

6. The semiconductor memory device according to claim 1, wherein, The width of the lower buffer film in the first direction is greater than the width of the upper buffer film in the first direction.

7. The semiconductor memory device according to claim 1, the semiconductor memory device further comprising a bit line spacer, the bit line spacer disposed along and on the sidewall of the conductive pattern, Among them, At least a portion of the lower buffer film overlaps with the bit line spacer in the third direction.

8. The semiconductor memory device according to claim 7, wherein At least a portion of the bit line spacer contacts the sidewall of the upper buffer film.

9. The semiconductor memory device according to claim 1, wherein, The width of the first upper insulating film in the first direction gradually decreases as the distance from the lower buffer film increases.

10. The semiconductor memory device according to claim 1, wherein, The thickness of the third upper insulating film in the third direction is less than the thickness of each of the first upper insulating film and the second upper insulating film in the third direction.

11. A semiconductor memory device, the semiconductor memory device comprising: A substrate, the substrate including an active region defined by an element isolation film; A gate electrode, the gate electrode disposed within the substrate and extending in a first direction; A lower buffer film, the lower buffer film disposed on the substrate and extending in a second direction intersecting the first direction; An upper buffer film, the upper buffer film disposed on the lower buffer film and extending in the second direction; A direct contact, the direct contact extending through the lower buffer film and the upper buffer film and contacting a portion of the active region; A conductive pattern, the conductive pattern disposed on the direct contact and the upper buffer film and extending in the second direction; And A capacitor structure, the capacitor structure disposed on the substrate and contacting another portion of the active region, Wherein, the width of the lower buffer film in the first direction is greater than the width of the upper buffer film in the first direction. Wherein, the lower buffer film includes a first lower insulating film, a second lower insulating film provided on the first lower insulating film, and a third lower insulating film provided between the first lower insulating film and the second lower insulating film. Wherein, the upper buffer film includes a first upper insulating film, a second upper insulating film provided on the first upper insulating film, and a third upper insulating film provided between the first upper insulating film and the second upper insulating film. Wherein, each of the third lower insulating film and the third upper insulating film includes a silicon carbonitride film.

12. The semiconductor memory device according to claim 11, wherein, Each of the third lower insulating film and the third upper insulating film has a thickness of 1 nm or less.

13. The semiconductor memory device according to claim 11, wherein The upper surface of the upper buffer film is in contact with the conductive pattern.

14. The semiconductor memory device according to claim 11, wherein, The upper surface of the upper buffer film is coplanar with the upper surface of the direct contact.

15. The semiconductor memory device according to claim 11, Among them, Each of the first upper insulating film and the first lower insulating film includes a silicon oxide film. Wherein, each of the second upper insulating film and the second lower insulating film includes a silicon nitride film.

16. The semiconductor memory device according to claim 11, wherein, The width of the first upper insulating film in the first direction gradually decreases as the distance from the lower buffer film increases.

17. The semiconductor memory device according to claim 11, wherein The thickness of the third lower insulating film is less than the thickness of each of the first lower insulating film and the second lower insulating film.

18. The semiconductor memory device according to claim 11, wherein The thickness of the first lower insulating film is equal to the thickness of the first upper insulating film.

19. The semiconductor memory device according to claim 11, wherein, The thickness of the second lower insulating film is different from the thickness of the second upper insulating film.

20. A semiconductor memory device, the semiconductor memory device comprising: A substrate, the substrate including an active region defined by an element isolation film; A gate electrode, the gate electrode provided in the substrate and extending in a first direction; A lower buffer film, the lower buffer film provided on the substrate and extending in a second direction intersecting the first direction; An upper buffer film, the upper buffer film provided on the lower buffer film and extending in the second direction; A direct contact, the direct contact extending through the lower buffer film and the upper buffer film and contacting a portion of the active region; A conductive pattern, the conductive pattern provided on the direct contact and the upper buffer film and extending in the second direction; A bit line spacer, the bit line spacer provided along the sidewalls of the conductive pattern and the upper buffer film and provided on the sidewalls of the conductive pattern and the upper buffer film; A buried contact, the buried contact provided on the substrate and contacting another portion of the active region; A landing pad, the landing pad electrically connected to the buried contact; And A capacitor structure, the capacitor structure electrically connected to the landing pad, Wherein, the upper buffer film includes a first upper insulating film, a third upper insulating film, and a second upper insulating film stacked in sequence in a third direction intersecting the first direction and the second direction, Wherein, the first upper insulating film includes a silicon oxide film, Wherein, the second upper insulating film includes a silicon nitride film, Wherein, the third upper insulating film includes a silicon carbonitride film, Among them, the thickness of the third upper insulating film is 1 nm or less. Among them, the width of the lower buffer film in the first direction is greater than the width of the upper buffer film in the first direction. Among them, at least a part of the lower buffer film overlaps with the bit line spacer in the third direction.

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