Preparation method of transistor structure, transistor structure and memory

Abstract

A preparation method of a transistor structure, a transistor structure and a memory, the preparation method of the transistor structure comprising: forming an active column on a substrate, the active column comprising a source region, a drain region and a channel region between the source region and the drain region; forming a first sacrificial layer on the surface of the source region and / or the drain region through a selective epitaxial growth process; forming a gate oxide layer and a gate conductive layer on the surface of the channel region; and removing the first sacrificial layer to form a first oxide layer. According to the preparation method, the lengths of the source region and / or the drain region and the channel region can be effectively controlled, the manufacturing process is simplified, meanwhile, damage to the source region and / or the drain region of the active column in the process of forming the gate oxide layer and the gate conductive layer on the surface of the channel region is prevented, the first sacrificial layer is removed, and the yield is improved. The first oxide layer is formed in the source electrode region and / or the drain electrode region of the active column, so that the interface state density of the source electrode region and / or the drain electrode region can be reduced, and the occurrence risk of electric leakage is reduced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a method for manufacturing a transistor structure, a transistor structure, and a memory. Background Art

[0002] As the integration density of memories develops towards a higher level, higher requirements are imposed on the arrangement of transistors and the transistor size in a memory array structure. Researchers have developed other transistor structures such as buried transistor structures, vertical transistor structures, three-dimensional stacked transistor structures, etc. to meet the requirements of high integration and high density of transistors.

[0003] As the size of the transistor structure decreases, the process of forming the source region or the drain region and the channel region becomes increasingly difficult to control. At the same time, the leakage problems of the source and drain of the transistor become more and more serious, affecting the performance of the transistor. Summary of the Invention

[0004] In view of the shortcomings of the existing methods, the present application provides a method for manufacturing a transistor structure, a transistor structure, and a memory, so as to solve the problems that the manufacturing process of the source region or the drain region and the channel region of the existing transistor structure is difficult and prone to leakage.

[0005] According to a first aspect of the embodiments of the present disclosure, a method for manufacturing a transistor structure is provided, including: forming an active pillar on a substrate, the active pillar including a source region, a drain region, and a channel region located between the source region and the drain region; forming a first sacrificial layer on the surface of the source region and / or the drain region by selective epitaxial growth; forming a gate oxide layer and a gate conductive layer on the surface of the channel region; removing the first sacrificial layer to form a first oxide layer.

[0006] In some embodiments, the method for forming the active pillar includes: etching on the substrate to form first grooves extending along a plurality of first directions and arranged along a second direction, and filling a first isolation layer in the first grooves; forming second grooves extending along a plurality of second directions and arranged along the second direction on the substrate, and filling a second isolation layer in the second grooves;

[0007] The depth of the first grooves is greater than the depth of the second grooves; the first direction is perpendicular to the second direction.

[0008] In some embodiments, before forming the first sacrificial layer on the surface of the source region and / or the drain region by selective epitaxial growth, it includes:

[0009] filling a second isolation layer in the second grooves, the second isolation layer including a first isolation sub-layer and a second isolation sub-layer, the first isolation sub-layer being located on the side wall of the second grooves, and the second isolation sub-layer being located within the first isolation sub-layer;

[0010] Etch away part of the first isolation layer and part of the first isolation sub-layer to expose the source region or the drain region.

[0011] In some embodiments, forming a gate oxide layer and a gate conductive layer on the surface of the channel region includes: continuing to etch away part of the first isolation sub-layer and part of the first isolation layer to expose the channel region; forming a gate oxide layer on the surface of the channel region; forming a gate conductive layer on the side of the gate oxide layer away from the channel region.

[0012] In some embodiments, removing the first sacrificial layer to form a first oxide layer includes: selectively etching away the first sacrificial layer to expose the surface of the source region and / or the drain region; forming a first oxide layer on the surface of the source region and / or the drain region.

[0013] In some embodiments, the first sacrificial layer is germanium silicide.

[0014] According to a second aspect of the embodiments of the present disclosure, a transistor structure is provided. The transistor structure is obtained by preparing according to any one of the above preparation methods, and includes: an active pillar, the active pillar includes a source region, a drain region, and a channel region located between the source region and the drain region; a first oxide layer, the first oxide layer is located on the surface of the source region and / or the drain region; a gate oxide layer, the gate oxide layer is located on the surface of the channel region; a gate conductive layer, the gate conductive layer is located on the side of the gate oxide layer away from the channel region.

[0015] In some embodiments, the gate conductive layer may be located on one side, two sides, three sides of the channel region or surround the channel region.

[0016] In some embodiments, the surface of the first isolation layer away from the active pillar is flush with the surface of the gate conductive layer away from the active pillar.

[0017] According to a third aspect of the embodiments of the present disclosure, a memory is provided, including the above transistor structure, and further including: a bit line structure, the bit line structure is electrically connected to one end of the source region or the drain region; a storage structure, the storage structure is connected to the other end of the source region or the drain region.

[0018] In the embodiments of the present disclosure, by selectively epitaxially growing to form a first sacrificial layer in the source region and / or the drain region of the active pillar, the lengths of the source region and / or the drain region and the channel region can be effectively controlled, the manufacturing process can be simplified, and at the same time, damage to the source region and / or the drain region of the active pillar during the process of forming the gate oxide layer and the gate conductive layer on the surface of the channel region can be prevented. Removing the first sacrificial layer and forming a first oxide layer in the source region and / or the drain region of the active pillar can reduce the interface state density of the source region and / or the drain region and reduce the risk of leakage. Description of the Drawings

[0019] Figure 1 It is a schematic flowchart of a preparation method of a transistor structure provided in an embodiment of the present disclosure;

[0020] Figure 2 is a top view schematic diagram of a transistor structure shown according to an exemplary embodiment;

[0021] Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A are cross-sectional schematic diagrams of the transistor along the aa' direction during the manufacturing process;

[0022] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Figure 9B are cross-sectional schematic diagrams of the transistor along the bb' direction during the manufacturing process;

[0023] Figure 10 is Figure 9A The cross-sectional schematic diagram shown is a partial enlarged schematic diagram.

[0024] Figure 11 is a three-dimensional schematic diagram of a memory provided in an embodiment of the present disclosure;

[0025] Figure 12 is Figure 11 The cross-sectional schematic diagram along the bit line direction of the three-dimensional schematic diagram shown.

[0026] Explanation of reference numerals:

[0027] 10: Substrate; 11: Active pillar; 111: Drain region; 112: Channel region; 113: Source region; 12: First sacrificial layer; 13: First oxide layer; 14: Gate oxide layer; 15: Gate conductive layer; 16: Bit line structure; 17: Storage structure; 18: Second isolation layer; 19: Third isolation layer; 191: First isolation sub-layer; 192: Second isolation sub-layer; T1: First groove; T2: Second groove; T3: Third groove; T4: Fourth groove; T5: Fifth groove. Detailed implementation manners

[0028] Next, the technical solutions of the present disclosure will be further elaborated in detail in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation manners described herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present disclosure and to be able to fully convey the scope of the present disclosure to those skilled in the art.

[0029] The present disclosure will be described more specifically by way of example with reference to the accompanying drawings in the following paragraphs. The advantages and features of the present disclosure will become clearer according to the following description and claims. It should be noted that the accompanying drawings are in very simplified forms and use non-precise scales, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0030] It can be understood that the meanings of "on", "above", and "over" in the present disclosure should be interpreted in the broadest manner, so that "on" not only means "on" something without any intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of being "on" something with intervening features or layers therebetween.

[0031] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and do not necessarily describe a specific order or sequence.

[0032] In the embodiments of the present disclosure, the term "layer" refers to a part of a material including a region having a thickness. The layer can extend over the entirety of a structure below or above, or can have a scope smaller than the scope of the structure below or above. In addition, the layer can be a region of a homogeneous or inhomogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure, or the layer can be between any horizontal planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include a plurality of sub-layers.

[0033] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0034] Figure 1 is a schematic flow chart of a method for preparing a transistor structure provided in an embodiment of the present disclosure; Figure 2 is a top view schematic diagram of a transistor shown according to an exemplary embodiment; Figure 3A 、 Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A 、 Figure 8A and Figure 9A are cross-sectional schematic diagrams of the transistor along the aa' direction during the preparation process; Figure 3A 、 Figure 4A 、 Figure 5B 、 Figure 6B 、 Figure 7B 、 Figure 8B and Figure 9B are cross-sectional schematic diagrams of the transistor along the bb' direction during the preparation process; Figure 10 is Figure 9A The cross-sectional schematic diagram shown is a partial enlarged schematic diagram.

[0035] The preparation method of the memory provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. As shown in FIG. 3, the preparation method at least includes the following steps:

[0036] S110: Form an active pillar on the substrate, where the active pillar includes a source region, a drain region, and a channel region located between the source region and the drain region;

[0037] S120: Form a first sacrificial layer on the surface of the source region and / or the drain region through an epitaxial growth process;

[0038] S130: Form a gate oxide layer and a gate conductive layer on the surface of the channel region;

[0039] S140: Remove the first sacrificial layer to form a first oxide layer.

[0040] It should be understood that Figure 1 the steps shown in Figure 1 are not exclusive, and other steps may be performed before, after, or between any of the shown operations;

[0041] In the manufacturing method of the semiconductor structure provided by the present disclosure, on the one hand, forming a vertical transistor structure on the substrate can reduce the occupied area of the transistor structure and improve the storage density. On the other hand, forming a first sacrificial layer on the surface of the source region and / or the drain region through a selective epitaxial growth process can effectively control the lengths of the source region and / or the drain region and the channel region, simplify the manufacturing process, and prevent damage to the source region and / or the drain region of the active pillar during the process of forming the gate oxide layer and the gate conductive layer on the surface of the channel region. On the third hand, forming a first oxide layer on the surface of the source region or the drain region of the transistor structure can reduce the interface state density on the surface of the source region or the drain region of the transistor structure, and prevent problems such as threshold voltage drift, increased leakage current, and decreased reliability of the transistor structure due to high interface state density.

[0042] Figure 2 FIG.

[0043] CombinedFigure 1 , Figure 2 、 Figure 3A and Figure 3B , in some embodiments, a substrate 10 is provided. The material of the substrate 10 includes semiconductor materials, such as elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), etc.), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. In the embodiments of the present application, a single-crystalline silicon substrate is taken as an example for illustration.

[0044] Continuing to refer to Figure 1 , Figure 2 、 Figure 3A and Figure 3B , in some embodiments, S110: The active column formed on the substrate is the active column 11. The method for forming the active column 11 includes patterning and etching on the substrate 10 to form a plurality of first grooves T1 extending in a first direction and arranged in a second direction. Specifically, one or more mask layers can be deposited on the surface of the substrate 10, a photoresist is deposited on the surface of the mask layer, an etching pattern is formed on the photoresist after exposure, and the mask layer and the substrate 10 are etched along the etching pattern to form the first grooves T1. The method for depositing the mask layer can include but is not limited to at least one of processes such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), High-Density Plasma (HDP) process, Plasma-Enhanced Deposition process, and Spin-on Dielectric (SOD) process. The etching method can be dry etching, wet etching, or a combination thereof.

[0045] Continuing to refer to Figure 1 , Figure 2 、 Figure 3A and Figure 3B, in some embodiments, a second isolation material is deposited in the first groove T1, and after polishing and planarizing, a second isolation layer 18 is formed. The material of the second isolation layer 18 can be a low dielectric constant material, such as silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, or silicon oxynitride, so as to reduce the coupling between adjacent bit line structures 17. The second isolation layer 18 can adopt a deposition process, and the deposition process can include but is not limited to at least one of processes such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP) process, Plasma Enhanced Deposition process, and Spin-on Dielectric (SOD). In the embodiments of the present application, silicon oxide is taken as an example for illustration.

[0046] Continue to refer to Figure 1 , Figure 2 、 Figure 3A and Figure 3B , in some embodiments, patterning and etching are performed on the substrate 10 to form a plurality of second grooves T2 extending in the second direction and arranged in the first direction. The first groove T1 and the second groove T2 are perpendicular to each other, and the depth of the first groove T1 is greater than the depth of the second groove T2, forming active pillars 11 perpendicular to the substrate 10. Specifically, one or more mask layers can be deposited on the surface of the substrate 10, a photoresist is deposited on the surface of the mask layer, an etching pattern is formed on the photoresist after exposure, and the mask layer, a part of the second isolation layer 18, and the substrate 10 are etched along the etching pattern to form the second groove T2. The method of depositing the mask layer can include but is not limited to at least one of processes such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), High Density Plasma (HDP) process, Plasma Enhanced Deposition process, and Spin-on Dielectric (SOD). The etching method can adopt dry etching, wet etching, or a combination thereof.

[0047] Continue to refer to Figure 1 , Figure 2 、 Figure 3A and Figure 3B, in some embodiments, a third isolation material is deposited in the second groove T2, and is polished and planarized to form a third isolation layer 19, wherein the third isolation layer 19 includes a first isolation sub-layer 191 and a second isolation sub-layer 192. The first isolation sub-layer 191 is deposited on the sidewall of the second groove T2, and the second isolation sub-layer 192 is deposited within the first isolation sub-layer 191. The first isolation sub-layer 191 and the second isolation sub-layer 192 fill the second groove T2. The materials of the first isolation sub-layer 191 and the second isolation sub-layer 192 can be low dielectric constant materials, such as: silicon oxide, silicon nitride, silicon carbide, silicon carbonitride or silicon oxynitride, so as to reduce the coupling between adjacent active pillar structures 11. The materials of the first isolation sub-layer 191 and the second isolation sub-layer 192 can be the same or different. The first isolation sub-layer 191 and the second isolation sub-layer 192 can adopt a deposition process, and the deposition process can include but is not limited to at least one of chemical vapor deposition process (CVD), physical vapor deposition process (PVD), atomic layer deposition process (ALD), high density plasma deposition (HDP) process, plasma enhanced deposition process and spin-on dielectric (SOD) process, etc. The first isolation sub-layer 191 and the second isolation sub-layer 192 can adopt the same process or different processes. In the embodiments of the present application, the case where the first isolation sub-layer 191 uses silicon oxide and the second isolation sub-layer 192 uses silicon nitride is taken as an example for illustration.

[0048] Reference Figure 1 , Figure 2 、 Figure 4A and Figure 4B , in some embodiments, a part of the second isolation layer 18 and a part of the first isolation sub-layer 191 are selectively etched away to expose the source region 113 or the drain region 111, or to expose a part of the source region 113 or the drain region 111, thereby forming a third groove T3. The third groove T3 surrounds the source region 113 or the drain region 111 and extends in the second direction. As can be seen from the above, the materials of the second isolation layer 18 and the first isolation sub-layer 191 are both silicon oxide, the material of the active pillar 11 is single crystal silicon, and the material of the second isolation sub-layer 192 is silicon nitride. A method with an etching selectivity ratio can be selected, such as dry etching or wet etching, to etch away a part of the second isolation layer 18 and a part of the first isolation sub-layer 191, and keep the active pillar 11 and the second isolation sub-layer 192, so as to form the third groove T3 that exposes the source region 113 or the drain region 111. Through selective etching, the number of photomasks can be reduced, the process time can be shortened, and the production efficiency can be improved.

[0049] ReferenceFigure 1 , Figure 2 、 Figure 5A and Figure 5B , in some embodiments, S120: A first sacrificial layer 12 is formed on the surface of the source region 113 or the drain region 111 using a selective epitaxial growth (SEG) process. The first sacrificial layer 12 surrounds the surface of the source region 113 or the drain region 111, fills the void in the first direction between the source region 113 or the drain region 111 and the second isolation layer, and forms third grooves T4 arranged at intervals in the second direction. That is, after the first sacrificial layer is formed, the first sacrificial layer is deposited on the surface of the source region 113 or the drain region 111 while exposing the fourth grooves T4 arranged at intervals in the second direction on the second isolation layer 18. Specifically, a precursor gas is introduced onto the surface of the source region 113 or the drain region 111 in a high-temperature environment, and atoms are orderly arranged along the lattice direction of the surface of the source region 113 and / or the drain region 111 to form a single-crystal thin layer that matches the lattice of the surface of the source region 113 and / or the drain region 111. In some embodiments, germanium silicide is formed on the surface of the source region 113 or the drain region 111 through a selective epitaxial growth (SEG) process. Compared with forming silicon on the surface of the source region 113 or the drain region 111, the temperature for forming germanium silicide is lower and the forming process is relatively simple. At the same time, it also has an etch selectivity ratio with the single-crystal silicon of the active pillar, and can selectively remove single-crystal silicon or single-crystal germanium silicide without damaging the other material.

[0050] Reference Figure 1 , Figure 2 、 Figure 6A and Figure 6B , in some embodiments, the second isolation layer 18 and a part of the first isolation layer 191 are continuously etched along the fourth groove T4 to expose the channel region 112 and form a fifth groove T5. Since germanium silicide is formed on the surface of the source region 113 or the drain region 111 using a selective epitaxial growth (SEG) process, it has an etch selectivity ratio with the second isolation layer 18 and the first isolation layer 191. That is, when etching the second isolation layer 18 and the first isolation layer 191, the first sacrificial layer 12 will not be damaged, nor will the source region 113 or the drain region 111. The fifth groove T5 extends along the second direction, exposing the periphery of the channel region 112, leaving enough process space for the subsequent preparation of the gate conductive layer 15, and at the same time, effectively and precisely controlling the lengths of the source region and / or the drain region and the channel region.

[0051] Reference Figure 1 , Figure 2 、 Figure 7A and Figure 7B, in some embodiments, S130: form a gate oxide layer 14 on the surface of the channel region 112, and form a gate conductive layer 15 on the surface of the gate oxide layer 14. The gate oxide layer 14 can be formed by one or more of in-situ steam generation (ISSG), chemical vapor deposition (CVD), atomic layer deposition (ALD), high density plasma (HDP) processes, etc. The material of the gate oxide layer 14 is selected from silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanate oxide or a combination thereof. In some embodiments, the channel region 112 can also be trimmed, and part of the silicon atoms on the surface of the channel region are etched away to form a dumbbell-shaped active column 11, which can leave enough process space for forming the gate oxide layer 14 and the gate conductive layer 15, improve the gate control ability, and improve the transistor performance. The gate conductive layer 15 is a material that can conduct electricity, and the material of the gate conductive layer 15 can include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon germanium). The method for forming the gate conductive layer 15 can be one or more of chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, electroplating, etc.

[0052] Reference Figure 1 , Figure 2 、 Figure 8A 、 Figure 8B 、 Figure 9A and Figure 9B, in some embodiments, S140: Remove the first sacrificial layer 12 to form the first oxide layer 13. The first sacrificial layer 12 is germanium silicon, and the material of the source region 113 or the drain region 112 is silicon. The first sacrificial layer 12 can be selectively etched away to expose the surface of the source region 113 or the drain region 112 without damaging the surface of the source region 113 or the drain region 112; form the first oxide layer 13 on the surface of the source region 113 or the drain region 112. The first oxide layer 13 can be formed by one or more of the in-situ steam generation (ISSG) process, chemical vapor deposition (CVD) process, atomic layer deposition (ALD) process, high density plasma (HDP) process, etc. The material of the first oxide layer is selected from silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanate oxide, or a combination thereof.

[0053] Figure 10 is Figure 9A The cross-sectional schematic diagram shown is a partial enlarged schematic diagram. In some embodiments, due to the presence of the second isolation layer 192, in the first direction, the surface of the first isolation layer 13 away from the active pillar is flush with the surface of the gate conductive layer 15 away from the active pillar.

[0054] Figure 11 is a three-dimensional schematic diagram of a transistor structure shown according to an exemplary embodiment; Figure 12 is Figure 11 a cross-sectional schematic diagram of the three-dimensional schematic diagram along the bit line direction. Combining Figure 11 and Figure 12 , the transistor structure includes an active pillar 11. The active pillar 11 includes a source region 113, a drain region 111, and a channel region 112 located between the source region 113 and the drain region 111; a first oxide layer 13, the first oxide layer 13 is located on the surface of the source region 113 and / or the drain region 111; a gate oxide layer 14, the gate oxide layer 14 is located on the surface of the channel region 112; a gate conductive layer 15, the gate conductive layer 15 is located on the side of the gate oxide layer 14 away from the channel region 112. The first oxide layer 13 located on the surface of the source region 113 and / or the drain region 111 can reduce the interface state density on the surface of the source region or the drain region of the transistor structure, and can prevent problems such as threshold voltage drift, increased leakage current, and decreased reliability of the transistor structure due to high interface state density.

[0055] Continue to refer to Figure 11 and Figure 12, in some embodiments, the active pillar 11 can be arranged parallel to the substrate, perpendicular to the substrate, arranged parallel to the substrate stack, or arranged perpendicular to the substrate stack, etc. The shape of the active pillar 11 can be one or more of strip-shaped, ribbon-shaped, cylindrical, conical, fork-shaped, U-shaped, etc. The material of the active pillar 11 is silicon material, which can be single crystal silicon, polycrystalline silicon, doped single crystal silicon, doped polycrystalline silicon, silicon-germanium, silicon on insulator, or germanium on insulator, etc. and their combinations. The active pillar 11 includes a source region 113, a drain region 111, and a channel region 112 located between the source region 113 and the drain region 111. The direction of the channel region 112 is consistent with the extension direction of the active pillar.

[0056] Continue to refer to Figure 11 and Figure 12 , in some embodiments, the first oxide layer 13 is located on the surface of the source region 113 and / or the drain region 111, that is, it can be only located on the surface of the source region 113, or only located on the surface of the drain region 111, or simultaneously located on the surfaces of the source region 113 and the drain region 111. It can be located on one side, both sides, three sides of the source region 113 and / or the drain region 111, or arranged around the source region 113 and / or the drain region 111. The first oxide layer 13 can be prepared by an in-situ steam generation process (ISSG), that is, hydrogen and oxygen are introduced on the surface of the source region 113 and / or the drain region 111 to generate water vapor at high temperature, so as to oxidize the silicon material on the surface of the source region 113 and / or the drain region 111 to generate a silicon dioxide layer. Because the silicon on the surface of the source region 113 and / or the drain region 111 is directly bonded to oxygen, the silicon dioxide layer prepared by the in-situ steam generation process (ISSG) has a more compact interface atomic arrangement, is closer to the single crystal structure, has a low defect density, low stress, and the interface state density can be lower than 1*10 10 cm -2Next, problems such as threshold voltage drift, increased leakage current, and decreased reliability of the transistor structure caused by high interface state density can be prevented. Furthermore, the silicon dioxide layer prepared by the In-Situ Steam Generation (ISSG) process has strong process controllability, and the thickness of the silicon dioxide layer can be effectively controlled according to process requirements, reducing silicon consumption on the surface of the source region 113 and / or the drain region 111, increasing the area of the source region 113 and / or the drain region 111, and reducing the contact resistance with the bit line and the memory structure. In addition, the first oxide layer 13 can be formed by using one or more of the Chemical Vapor Deposition (CVD) process, the Atomic Layer Deposition (ALD) process, the High Density Plasma (HDP) process, etc. The material of the first oxide layer is selected from silicon dioxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanate oxide, or a combination thereof.

[0057] Continue to refer to Figure 11 and Figure 12, in some embodiments, the gate oxide layer 14 is located on the surface of the channel region 112. The gate oxide layer 14 can be located on one side, two sides, three sides of the channel region 112, or surround the channel region 112. The gate oxide layer 14 can be prepared by In-Situ Steam Generation (ISSG), Rapid Thermal Oxidation (RTO), Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD). The material of the gate oxide layer 14 is selected from silicon oxide, silicon oxynitride, aluminum oxide, hafnium oxide, hafnium oxynitride, zirconium oxide, tantalum oxide, titanium oxide, strontium titanate oxide, or a combination thereof. The gate conductive layer 15 is located on the side of the gate oxide layer 14 away from the channel region 112, and can conformally cover the surface of the gate oxide layer 14. For example, it can be located on one side, two sides, three sides of the channel region 112, or surround the channel region 112. It can also partially overlap with the gate oxide layer 14 and independently be located on one side, two sides, three sides of the channel region 112, or surround the channel region 112. The area of the gate conductive layer 15 is less than or equal to the area of the gate oxide layer 14. The gate conductive layer 15 can be prepared by one or more of the methods such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), sputtering, electroplating, etc. The material of the gate conductive layer 15 can include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon germanium).

[0058] Continue to refer to Figure 11 and Figure 12, in some embodiments, the surface of the first oxide layer 13 away from the active pillar 10 is flush with the surface of the gate conductive layer 15 away from the active pillar 10. The first oxide layer 13 is located on the surface of the source region 113 and / or the drain region 111. The gate conductive layer 15 is located on the side of the gate oxide layer 14 away from the channel region 112. The thicknesses of the first oxide layer 13 and the gate oxide layer 14 are adjusted according to the device performance requirements. The thicknesses of the first oxide layer 13, the gate oxide layer 14, and the gate conductive layer 15 are different from each other but are also mutually restricted. In addition, the diameter of the channel region 112 can also be different from the diameter of the source region 113 and / or the drain region 111. The diameter of the channel region 112 is smaller than the diameter of the source region 113 and / or the drain region 111, forming a dumbbell-shaped active pillar 10, which can provide a process space for the gate oxide layer 14 and the gate conductive layer 15 and reduce the difficulty of the manufacturing process. The surface of the first oxide layer 13 away from the active pillar 10 being flush with the surface of the gate conductive layer 15 away from the active pillar 10 can make the outer surface of the transistor flush, which is beneficial to simplifying the manufacturing process and can effectively control the distance between adjacent transistor structures.

[0059] Continue to refer to Figure 11 and Figure 12 , embodiments of the present disclosure further provide a memory. The memory includes the above transistor structure and further includes a bit line structure 16, where the bit line structure 16 is electrically connected to one end of the source region 113 or the drain region 111; and a storage structure 17, where the storage structure 17 is electrically connected to the other end of the source region 113 or the drain region 111. The opening and closing of the transistor are controlled by a voltage signal on the gate conductive layer 15, and then the data information stored in the storage structure 17 is read through the bit line structure 16, or the data information is written into the storage structure 17 through the bit line structure 16 for storage. In some embodiments, the bit line structure 16 is made of a conductive material. The material of the bit line structure 16 may include one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), cobalt (Co), nickel (Ni)); alloys (e.g., Co-based alloys, Ti-based alloys, Co and Ni-based alloys, Fe and Co-based alloys); conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides); and conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped silicon germanium). In some embodiments, there is also a transition contact layer (not shown) between the bit line structure 16 and the source region 113 or the drain region 111. The transition contact layer is made of a conductive material and can be a metal silicide material, which is used to reduce the contact resistance between the bit line structure 16 and the source region 113 or the drain region 111.

[0060] Continue to refer to Figure 1 and Figure 2, in some embodiments, the storage structure 17 is electrically connected to the other end of the source region 113 or the drain region 111. The storage structure 17 may include one or more of a capacitor, a ferroelectric storage structure, a phase change storage structure, a resistive random access memory (RRAM) structure, and a magnetic random access memory (MRAM) structure, and is configured to store the information conducted by the bit line structure 16.

[0061] As described above, the specific embodiments of the present disclosure are only provided, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily conceive of changes or substitutions within the technical scope disclosed by the present disclosure, and all such changes or substitutions should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A method for preparing a transistor structure, characterized in that, Comprising: Forming an active column on a substrate, the active column including a source region, a drain region, and a channel region located between the source region and the drain region; Forming a first sacrificial layer on the surface of the source region and / or the drain region by selective epitaxial growth process; Forming a gate oxide layer and a gate conductive layer on the surface of the channel region; Removing the first sacrificial layer to form a first oxide layer.

2. The manufacturing method according to claim 1, wherein: The method of forming the active column includes: Etching on the substrate to form first grooves extending along a plurality of first directions and arranged along a second direction, and filling a first isolation layer in the first grooves; Forming second grooves extending along a plurality of second directions and arranged along the second direction on the substrate, and filling a second isolation layer in the second grooves; The depth of the first grooves is greater than the depth of the second grooves; The first direction is perpendicular to the second direction.

3. The manufacturing method according to claim 2, wherein: Before forming the first sacrificial layer on the surface of the source region and / or the drain region by selective epitaxial growth process, it includes: Filling a second isolation layer in the second grooves, the second isolation layer including a first isolation sub-layer and a second isolation sub-layer, the first isolation sub-layer being located on the sidewall of the second grooves, and the second isolation sub-layer being located within the first isolation sub-layer; Etching to remove part of the first isolation layer and part of the first isolation sub-layer to expose the source region or the drain region.

4. The manufacturing method according to claim 3, wherein: Forming a gate oxide layer and a gate conductive layer on the surface of the channel region includes: Continuing to etch to remove part of the first isolation sub-layer and part of the first isolation layer to expose the channel region; Forming a gate oxide layer on the surface of the channel region; Forming a gate conductive layer on the side of the gate oxide layer away from the channel region.

5. The manufacturing method according to claim 3, wherein: Removing the first sacrificial layer to form a first oxide layer includes: Selectively etching to remove the first sacrificial layer to expose the surface of the source region and / or the drain region; Forming a first oxide layer on the surface of the source region and / or the drain region.

6. The manufacturing method according to any one of claims 1 to 5, wherein: The first sacrificial layer is germanium silicon.

7. A transistor structure, characterized in that ； The transistor structure is prepared by the manufacturing method according to any one of claims 1 to 6, and includes: An active column, the active column including a source region, a drain region, and a channel region located between the source region and the drain region; A first oxide layer, the first oxide layer being located on the surface of the source region and / or the drain region; A gate oxide layer, the gate oxide layer being located on the surface of the channel region; A gate conductive layer, the gate conductive layer being located on the side of the gate oxide layer away from the channel region.

8. The transistor structure according to claim 7, wherein: The gate conductive layer can be located on one side, two sides, three sides of the channel region or surround the channel region.

9. The transistor structure according to claim 7, wherein: The surface of the first oxide layer away from the active column is flush with the surface of the gate conductive layer away from the active column.

10. A memory, characterized in that, Comprising: The transistor structure according to any one of claims 7 to 9; A bit line structure, the bit line structure being electrically connected to one end of the source region or the drain region; A storage structure, the storage structure being electrically connected to the other end of the source region or the drain region.

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