SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) gate oxide layer accelerated degradation test circuit and method considering channel current stress

Abstract

The invention discloses a SiC MOSFET gate oxide layer accelerated degradation test circuit and method considering channel current stress, the introduction of the channel current stress is considered in the circuit, a mirror current source circuit is adopted in a power loop, and the circuit design can more comprehensively simulate working conditions in practical application, so that the reliability of a gate oxide layer of a SiC MOSFET is more accurately evaluated. According to the test method disclosed by the invention, the VDS (ON) is used as a temperature-sensitive parameter to monitor the junction temperature, and the need of using an additional temperature sensor is omitted, so that the test cost is remarkably reduced. By directly extracting the temperature information from the electrical parameters, the strategy not only simplifies the hardware configuration, but also improves the overall efficiency and reliability of the experiment setting. Besides, the test process is more flexible, rapid and accurate temperature monitoring under different test environments and conditions is facilitated, and the practicability of the accelerated degradation test scheme is enhanced.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic detection, and in particular relates to a SiC MOSFET gate oxide layer accelerated degradation test circuit and method taking channel current stress into consideration. Background Art

[0002] In recent years, third-generation semiconductor materials, particularly SiC, have been widely used in electric vehicles, rail transit, smart grids, and other fields due to their wide bandgap, high critical breakdown field strength, and high-speed switching characteristics. Although SiC MOSFETs offer superior performance to Si MOSFETs, their interface trap density is typically one to two orders of magnitude higher than that of Si. This high interface trap density can lead to threshold hysteresis in SiC MOSFET devices, significantly impacting the reliability of the SiC MOSFET gate oxide layer. The high density of interface traps in the gate oxide layer has become a significant barrier to the practical application of SiC MOSFETs.

[0003] In order to effectively evaluate the gate oxide quality of SiC MOSFET, many scholars have used different evaluation methods to conduct accelerated degradation tests on SiC MOSFET. The most commonly used method is the High Temperature Gate Bias (HTGB) test. The HTGB test is an important method for evaluating the working condition of SiC MOSFET in the on state. This test places the device under test (DUT) in a high temperature and high gate voltage stress environment for a long time. By monitoring the threshold voltage (V TH ), on-resistance (V DS(ON) ) and gate leakage current (I GSS ) and other key electrical parameters can reflect the health of the DUT gate oxide layer. Figure 1 In the HTGB test, high gate voltage stress is applied to the gate-source terminals, while the drain-source terminals are shorted, simulating the device's actual operating environment. However, while the HTGB test assesses the gate oxide quality of SiC MOSFETs under high temperature stress and high gate voltage stress, in real applications, SiC MOSFETs often operate under high load current stress. In such environments, the potential impact of the directional migration of a large number of carriers in the channel region on the health of the gate oxide layer is not fully reflected in the HTGB test. Summary of the Invention

[0004] The present invention addresses the problem that the existing SiC MOSFET gate oxide layer accelerated degradation test does not consider the channel current stress and is difficult to monitor the gate oxide layer degradation characterization parameters and junction temperature at the same time. The present invention proposes a SiC MOSFET gate oxide layer accelerated degradation test circuit and method that considers the channel current stress.DS(ON) , enabling real-time monitoring of device junction temperature and evaluation of gate oxide quality. This design not only simplifies the monitoring process but also provides a reliable technical means for studying the impact of negative channel current stress on gate oxide reliability, which is of great significance for the reliability evaluation of SiC MOSFET gate oxide layers.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows: a SiC MOSFET gate oxide layer accelerated degradation test circuit considering channel current stress, characterized in that the circuit includes a drive circuit, a power loop circuit and a data acquisition circuit;

[0006] The drive circuit mainly comprises an isolated half-bridge drive chip (U1) and a half-bridge circuit. The INA pin and the INB pin of the isolated half-bridge drive chip (U1) respectively receive two complementary square wave signals output by a microprocessor (MCU); the VCCI pin of the isolated half-bridge drive chip (U1) is connected to the positive electrode of a 3.3V power supply, and the GND pin, the DISABLE pin and the negative electrode of the 3.3V power supply are connected to the DGND pin of the microprocessor.

[0007] The DT pin of the isolated half-bridge driver chip (U1) is connected to one end of the No. 1 resistor (R1) and one end of the No. 1 capacitor (C1). The other end of the No. 1 resistor (R1) and the other end of the No. 1 capacitor (C1) are connected in parallel and then connected to the DGND pin of the microprocessor. The VDDB pin of the isolated half-bridge driver chip (U1), one end of the No. 3 capacitor (C3), and one end of the No. 2 resistor (R2) are all connected to the positive output end of the +12V power supply. Its VSSB pin, the other end of the No. 3 capacitor (C3), and the negative electrode of the +12V power supply are all connected to the low gate voltage power supply (V GS_LOW ) is connected to the positive output terminal; low gate voltage power supply (V GS_LOW ) is connected to the Kelvin source of the device under test, the other end of the second resistor (R2) is connected to the anode of the first diode (D1), the VDDA pin of the isolated half-bridge driver chip (U1) is connected to one end of the second capacitor (C2) and the cathode of the first diode (D1), and the other end of the second capacitor (C2) is connected to the VSSA pin of the isolated half-bridge driver chip (U1);

[0008] The half-bridge circuit includes an upper N-channel MOSFET (M1) and a lower N-channel MOSFET (M2). The OUTA pin of the isolated half-bridge driver chip (U1) is connected to one end of a third resistor (R3), and the other end of the third resistor (R3) is connected to the gate of the upper N-channel MOSFET (M1); the drain of the upper N-channel MOSFET (M1) is connected to a high gate voltage power supply (V GS_HIGH ) positive pole; high gate voltage power supply (V GS_HIGH ) is connected to the Kelvin source of the device under test;

[0009] The OUTB pin of the isolated half-bridge driver chip (U1) is connected to one end of the fourth resistor (R4), and the other end of the fourth resistor (R4) is connected to the gate of the lower N-channel MOSFET (M2). The source of the lower N-channel MOSFET (M2) is connected to the low gate voltage power supply (V GS_LOW ) is connected to the positive output terminal;

[0010] The source of the upper N-channel MOSFET (M1), the drain of the lower N-channel MOSFET (M2), and the VSSA pin of the isolated half-bridge driver chip (U1) are connected in parallel and then connected to one end of a fifth resistor (R5). The other end of the fifth resistor (R5) is respectively connected to the gate of the device under test (DUT) and one end of a sixth resistor (R6). The other end of the sixth resistor (R6) is connected to the Kelvin source of the device under test (DUT).

[0011] The power loop circuit is composed of a No. 7 resistor (R7), an No. 8 resistor (R8), a No. 9 resistor (R9), a No. 1 NPN transistor (Q1), and a No. 2 NPN transistor (Q2). One end of the No. 7 resistor (R7) is connected to the gate of the device under test (DUT), and the other end of the No. 7 resistor (R7) is connected to the Kelvin source of the device under test (DUT); one end of the No. 8 resistor (R8) is connected to the drain of the device under test (DUT), and the other end of the No. 8 resistor (R8) and one end of the No. 9 resistor (R9) are connected in parallel and then connected to the programmable The positive electrode of the programmable DC power supply (E); the source of the device under test (DUT) is connected to the collector of the No. 1 NPN transistor (Q1), the bases of the No. 1 NPN transistor (Q1) and the No. 2 NPN transistor (Q2) are connected, the emitter of the No. 1 NPN transistor (Q1), the emitter of the No. 2 NPN transistor (Q2), and the negative electrode of the programmable DC power supply (E) are connected in parallel and then grounded; the other end of the No. 9 resistor (R9) is connected to the base of the No. 2 NPN transistor (Q2) and the collector of the No. 2 NPN transistor (Q2);

[0012] The data acquisition circuit is composed of an isolation amplifier (U2), a differential circuit and an ADC analog-to-digital conversion chip. The drain of the device under test (DUT) is connected to the first input terminal of the isolation amplifier (U2), and the second input terminal of the isolation amplifier (U2) is connected to the Kelvin source of the device under test (DUT);

[0013] The differential circuit includes a tenth resistor (R10), an eleventh resistor (R11), a twelfth resistor (R12), a thirteenth resistor (R13), and an operational amplifier (U3); an OUTP pin of the isolation amplifier (U2) is connected to one end of the tenth resistor (R10); the other end of the tenth resistor (R10) and one end of the twelfth resistor (R12) are connected in parallel and then connected to the positive input end of the operational amplifier (U3); and the other end of the twelfth resistor (R12) is connected to the DGND pin of the microprocessor;

[0014] The OUTN pin of the isolation amplifier (U2) is connected to one end of the eleventh resistor (R11), the other end of the eleventh resistor (R11) is connected in parallel with one end of the thirteenth resistor (R13) and then connected to the negative input end of the operational amplifier (U3), the other end of the thirteenth resistor (R13) is connected in parallel with the output end of the operational amplifier (U3) and then connected to the input end of the ADC analog-to-digital conversion chip, and the output end of the ADC analog-to-digital conversion chip is connected to the host computer;

[0015] The device under test (DUT) is a SiC MOSFET.

[0016] Furthermore, the present invention designs a SiC MOSFET gate oxide layer accelerated degradation test method considering channel current stress, characterized in that the method uses the above-mentioned circuit and the following steps:

[0017] Step 1: First, connect the drive circuit, power loop circuit, data acquisition circuit, and device under test (DUT) in the circuit described above through a circuit board. Then, place the entire circuit in a constant temperature incubator to ensure that the ambient temperature of the device under test (DUT) remains stable.

[0018] Step 2: The microprocessor outputs two complementary square wave signals. The two square wave signals pass through the isolated half-bridge driver chip (U1), causing the upper N-channel MOSFET (M1) and the lower N-channel MOSFET (M2) of the half-bridge circuit to alternately turn on, causing the gate voltage of the device under test (DUT) to alternately switch between low gate voltage and high gate voltage. The duty cycle is controlled by the microprocessor. The high gate voltage aging time of the device under test (DUT) is set to 800ms, and the low gate voltage aging time of the device under test (DUT) is set to 200μs.

[0019] Step 3: Turn on the programmable DC power supply (E) and operate it in CV mode. By adjusting the parameters of the programmable DC power supply (E), the junction temperature of the device under test (DUT) gradually increases and stabilizes at a preset value. During this process, the device under test (DUT) is subjected to dual aging conditions of high gate stress and high junction temperature stress.

[0020] Step 4: When the device under test (DUT) is under the above dual aging conditions, the host computer obtains the on-state voltage V of the device under test (DUT) in real time through the ADC analog-to-digital conversion chip DS(ON) ; Under each parameter value of the programmable DC power supply (E), the median filtering method is used to collect the conduction voltage V at the middle moment of 5 consecutive high gate voltage time periods. DS(ON) Calculate the median value as the on-state voltage V of the device under test (DUT) at high gate voltage. DS(ON)-HIGH Similarly, the on-state voltage V is collected at the middle moment of 5 consecutive low gate voltage time periods.DS(ON) Calculate the median value as the on-state voltage V of the device under test (DUT) at low gate voltage. DS(ON)-LOW ; At low gate voltage, using the on-state voltage V DS(ON)-LOW Calculate the on-resistance R DS(ON)-LOW , used to monitor the degradation of the gate oxide layer; at high gate voltage, the on-state voltage V DS(ON)-HIGH As a temperature-sensitive parameter, it is used to monitor junction temperature in real time;

[0021] Step 5: Based on the on-resistance R at low gate voltage under the set aging time DS(ON)-LOW The accelerated degradation performance of the gate oxide layer of the device under test (DUT) considering the channel current stress is obtained by calculating the change in the gate oxide layer.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] 1. By introducing channel current stress into the accelerated degradation test, the technical solution of the present invention can more comprehensively simulate the working conditions in actual applications, thereby more accurately evaluating the gate oxide layer reliability of SiC MOSFET.

[0024] 2. The present invention proposes to monitor a single parameter V DS(ON) This method of simultaneously monitoring junction temperature and evaluating gate oxide quality simplifies the traditional monitoring process and reduces experimental complexity. This strategy not only improves monitoring efficiency but also enhances the reliability and accuracy of test data.

[0025] 3. This method uses V DS(ON ) as a temperature-sensitive parameter to monitor junction temperature, eliminating the need for additional temperature sensors and significantly reducing testing costs. By extracting temperature information directly from electrical parameters, this strategy not only simplifies hardware configuration but also improves the overall efficiency and reliability of the experimental setup. Furthermore, it provides greater flexibility in the testing process, facilitating rapid and accurate temperature monitoring under diverse test environments and conditions, enhancing the practicality of this accelerated degradation testing solution.

[0026] 4. The active channel bias test circuit designed by the present invention adopts a mirror current source circuit in the power loop. The simulation results show that when the gate oxide layer of the device ages and the on-resistance (R DS(ON) ) changes, the load current fluctuation is reduced by about 50% compared to the case without the mirror current source circuit. This design significantly improves R DS(ON) This circuit design not only optimizes the stability and reliability of the test but also provides technical support for high-precision performance evaluation. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1This is the schematic diagram of the HTGB test.

[0028] Figure 2 The present invention is a schematic structural diagram of an embodiment of a driving circuit of a SiC MOSFET gate oxide layer accelerated degradation test circuit taking channel current stress into consideration.

[0029] Figure 3 This is a schematic diagram of the driving waveform of an embodiment of the SiC MOSFET gate oxide layer accelerated degradation test circuit considering channel current stress of the present invention (in the figure, V GS represents the gate voltage of the device under test)

[0030] Figure 4 The present invention is a schematic structural diagram of an embodiment of a power loop circuit of a SiC MOSFET gate oxide layer accelerated degradation test circuit taking channel current stress into consideration.

[0031] Figure 5 The present invention is a schematic structural diagram of an embodiment of a data acquisition circuit for a SiC MOSFET gate oxide layer accelerated degradation test circuit taking channel current stress into consideration. DETAILED DESCRIPTION

[0032] The technical solution of the present invention is further described below in conjunction with specific embodiments and drawings.

[0033] The present invention provides a SiC MOSFET gate oxide accelerated degradation test circuit that takes channel current stress into account. The circuit includes a drive circuit, a power loop circuit, and a data acquisition circuit. In the following description, DGND represents the ground pin of the microprocessor (MCU), KS represents the Kelvin source of the device under test (DUT), and DGND and KS are electrically isolated. The device under test (DUT) is a SiC MOSFET.

[0034] The driving circuit mainly includes an isolated half-bridge driving chip U1 and a half-bridge circuit. Its structure and principle diagram are as follows: Figure 2 As shown in Figure 2, the INA and INB pins of isolated half-bridge driver chip U1 receive two complementary square wave signals output by the microprocessor (MCU) to control the output waveforms. The VCCI pin of isolated half-bridge driver chip U1 is connected to the positive terminal of the 3.3V power supply. The GND and DISABLE pins, as well as the negative terminal of the 3.3V power supply, are connected to the DGND pin of the microprocessor to ensure normal operation of isolated half-bridge driver chip U1.

[0035] The DT pin of the isolated half-bridge driver chip U1 is connected to one end of the No. 1 resistor R1 and one end of the No. 1 capacitor C1. The other end of the No. 1 resistor R1 and the other end of the No. 1 capacitor C1 are connected in parallel to the DGND pin of the microprocessor to set the dead time of the two output signals.

[0036] The VDDB pin of the isolated half-bridge driver chip U1, one end of the third capacitor C3, and one end of the second resistor R2 are all connected to the positive output terminal of the +12V power supply, and its VSSB pin, the other end of the third capacitor C3, and the negative electrode of the +12V power supply are all connected to the low gate voltage power supply V GS_LOW The positive output terminal is connected to the low gate voltage power supply V GS_LOW The output voltage is the low gate voltage required by the device under test DUT, so that the device under test DUT is under low gate voltage; the low gate voltage power supply V GS_LOW The negative electrode of the No. 2 resistor R2 is connected to the Kelvin source KS of the device under test, the other end of the No. 2 resistor R2 is connected to the positive electrode of the No. 1 diode D1, the VDDA pin of the isolated half-bridge driver chip U1 is connected to one end of the No. 2 capacitor C2 and the negative electrode of the No. 1 diode D1, and the other end of the No. 2 capacitor C2 is connected to the VSSA pin of the isolated half-bridge driver chip U1.

[0037] The half-bridge circuit includes an upper N-channel MOSFET M1 and a lower N-channel MOSFET M2. The OUTA pin of the isolated half-bridge driver chip U1 is connected to one end of the third resistor R3. The other end of the third resistor R3 is connected to the gate of the upper N-channel MOSFET M1. The drain of the upper N-channel MOSFET M1 is connected to the high gate voltage power supply V GS HIGH Positive pole; high gate voltage power supply V GS HIGH The output voltage is the high gate voltage required by the device under test DUT, so that the device under test DUT is under high gate voltage; the high gate voltage power supply V GS_HIGH The negative pole is connected to the Kelvin source KS of the device under test.

[0038] The OUTB pin of the isolated half-bridge driver chip U1 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is connected to the gate of the lower tube N-channel MOSFET M2. The source of the lower tube N-channel MOSFET M2 is connected to the low gate voltage power supply V GS_LOW The positive output terminal is connected;

[0039] The source of the upper N-channel MOSFET M1, the drain of the lower N-channel MOSFET M2, and the VSSA pin of the isolated half-bridge driver chip U1 are connected in parallel and connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is respectively connected to the gate of the device under test DUT and one end of the sixth resistor R6. The other end of the sixth resistor R6 is connected to the Kelvin source KS of the device under test DUT.

[0040] By programming and controlling the period and duty cycle of the PWM signal output by the microprocessor (MCU), the OUTA and OUTB pins of the isolated half-bridge driver chip U1 alternately output complementary square waves, thereby controlling the MOSFETs M1 and M2 in the half-bridge circuit to alternately turn on, achieving the gate voltage of the device under test (DUT) at the low gate voltage power supply V GS_LOW and high gate voltage power supply V GS_HIGH This design ensures the stability and flexibility of the drive signal, can adapt to different gate voltage requirements, and provides precise and reliable technical support for dynamic control in testing.

[0041] The power loop circuit adopts the mirror current source circuit design, such as Figure 4 As shown, the circuit is composed of resistor No. 7 R7, resistor No. 8 R8, resistor No. 9 R9, NPN transistor No. 1 Q1, and NPN transistor No. 2 Q2. Resistors No. 8 R8 and No. 9 R9 are high-power ripple resistors. NPN transistor No. 1 Q1 and NPN transistor No. 2 Q2 are of the same model.

[0042] One end of the seventh resistor R7 is connected to the gate of the device under test DUT, and the other end of the seventh resistor R7 is connected to the Kelvin source KS of the device under test DUT; one end of the eighth resistor R8 is connected to the drain of the device under test DUT, and the other end of the eighth resistor R8 and one end of the ninth resistor R9 are connected in parallel and then connected to the positive electrode of the programmable DC power supply E;

[0043] The source of the device under test (DUT) is connected to the collector of NPN transistor Q1. The bases of NPN transistors Q1 and Q2 are connected. The emitters of NPN transistors Q1 and Q2, as well as the negative electrode of the programmable DC power supply (E), are connected in parallel and then grounded. The other end of resistor R9 is connected to the base and collector of NPN transistor Q2. The negative electrode of the programmable DC power supply is GND. GND, DGND, and KS are electrically isolated.

[0044] During operation, the programmable DC power supply E, the ninth resistor R9 and the second NPN transistor Q2 jointly generate a reference current I R9 This current generates the corresponding load current I at the collector of the No. 1 NPN transistor Q1 through the mirror current source mechanism. R8 Due to the stability of the mirror current source, when the gate oxide layer of the device under test ages and the on-resistance (R DS(ON) ) changes, the load current fluctuation flowing through the device under test is effectively suppressed. Compared with the traditional design, this circuit can significantly reduce the fluctuation amplitude of the load current, thereby improving R DS(ON) Measurement accuracy and stability.

[0045] The data acquisition circuit is composed of an isolation amplifier U2, a differential circuit and an ADC analog-to-digital conversion chip. Its schematic diagram is as follows: Figure 5 As shown, the drain D of the device under test (DUT) is connected to the first input terminal of the isolation amplifier U2, and the second input terminal of the isolation amplifier U2 is connected to the Kelvin source KS of the device under test (DUT).

[0046] The differential circuit includes resistor No. 10 R10, resistor No. 11 R11, resistor No. 12 R12, resistor No. 13 R13, and operational amplifier U3. The OUTP pin of isolation amplifier U2 is connected to one end of resistor No. 10 R10. The other end of resistor No. 10 and one end of resistor No. 12 R12 are connected in parallel and then connected to the positive input of operational amplifier U3. The other end of resistor No. 12 R12 is connected to the DGND pin of the microprocessor. The OUTN pin of isolation amplifier U2 is connected to one end of resistor No. 11 R11. The other end of resistor No. 11 R11 is connected in parallel with one end of resistor No. 13 R13 and then connected to the negative input of operational amplifier U3. The other end of resistor No. 13 R13 is connected in parallel with the output of operational amplifier U3 and then connected to the input of an ADC analog-to-digital conversion chip. The output of the ADC analog-to-digital conversion chip is connected to a host computer.

[0047] The MCU is the TMS320F28335 from Puzhong Technology. The isolated half-bridge driver chip U1 uses the Texas Instruments UCC21520DWR, which has a maximum operating frequency of 5MHz. The isolation amplifier U2 uses the Texas Instruments ISO224ADWVR, which has a ±4V differential output voltage range and a common-mode voltage of VDD2 / 2, meeting the required specifications. The operational amplifier U3 uses the Texas Instruments OPA2228U, which has a 10V / μs slew rate and 33MHz bandwidth. The ADC chip is the Texas Instruments ADS8860IDGS, a 16-bit, 1MSPS single-ended input analog-to-digital converter. This device operates with an external 2.5V to 5V reference, providing a wide signal range without the need for additional signal conditioning.

[0048] Since U1 is an isolated driver chip, the MCU ground (DGND) is electrically isolated from the Kelvin source (KS) of the device under test. Therefore, when measuring the on-state voltage V DS(ON) When the ADC is connected to the DUT, an isolation amplifier U2 is used to achieve electrical isolation between the ADC analog-to-digital conversion chip and the device under test (DUT). Specifically, the drain D and Kelvin source KS of the DUT are connected to the input of the isolation amplifier U2. The differential voltage (V OUTP -V OUTN ) is V DS(ON) / 3. In order to convert the differential signal into a single-ended signal, a differential circuit is designed after the isolation amplifier U2, in which the OUTP and OUTN pins are connected to the positive and negative input terminals of the differential operational amplifier U3 through resistors R10 and R11, respectively. The positive input terminal of the operational amplifier U3 is connected to DGND through resistor R12, and the negative input terminal is connected to the output terminal of the operational amplifier U3 through resistor R13, forming a differential amplifier circuit. The resistance values of resistors R10 (R10), R11 (R11), R12 (R12), and R13 are set to be equal. This makes the gain multiplier of the differential amplifier circuit 1. The output terminal of the operational amplifier U3 is connected to the input terminal of the 16-bit high-precision ADC analog-to-digital conversion chip. The turn-on voltage V DS(ON) The 16-bit high-precision ADC chip converts the signal into a digital signal and uploads it to the host computer for subsequent calculation. According to the measurement results, at low gate voltage, the on-state voltage V DS(ON)-LOW Used to calculate the on-resistance R DS(ON)-LOW , used to monitor the degradation of the gate oxide layer; at high gate voltage, the on-state voltage V DS(ON)-HIGH The gate oxide layer is used as a temperature-sensitive parameter for real-time monitoring of junction temperature. The gate oxide layer accelerated degradation test circuit designed by this invention, which takes channel current stress into account, combines measurement parameters under high and low gate voltage conditions to accurately monitor gate oxide layer degradation and junction temperature. The design of an isolation amplifier and differential circuit not only ensures isolation and accuracy of the measurement, but also significantly improves the stability and reliability of the circuit system.

[0049] Furthermore, the present invention provides a method for testing accelerated degradation of a SiC MOSFET gate oxide layer taking into account channel current stress. The method uses the circuit described above and the following steps:

[0050] Step 1: First, the driving circuit, power loop circuit, data acquisition circuit and device under test (DUT) in the circuit described above are electrically connected through the circuit board, and then placed in a temperature chamber with a constant temperature value to ensure that the ambient temperature of the device under test (DUT) remains stable.

[0051] Step 2: The microprocessor (MCU) outputs two complementary square wave signals. These two square wave signals pass through the isolated half-bridge driver chip U1, causing the upper N-channel MOSFET M1 and the lower N-channel MOSFET M2 of the half-bridge circuit to alternately turn on, causing the gate voltage of the device under test (DUT) to alternately switch between low gate voltage and high gate voltage. The duty cycle is controlled by the microprocessor. The high gate voltage aging time of the device under test (DUT) is set to 800ms. The low gate voltage measures the health of the gate oxide. The low gate voltage aging time of the device under test (DUT) is set to 200μs to ensure stable junction temperature.

[0052] Step 3: Turn on the programmable DC power supply E and make it work in CV mode. The programmable DC power supply E has the ability to output a maximum voltage of 80V and a current of 480A. By adjusting the parameters of the programmable DC power supply E, the junction temperature of the device under test DUT is gradually increased and stabilized at the preset value. During this process, the device under test DUT is in a high gate stress (i.e., high gate voltage power supply V GS-HIGH The double aging conditions of stress generated by the action of the electrode and high junction temperature stress are tested.

[0053] Step 4: When the device under test (DUT) is under the above-mentioned dual aging conditions, the host computer obtains the on-state voltage V of the device under test (DUT) in real time through the ADC analog-to-digital conversion chip. DS(ON) Under each parameter value of the programmable DC power supply E (i.e. input voltage and current value), the median filtering method is used to collect the conduction voltage V at the middle moment of 5 consecutive high gate voltage time periods. DS(ON) Calculate the median value as the on-state voltage V of the device under test (DUT) at high gate voltage. DS(ON)-HIGH Similarly, collect the conduction voltage V at the middle moment of 5 consecutive low gate voltage time periods DS(ON) Calculate the median value as the on-state voltage V of the device under test (DUT) at low gate voltage. DS(ON)-LOW At low gate voltage, the on-state voltage V DS(ON)-LOW Calculate the on-resistance R DS(ON)-LOW , used to monitor the degradation of the gate oxide layer; at high gate voltage, the on-state voltage V DS(ON)-HIGH As a temperature-sensitive parameter, it is used to monitor junction temperature in real time.

[0054] Step 5: Based on the on-resistance R at low gate voltage under the set aging time DS(ON)-LOW The accelerated degradation performance of the gate oxide layer of the device under test (DUT) considering the channel current stress is obtained by calculating the change in the gate oxide layer.

[0055] The following is a comprehensive explanation of the strategy for simultaneously monitoring device junction temperature and gate oxide quality:

[0056] The on-resistance of SiC MOSFET is mainly composed of channel region resistance, JEFT region resistance and drift region resistance. According to research, compared with SiMOSFET, the channel region resistance in SiC MOSFET accounts for a larger proportion of the on-resistance. The on-resistance of 600V and 1200V SiC MOSFET is mainly controlled by the channel resistance. In 600V and 1200V devices, the channel resistance accounts for approximately 66% and 48% of the total resistance respectively.

[0057] The expression for channel resistance is:

[0058] R CH =L CH / (Zμ inv Cox (V GS -V TH ))

[0059] Among them, L CH represents the channel length, Z represents the channel width, μ inv is the free electron mobility, C ox is the gate oxide capacitance, V GS is the applied gate stress, V TH is the threshold voltage. As can be seen from the formula, the channel resistance and the threshold voltage V TH There is a strong correlation. When the gate oxide layer of the device degrades, V TH Increase, resulting in an increase in channel resistance at a fixed gate voltage, which in turn causes an increase in on-resistance. This is because the device aging effect weakens the formation of the conduction channel, and this phenomenon is particularly evident at low gate voltages. GS At a low level, V GS -V TH The change of R at low gate voltage is significant, so the change of on-resistance caused by gate oxide degradation is also more significant. DS(ON)-LOW The change of V with the aging of gate oxide layer is TH An effective indirect indicator of drift, R DS(ON)-LOW As an effective precursor parameter for monitoring gate oxide degradation, it can be used to characterize the gate oxide layer quality of SiC MOSFET.

[0060] Under high gate voltage stress, when the gate oxide layer degrades and causes the threshold voltage V TH When a slight change occurs, V GS-VTH The change is small and can be almost ignored. At this time, the channel resistance and on-resistance remain basically unchanged, that is, the effect of gate oxide degradation on on-resistance under high gate voltage is considered to be negligible. When the load current flowing through the device under test is constant, its on-voltage drop is mainly determined by the on-resistance R under high gate voltage. DS(ON)-HIGH Therefore, the conduction voltage drop V DS(ON)-HIGH As a temperature-sensitive parameter that reflects changes in junction temperature.

[0061] Based on the above analysis, the present invention designs the following method in the active channel bias test: the device is subjected to an aging test at a high gate voltage, and V DS(ON)-HIGH To obtain the junction temperature of the device, thus verifying the junction temperature stability during the entire aging process; measuring V at low gate voltage DS(ON)-LOW To calculate the on-resistance R DS(ON)-LOW , used to characterize the degradation of the SiC MOSFET gate oxide layer.

[0062] When the DUT's gate oxide degrades, causing changes in on-resistance, the load current remains virtually unchanged. This means the load current remains constant at a fixed gate voltage throughout the test. At the start of the test, a current clamp is used to measure the load current at both high and low gate voltages. This current serves as the constant load current throughout the accelerated degradation test.

[0063] It is worth noting that this test requires the active channel bias test to be aged for a long time under high gate voltage stress and the junction temperature to be monitored in real time during this period. During the measurement phase, it is necessary to switch to low gate voltage to measure V DS(ON)-LOW , and thus calculate R DS(ON)-LOW , which is used to characterize the degree of degradation of the gate oxide layer. However, when the SiC MOSFET to be tested switches from a high gate voltage aging state to a low gate voltage measurement state, its on-resistance will increase, resulting in increased conduction loss of the device during the low gate voltage measurement phase. The resulting self-heating effect may increase the junction temperature of the device. DS(ON) Highly sensitive to junction temperature, in order to avoid the junction temperature fluctuations on R DS(ON)-LOW In order to more accurately reflect the health status of the gate oxide layer, it is necessary to ensure that the junction temperature of the device remains almost unchanged during the measurement phase. Therefore, in the low gate voltage measurement phase, the measurement duration needs to be shortened as much as possible. To this end, the present invention designs an extremely short low gate voltage test duration. In one test cycle, the device under test is under high gate voltage stress for about 800ms, while it is under low gate voltage stress for only about 200μs. Since the low gate voltage duration is extremely short, it can be considered that the junction temperature of the device remains stable during this 200μs period, thereby effectively avoiding the influence of junction temperature fluctuations on the measurement results. In this experiment, only V is monitored in real time. DS(ON) That is, it can be used to monitor the junction temperature and gate oxide layer degradation. The active channel bias test designed by the present invention can be used to explore the influence of channel current stress on the degradation of the SiC MOSFET gate oxide layer.

[0064] Any matters not described in the present invention are applicable to the prior art.

Claims

1. The SiC MOSFET gate oxide layer accelerated degradation test circuit considering channel current stress is characterized by: The circuit includes a driving circuit, a power loop circuit and a data acquisition circuit; The drive circuit mainly comprises an isolated half-bridge drive chip (U1) and a half-bridge circuit. The INA pin and the INB pin of the isolated half-bridge drive chip (U1) respectively receive two complementary square wave signals output by a microprocessor (MCU); the VCCI pin of the isolated half-bridge drive chip (U1) is connected to the positive electrode of a 3.3V power supply, and the GND pin, the DISABLE pin and the negative electrode of the 3.3V power supply are connected to the DGND pin of the microprocessor. The DT pin of the isolated half-bridge driver chip (U1) is connected to one end of the No. 1 resistor (R1) and one end of the No. 1 capacitor (C1). The other end of the No. 1 resistor (R1) and the other end of the No. 1 capacitor (C1) are connected in parallel and then connected to the DGND pin of the microprocessor. The VDDB pin of the isolated half-bridge driver chip (U1), one end of the No. 3 capacitor (C3), and one end of the No. 2 resistor (R2) are all connected to the positive output end of the +12V power supply. Its VSSB pin, the other end of the No. 3 capacitor (C3), and the negative electrode of the +12V power supply are all connected to the low gate voltage power supply (V GS_LOW ) is connected to the positive output terminal; low gate voltage power supply (V GS_LOW ) is connected to the Kelvin source of the device under test, the other end of the second resistor (R2) is connected to the anode of the first diode (D1), the VDDA pin of the isolated half-bridge driver chip (U1) is connected to one end of the second capacitor (C2) and the cathode of the first diode (D1), and the other end of the second capacitor (C2) is connected to the VSSA pin of the isolated half-bridge driver chip (U1); The half-bridge circuit includes an upper N-channel MOSFET (M1) and a lower N-channel MOSFET (M2). The OUTA pin of the isolated half-bridge driver chip (U1) is connected to one end of a third resistor (R3), and the other end of the third resistor (R3) is connected to the gate of the upper N-channel MOSFET (M1); the drain of the upper N-channel MOSFET (M1) is connected to a high gate voltage power supply (V GS_HIGH ) positive pole; high gate voltage power supply (V GS_HIGH ) is connected to the Kelvin source of the device under test; The OUTB pin of the isolated half-bridge driver chip (U1) is connected to one end of the fourth resistor (R4), and the other end of the fourth resistor (R4) is connected to the gate of the lower N-channel MOSFET (M2). The source of the lower N-channel MOSFET (M2) is connected to the low gate voltage power supply (V GS_LOW ) is connected to the positive output terminal; The source of the upper N-channel MOSFET (M1), the drain of the lower N-channel MOSFET (M2), and the VSSA pin of the isolated half-bridge driver chip (U1) are connected in parallel and then connected to one end of a fifth resistor (R5). The other end of the fifth resistor (R5) is respectively connected to the gate of the device under test (DUT) and one end of a sixth resistor (R6). The other end of the sixth resistor (R6) is connected to the Kelvin source of the device under test (DUT). The power loop circuit is composed of a No. 7 resistor (R7), an No. 8 resistor (R8), a No. 9 resistor (R9), a No. 1 NPN transistor (Q1), and a No. 2 NPN transistor (Q2). One end of the No. 7 resistor (R7) is connected to the gate of the device under test (DUT), and the other end of the No. 7 resistor (R7) is connected to the Kelvin source of the device under test (DUT); one end of the No. 8 resistor (R8) is connected to the drain of the device under test (DUT), and the other end of the No. 8 resistor (R8) and one end of the No. 9 resistor (R9) are connected in parallel and then connected to the programmable The positive electrode of the programmable DC power supply (E); the source of the device under test (DUT) is connected to the collector of the No. 1 NPN transistor (Q1), the bases of the No. 1 NPN transistor (Q1) and the No. 2 NPN transistor (Q2) are connected, the emitter of the No. 1 NPN transistor (Q1), the emitter of the No. 2 NPN transistor (Q2), and the negative electrode of the programmable DC power supply (E) are connected in parallel and then grounded; the other end of the No. 9 resistor (R9) is connected to the base of the No. 2 NPN transistor (Q2) and the collector of the No. 2 NPN transistor (Q2); The data acquisition circuit is composed of an isolation amplifier (U2), a differential circuit and an ADC analog-to-digital conversion chip. The drain of the device under test (DUT) is connected to the first input terminal of the isolation amplifier (U2), and the second input terminal of the isolation amplifier (U2) is connected to the Kelvin source of the device under test (DUT); The differential circuit includes a tenth resistor (R10), an eleventh resistor (R11), a twelfth resistor (R12), a thirteenth resistor (R13), and an operational amplifier (U3); an OUTP pin of the isolation amplifier (U2) is connected to one end of the tenth resistor (R10); the other end of the tenth resistor (R10) and one end of the twelfth resistor (R12) are connected in parallel and then connected to the positive input end of the operational amplifier (U3); and the other end of the twelfth resistor (R12) is connected to the DGND pin of the microprocessor; The OUTN pin of the isolation amplifier (U2) is connected to one end of the eleventh resistor (R11), the other end of the eleventh resistor (R11) is connected in parallel with one end of the thirteenth resistor (R13) and then connected to the negative input end of the operational amplifier (U3), the other end of the thirteenth resistor (R13) is connected in parallel with the output end of the operational amplifier (U3) and then connected to the input end of the ADC analog-to-digital conversion chip, and the output end of the ADC analog-to-digital conversion chip is connected to the host computer; The device under test (DUT) is a SiC MOSFET.

2. The SiC MOSFET gate oxide layer accelerated degradation test circuit considering channel current stress according to claim 1, characterized in that: The isolated half-bridge driver chip (U1) is UCC21520DWR produced by Texas Instruments.

3. The SiC MOSFET gate oxide layer accelerated degradation test circuit considering channel current stress according to claim 1, characterized in that: The isolation amplifier (U2) used is ISO224ADWVR produced by Texas Instruments.

4. The SiC MOSFET gate oxide layer accelerated degradation test circuit considering channel current stress according to claim 1, characterized in that: The operational amplifier (U3) uses the OPA2228U produced by Texas Instruments.

5. The SiC MOSFET gate oxide layer accelerated degradation test circuit considering channel current stress according to claim 1, characterized in that: The ADC analog-to-digital conversion chip used is ADS8860IDGS produced by Texas Instruments.

6. The SiC MOSFET gate oxide layer accelerated degradation test circuit considering channel current stress according to claim 1, characterized in that: The resistance values of resistor No. 10 (R10), resistor No. 11 (R11), resistor No. 12 (R12), and resistor No. 13 (R13) are all equal.

7. A SiC MOSFET gate oxide layer accelerated degradation test method considering channel current stress, characterized in that: The method comprises the circuit according to any one of claims 1 to 6 and the following steps: Step 1: First, connect the drive circuit, power loop circuit, data acquisition circuit, and device under test (DUT) in the circuit described above through a circuit board. Then, place the entire circuit in a constant temperature incubator to ensure that the ambient temperature of the device under test (DUT) remains stable. Step 2: The microprocessor outputs two complementary square wave signals. The two square wave signals pass through the isolated half-bridge driver chip (U1), causing the upper N-channel MOSFET (M1) and the lower N-channel MOSFET (M2) of the half-bridge circuit to alternately turn on, causing the gate voltage of the device under test (DUT) to alternately switch between low gate voltage and high gate voltage. The duty cycle is controlled by the microprocessor. The high gate voltage aging time of the device under test (DUT) is set to 800ms, and the low gate voltage aging time of the device under test (DUT) is set to 200μs. Step 3: Turn on the programmable DC power supply (E) and operate it in CV mode. By adjusting the parameters of the programmable DC power supply (E), the junction temperature of the device under test (DUT) gradually increases and stabilizes at a preset value. During this process, the device under test (DUT) is subjected to dual aging conditions of high gate stress and high junction temperature stress. Step 4: When the device under test (DUT) is under the above dual aging conditions, the host computer obtains the on-state voltage V of the device under test (DUT) in real time through the ADC analog-to-digital conversion chip DS(ON) ; Under each parameter value of the programmable DC power supply (E), the median filtering method is used to collect the conduction voltage V at the middle moment of 5 consecutive high gate voltage time periods DS(ON) Calculate the median value as the on-state voltage V of the device under test (DUT) at high gate voltage. DS(ON)-HIGH Similarly, the on-state voltage V is collected at the middle moment of 5 consecutive low gate voltage time periods. DS(ON) Calculate the median value as the on-state voltage V of the device under test (DUT) at low gate voltage. DS(ON)-LOW ; At low gate voltage, using the on-state voltage V DS(ON)-LOW Calculate the on-resistance R DS(ON)-LOW , used to monitor the degradation of the gate oxide layer; at high gate voltage, the on-state voltage V DS(ON)-HIGH As a temperature-sensitive parameter, it is used to monitor junction temperature in real time; Step 5: Based on the on-resistance R at low gate voltage under the set aging time DS(ON)-LOW The accelerated degradation performance of the gate oxide layer of the device under test (DUT) considering the channel current stress is obtained by calculating the change in the gate oxide layer.

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