Formation method of semiconductor structure

Abstract

The invention provides a method for forming a semiconductor structure. The method comprises the following steps: providing a substrate; a plurality of separately arranged fin parts are formed on the substrate, each fin part comprises a first sacrificial layer and a plurality of overlapped composite layers located on the surface of the first sacrificial layer, and each composite layer comprises a second sacrificial layer and a channel layer located on the surface of the second sacrificial layer; a pseudo gate structure is formed on the substrate, the pseudo gate structure comprises a first pseudo gate part, and the first pseudo gate part stretches across the fin part and is located on part of the side wall and the top surface of the fin part; forming a protection layer on the exposed side wall surface and the top surface of the fin part, wherein the protection layer exposes the side wall surface of the first sacrificial layer; taking the protection layer as a mask, removing the first sacrificial layer, and forming an isolation groove between the composite layer and the substrate; and a bottom isolation layer is formed in the isolation groove, so that the performance of the GAA containing the BDI structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a method for forming a semiconductor structure. Background Art

[0002] With the further development of semiconductor technology, traditional fin field-effect transistors have limitations in further increasing the operating current. Specifically, since only the regions near the top surface and sidewalls in the fin are used as the channel region, the volume of the fin used as the channel region is small, which limits the increase in the operating current of the fin field-effect transistor. Therefore, a MOSFET with a gate all around (GAA) structure is proposed, which increases the volume used as the channel region and further increases the operating current of the GAA structure MOSFET.

[0003] In the GAA structure, the BDI (Bottom Dielectric Isolation) structure can effectively block the leakage problem among the fin, source, and drain terminals, and has broad application prospects.

[0004] However, the performance of the current GAA containing the BDI structure still needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the GAA containing the BDI structure.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of discretely arranged fins on the substrate, the fins including a first sacrificial layer and a plurality of overlapping composite layers on the surface of the first sacrificial layer, the composite layers including a second sacrificial layer and a channel layer on the surface of the second sacrificial layer; forming a dummy gate structure on the substrate, the dummy gate structure including a first dummy gate portion that straddles the fins and is located on a part of the sidewalls and the top surface of the fins; forming a protective layer on the exposed sidewall surfaces and the top surface of the fins, the protective layer exposing the sidewall surface of the first sacrificial layer; using the protective layer as a mask to remove the first sacrificial layer and form an isolation groove between the composite layer and the substrate; and forming a bottom isolation layer in the isolation groove.

[0007] Optionally, the method for forming the bottom isolation layer includes: forming an initial bottom isolation layer on the surface of the substrate, the sidewall and top surface of the fins, and the top and sidewall surfaces of the first dummy gate portion; and etching the initial bottom isolation layer to form a bottom isolation layer between the substrate and the composite layer.

[0008] Optionally, the material of the bottom isolation layer includes one or a combination of silicon oxide, silicon nitride, silicon oxynitride, low-K dielectric material, or ultra-low-K dielectric material.

[0009] Optionally, after forming the bottom isolation layer, the method further includes: forming source / drain openings in the fin portions on both sides of the first dummy gate portion; forming source / drain doped layers in the source / drain openings; depositing a dielectric layer on the surface of the substrate, with the bottom of the dummy gate structure exposed at the top of the dielectric layer; removing the dummy gate structure to form a gate opening; removing the second sacrificial layer exposed in the gate opening to form a gate trench; and forming a gate structure in the gate opening and the gate trench.

[0010] Optionally, the dummy gate structure further includes second dummy gate portions on the substrate on both sides of the first dummy gate portion, and the surface of the second dummy gate portion is lower than the top surface of the fin portion and higher than or flush with the top surface of the first sacrificial layer.

[0011] Optionally, the method for forming the protective layer includes: forming an initial protective layer on the surface of the first dummy gate portion, the surface of the second dummy gate portion, and the exposed sidewalls and top surface of the fin portion; etching and removing the initial protective layer on the surface of the second dummy gate portion to form a protective layer on the sidewalls and top surface of the fin portion.

[0012] Optionally, after forming the protective layer and before forming the isolation trench, the method further includes removing the second dummy gate portion.

[0013] Optionally, before forming the protective layer, a third sacrificial layer is formed on the substrate, the surface of the third sacrificial layer is lower than the top surface of the fin portion and higher than or flush with the top surface of the first sacrificial layer; after forming the protective layer, the third sacrificial layer is removed.

[0014] Optionally, the etching rate of the first sacrificial layer by the etching process for removing the first sacrificial layer is greater than the etching rate of the second sacrificial layer.

[0015] Optionally, the material of the second sacrificial layer is silicon germanium, and the mass percentage of germanium atoms in the second sacrificial layer is 20% to 35%.

[0016] Optionally, the material of the first sacrificial layer is silicon germanium, and the mass percentage of germanium atoms in the first sacrificial layer is 40% to 80%.

[0017] Optionally, the thickness of the protective layer is 10 angstroms to 40 angstroms.

[0018] Optionally, the material of the protective layer includes silicon nitride and a nitrogen-containing low-k dielectric material.

[0019] Optionally, the fin portion further includes a bottom structure located between the first sacrificial layer and the substrate.

[0020] Optionally, the substrate surface further has an isolation structure, and the surface of the isolation structure is lower than or flush with the top surface of the bottom structure.

[0021] Optionally, the material of the channel layer includes silicon.

[0022] Optionally, before forming the dummy gate structure on the substrate, it further includes forming a gate dielectric layer on the sidewalls and top surface of the fin.

[0023] Optionally, using the protective layer as a mask to remove the first sacrificial layer, it further includes: removing the gate dielectric layer on the sidewalls of the first sacrificial layer.

[0024] Optionally, the process of removing the first sacrificial layer is a wet etching process, and the wet etching process uses a mixture of fluoride ions and hydrogen peroxide as the etching liquid.

[0025] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0026] In the formation method of the technical solution of the present invention, the fin is located on the surface of the substrate. The fin includes a first sacrificial layer and several overlapping composite layers on the surface of the first sacrificial layer. The composite layer includes a second sacrificial layer and a channel layer on the surface of the second sacrificial layer. A protective layer is formed on the exposed sidewall surface and top surface of the fin. The protective layer exposes the sidewall surface of the first sacrificial layer. Using the protective layer as a mask, the first sacrificial layer is removed. An isolation groove is formed between the composite layer and the substrate, and a bottom isolation groove is formed in the isolation groove. During the process of etching and removing the exposed first sacrificial layer, the protective layer on the sidewall of the fin is used to protect the second sacrificial layer from being damaged. At the same time, since the second sacrificial layer is protected, the formation process window of the bottom isolation layer is increased, solving the problem of long-channel silicon germanium residue, and having a wide range of applications. Description of the Drawings

[0027] Figure 1 are schematic diagrams of the structures of each step of a semiconductor structure and its formation method in an embodiment.

[0028] Figures 2 to 19 are schematic diagrams of the structures of each step of a semiconductor structure and its formation method in an embodiment of the present invention Detailed Embodiments

[0029] As in the background art, the performance of the existing GAA containing the BDI structure still needs to be improved. Please refer to Figure 1 for description.

[0030] Please refer to Figure 1 , a substrate 100; several discretely arranged fins 101 on the substrate 100. The fin includes several overlapping sacrificial layers 103 and a channel layer 104 on the surface of adjacent sacrificial layers 103; a bottom isolation layer 102 between the surface of the substrate 100 and the bottom sacrificial layer 103.

[0031] The inventors found that during the formation of the bottom isolation layer 102, an etching process is used to remove the high-concentration sacrificial layer between the substrate and the fin, thereby providing a space for the formation of the bottom isolation layer 102. However, the etching process can cause damage to the sidewalls of the sacrificial layer 103, resulting in depressions, which in turn affect the subsequent process of forming the gate. On the other hand, if the time for removing the high-concentration sacrificial layer between the substrate and the fin is controlled and shortened during the etching process, the high-concentration sacrificial layer in the long-channel region will be completely etched, making it difficult to balance the two.

[0032] On this basis, the present invention provides a method for forming a semiconductor structure. A protective layer is formed on the sidewall surface and the top surface of the fin that is exposed. The sidewall surface of the first sacrificial layer is exposed by the protective layer. Using the protective layer as a mask, the first sacrificial layer is removed. An isolation groove is formed between the composite layer and the substrate. A bottom isolation groove is formed in the isolation groove. During the process of etching and removing the exposed first sacrificial layer, the protective layer on the sidewall of the fin is used to protect the second sacrificial layer from being damaged. At the same time, since the second sacrificial layer is protected, the formation process window of the bottom isolation layer is increased, the problem of long-channel silicon germanium residue is solved, and it has a wide range of applications.

[0033] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the accompanying drawings.

[0034] Figures 2 to 19 It is a schematic structural diagram of each step of a semiconductor structure and its forming method in an embodiment of the present invention.

[0035] First, please refer to Figure 2 and Figure 3 , a substrate 200 is provided, and a plurality of discretely arranged fins 204 are formed on the substrate 200. The fins 204 include a first sacrificial layer 201 and a plurality of overlapping composite layers 202 located on the surface of the first sacrificial layer 201. The composite layer 202 includes a second sacrificial layer 202a and a channel layer 202b located on the surface of the second sacrificial layer 202a.

[0036] Figure 3 For Figure 2 a cross-sectional view taken along line A-A.

[0037] In this embodiment, the fin 204 further includes: a bottom structure 204a located between the first sacrificial layer 201 and the substrate 200.

[0038] In this embodiment, the substrate 200 surface further has an isolation structure 203, and the surface of the isolation structure 203 is lower than or flush with the top surface of the bottom structure 204a.

[0039] In this embodiment, the number of the fin portions 204 is two; the number of layers of the second sacrificial layer 202a is three; and the number of layers of the channel layer 202b is three.

[0040] In this embodiment, the method for forming the fin portions 204 includes: forming a fin material film (not shown) on the substrate 200, where the fin material film includes a plurality of sacrificial material films overlapping along the normal direction of the surface of the substrate 200 and channel material films located between two adjacent sacrificial material films; forming a patterned layer (not shown) on the fin material film; etching the fin material film using the patterned layer as a mask until the top surface of the substrate 200 is exposed, so as to form the fin portions 204, where the structure of the fin portions 204 includes a first sacrificial layer 201 and a plurality of overlapping composite layers 202 located on the surface of the first sacrificial layer 201, and the composite layer 202 includes a second sacrificial layer 202a and a channel layer 202b located on the surface of the second sacrificial layer 202a.

[0041] In this embodiment, a plurality of fin portions 204 are arranged in parallel along the first direction Y.

[0042] In this embodiment, the material of the first sacrificial layer 201 is silicon germanium, and the mass percentage of germanium atoms in the first sacrificial layer 201 is 40% to 80%.

[0043] In this embodiment, the material of the second sacrificial layer 202a is silicon germanium, and the mass percentage of germanium atoms in the second sacrificial layer 202a is 20% to 35%.

[0044] In this embodiment, the material of the channel layer 202b is silicon.

[0045] Please refer to Figures 4 to 6 , an initial dummy gate structure is formed on the substrate 200, and the initial dummy gate structure is etched to form a dummy gate structure 205.

[0046] Figure 5 For Figure 4 the cross-sectional view taken along line A-A, Figure 6 For Figure 4 the cross-sectional view taken along line B-B.

[0047] In this embodiment, the initial dummy gate structure 205 extends along the second direction X, and the first direction Y is perpendicular to the second direction X.

[0048] Figure 5 For Figure 4 the cross-sectional view at A-A in Figure 6 For Figure 4 the cross-sectional view at B-B in.

[0049] In this embodiment, the dummy gate structure 205 includes a first dummy gate portion 205a that straddles the fin portion 204 and is located on a partial sidewall and the top surface of the fin portion 204.

[0050] In this embodiment, the dummy gate structure 205 further includes second dummy gate portions 205b on the substrate 200 on both sides of the first dummy gate portion 205a. The surface of the second dummy gate portion 205b is lower than the top surface of the fin portion 204 and higher than or flush with the top surface of the first sacrificial layer 201.

[0051] In this embodiment, the dummy gate structure 205 includes: a gate dielectric layer 207 on the fin portion 204, a dummy gate layer 208 on the gate dielectric layer 207, a gate protection layer 209 on the dummy gate layer 208, and sidewalls 206 on the sidewalls of the dummy gate layer 208 and the gate protection layer 209.

[0052] In this embodiment, the second dummy gate portion 205b is located on the surface of the isolation structure 203.

[0053] A protection layer is formed on the exposed sidewall surface and the top surface of the fin portion. The sidewall surface of the first sacrificial layer 201 is exposed by the protection layer. For the formation method of the protection layer, please refer to Figures 7 to 10 .

[0054] Please refer to Figures 7 to 8 , and an initial protection layer 210 is formed on the surface of the first dummy gate portion 205a, the surface of the second dummy gate portion 205b, and the exposed sidewalls and the top surface of the fin portion 204.

[0055] Figure 7 The view direction of Figure 5 is the same as the view direction of Figure 8 The view direction of Figure 6 is the same as the view direction of

[0056] In this embodiment, the formation process of the initial protection layer 210 is a chemical vapor deposition process.

[0057] In other embodiments, the formation process of the initial protection layer 210 can also be one or a combination of a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0058] Please refer to Figures 9 to 10 , etch and remove the initial protection layer 210 on the surface of the second dummy gate portion 205b, and form a protection layer 211 on the sidewalls and the top surface of the fin portion 204.

[0059] Figure 9 The view direction of Figure 7 is the same as the view direction of Figure 10 The view direction of Figure 8have the same view direction.

[0060] In this embodiment, while removing the initial protective layer 210 on the surface of the second dummy gate portion 205b, the top surface of the fin portion 204 and the initial protective layer 210 on the top surface of the first dummy gate portion 205a are also removed.

[0061] In this embodiment, the thickness of the protective layer 211 is 10 angstroms to 40 angstroms.

[0062] In this embodiment, when the thickness of the protective layer 211 is less than 10 angstroms, the thickness of the protective layer 211 is too thin at this time and cannot play a good protective role; when the thickness of the protective layer 211 is greater than 40 angstroms, the thickness of the protective layer 211 is too thick at this time, which is not conducive to subsequent removal.

[0063] In this embodiment, the process of etching the initial protective layer 210 is a dry etching process.

[0064] In other embodiments, the process of etching the initial protective layer 210 can also be a dry etching process.

[0065] In this embodiment, the material of the protective layer 211 is silicon nitride.

[0066] In other embodiments, the material of the protective layer 211 includes one or a combination of silicon nitride and a nitrogen-containing low-k dielectric material.

[0067] In other embodiments, before forming the protective layer 211, a third sacrificial layer is formed on the substrate 200, and the surface of the third sacrificial layer is lower than the top surface of the fin portion 204 and higher than or flush with the top surface of the first sacrificial layer 201; after forming the protective layer 211, the third sacrificial layer is removed.

[0068] Please refer to Figures 11 to 12 , remove the second dummy gate portion 205b to expose the sidewall surface of the first sacrificial layer 201.

[0069] Figure 11 have the same view direction as Figure 9 have the same view direction, Figure 12 have the same view direction as Figure 10 have the same view direction.

[0070] In this embodiment, the process of removing the second dummy gate portion 205b is a wet etching process.

[0071] Please refer to Figures 13 to 14 , using the protective layer 211 as a mask, remove the first sacrificial layer 201 to form an isolation groove 212 between the composite layer 202 and the substrate 200.

[0072] Figure 13 have the same view direction as Figure 11has the same view direction as Figure 14 has a view direction that is the same as that of Figure 12 has the same view direction.

[0073] In this embodiment, while removing the first sacrificial layer 201, the gate dielectric layer 207 on the sidewall of the first sacrificial layer 201 is also removed.

[0074] In this embodiment, the etching rate of the wet etching process for the first sacrificial layer 201 is greater than that for the second sacrificial layer 202a.

[0075] In this embodiment, the wet etching process is used to remove the first sacrificial layer 201, and a mixture of fluoride ions and hydrogen peroxide is used as the etching liquid in the wet etching process.

[0076] In this embodiment, HF completely etches the gate dielectric layer 207 on the surface without etching the protective layer 211 on the sidewall of the second sacrificial layer 202a; E-2504 is mainly a mixture of F- and H2O2. The higher the concentration of F-, the faster the etching rate of the first sacrificial layer 201, and it has a high selectivity ratio for the channel layer 202b, the gate dielectric layer 207, and the protective layer 211, and the etching selectivity ratio is greater than 50; the process time of E-2504 can be appropriately extended to remove the first sacrificial layer 201 in all areas, reduce the residue of the first sacrificial layer 201, and improve the removal efficiency.

[0077] Please refer to Figures 15 to 16 , and a bottom isolation layer 213 is formed in the isolation trench 212.

[0078] Figure 15 has a view direction that is the same as that of Figure 13 has the same view direction, Figure 16 has a view direction that is the same as that of Figure 14 has the same view direction.

[0079] In this embodiment, the material of the bottom isolation layer 213 includes one or a combination of silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material, or ultra-low-k dielectric material.

[0080] In this embodiment, the method for forming the bottom isolation layer 213 includes: forming an initial bottom isolation layer (not shown in the figure) on the surface of the substrate 200, the sidewall and top surface of the fin 204, and the top and sidewall surfaces of the first dummy gate portion 205a; etching the initial bottom isolation layer (not shown in the figure) to form the bottom isolation layer 213 between the substrate 200 and the composite layer 202.

[0081] In this embodiment, a protective layer 211 is formed on the sidewall surface and the top surface of the fin 204 that are exposed. The protective layer 211 exposes the sidewall surface of the first sacrificial layer 201. Using the protective layer 211 as a mask, the first sacrificial layer 201 is removed, and an isolation trench 212 is formed between the composite layer 202 and the substrate 200. A bottom isolation trench 212 is formed in the isolation trench 212. During the process of etching to remove the exposed first sacrificial layer 201, the protective layer 211 on the sidewall of the fin 204 is used to protect the second sacrificial layer 202a from being damaged. At the same time, since the second sacrificial layer 202a is protected, the process window for forming the bottom isolation layer 213 is increased, solving the problem of long-channel silicon germanium residue, and having a wide range of applications.

[0082] Please refer to Figures 17 to 19 , the dummy gate structure 205 is removed to form a gate structure 215.

[0083] Figure 18 For Figure 17 a cross-sectional view taken along line A-A, Figure 19 For Figure 17 a cross-sectional view taken along line B-B.

[0084] In this embodiment, the method for forming the gate structure 215 includes: forming source / drain openings (not shown in the figure) in the fins 204 on both sides of the first dummy gate portion 205a; forming source / drain doped layers 214 in the source / drain openings; depositing a dielectric layer 216 on the surface of the substrate 200, and the top of the dielectric layer 216 exposes the bottom of the dummy gate structure 205; removing the dummy gate structure 205 to form a gate opening (not shown in the figure); removing the second sacrificial layer 202a exposed in the gate opening to form a gate trench, and forming the gate structure 215 in the gate opening and the gate trench.

[0085] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate; Forming a plurality of fin portions arranged separately on the substrate, the fin portions including a first sacrificial layer and a plurality of overlapping composite layers on the surface of the first sacrificial layer, the composite layers including a second sacrificial layer and a channel layer on the surface of the second sacrificial layer; Forming a dummy gate structure on the substrate, the dummy gate structure including a first dummy gate portion that straddles the fin portions and is located on partial sidewalls and the top surface of the fin portions; Forming a protective layer on the exposed sidewall surfaces and the top surface of the fin portions, the protective layer exposing the sidewall surface of the first sacrificial layer; Using the protective layer as a mask to remove the first sacrificial layer and form isolation trenches between the composite layers and the substrate; Forming a bottom isolation layer in the isolation trenches.

2. The method for forming a semiconductor structure according to claim 1, wherein, The method of forming the bottom isolation layer includes: forming an initial bottom isolation layer on the surface of the substrate, the sidewall and top surface of the fin portions, and the top and sidewall surfaces of the first dummy gate portion; etching the initial bottom isolation layer to form the bottom isolation layer between the substrate and the composite layers.

3. The method for forming a semiconductor structure according to claim 1, wherein, The material of the bottom isolation layer includes one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, low-K dielectric material, or ultra-low-K dielectric material.

4. The method for forming a semiconductor structure according to claim 1, wherein, After forming the bottom isolation layer, it further includes: forming source-drain openings in the fin portions on both sides of the first dummy gate portion; forming source-drain doped layers in the source-drain openings; depositing a dielectric layer on the surface of the substrate, the top of the dielectric layer exposing the bottom of the dummy gate structure; removing the dummy gate structure to form a gate opening; removing the second sacrificial layer exposed in the gate opening to form a gate trench, and forming a gate structure in the gate opening and the gate trench.

5. The method for forming a semiconductor structure according to claim 1, wherein The dummy gate structure further includes second dummy gate portions on the substrate on both sides of the first dummy gate portion, the surface of the second dummy gate portions being lower than the top surface of the fin portions and higher than or flush with the top surface of the first sacrificial layer.

6. The method for forming a semiconductor structure according to claim 5, wherein, The method of forming the protective layer includes: forming an initial protective layer on the surface of the first dummy gate portion, the surface of the second dummy gate portions, and the exposed sidewall and top surface of the fin portions; etching and removing the initial protective layer on the surface of the second dummy gate portions to form the protective layer on the sidewall and top surface of the fin portions.

7. The method for forming a semiconductor structure according to claim 5, wherein, It further includes: Before forming the isolation trenches after forming the protective layer, it further includes removing the second dummy gate portions.

8. The method for forming a semiconductor structure according to claim 1, wherein, It further includes: Before forming the protective layer, forming a third sacrificial layer on the substrate, the surface of the third sacrificial layer being lower than the top surface of the fin portions and higher than or flush with the top surface of the first sacrificial layer; after forming the protective layer, removing the third sacrificial layer.

9. The method for forming a semiconductor structure according to claim 1, wherein, The etching rate of the etching process for removing the first sacrificial layer for the first sacrificial layer is greater than the etching rate for the second sacrificial layer.

10. The method for forming a semiconductor structure according to claim 9, wherein, The material of the second sacrificial layer is silicon germanium, and the mass percentage of germanium atoms in the second sacrificial layer is 20% to 35%.

11. The method for forming a semiconductor structure according to claim 9, wherein, The material of the first sacrificial layer is silicon germanium, and the mass percentage of germanium atoms in the first sacrificial layer is 40% to 80%.

12. The method for forming a semiconductor structure according to claim 1, wherein, The thickness of the protective layer is 10 angstroms to 40 angstroms.

13. The method for forming a semiconductor structure according to claim 1, wherein, The materials of the protection layer include silicon nitride and nitrogen-containing low-k dielectric materials.

14. The method for forming a semiconductor structure according to claim 1, wherein The fin further includes a bottom structure located between the first sacrificial layer and the substrate.

15. The method for forming a semiconductor structure according to claim 14, wherein, The surface of the substrate further has an isolation structure, and the surface of the isolation structure is lower than or flush with the top surface of the bottom structure.

16. The method for forming a semiconductor structure according to claim 1, wherein The material of the channel layer includes silicon.

17. The method for forming a semiconductor structure according to claim 1, wherein, Before forming the pseudo-gate structure on the substrate, forming a gate dielectric layer on the sidewalls and the top surface of the fin is further included.

18. The method for forming a semiconductor structure according to claim 17, wherein, Using the protection layer as a mask to remove the first sacrificial layer further includes removing the gate dielectric layer on the sidewalls of the first sacrificial layer.

19. The method for forming a semiconductor structure according to claim 1, wherein, The process of removing the first sacrificial layer is a wet etching process, and the wet etching process uses a mixture of fluoride ions and hydrogen peroxide as the etching liquid.

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