Transistor with extended gate structure and manufacturing method thereof

Abstract

The invention discloses a transistor with an extended gate structure and a manufacturing method thereof. A method of manufacturing a semiconductor device includes: forming a dummy gate and a gate spacer; forming an interlayer dielectric layer; forming a trench having a lower portion and an upper portion, the upper portion being wider than the lower portion; and forming a gate structure in the trench. The gate structure has an upper portion in the trench upper portion and a lower portion in the trench lower portion. The upper portion of the gate structure is wider than the lower portion of the gate structure. The first gate spacer has a first inner sidewall facing the lower portion of the gate structure. The second gate spacer has a second inner sidewall facing the lower portion of the gate structure. The first inner sidewall is spaced apart from the second inner sidewall by a first distance. An upper portion of the gate structure is wider than the first distance.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and more particularly to a transistor having an extended gate structure and a method of manufacturing the same. Background Art

[0002] The size of transistors decreases as the process node advances and integrated circuits become more dense. Shrinking transistors to smaller sizes allows more transistors to be integrated into a given area and is generally advantageous, but challenges also arise when some features become very small. Summary of the Invention

[0003] According to a first aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, the method comprising: forming a dummy gate and gate spacers on a semiconductor region of a substrate; forming an interlayer dielectric layer along sidewalls of the gate spacers; forming a trench having a lower portion and an upper portion, the upper portion of the trench being wider than the lower portion of the trench, forming the trench comprising: removing a portion of the gate spacers and removing the dummy gate; and forming a gate structure in the trench, wherein: the gate structure has a lower portion and an upper portion, the upper portion of the gate structure is in the upper portion of the trench, the lower portion of the gate structure is in the lower portion of the trench, and the upper portion of the gate structure is wider than the lower portion of the gate structure, a first gate spacer of the gate spacers has a first inner sidewall facing a first side of the lower portion of the gate structure, and a second gate spacer of the gate spacers has a second inner sidewall facing a second side of the lower portion of the gate structure, the first inner sidewall is spaced apart from the second inner sidewall by a first distance, and the upper portion of the gate structure has a width greater than the first distance.

[0004] According to a second aspect of the present disclosure, there is provided a semiconductor device, comprising: a semiconductor region having a channel region therein; a gate structure adjacent to the channel region; a first gate spacer and a second gate spacer, the first gate spacer being located on a first side of the gate structure, the second gate spacer being located on a second side of the gate structure; and an interlayer dielectric layer along sidewalls of the first spacer and the second gate spacer, wherein: the gate structure has a lower portion and an upper portion, the width of the upper portion of the gate structure is different from the width of the lower portion of the gate structure, the first gate spacer has a first inner sidewall facing a first side of the lower portion of the gate structure, and the second gate spacer has a second inner sidewall facing a second side of the lower portion of the gate structure, the first inner sidewall is spaced apart from the second inner sidewall by a first distance, and the upper portion of the gate structure has a width greater than the first distance.

[0005] According to a third aspect of the present disclosure, there is provided a semiconductor device, comprising: a semiconductor region; a gate structure located on the semiconductor region; an insulating layer of a dielectric material, contacting the top of the gate structure and extending over the entire width of the top of the gate structure; a first gate spacer and a second gate spacer; and an interlayer dielectric layer along the sides of the first spacer and the second gate spacer, wherein: the gate structure has a lower part and an upper part, the lower part extends vertically between the first spacer and the second gate spacer and has a first width, and the upper part extends vertically from the lower part to the insulating layer and has a second width greater than the first width, the first gate spacer has a first inner sidewall facing a first side of the lower part of the gate structure, and the second gate spacer has a second inner sidewall facing a second side of the lower part of the gate structure, the first inner sidewall is spaced from the second inner sidewall by a first distance, and the insulating layer has a width greater than the first distance. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure may be best understood when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0007] Figure 1 is a flowchart of operations in a method of manufacturing a semiconductor device according to some embodiments.

[0008] Figures 2A to 2H is a cross-sectional view of a transistor structure at various stages in a manufacturing process according to some embodiments.

[0009] Figure 3A and Figure 3B is a cross-sectional view of a transistor structure according to some embodiments of Figure 2G of.

[0010] Figure 4 is a cross-sectional view of a transistor structure according to some embodiments.

[0011] Figure 5 is a cross-sectional view of a transistor structure according to some embodiments.

[0012] Figures 6A to 6C is a cross-sectional view of a transistor structure according to some embodiments. DETAILED DESCRIPTION

[0013] This disclosure describes embodiments and examples of the subject matter set forth herein. Although specific examples of components, materials, values, steps, arrangements, etc. may be described, such examples are not limiting and other components, materials, values, steps, arrangements, etc. may be contemplated.

[0014] As used herein, unless otherwise indicated, terms beginning with “a” or “an” (and “the” when the reference basis is “a” or “an”) refer to both the singular and plural of such terms.

[0015] Furthermore, throughout this disclosure and the figures, the same reference numerals are intended to denote the same elements, but the same reference numerals or other reference descriptors do not imply a particular hierarchy or order. Similarly, references to “first,” “second,” “third,” etc. do not imply a particular order.

[0016] Moreover, the description of a first element being “on” a second element may include cases where the first element is directly on the second element (i.e., the first element and the second element are in direct contact), and may also include cases where additional elements are between the first element and the second element (e.g., cases where the first element and the second element are not in direct contact).

[0017] In addition, the terms “comprise,” “comprises,” “include,” “includes,” “have,” “has,” and variations of the foregoing terms denote non-exclusive inclusion. For example, a process, article, or apparatus that “comprises” a list or set of stated elements is not limited to only the stated elements but may include other elements not expressly listed or recited.

[0018] Furthermore, the term “or” is inclusive and not exclusive, such that the term “or” means “and / or” unless otherwise indicated. Thus, unless otherwise indicated, “A or B” means “A and / or B” and encompasses A alone, B alone, and both A and B.

[0019] In addition, spatial relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” etc., may be used herein to facilitate describing the relationship of one element or feature shown in the figures to another (one or more) element or (one or more) feature, but do not imply a fixed orientation. Spatial relative terms are intended to cover different orientations in addition to the orientation depicted in the figures.

[0020] Furthermore, “(one or more) source / drain” may refer to the source or the drain individually or jointly, depending on the context.

[0021] In some embodiments, a transistor includes a gate structure adjacent to a channel region; source and drain regions adjacent to the channel region; a gate contact connected to the gate structure; and a source / drain contact connected to the source / drain region. In some embodiments, the gate structure includes a conductive (i.e., electrically conductive) fill material (i.e., conductive material) at least partially surrounded by a work function (WF) layer, wherein the conductive fill material and the work function layer are separated from the channel region by a gate dielectric layer. In some embodiments, insulating (i.e., electrically insulating) gate spacers are disposed on the sidewalls of the gate dielectric layer and / or the gate structure. In some embodiments, the gate spacers are surrounded by a dielectric layer. In some embodiments, the dielectric layer includes an interlayer dielectric (ILD) layer. In some embodiments, the gate structure has an insulating layer thereon. In some embodiments, the gate structure has an upper portion and a lower portion, and the upper portion of the gate structure is wider than the lower portion of the gate structure and overhangs the gate spacers. In some embodiments, the conductive fill material has an upper portion and a lower portion, and the upper portion of the conductive fill material is wider than the lower portion of the conductive fill material. The design of the transistor helps to achieve fine-tuning of the profile of the gate structure to reduce the gate resistance (Rg), and helps to achieve devices with large pitch, but provides higher speed compared to other methods.

[0022] Figure 1 is a flowchart of operations in a method of manufacturing a semiconductor device according to some embodiments, and Figures 2A to 2G is a cross-sectional view of a transistor structure at various stages in a manufacturing process according to some embodiments.

[0023] Figure 1 The operations in are part of a method 100 of forming a transistor using a post-gate process (e.g., replacement metal gate (RMG) process) according to some embodiments.

[0024] In some embodiments, the transistor includes a field effect transistor (FET). In some embodiments, the transistor includes a metal oxide semiconductor field effect transistor (MOSFET). In some embodiments, the transistor includes a planar transistor, a finFET transistor, etc.

[0025] Reference Figure 1 and Figure 2A , operation 110 includes: forming a dummy gate 270 on the fin 215 of the substrate 210, and forming gate spacers 240 on the sidewalls of the dummy gate 270.

[0026] In some embodiments, the substrate 210 is a semiconductor substrate. In some embodiments, the substrate 210 is a bulk semiconductor substrate, a silicon-on-insulator (SOI) substrate, a semiconductor-on-insulator substrate, etc. In some embodiments, the substrate 210 is doped with an n-type or p-type dopant, or is undoped. In some embodiments, the substrate 210 is a semiconductor wafer or includes a semiconductor wafer, such as a single-crystalline semiconductor wafer, which is a part of a single-crystalline semiconductor ingot. In some embodiments, the substrate 210 includes a buried oxide layer.

[0027] In some embodiments, the fin 215 is a semiconductor material. In some embodiments, the fin 215 has the same material as the uppermost region of the substrate 210. In some embodiments, the semiconductor fin 215 includes silicon. In some embodiments, the transistor is a MOSFET, and a dummy gate is formed on the substrate 210 rather than on the fin 215.

[0028] In some embodiments, the fin 215 is formed by reducing the thickness in the region of the substrate 210 adjacent to the fin 215. In some embodiments, the fin 215 is formed by etching or patterning the substrate 210. In some embodiments, the fin 215 is formed by patterning and etching the substrate 210 using a lithography process, which includes: depositing a layer of photoresist material on the substrate, irradiating or exposing the photoresist material according to a pattern corresponding to the fin 215, developing the photoresist material to remove a part of the photoresist material, and using the remaining photoresist material to protect the underlying part of the substrate 210 during etching. In some embodiments, the fin 215 is formed on the substrate 210 by a growth process (such as an epitaxial growth process).

[0029] In some embodiments, the dummy gate 270 includes polysilicon (also known as polycrystalline silicon or poly-Si or PO) or polysilicon germanium (poly-SiGe). In some embodiments, the dummy gate 270 includes polysilicon. In some embodiments, the dummy gate 270 is formed by depositing a layer (such as a polysilicon layer) and patterning the deposited layer. In some embodiments, the dummy gate is formed as one or more layers of one or more different materials.

[0030] In some embodiments, the gate spacer 240 is formed along the sidewalls of the dummy gate 270 by: depositing a dielectric layer on the substrate 210 to cover the dummy gate 270, and then partially removing the deposited dielectric layer such that the gate spacer 240 remains along the sidewalls of the dummy gate 270.

[0031] In some embodiments, the gate spacer 240 includes a single-layer structure. In some embodiments, the gate spacer 240 includes a multi-layer structure. In some embodiments, the gate spacer 240 includes an insulating material. In some embodiments, the gate spacer 240 includes silicon oxide, SiON, SiCN, SiOC, SiOCN, or SiN, etc.

[0032] In some embodiments, forming the gate spacer 240 includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.

[0033] In some embodiments, partial removal of the deposited dielectric layer is performed using a process including an anisotropic etching operation. In some embodiments, the anisotropic etching operation forms the gate spacer 240 along the sidewalls of the dummy gate 270 by selectively removing the horizontal portions of the dielectric layer relative to the vertical portions of the dielectric layer, such that the etching operation produces a vertically oriented gate spacer 240 along the sidewalls of the dummy gate 270. In some embodiments, the anisotropic etching operation produces an upper portion of the gate spacer 240 having a circular profile that curves toward the dummy gate 270. In some embodiments, the formation of the gate spacer 240 along the sidewalls of the dummy gate 270 does not use a photoresist layer or pattern or lithography operation.

[0034] Reference Figure 1 and Figure 2B , in operation 120, the portion of the fin 215 adjacent to the gate spacer 240 is removed to form a recess 215r for the source / drain region.

[0035] In some embodiments, the gate spacer 240 is used to define the source / drain region (junction) profile. In some embodiments, the gate spacer 240 is used to offset the doped region from the gate structure for forming the source / drain region.

[0036] Reference Figure 2B , the portion of the fin 215 exposed by the dummy gate 270 and the gate spacer 240 is removed or recessed to form a recess 215r along the gate spacer 240.

[0037] In some embodiments, removing the portion of the fin 215 includes: in Figure 2AA photoresist layer or a capping layer (such as an oxide capping layer) is formed on the structure of , the photoresist or capping layer is patterned to have an opening exposing a portion of the fin 215, and an etching process is used to etch the exposed portion of the fin 215. In some embodiments, the fin 215 is etched using a dry etching process. In some embodiments, the etching process is a wet etching process, or a combination of dry and wet etching processes. In some embodiments, removing a portion of the fin 215 includes a photolithography process, which includes: coating a photoresist (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, etc. In some embodiments, removing a portion of the fin 215 includes maskless lithography, electron beam writing, ion beam writing, etc. In some embodiments, removing a portion of the fin 215 includes a nanoimprint process. In some embodiments, a pre-cleaning process is performed using an HF solution, etc. to clean the recess 215r.

[0038] Reference Figure 1 and Figure 2C , in operation 130, after removing a portion of the fin 215 along the gate spacer 240, an epitaxial layer 260 is formed in the recess 215r to form the source / drain regions of the fin 215, and an interlayer dielectric (ILD) layer 250 is formed on the substrate 210 outside the gate spacer 240.

[0039] In some embodiments, the epitaxial layer 260 is formed using one or more epitaxial or epitaxial (epi) processes such that Si features, SiGe features, etc. are formed in a crystalline state at the source / drain regions. In some embodiments, the lattice constant of the epitaxial layer 260 is different from the lattice constant of the fin 215 such that the channel region of the fin 215 is strained or stressed by the epitaxial layer 260. In some embodiments, the strained or stressed channel region helps to improve carrier mobility and enhance device performance. In some embodiments, the epitaxial process includes CVD deposition techniques (such as vapor phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, etc. In some embodiments, the epitaxial process incorporates dopants into the epitaxial layer 260. In some embodiments, the epitaxial process uses gaseous or liquid precursors that interact with the material (such as silicon) of the fin 215 at the source / drain regions. In some embodiments, the strained channel region is implemented to increase carrier mobility and enhance device performance. In some embodiments, the epitaxial layer 260 is doped using a P-type dopant (such as boron or BF2), an N-type dopant (such as phosphorus or arsenic), etc. In some embodiments, a junction implantation process is performed to dope the epitaxial layer 260. In some embodiments, an annealing process (such as rapid thermal annealing (RTA) and / or laser annealing) is performed to activate the epitaxial layer 260.

[0040] In some embodiments, the ILD layer 250 includes an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, SiBN, SiCBN, tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, combinations of the foregoing, and the like. Examples of low-k dielectric materials include fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorocarbon, parylene, benzocyclobutene (BCB), polyimide, and the like. In some embodiments, the ILD layer 250 includes a single layer. In some embodiments, the ILD layer 250 includes multiple layers.

[0041] In some embodiments, the ILD layer 250 is formed by CVD, ALD, spin-on glass (SOG), or the like. In some embodiments, a chemical mechanical planarization (CMP) process is used to planarize the ILD layer 250 and expose the top of the dummy gate 270.

[0042] In Figure 2C , the dummy gate 270 and the gate spacer 240 are on the fin 215, and the dummy gate 270 and the gate spacer 240 have a common bottom that is at approximately the same level as the top of the epitaxial layer 260. The gate spacer 240 is along the sidewalls of the dummy gate 270 and completely covers the sidewalls of the dummy gate 270.

[0043] Reference Figure 1 and Figure 2D , in operation 140, a portion of the dummy gate 270 is removed to form an opening 280, where the gate spacer 240 is on the sides of the opening 280.

[0044] In some embodiments, an etching process (e.g., a wet etching process or a dry etching process) is used to partially remove the dummy gate 270, and the etching process selectively removes the material of the dummy gate 270 relative to the material of the gate spacer 240. In some embodiments, the wet etching process employs an etchant including ammonium hydroxide, etc. In some embodiments, a dry etching process or a combination of dry and wet etching processes is used to partially remove the dummy gate 270. In some embodiments, an anisotropic etching operation is used to partially remove the dummy gate 270. In some embodiments, an etching process including a dry etching process using (one or more) reactive gases is used to partially remove the material of the dummy gate 270, and the dry etching process selectively etches the dummy gate material relative to the materials of the gate spacer 240 and the ILD layer 250. In some embodiments, the dummy gate 270 is partially removed without using a mask.

[0045] Reference Figure 1 and Figure 2E, in operation 150, a photoresist pattern PR is formed on the ILD layer 250 to be used as an etching mask. In Figure 2E , the photoresist pattern PR has an opening that exposes the upper surface of the partially removed dummy gate 270, the gate spacer 240, and the region of the ILD layer 250 beyond the outer sidewall 240so of the gate spacer 240.

[0046] In some embodiments, the photoresist pattern PR exposes the upper surfaces of the partially removed dummy gate 270 and the gate spacer 240, and the side boundaries of the opening in the photoresist pattern PR are substantially aligned with the outer sidewall 240so of the gate spacer 240 (see also Figure 4 and Figure 6B for the transistor structure II).

[0047] In some embodiments, the photoresist pattern PR exposes the upper surface of the dummy gate 270, and the side boundaries of the opening in the photoresist pattern PR are closer together than the outer sidewall 240so of the gate spacer 240 (see also Figure 5 and Figure 6C for the transistor structure III).

[0048] Referring to Figure 1 and Figure 2F , in operation 160, the photoresist pattern PR is used as an etching mask in one or more etching processes that remove the remaining portion of the dummy gate 270, a portion of the gate spacer 240, and a portion of the ILD layer 250, thereby creating a stepped opening or a T-shaped trench 290, and removing the photoresist pattern PR.

[0049] In Figure 2F , the T-shaped trench 290 has a wider upper portion 290u and a narrower lower portion 290l.

[0050] In some embodiments, the step at the transition of the upper portion 290u to the lower portion 290l of the T-shaped trench 290 is sharp at the corner 240c of the gate spacer 240. In some embodiments, the step is rounded at the corner 240c due to etching.

[0051] In Figure 2F , the removal of a portion of the gate spacer 240 and a portion of the ILD layer 250 results in the upper portion 290u of the T-shaped trench 290 being defined by the sidewall 250s of the ILD layer 250, where the sidewall 250s of the ILD layer 250 is spaced apart by a distance greater than the outer sidewall 240so of the gate spacer 240, i.e., the ILD layer 250 is laterally removed beyond the outer sidewall 240so of the gate spacer 240 (see also Figure 6Ain the transistor structure I). Thus, the sidewalls 250s of the ILD layer 250 on the sides of the upper portion 290u of the T-shaped trench 290 are spaced apart by a distance greater than the distance between the outer sidewalls 240so of the gate spacers 240.

[0052] In some embodiments, the sidewalls 250s of the ILD layer 250 are spaced apart by the same distance as the distance between the outer sidewalls 240so of the gate spacers 240, i.e., the ILD layer 250 is removed to be aligned with the outer sidewalls 240so of the gate spacers 240 (see Figure 4 and Figure 6B in the transistor structure II). That is, the sidewalls 250s of the ILD layer 250 on the sides of the upper portion 290u of the T-shaped trench 290 are substantially aligned with the outer sidewalls 240so of the gate spacers 240.

[0053] In some embodiments, the sidewalls 250s of the ILD layer 250 are spaced apart by a distance less than the distance between the outer sidewalls 240so of the gate spacers 240 and greater than the distance between the inner sidewalls 240si of the gate spacers 240, while the gate spacers 240 maintain the basic height or the entire height of the T-shaped trench 290 (see Figure 5 and Figure 6C in the transistor structure III, where the height of the gate spacers 240 is such that the gate spacers 240 extend vertically to vertically overlap with an insulating layer (e.g., a self-aligned contact (SAC) layer 235) (i.e., a hypothetical horizontal line passing through one gate spacer 240 also passes through the SAC layer 235)). In this case, a step in the T-shaped trench 290 is formed in the gate spacers 240, corresponding to the step from dimension W10 to dimension W20 in Figure 5 .

[0054] In Figure 2F , using the control of the sidewall removal process, the sidewalls 250s of the ILD layer 250 are formed to be inclined at an angle D1 greater than 90 degrees (where 90 degrees is vertical or parallel to the Z-axis).

[0055] In some embodiments, the sidewalls 250s of the ILD layer 250 are vertical, i.e., such that D1 is substantially 90 degrees (e.g., see Figure 4 ).

[0056] In some embodiments, the photoresist pattern PR together with the remaining portion of the dummy gate 270, a portion of the gate spacers 240, and a portion of the ILD layer 250 are removed. In some embodiments, after removing the remaining portion of the dummy gate 270, a portion of the gate spacers 240, and a portion of the ILD layer 250, the photoresist pattern PR is removed in a separate operation.

[0057] In some embodiments, removing the remaining portion of the dummy gate 270, a portion of the gate spacer 240, and a portion of the ILD layer 250 involves a first operation of removing the remaining portion of the dummy gate 270 and a second operation of removing a portion of the gate spacer 240 and a portion of the ILD layer 250. In some embodiments, the first operation is before the second operation. In some embodiments, the first operation is after the second operation. In some embodiments, removing the remaining portion of the dummy gate 270, a portion of the gate spacer 240, and a portion of the ILD layer 250 is performed using wet etching or isotropic etching. In some embodiments, the first operation and the second operation are performed using different wet etching or isotropic etching chemicals.

[0058] Referring Figure 1 and Figure 2G , in operation 170, a replacement gate is formed. Operation 170 includes sequentially forming a gate dielectric layer 230, a work function layer 225, a fill conductor 220, and a SAC layer 235. In some embodiments, forming the gate dielectric layer 230, the work function layer 225, and the fill conductor 220 are operations included in a metal gate cycle.

[0059] In Figure 2G , a gate dielectric layer 230 is formed on the fin 215.

[0060] In some embodiments, the gate dielectric layer 230 is formed to line Figure 2F the entire T-shaped trench 290, which is formed by removing the remaining portion of the dummy gate 270, a portion of the gate spacer 240, and a portion of the ILD layer 250. In some embodiments, the gate dielectric layer 230 is formed to surround the entire exposed area of the fin 215. In some embodiments, the gate dielectric layer 230 is formed (e.g., patterned) to surround the central portion of the fin 215 and expose a portion of the fin 215.

[0061] In some embodiments, the gate dielectric layer 230 includes one or more layers of insulating material, such as silicon oxide or a high-k material. In some embodiments, the gate dielectric layer 230 includes a multi-layer structure, such as a silicon oxide layer (e.g., as an interface layer) and another high-k material layer. In some embodiments, the gate dielectric layer 230 is a conformal layer. In some embodiments, the thickness of the gate dielectric layer 230 on top of the fin 215 is different from the thickness of the gate dielectric layer 230 on the sidewall of the fin 215.

[0062] In some embodiments, forming the gate dielectric layer 230 includes processes such as thermal oxidation, chemical vapor deposition, sputtering.

[0063] In some embodiments, the gate dielectric layer 230 includes one or more high-k dielectric materials, such as metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, etc. In some embodiments, the gate dielectric layer 230 includes one or more of the following: hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO), tantalum pentoxide (Ta2O5), yttrium oxide (Y2O3), strontium titanate (SrTiO3, STO), barium titanate (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), silicon oxynitride (SiON), etc. In some embodiments, the gate dielectric layer 230 is formed of a material different from that of the ILD layer 250.

[0064] In some embodiments, forming the gate dielectric layer 230 is performed using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, ozone oxidation, a combination of the foregoing, and the like.

[0065] In Figure 2G a work function layer 225 is formed over the gate dielectric layer 230.

[0066] In Figure 2G a lateral extent of the work function layer 225 extends beyond an outer sidewall 240so of the gate spacer 240.

[0067] In some embodiments, the lateral extent of the work function layer 225 is narrower than the outer sidewall 240so of the gate spacer 240, but wider than an inner sidewall 240si of the gate spacer 240 (see, for example, Figure 5 and Figure 6C for the transistor structure III).

[0068] In some embodiments, the work function layer 225 adjusts the threshold voltage of the transistor. In some embodiments, the transistor is a P-type FET (PFET) and includes a P-type work function metal or metal-containing material (such as TiN, TaC, TaN, Co, Ru, Mo, Al, or WN) or silicide (such as ZrSi2, MoSi2, TaSi2, or NiSi2) or other P-type work function layers, or a combination of the foregoing. In some embodiments, the work function layer 225 includes a P-type work function material to provide a desired work function value for the P-type gate of a P-type semiconductor device. In some embodiments, the transistor is an N-type FET (NFET) and includes an N-type work function metal or metal-containing material (such as Ti, Ag, Al, TiAl, TaAl, TaAlC, TaAlN, TaC, TaCN, TaSiN, Mn, or Zr) or other N-type work function layers, or a combination of the foregoing. In some embodiments, the work function layer 225 includes an N-type work function material to provide a desired work function value for the N-type gate of an N-type semiconductor device.

[0069] In some embodiments, the work function layer 225 is a conformal layer having an overall uniform thickness (width). In some embodiments, different portions of the work function layer 225 have different widths.

[0070] In some embodiments, the work function layer 225 is deposited using one or more of the following: atomic layer deposition (ALD), evaporation, sputtering, chemical vapor deposition (CVD), PVD, remote plasma CVD (RPCVD), plasma enhanced CVD (PECVD), metalorganic CVD (MOCVD), electroplating, a combination of the foregoing, etc. In some embodiments, the work function layer 225 is formed by conformal deposition of a work function material. In some embodiments, the work function material is deposited over the entire area of the substrate 210, and then the work function material is removed from the area surrounding the gate structure using a CMP process, and then the work function material is partially removed from the upper inner sidewall of the gate spacer 240 by protecting the lower portion of the work function material (e.g., using a masking material, performing an etching process (such as a back-etching process), and then removing the masking material).

[0071] In Figure 2G , a fill conductor 220 is formed over the work function layer 225.

[0072] In Figure 2G , the fill conductor 220 has a stepped or T-shaped configuration having a wider upper portion 220u (cap) that is connected to a narrower lower portion 220l (tail).

[0073] In some embodiments, the gate dielectric layer 230 and the work function layer 225 are conformal layers that conform to the sidewalls of the T-shaped trench 290 and have a substantially uniform thickness, and a fill conductor 220 is formed in the remaining volume of the T-shaped trench 290 such that the shape and slope of the sidewalls of the T-shaped trench 290 are reflected in the resulting shape and slope of the sidewalls of the fill conductor 220.

[0074] In Figure 2G , the fill conductor 220 overhangs the gate spacer 240, i.e., the width of the upper portion 220u of the fill conductor 220 determined parallel to the X-axis is greater than the distance determined parallel to the X-axis between the inner sidewalls 240si of the gate spacer 240.

[0075] In some embodiments, the fill conductor 220 is wider than that shown in Figure 2G and overhangs the ILD layer 250 above the gate spacer 240, i.e., the lateral extent of the fill conductor 220 extends beyond the outer sidewalls 240so of the gate spacer 240.

[0076] In some embodiments, the fill conductor 220 is formed to the entire height of the ILD layer 250. In some embodiments, an etching process (e.g., a back-etching process) is used to partially remove the fill conductor 220, the work function layer 225, and the gate dielectric layer 230, and an SAC layer 235 is formed in the resulting space.

[0077] In Figure 2G , the lower portion 220l of the fill conductor 220 is present in the lower portion 225l of the work function layer 225. The upper portion 220u of the fill conductor 220 extends laterally over the work function layer 225, which helps increase the contact area between the fill conductor 220 and the work function layer 225 and helps improve (i.e., reduce) the gate resistance Rg.

[0078] In Figure 2G , the fill conductor 220 and the work function layer 225 are laterally bounded by the gate dielectric layer 230. In some embodiments, keeping the lateral extent of the fill conductor 220 and the work function layer 225 within the boundaries of the gate dielectric layer 230 helps reduce gate leakage and avoid short circuits.

[0079] In some embodiments, the fill conductor 220 is formed by filling the region between the inner sidewalls of the work function layer 225 such that the width of the fill conductor is a function of the width of the T-shaped trench 290, the thickness of the gate dielectric layer 230, and the thickness of the work function layer 225.

[0080] In some embodiments, the fill conductor 220 includes one or more layers of conductive metal or metal-containing material(s). In some embodiments, the fill conductor 220 is or includes the following: tungsten, aluminum, copper, etc. In some embodiments, the fill conductor 220 is primarily tungsten. In some embodiments, the material of the fill conductor 220 is more conductive than the material of the work function layer 225.

[0081] In some embodiments, forming the fill conductor 220 includes a deposition process (such as CVD, PVD, ALD, etc.), and after this deposition process, a CMP process is used to remove the excess fill conductor 220 that spills out of the T-shaped trench 290.

[0082] In some embodiments, the top of the fill conductor 220 is processed to be recessed. In some embodiments, an etchant that is highly selective between the fill conductor 220 and the gate spacer 240 is used to recess the top of the fill conductor 220. In some embodiments, the top of the fill conductor 220 and the top of the work function layer 225 are processed to be recessed. In some embodiments, the top of the fill conductor 220, the top of the work function layer 225, and the top of the gate dielectric layer 230 are processed to be recessed. In some embodiments, a metal gate etch-back (MGEB) process is used to recess the top of the gate structure and the gate dielectric layer 230. In some embodiments, the metal gate etch-back process includes a plasma etching process that employs one or more etchants, such as fluorine-containing gases (e.g., one or more of CF4, SF6, CH2F2, CHF3, or C2F6) and / or chlorine-containing gases (e.g., one or more of Cl2, CHCl3, CCl4, BCl3, or SCl4).

[0083] In Figure 2G a SAC layer 235 is formed over the recessed fill conductor 220, work function layer 225, and gate dielectric layer 230.

[0084] In Figure 2G a SAC layer 235 is formed to the entire width of the fill conductor 220, work function layer 225, and gate dielectric layer 230, i.e., the SAC layer 235 covers all of the fill conductor 220, work function layer 225, and gate dielectric layer 230.

[0085] In Figure 2G a SAC layer 235 horizontally overlaps with the gate spacer 240. In other words, an imaginary vertical line passing through a gate spacer 240 also passes through the SAC layer 235.

[0086] In some embodiments, the SAC layer 235 includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, a low dielectric constant dielectric material, and the like. In some embodiments, the SAC layer 235 includes silicon nitride.

[0087] In some embodiments, the SAC layer 235 is formed using a deposition process (such as ALD, CVD, PVD, etc.). In some embodiments, after the deposition process, a CMP process is performed to remove the portion of the SAC layer 235 that extends over the ILD layer 250.

[0088] Reference Figure 1 and Figure 2H , in operation 180, the resulting structures of operation 170 and Figure 2G are processed to form source / drain (S / D) contacts that contact the epitaxial layer 260 adjacent to the gate.

[0089] Figure 3A is a diagram of a transistor structure with annotations showing various dimensions and angles. Figure 2G of

[0090] In Figure 3A , the width (dimension W1) of the upper portion of the gate structure is greater than the width (dimension W2) of the lower portion of the gate structure (i.e., W1 > W2). In some embodiments, this structure allows the fill conductor 220 to have a larger width and helps to reduce the gate resistance Rg while maintaining device performance. Compared with the case where the entire gate structure has a width of W2, W1 > W2 provides a relatively larger number of fill conductors 220. In some embodiments, the gate resistance Rg decreases as the width W1 increases. In some embodiments, the increase in W1 is limited by the need to avoid the gate structure getting too close to adjacent structures (such as contacts). In some embodiments, the relationship between W1 and W2 determines the process window.

[0091] In Figure 3A , the upper portion of the gate structure overhangs the gate spacer 240 by at least a dimension DM-04. In some embodiments, DM-04 is small enough to avoid the gate structure getting too close to adjacent structures, such as avoiding bridging to the source / drain contacts.

[0092] In Figure 3A , the fin 215 has sidewalls that are aligned with the outer sidewalls of the gate spacer 240.

[0093] In some embodiments, the gate spacer 240 has a lateral extent (dimension DM-40) that is less than the lateral extent of the sidewall of the fin 215, such that the fin 215 is wider than the dimension DM-40. In some embodiments, the gate spacer 240 has a lateral extent that is greater than the lateral extent of the sidewall of the fin 215, such that the fin 215 is narrower than the dimension DM-40, and the gate spacer 240 laterally overhangs beyond the sidewall of the fin 215.

[0094] In Figure 3A , the upper portion 225u of the work function layer 225 has a lateral dimension (dimension DM-06) that is greater than the lateral extent of the gate spacer 240 (dimension DM-40).

[0095] In Figure 3A , the upper portion 220u of the fill conductor 220 has a lateral dimension (dimension DM-03) that is greater than the lateral extent of the lower portion 220l of the fill conductor 220 (dimension DM-09). In other words, the upper portion 220u of the fill conductor 220 is wider than the lower portion 220l of the fill conductor. As used herein, "wider" refers to a dimension determined parallel to the X-axis. Relative to a structure in which the fill conductor 220 has a single width throughout its width (e.g., having a width DM-09 throughout the height of the fill conductor 220), the wider upper portion 220u of the fill conductor 220 makes it easier to form the lower portion 220l by effectively reducing the aspect ratio of the fill conductor 220 as a whole, and helps to reduce the gate resistance (Rg).

[0096] In some embodiments, the width (dimension DM-09) of the lower portion 220l of the fill conductor 220 is substantially constant as the distance from the substrate increases.

[0097] In some embodiments, the upper portion 220u of the fill conductor 220 is wider than the lower portion 220l of the fill conductor by a substantial length or the entire length of the gate structure, i.e., Figure 3A the length in the Y-axis direction (into / out of the page).

[0098] In some embodiments, the ratio of the width of the upper portion 220u of the fill conductor 220 to the width of the lower portion 220l of the fill conductor 220 (DM-03:DM-09) is substantially equal to the ratio of the width of the upper portion of the gate structure to the width of the lower portion of the gate structure (W1:W2).

[0099] In Figure 3A , the sidewall angle of the upper portion 220u of the fill conductor 220 is angle D5.

[0100] In some embodiments, angles D1 and D5 are equal to each other, the width of the upper portion 220u of the fill conductor is a constant fraction of the width W1 of the upper portion of the gate structure, and the cross-sectional shape of the fill conductor 220 in the X-Z plane corresponds to (but is smaller than) the cross-sectional shape of the gate structure in the X-Z plane. Increasing the widths of the upper portion of the gate structure and the upper portion 220u of the fill conductor (i.e., increasing W1 and DM-03) increases the number and surface area of the fill conductors 220 and helps to reduce the gate resistance Rg.

[0101] In Figure 3A , the upper portion 220u of the fill conductor 220 has a lateral dimension (dimension DM-03) that is greater than the distance between the inner sidewalls 240si of the gate spacers 240 (see dimension W2). In other words, the upper portion 220u of the fill conductor 220 is wider than the width W2 of the lower portion of the gate structure (i.e., wider than the distance between the inner sidewalls 240si of the gate spacers 240), and the upper portion 220u of the fill conductor 220 overhangs the inner sidewalls 240si of the gate spacers 240.

[0102] In some embodiments, the upper portion 220u of the fill conductor 220 has a lateral dimension (e.g., dimension DM-03 at the bottom of the upper portion 220u or dimension DM-31 at the top of the upper portion 220u) that is greater than the distance (dimension DM-40) between the outer sidewalls 240so of the gate spacers 240.

[0103] In some embodiments, the upper portion 220u of the fill conductor 220 has a lateral dimension (DM-03) that is greater than the lateral extent (dimension DM-09) of the lower portion 220l but less than the distance between the inner sidewalls 240si of the gate spacers 240 (e.g., see Figure 4 and Figure 5 ).

[0104] In Figure 3A , the width of the upper portion 220u of the fill conductor 220 transitions to the width of the lower portion 220l of the fill conductor 220 in a stepped manner, i.e., there is a step from dimension DM-03 to dimension DM-09.

[0105] In some embodiments, the step in the fill conductor 220 is circular. In some embodiments, the width of the upper portion 220u of the fill conductor 220 transitions gradually or continuously to the width of the lower portion 220l of the fill conductor 220.

[0106] In Figure 3A , the overall or outer width of the upper portion 225u of the work function layer 225 transitions to the overall or outer width of the lower portion 225l of the work function layer 225 in a stepped manner, i.e., there is a step from dimension DM-06 to dimension DM-50.

[0107] In some embodiments, the steps in the work function layer 225 are circular. In some embodiments, the overall or outer width of the upper portion 225u of the work function layer 225 transitions to the overall or outer width of the lower portion 225l of the work function layer 225 in a curved step manner, i.e., there is a curved step from dimension DM-06 to dimension DM-50. For example, the upper inner corner 240c of the gate spacer 240 is circular, e.g., due to being made circular during an etching operation. In some embodiments, the overall or outer width of the upper portion 225u of the work function layer 225 gradually or continuously transitions to the overall or outer width of the lower portion 225l of the work function layer 225.

[0108] In Figure 3A , the height of the lower portion of the gate structure (dimension H2) and the total height of the gate structure having the SAC layer 235 (see dimension H1) satisfy the relation H2 / H1 ≥ 1 / 3. In some embodiments, maintaining H2 ≥ H1*1 / 3 helps to provide high device performance.

[0109] In Figure 3A , the angle D1 of the sidewall 250s of the ILD layer 250 satisfies the relation 120 degrees ≥ D1 ≥ 90 degrees. The relation D1 > 90 degrees allows the upper surface width (dimension DM-31) of the upper portion 220u of the fill conductor 220 to be greater than the lower surface width (dimension DM-03) of the upper portion 220u of the fill conductor 220, and simplifies the formation of the fill conductor 220. The relation D1 ≤ 120 degrees helps to maintain the distance between the gate structure and adjacent structures (e.g., source / drain contacts) (e.g., see Figure 2H ) showing the source / drain contacts).

[0110] In Figure 3A , the sidewall angle (angle D5) of the upper portion 220u of the fill conductor 220 satisfies the relation 120 degrees ≥ D5 ≥ 90 degrees. In some embodiments, 120 degrees ≥ D5 ≥ 90 degrees simplifies the formation (e.g., filling) of the fill conductor 220. In Figure 3A , D1 = D5.

[0111] In Figure 3A , D1 > 90 degrees, which makes DM-01 > DM-06, i.e., the upper portion 225u of the work function layer 225 becomes wider as the distance from the substrate increases (as determined parallel to the X-axis). Further, D5 > 90 degrees results in DM-31 > DM-03, and the upper portion 220u of the fill conductor 220 becomes wider as the distance from the substrate increases (as determined parallel to the X-axis).

[0112] In Figure 3A , the gate spacer 240 has a height (DM-10) corresponding to the height (H2) of the lower portion of the gate structure.

[0113] Figure 3B a transistor structure having annotations showing overlapping features Figure 2G diagram.

[0114] In Figure 3B , the upper portion 220u of the fill conductor 220 is wider than the distance between the inner sidewalls 240si of the gate spacers 240, such that the upper portion 220u of the fill conductor 220 overhangs the gate spacers 240. In other words, a first imaginary vertical line ln_a passes through the upper portion 220u of the fill conductor 220 and one of the gate spacers 240 (it should be understood that in the case where the gate structure has mirror symmetry, the same is true for the opposite side of the gate structure). In this document, "vertical" refers to an element parallel to the Z-axis.

[0115] In Figure 3B , the work function layer 225 also overhangs the gate spacers 240. In other words, a second imaginary vertical line ln_b passes through the upper portion 225u of the work function layer 225 and one of the gate spacers 240 (it should be understood that in the case where the gate structure has mirror symmetry, the same is true for the opposite side of the gate structure).

[0116] In Figure 3B , the work function layer 225 overhangs the ILD layer 250. In other words, a third imaginary vertical line ln_c passes through the upper portion 225u of the work function layer 225 and the ILD layer 250 (it should be understood that in the case where the gate structure has mirror symmetry, the same is true for the opposite side of the gate structure).

[0117] Figure 4 is a diagram of a transistor structure according to some embodiments.

[0118] Figure 4 is a diagram of a transistor structure according to some embodiments, which is generally corresponding to the transistor structures of Figure 2G , Figure 3A and Figure 3B , but has a vertical side aligned with the outer sidewall 240so of the gate spacer 240. Elements not explicitly described in conjunction with Figure 4 are assumed to be substantially the same as the elements described above in conjunction with Figure 2G , Figure 3A and Figure 3B .

[0119] In Figure 4 , the total width W10 of the upper portion of the gate structure is substantially equal to the total width of the lower portion of the gate structure including the gate spacers 240. Thus, in Figure 4 , W10 = W2 + 2*W3.

[0120] In Figure 4 , the sidewalls 250s of the ILD layer 250 and the sides of the upper portion 220u of the fill conductor 220 are vertical, i.e., having angles D1 and D5 that are substantially equal to 90 degrees. In Figure 3A , D1 = D5.

[0121] In some embodiments, D1 and D5 are equal to each other and satisfy the relationship 120 degrees ≥ D1 ≥ 90 degrees and 120 degrees ≥ D5 ≥ 90 degrees.

[0122] In Figure 4 , the width of the upper portion 220u of the fill conductor 220 is less than the distance between the inner sidewalls 240si of the gate spacers 240. In other words, an imaginary vertical line passing through the upper portion 220u of the fill conductor 220 does not pass through a gate spacer 240.

[0123] In some embodiments, the upper portion 225u of the work function layer 225 is made relatively thin and the upper portion 220u of the fill conductor 220 is made correspondingly larger, e.g., such that an imaginary vertical line passes through the upper portion 220u of the fill conductor 220 and a gate spacer 240 (see the imaginary line ln_a in Figure 3B ).

[0124] In Figure 4 , the upper portion 220u of the fill conductor 220 is wider than the lower portion 220l of the fill conductor, which makes it easier to form the lower portion 220l and helps to reduce the gate resistance Rg while maintaining device performance.

[0125] In Figure 4 , the gate spacers 240 have a height corresponding to the height of the lower portion of the gate structure (dimension DM-10), i.e., the gate spacers 240 are not the entire height of the gate structure. In some embodiments, the height of the gate spacers 240 is less than the entire height of the gate structure, which simplifies the fabrication of the gate by allowing a greater variation in the etching characteristics, due to the generally larger thickness of the gate spacers 240.

[0126] Figure 5 is a diagram of a transistor structure according to some embodiments.

[0127] Figure 5 is a diagram of a transistor structure in which the outer sidewalls of the upper portion of the gate structure are closer together compared to the outer sidewalls 240so of the gate spacers 240, but are farther apart compared to the inner sidewalls 240si of the gate spacers 240. Elements not explicitly described are assumed to be substantially the same as the elements described above in connection with Figure 5 and Figure 3B and Figure 4 .

[0128] InFigure 5 In [reference], the side surface of the upper portion 220u of the fill conductor 220 is vertical, that is, the angle D5 is substantially equal to 90 degrees. In addition, the gate spacer 240 has a substantially square step therein, such that the angle D10 enclosed by the step is substantially equal to 90 degrees. In Figure 5 [reference], D10 = D5.

[0129] In some embodiments, D10 and D5 are equal to each other and satisfy the relations 120 degrees ≥ D10 ≥ 90 degrees and 120 degrees ≥ D5 ≥ 90 degrees.

[0130] In Figure 5 [reference], the upper portion 220u of the fill conductor 220 has a width smaller than the distance between the inner sidewalls 240si of the gate spacer 240. In other words, an imaginary vertical line passing through the upper portion 220u of the fill conductor 220 does not pass through a gate spacer 240.

[0131] In some embodiments, the upper portion 225u of the work function layer 225 is made relatively thin, and the upper portion 220u of the fill conductor 220 is made correspondingly larger, for example, such that the imaginary vertical line passes through the upper portion 220u of the fill conductor 220 and a gate spacer 240 (see the imaginary line ln_a in Figure 3B [reference]).

[0132] In Figure 5 [reference], the upper portion 220u of the fill conductor 220 is wider than the lower portion 220l of the fill conductor, which makes it easier to form the lower portion 220l and helps reduce the gate resistance Rg while maintaining the device performance.

[0133] In Figure 5 [reference], the gate spacer 240 has a height sufficient to substantially cover the entire height of the gate structure. Accordingly, the entirety of the gate dielectric layer 230 is separated from the surrounding ILD layer 250 by the gate spacer 240. In some embodiments, separating the entirety of the gate dielectric layer 230 from the surrounding ILD layer 250 by the gate spacer 240 helps improve the insulation of the gate.

[0134] Figures 6A to 6C is a cross-sectional view of a transistor structure according to some embodiments.

[0135] Figures 6A to 6C Includes three photoresist patterns PR and three corresponding transistor structures.

[0136] Figure 6A The photoresist pattern PR of Figure 2E corresponds to the photoresist pattern PR previously described in

[0137] Figure 6AThe photoresist pattern PR in has an opening, and the side boundaries of the opening are spaced apart by a distance dI (determined parallel to the X-axis). Figure 6B The photoresist pattern PR in has an opening, and the side boundaries of the opening are spaced apart by a distance dII. Figure 6B The side boundaries of the opening in the photoresist pattern PR in are substantially aligned with the outer sidewalls of the gate spacers 240. Figure 6C The photoresist pattern PR in has an opening, and the side boundaries of the opening are spaced apart by a distance dIII, where the distance dIII is less than the distance dII.

[0138] Figure 6A The photoresist pattern PR in is used to form a transistor structure I, where the upper part of the gate structure is wider than the outer sidewalls 240so of the gate spacers 240. Figure 6B The photoresist pattern PR in is used to form a transistor structure II, where the upper part of the gate structure has the same width as the outer sidewalls 240so of the gate spacers 240. Figure 6C The photoresist pattern PR in is used to form a transistor structure III, where the upper part of the gate structure is narrower than the outer sidewalls 240so of the gate spacers 240 but wider than the inner sidewalls 240si of the gate spacers 240.

[0139] In some embodiments of the transistor structure I, the upper part 225u of the work function layer 225 is wider than the outer sidewalls 240so of the gate spacers 240. In some embodiments of the transistor structure I, the upper part 220u of the fill conductor 220 is wider than the outer sidewalls 240so of the gate spacers 240.

[0140] In some embodiments of the transistor structure II, the upper part 225u of the work function layer 225 is wider than the inner sidewalls 240si of the gate spacers 240. In some embodiments of the transistor structure II, the upper part 220u of the fill conductor 220 is wider than the inner sidewalls 240si of the gate spacers 240.

[0141] In some embodiments of the transistor structure III, the upper part 225u of the work function layer 225 is wider than the inner sidewalls 240si of the gate spacers 240. In some embodiments of the transistor structure III, the upper part 220u of the fill conductor 220 is wider than the inner sidewalls 240si of the gate spacers 240.

[0142] In transistor structures I and II, 120 degrees ≥ D1 ≥ 90 degrees, and in transistor structure III, 120 degrees ≥ D10 ≥ 90 degrees. Keeping the angles D1 and D10 at 120 degrees or below helps avoid problems with adjacent structures, such as helping to avoid bridging with adjacent contacts (such as source / drain contacts). Keeping the angles D1 and D10 at 90 degrees or above helps with the filling of the fill conductor 220.

[0143] In transistor structures I, II, and III, the SAC layer 235 overlaps the gate spacer 240. In other words, an imaginary vertical line passing through one gate spacer 240 also passes through the SAC layer 235.

[0144] In some embodiments, a method of manufacturing a semiconductor device includes: forming a dummy gate and gate spacers on a semiconductor region of a substrate; forming an interlayer dielectric layer along sidewalls of the gate spacers; forming a trench having a lower portion and an upper portion, the upper portion of the trench being wider than the lower portion of the trench, forming the trench including: removing a portion of the gate spacers, and removing the dummy gate; and forming a gate structure in the trench. The gate structure has a lower portion and an upper portion, the upper portion of the gate structure is in the upper portion of the trench, the lower portion of the gate structure is in the lower portion of the trench, and the upper portion of the gate structure is wider than the lower portion of the gate structure. A first gate spacer in the gate spacers has a first inner sidewall facing a first side of the lower portion of the gate structure, and a second gate spacer in the gate spacers has a second inner sidewall facing a second side of the lower portion of the gate structure. The first inner sidewall and the second inner sidewall are spaced apart by a first distance, and the upper portion of the gate structure has a width greater than the first distance. In some embodiments, forming the trench includes: removing a portion of the interlayer dielectric layer, sidewalls of the upper portion of the trench being defined by sidewalls of the interlayer dielectric layer, and a minimum spacing of the sidewalls being greater than a distance between outer sides of the gate spacers. In some embodiments, forming the trench includes: performing at least one etching operation to remove the portion of the interlayer dielectric layer, the portion of the gate spacers, and the dummy gate, and the portion of the interlayer dielectric layer being etched such that the upper portion of the trench is wider than the distance between outer sides of the gate spacers. In some embodiments, forming the trench includes: forming the sidewalls to have an angle D1 in a range from 90 degrees to 120 degrees with respect to a main plane of the substrate surface. In some embodiments, the upper portion of the gate structure is formed to have sidewalls having an angle D1 with respect to the main plane of the substrate surface. In some embodiments, D1 is greater than 90 degrees. In some embodiments, the method further includes: forming an insulating layer on top of the gate structure, and the gate spacers have a height that is at least 1 / 3 of a total distance from a bottom of the gate spacers to a top of the insulating layer. In some embodiments, forming the trench includes: removing a portion of the interlayer dielectric layer, sidewalls of the upper portion of the trench being defined by sidewalls of the interlayer dielectric layer, and a minimum spacing of the sidewalls being substantially the same as the distance between outer sides of the gate spacers. In some embodiments, forming the trench includes: performing at least one etching operation to remove the portion of the interlayer dielectric layer, the portion of the gate spacers, and the dummy gate, and the portion of the interlayer dielectric layer being etched such that sidewalls of the interlayer dielectric layer in the upper portion of the trench are substantially aligned with outer sides of the gate spacers. In some embodiments, the method further includes: forming an insulating layer on top of the gate structure, and the gate spacers have a height that is at least 1 / 3 of a total distance from a bottom of the gate spacers to a top of the insulating layer. In some embodiments, forming the trench includes: making an upper portion of the gate spacers narrower, and sidewalls of the upper portion of the trench being defined by sidewalls of the upper portion of the gate spacers.In some embodiments, forming the trench includes: performing at least one etching operation to remove the portion of the gate spacer and the dummy gate, and the gate spacer is etched such that the sidewalls of the upper portion of the trench are aligned with the points between the inner and outer sides of the gate spacer. In some embodiments, the gate structure includes a fill conductor, the fill conductor is formed to have a lower portion and an upper portion, the upper portion of the fill conductor is in the upper portion of the trench, the lower portion of the fill conductor is in the lower portion of the trench, and the upper portion of the fill conductor is wider than the lower portion of the fill conductor. In some embodiments, forming the gate structure includes: forming a gate dielectric layer, the gate dielectric layer is formed to have a substantially uniform first thickness; forming a work function layer on the gate dielectric layer, the work function layer is formed to have a substantially uniform second thickness; and forming a fill conductor on the work function layer, the fill conductor is formed to fill the remaining portion of the trench not occupied by the gate dielectric layer and the work function layer, and the fill conductor has a higher conductivity than the work function layer.

[0145] In some embodiments, a semiconductor device includes: a semiconductor region having a channel region therein; a gate structure adjacent to the channel region; a first gate spacer on a first side of the gate structure and a second gate spacer on a second side of the gate structure; and an interlayer dielectric layer along the sidewalls of the first gate spacer and the second gate spacer. The gate structure has a lower portion and an upper portion, the upper portion of the gate structure is wider than the lower portion of the gate structure, the first gate spacer has a first inner sidewall facing the first side of the lower portion of the gate structure, and the second gate spacer has a second inner sidewall facing the second side of the lower portion of the gate structure, the first inner sidewall is spaced apart from the second inner sidewall by a first distance, and the width of the upper portion of the gate structure is greater than the first distance. In some embodiments, the width of the upper portion of the gate structure is greater than the distance between the outer sidewalls of the first gate spacer and the second gate spacer. In some embodiments, the width of the upper portion of the gate structure is substantially the same as the distance between the outer sidewalls of the first gate spacer and the second gate spacer. In some embodiments, each of the first gate spacer and the second gate spacer has a wider bottom and a narrower top, with a substantially horizontal step therebetween, and the outer sidewalls of the upper portion of the gate structure contact the inner sidewalls of the tops of the first gate spacer and the second gate spacer. In some embodiments, the semiconductor device further includes an insulating layer on top of the gate structure, and the height of the first gate spacer and the second gate spacer is at least 1 / 3 of the total distance from the bottoms of the first gate spacer and the second gate spacer to the top of the insulating layer.

[0146] In some embodiments, a semiconductor device includes a semiconductor region; a gate structure; an insulating layer of a dielectric material that contacts a top of the gate structure and extends across an entire width of the top of the gate structure; a first gate spacer and a second gate spacer; and an interlayer dielectric layer along sides of the first gate spacer and the second gate spacer. The gate structure has a lower portion and an upper portion, the lower portion extends vertically between the first gate spacer and the second gate spacer and has a first width, and the upper portion extends vertically from the lower portion to the insulating layer and has a second width greater than the first width. The first gate spacer has a first inner sidewall facing a first side of the lower portion of the gate structure, and the second gate spacer has a second inner sidewall facing a second side of the lower portion of the gate structure. The first inner sidewall is spaced from the second inner sidewall by a first distance, and the insulating layer has a width greater than the first distance.

[0147] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

[0148] Example

[0149] Example 1. A method of manufacturing a semiconductor device, the method comprising: forming a dummy gate and gate spacers on a semiconductor region of a substrate; forming an interlayer dielectric layer along sides of the gate spacers; forming a trench having a lower portion and an upper portion, the upper portion of the trench being wider than the lower portion of the trench, forming the trench including: removing a portion of the gate spacers, and removing the dummy gate; and forming a gate structure in the trench, wherein: the gate structure has a lower portion and an upper portion, the upper portion of the gate structure is in the upper portion of the trench, the lower portion of the gate structure is in the lower portion of the trench, and the upper portion of the gate structure is wider than the lower portion of the gate structure. The first gate spacer of the gate spacers has a first inner sidewall facing a first side of the lower portion of the gate structure, and the second gate spacer of the gate spacers has a second inner sidewall facing a second side of the lower portion of the gate structure. The first inner sidewall is spaced from the second inner sidewall by a first distance, and the upper portion of the gate structure has a width greater than the first distance.

[0150] Example 2. The method according to Example 1, wherein: forming the trench includes: removing a portion of the interlayer dielectric layer, the side surfaces of the upper portion of the trench being defined by the side walls of the interlayer dielectric layer, and a minimum spacing of the side walls being greater than a distance between outer sides of the gate spacers.

[0151] Example 3. The method according to Example 2, wherein: forming the trench includes: performing at least one etching operation to remove the portion of the interlayer dielectric layer, the portion of the gate spacers, and the dummy gate, and the portion of the interlayer dielectric layer being etched such that an upper portion of the trench is wider than a distance between outer sides of the gate spacers.

[0152] Example 4. The method according to Example 2, wherein forming the trench includes: forming the side walls to have an angle D1 in a range from 90 degrees to 120 degrees with respect to a main plane of a surface of the substrate.

[0153] Example 5. The method according to Example 4, wherein an upper portion of the gate structure is formed to have side surfaces having the angle D1 with respect to the main plane of the surface of the substrate.

[0154] Example 6. The method according to Example 5, wherein D1 is greater than 90 degrees.

[0155] Example 7. The method according to Example 2, further comprising: forming an insulating layer on a top of the gate structure, wherein a height of the gate spacers is at least 1 / 3 of a total distance from a bottom of the gate spacers to a top of the insulating layer.

[0156] Example 8. The method according to Example 1, wherein: forming the trench includes: removing a portion of the interlayer dielectric layer, the side surfaces of the upper portion of the trench being defined by the side walls of the interlayer dielectric layer, and a minimum spacing of the side walls being substantially the same as a distance between outer sides of the gate spacers.

[0157] Example 9. The method according to Example 8, wherein: forming the trench includes: performing at least one etching operation to remove the portion of the interlayer dielectric layer, the portion of the gate spacers, and the dummy gate, and the portion of the interlayer dielectric layer being etched such that side walls of the interlayer dielectric layer in an upper portion of the trench are substantially aligned with outer sides of the gate spacers.

[0158] Example 10. The method according to Example 8, further comprising: forming an insulating layer on a top of the gate structure, wherein a height of the gate spacers is at least 1 / 3 of a total distance from a bottom of the gate spacers to a top of the insulating layer.

[0159] Example 11. The method according to Example 1, wherein: forming the trench includes: making the upper part of the gate spacer narrower, and the side surfaces of the upper part of the trench are defined by the side walls of the upper part of the gate spacer.

[0160] Example 12. The method according to Example 11, wherein: forming the trench includes: performing at least one etching operation to remove this part of the gate spacer and the dummy gate, and the gate spacer is etched such that the side walls of the upper part of the trench are aligned with the point between the inner and outer sides of the gate spacer.

[0161] Example 13. The method according to Example 1, wherein: the gate structure includes a filling conductor, the filling conductor is formed to have a lower part and an upper part, the upper part of the filling conductor is in the upper part of the trench, the lower part of the filling conductor is in the lower part of the trench, and the upper part of the filling conductor is wider than the lower part of the filling conductor.

[0162] Example 14. The method according to Example 1, wherein forming the gate structure includes: forming a gate dielectric layer, the gate dielectric layer is formed to have a substantially uniform first thickness; forming a work function layer on the gate dielectric layer, the work function layer is formed to have a substantially uniform second thickness; and forming a filling conductor on the work function layer, the filling conductor is formed to fill the remaining part of the trench not occupied by the gate dielectric layer and the work function layer, and the filling conductor has a greater conductivity than the work function layer.

[0163] Example 15. A semiconductor device, comprising: a semiconductor region having a channel region therein; a gate structure adjacent to the channel region; a first gate spacer and a second gate spacer, the first gate spacer is located on a first side of the gate structure, the second gate spacer is located on a second side of the gate structure; and an interlayer dielectric layer along the side surfaces of the first spacer and the second gate spacer, wherein: the gate structure has a lower part and an upper part, the width of the upper part of the gate structure is different from the width of the lower part of the gate structure, the first gate spacer has a first inner side wall facing the first side of the lower part of the gate structure, and the second gate spacer has a second inner side wall facing the second side of the lower part of the gate structure, the first inner side wall is spaced apart from the second inner side wall by a first distance, and the width of the upper part of the gate structure is greater than the first distance.

[0164] Example 16. The semiconductor device according to Example 15, wherein the width of the upper part of the gate structure is greater than the distance between the outer side walls of the first gate spacer and the second gate spacer.

[0165] Example 17. The semiconductor device according to Example 15, wherein an upper portion of the gate structure has a width substantially the same as a distance between outer sidewalls of the first gate spacer and the second gate spacer.

[0166] Example 18. The semiconductor device according to Example 15, wherein: each of the first gate spacer and the second gate spacer has a wider bottom and a narrower top, with a substantially horizontal step therebetween, and an outer sidewall of an upper portion of the gate structure contacts inner sidewalls of tops of the first gate spacer and the second gate spacer.

[0167] Example 19. The semiconductor device according to Example 15, further comprising an insulating layer on a top of the gate structure, wherein the first gate spacer and the second gate spacer have a height that is at least 1 / 3 of a total distance from bottoms of the first gate spacer and the second gate spacer to a top of the insulating layer.

[0168] Example 20. A semiconductor device, comprising: a semiconductor region; a gate structure located on the semiconductor region; an insulating layer of a dielectric material contacting a top of the gate structure and extending across an entire width of the top of the gate structure; a first gate spacer and a second gate spacer; and an interlayer dielectric layer along sides of the first spacer and the second gate spacer, wherein: the gate structure has a lower portion and an upper portion, the lower portion vertically extends between the first spacer and the second spacer and has a first width, and the upper portion vertically extends from the lower portion to the insulating layer and has a second width greater than the first width, the first gate spacer has a first inner sidewall facing a first side of the lower portion of the gate structure, and the second gate spacer has a second inner sidewall facing a second side of the lower portion of the gate structure, the first inner sidewall is spaced apart from the second inner sidewall by a first distance, and the insulating layer has a width greater than the first distance.

Claims

1. A method of manufacturing a semiconductor device, the method comprising: Forming a dummy gate and gate spacers on a semiconductor region of a substrate; Forming an interlayer dielectric layer along sides of the gate spacers; Forming a trench having a lower portion and an upper portion, the upper portion of the trench being wider than the lower portion of the trench, forming the trench comprising: Removing a portion of the gate spacers, and Removing the dummy gate; and Forming a gate structure in the trench, wherein: The gate structure has a lower portion and an upper portion, the upper portion of the gate structure is in the upper portion of the trench, the lower portion of the gate structure is in the lower portion of the trench, and the upper portion of the gate structure is wider than the lower portion of the gate structure, A first gate spacer of the gate spacers has a first inner sidewall facing a first side of the lower portion of the gate structure, and a second gate spacer of the gate spacers has a second inner sidewall facing a second side of the lower portion of the gate structure, the first inner sidewall being spaced apart from the second inner sidewall by a first distance, and The upper portion of the gate structure has a width greater than the first distance.

2. The method according to claim 1, wherein: Forming the trench comprises: removing a portion of the interlayer dielectric layer, Sides of the upper portion of the trench are defined by sidewalls of the interlayer dielectric layer, and A minimum spacing of the sidewalls is greater than a distance between outer sides of the gate spacers.

3. The method according to claim 2, wherein: Forming the trench comprises: performing at least one etching operation to remove the portion of the interlayer dielectric layer, the portion of the gate spacers, and the dummy gate, and The portion of the interlayer dielectric layer is etched such that the upper portion of the trench is wider than the distance between outer sides of the gate spacers.

4. The method according to claim 2, wherein Forming the trench comprises: forming the sidewalls to have an angle D1 in a range from 90 degrees to 120 degrees with respect to a main plane of a surface of the substrate.

5. The method according to claim 4, wherein, The upper portion of the gate structure is formed to have sidewalls having the angle D1 with respect to the main plane of the surface of the substrate.

6. The method according to claim 5, wherein, D1 is greater than 90 degrees.

7. The method according to claim 2 further comprises: Forming an insulating layer on top of the gate structure, Wherein, a height of the gate spacers is at least 1 / 3 of a total distance from a bottom of the gate spacers to a top of the insulating layer.

8. The method according to claim 1, wherein: Forming the trench comprises: removing a portion of the interlayer dielectric layer, Sides of the upper portion of the trench are defined by sidewalls of the interlayer dielectric layer, and A minimum spacing of the sidewalls is substantially the same as the distance between outer sides of the gate spacers.

9. A semiconductor device, comprising: A semiconductor region having a channel region therein; A gate structure adjacent to the channel region; A first gate spacer and a second gate spacer, the first gate spacer being located on a first side of the gate structure, the second gate spacer being located on a second side of the gate structure; And An interlayer dielectric layer along sides of the first spacer and the second gate spacer, wherein: The gate structure has a lower part and an upper part, and the width of the upper part of the gate structure is different from the width of the lower part of the gate structure. The first gate spacer has a first inner sidewall facing the first side of the lower part of the gate structure, and the second gate spacer has a second inner sidewall facing the second side of the lower part of the gate structure. The first inner sidewall is spaced apart from the second inner sidewall by a first distance, and the upper part of the gate structure has a width greater than the first distance.

10. A semiconductor device, comprising: a semiconductor region; a gate structure located on the semiconductor region; an insulating layer of a dielectric material, contacting the top of the gate structure and extending over the entire width of the top of the gate structure; a first gate spacer and a second gate spacer; and an interlayer dielectric layer along the sides of the first spacer and the second gate spacer, wherein: the gate structure has a lower part and an upper part, the lower part vertically extends between the first spacer and the second gate spacer and has a first width, and the upper part vertically extends from the lower part to the insulating layer and has a second width greater than the first width, the first gate spacer has a first inner sidewall facing the first side of the lower part of the gate structure, and the second gate spacer has a second inner sidewall facing the second side of the lower part of the gate structure. The first inner sidewall is spaced apart from the second inner sidewall by a first distance, and the insulating layer has a width greater than the first distance.

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