Source region embedded heteroepitaxy power mosfet device and manufacturing method thereof
By embedding a source region with heterojunction epitaxy in power MOSFETs to induce stress on the silicon channel, the mobility of charge carriers is enhanced, addressing the mobility degradation issue and reducing on-state resistance.
Patent Information
- Application Number
- CN202510386349.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2025-07-08
AI Technical Summary
The challenge in existing MOSFET devices is the reduced mobility of charge carriers due to the influence of gate oxide-silicon interface defects and high vertical electric field strength, particularly in thin gate oxide layers of low threshold voltage power MOSFETs, leading to significant degradation of carrier mobility.
The implementation of a source region embedded with heterojunction epitaxy in power MOSFETs, where different lattice constants of heterojunction materials induce stress on the silicon channel, enhancing carrier mobility by forming either compressive or tensile stress depending on the device type.
This approach improves carrier mobility and reduces on-state resistance, thereby lowering power consumption in power MOSFETs.
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Figure CN120282477A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of power MOSFET devices, and particularly relates to a power MOSFET device with a source region embedded with heteroepitaxy and a manufacturing method thereof. Background Art
[0002] In a MOFET device, due to the scattering effect of the carriers in the conductive channel by the defects at the gate oxide-silicon interface and the effect of the electric field intensity perpendicular to the gate oxide-silicon interface, when the electric field intensity perpendicular to the gate interface increases, the carrier density in the conductive channel increases and gets closer to the gate oxide-silicon interface, thus being more vulnerable to the influence of interface defects, and the mobility of the carriers in the conductive channel is significantly lower than that of the carriers inside the body region. For a power MOSFET device with a low turn-on threshold, since the thickness of its gate oxide layer is thinner and the electric field intensity is greater, the mobility of the carriers in its conductive channel is more easily affected by this phenomenon. Summary of the Invention
[0003] Aiming at the deficiencies of the above-mentioned prior art, the technical problem to be solved by the present invention is: to provide a power MOSFET device with a source region embedded with heteroepitaxy and a manufacturing method thereof.
[0004] To solve the above technical problem, the present invention provides the following technical solution:
[0005] A power MOSFET device with a source region embedded with heteroepitaxy and a manufacturing method thereof, including the following steps:
[0006] S100. Grow an epitaxial layer on a silicon substrate;
[0007] S200. Fabricate a trench gate structure on the epitaxial layer;
[0008] S300. Form a body region by implantation in the upper part of the epitaxial layer, and activate the impurities in the body region through a thermal process; during this process, the silicon in the upper part of the epitaxial layer and the trench gate structure will be oxidized to form a surface oxide layer;
[0009] S400. Remove the surface oxide layer in a predetermined region, and etch to form a source groove in this region through an anisotropic etching process;
[0010] S500. Fill the source groove by growing heteroepitaxy to form a source region;
[0011] S600. Fabricate a source contact that penetrates the source region and extends into the body region, and form an ohmic contact region at the bottom of the source contact;
[0012] S700. Complete subsequent manufacturing processes.
[0013] Further, fabricating the trench gate structure includes the following sub-steps:
[0014] S210. Prepare a hard mask on the epitaxial layer;
[0015] S220. Etch a gate trench pattern on the hard mask through a lithography process, and etch a gate trench on the epitaxial layer;
[0016] S230. Remove the photoresist and the hard mask by wet etching, and perform wet cleaning;
[0017] S240. Grow a layer of silicon dioxide on the sidewalls of the gate trench as a sacrificial oxide layer by a thermal oxidation process, and remove the sacrificial oxide layer by wet etching;
[0018] S250. Grow a gate oxide layer on the sidewalls of the gate trench by a thermal oxidation process;
[0019] S260. Deposit gate polysilicon by low-pressure chemical vapor deposition;
[0020] S270. Remove the gate polysilicon outside the gate trench by chemical mechanical polishing;
[0021] S280. Adjust the morphology of the gate polysilicon on the silicon platform region by dry etching to obtain a trench gate structure.
[0022] Further, in the step S210, the hard mask is a silicon dioxide mask layer prepared on the epitaxial layer; or the hard mask includes a silicon dioxide cushion layer, a silicon nitride mask layer, and a silicon dioxide mask layer sequentially prepared on the epitaxial layer.
[0023] Further, the step S600 includes the following sub-steps:
[0024] S610. Form a silicon dioxide dielectric layer on the epitaxial layer by chemical vapor deposition;
[0025] S620. Define the pattern of the source region contact hole using photoresist, and etch the silicon dioxide dielectric layer and the epitaxial layer by dry etching to form a source region contact hole;
[0026] S630. Form an ohmic contact region at the bottom of the source region contact hole by ion implantation;
[0027] S640. Activate impurities by rapid thermal annealing;
[0028] S650. Deposit metallic tungsten in the source region contact hole by a tungsten plug process, and remove the metallic tungsten outside the source region contact hole by dry etching to form a tungsten plug in the source region contact hole as the source region contact.
[0029] Further, in the step S400, when removing the surface oxide layer in a predetermined area, a photomask is used and a photolithography process is adopted to etch and remove the surface oxide layer in this area, exposing the silicon surface.
[0030] Further, in the step S500, the heteroepitaxy bulges upward near the trench gate structure and extends to the upper end of the surface oxide layer above the trench gate structure.
[0031] Further, when the power MOSFET device is a PMOS device, in the step S500, a material with a lattice spacing larger than that of silicon is grown through an epitaxial growth process to form a source region; when the power MOSFET device is an NMOS device, in the step S500, a material with a lattice spacing smaller than that of silicon is grown through an epitaxial growth process to form a source region.
[0032] Further, when the power MOSFET device is a PMOS device, in the step S500, SiGe is grown through an epitaxial growth process to form a source region, and the temperature is 500°C to 800°C;
[0033] When the power MOSFET device is an NMOS device, in the step S500, SiC is grown through an epitaxial growth process to form a source region, and the temperature is 1500°C to 1700°C; or SiC is grown through an atomic layer deposition process to form a source region, and the temperature is 580°C to 620°C.
[0034] Further, when the power MOSFET device is a PMOS device, during the process of forming a source region by growing heteroepitaxy, a pentavalent element is in-situ doped at the same time; when the power MOSFET device is an NMOS device, during the process of forming a source region by growing heteroepitaxy, a trivalent element is in-situ doped at the same time; the doping concentration range is E18cm -3 ~E19cm -3 , and the formed concentration peak is at E19cm -3 ~E20cm -3 .
[0035] A power MOSFET device with a source region embedded with heteroepitaxy is fabricated by using the method for fabricating a power MOSFET device with a source region embedded with heteroepitaxy as described in any one of the above.
[0036] In the present invention, first, an anisotropic etching process is used to etch and form a source electrode groove in the area for forming the source region, and then a source region is formed by adopting the method of embedding heteroepitaxy. The different lattice constants of the heteroepitaxial material and the silicon material are used to generate the required elastic deformation, and corresponding local stress is applied to the silicon near the conductive channel in the source-drain direction, thereby improving the carrier mobility in the source-drain direction, further reducing the on-resistance of the power MOSFET device, and reducing power consumption. Brief Description of the Drawings
[0037] The drawings described herein are provided to further understand the present application and form a part of the present application. The schematic embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. In the drawings:
[0038] Figure 1 FIG. 8 is a schematic structural diagram of a power MOSFET device in the prior art.
[0039] Figure 2 FIG. 9 is a schematic structural diagram of another power MOSFET device in the prior art.
[0040] Figure 3 FIG. 10 is a flowchart of an embodiment of a method for manufacturing a power MOSFET device with a source region embedded with heteroepitaxy according to the present invention.
[0041] Figure 4 FIG. 11 is a schematic structural diagram after forming a hard mask.
[0042] Figure 5 FIG. 12 is a schematic structural diagram after etching out the gate trench pattern.
[0043] Figure 6 FIG. 13 is a schematic structural diagram after etching to form a gate trench and removing the hard mask.
[0044] Figure 7 FIG. 14 is a schematic structural diagram after growing a gate oxide layer.
[0045] Figure 8 FIG. 15 is a schematic structural diagram after forming a trench gate structure.
[0046] Figure 9 FIG. 16 is a schematic structural diagram after implanting to form a body region.
[0047] Figure 10 FIG. 17 is a schematic structural diagram after etching to form a source recess.
[0048] Figure 11 FIG. 18 is a schematic structural diagram after growing heteroepitaxy to form a source region.
[0049] Figure 12 FIG. 19 is a schematic structural diagram after forming a silicon dioxide dielectric layer.
[0050] Figure 13 FIG. 20 is a schematic structural diagram after forming a source contact hole.
[0051] Figure 14 FIG. 21 is a schematic structural diagram after forming an ohmic contact region.
[0052] Figure 15 FIG. 22 is a schematic structural diagram after forming a source contact.
[0053] Figure 16 Performance simulation diagram of hole density when the PMOS device with Figure 2 structure is turned on.
[0054] Figure 17 Performance simulation diagram of hole density when the PMOS device with the structure of this embodiment is turned on.
[0055] Figure 18 For Figure 2 structure and the structure of this embodiment, the conduction current curve diagram obtained by simulation.
[0056] Figure 19 For Figure 2 structure and the structure of this embodiment, the hole current density curve diagram of the cross-section of the conductive channel position obtained by simulation.
[0057] The reference signs in the specification drawings are as follows:
[0058] Epitaxial layer - 1; Silicon dioxide cushion layer - 2; Silicon nitride mask layer - 3; Silicon dioxide mask layer - 4; Gate trench pattern - 5; Gate trench - 6; Gate oxide layer - 7; Gate polysilicon - 8; Surface oxide layer - 9; Body region - 10; Source groove - 11; Source region - 12; Silicon dioxide dielectric layer - 13; Source region contact hole - 14; Ohmic contact region - 15; Tungsten plug - 16. Specific implementation mode
[0059] The following specific examples are used to illustrate the implementation mode of the present invention. The diagrams provided in the following examples only illustrate the basic concept of the present invention in a schematic manner. Without conflict, the following examples and the features in the examples can be combined with each other.
[0060] Please refer to Figure 1 , which is an existing power mosfet device structure. Its gate polysilicon 8 is formed after etch-back and is lower than the upper surface of the epitaxial layer 1. Please refer to Figure 2 , which is another existing power mosfet device structure. Its gate polysilicon 8 is formed by chemical mechanical polishing after forming a hard mask, so as to form a protruding structure protruding from the upper surface of the epitaxial layer 1 at the gate trench pattern 5 of the hard mask. Although the gate polysilicon 8 structures of the above two structures are different, their source regions 12 are both formed by ion implantation process (implantation concentration is about E15cm -3 , and the formed concentration peak is at E19cm -3 ~E20cm -3 ) and high-temperature thermal process (900°C - 1000°C, 30 - 60 minutes) for activation, so as to reduce the resistance by using the majority carrier concentration provided by impurity doping. The carriers in the conductive channel are greatly affected by the defects at the gate oxide-silicon interface.
[0061] Please refer to Figure 3 , Figure 3 , which is a flowchart of an embodiment of a method for fabricating a power MOSFET device with a source region embedded with heteroepitaxy. The method for fabricating a power MOSFET device with a source region embedded with heteroepitaxy in this embodiment includes the following steps:
[0062] S100. Grow epitaxial layer 1 on a silicon substrate. The epitaxial layer 1 can be one layer or multiple layers. The epitaxial layer 1 is generally grown by chemical vapor deposition. The epitaxial layer 1 is doped with trivalent elements (such as boron) or pentavalent elements (such as arsenic, phosphorus) according to the device polarity. The thickness of the epitaxial layer 1 can be determined according to the working voltage or a multi-layer structure of the epitaxial layer 1 can be adopted.
[0063] It should be noted that only the epitaxial layer 1 is shown in the figure, the silicon substrate at the lower end of the epitaxial layer 1 is not shown, and the figures in the drawings are all schematic diagrams of relevant regions in a cell structure during the device preparation process, not a complete structure schematic diagram.
[0064] S200. Fabricate a trench gate structure on the epitaxial layer 1. Fabricating the trench gate structure can include the following sub-steps:
[0065] S210. Please refer to Figure 4 , and prepare a hard mask on the epitaxial layer 1. The hard mask can be a silicon dioxide mask layer 4 prepared on the epitaxial layer 1. In this embodiment, the hard mask includes a silicon dioxide cushion layer 2, a silicon nitride mask layer 3, and a silicon dioxide mask layer 4 sequentially prepared on the epitaxial layer 1, so that the hard mask forms a multi-layer combined structure of a silicon dioxide - silicon nitride - silicon dioxide insulator mask. Both the silicon dioxide mask layer 4 and the silicon nitride mask layer 3 can be prepared by chemical vapor deposition process.
[0066] S220. Please refer to Figure 5 , and etch a gate trench pattern 5 on the hard mask through a photolithography process. Then, please refer to Figure 6 , and etch to form a gate trench 6 on the epitaxial layer 1. Specifically, in this step, first cover a photoresist on the silicon dioxide mask layer 4, and expose the pattern of the gate trench 6 on the photoresist through a mask; then dry-etch the silicon dioxide mask layer 4, the silicon nitride mask layer 3, and the silicon dioxide cushion layer 2 by using the photoresist pattern to form a gate trench pattern 5 on the hard mask; finally, use the gate trench pattern 5 to dry-etch to form a gate trench 6 on the epitaxial layer 1.
[0067] S230. Please continue to refer to Figure 6 , remove the photoresist and the hard mask (i.e., the silicon dioxide cushion layer 2, the silicon nitride mask layer 3, and the silicon dioxide mask layer 4) by wet etching, and perform wet cleaning.
[0068] S240. A sacrificial oxide layer (not shown in the figure) is grown on the sidewalls of the gate trench 6 by a thermal oxidation process, and the sacrificial oxide layer is removed by wet etching. The thickness of the sacrificial oxide layer is generally 5 nm to 50 nm. By forming the sacrificial oxide layer, the cell trench and the gate interconnect trench can be rounded and plasma damage can be repaired by the thermal oxidation process.
[0069] S250. Please refer to Figure 7 , a gate oxide layer 7 is grown on the sidewalls of the gate trench 6 by a thermal oxidation process. The thickness of the grown gate oxide layer 7 is determined according to the requirements of device performance, and the thickness of the gate oxide layer 7 is generally 5 nm to 50 nm.
[0070] S260. Please refer to Figure 8 , the gate polysilicon 8 is deposited by low-pressure chemical vapor deposition. The gate polysilicon 8 needs to fill the gate trench 6, and the thickness is determined according to the actual depth of the gate trench 6.
[0071] S270. Please continue to refer to Figure 8 , the gate polysilicon 8 outside the gate trench 6 is removed by chemical mechanical polishing. Since an oxide layer is also formed on the surface of the epitaxial layer 1 outside the gate trench 6 when the gate oxide layer 7 is grown on the sidewalls of the gate trench 6 in step S250. Therefore, the oxide layer on the surface of the epitaxial layer 1 can be used as a stop layer during chemical mechanical polishing. Of course, since the position of stopping polishing cannot be set very precisely during chemical mechanical polishing, in the actual process, after polishing to the oxide layer on the surface of the epitaxial layer 1, a part will be polished downward more.
[0072] S280. Please continue to refer to Figure 8 , the morphology of the gate polysilicon 8 on the silicon platform region is adjusted by dry etching to obtain a trench gate structure. This step is mainly to remove the gate polysilicon 8 on the surface of the epitaxial layer 1 (i.e., the silicon platform region) that extends laterally from the gate trench 6 to both sides to avoid affecting subsequent ion implantation and to adjust the gate resistance. Of course, it is not necessary to remove all the gate polysilicon 8 that extends laterally from the gate trench 6 to the silicon platform region, and a small amount of gate polysilicon 8 can also remain in the region on the silicon platform region that does not affect the implantation of the body region 10.
[0073] S300. Please refer to Figure 9 , an impurity is implanted into the upper part of the epitaxial layer 1 to form a body region 10, and the impurity in the body region 10 is activated by a thermal process. The impurity implanted to form the body region 10 can be a trivalent element or a pentavalent element, and the specific type is determined according to the polarity of the device. When the impurity in the body region 10 is activated by the thermal process, the silicon above the epitaxial layer 1 and the gate polysilicon 8 will also be oxidized into silicon dioxide, thereby forming a surface oxide layer 9.
[0074] S400. Please refer toFigure 10 , remove the surface oxide layer 9 in a predetermined area, and etch to form a source groove 11 in this area through an anisotropic etching process. The predetermined area is the area for forming the source region 12. When removing the surface oxide layer 9 in the predetermined area, a source region mask can be used, and the surface oxide layer 9 in the area for forming the source region 12 can be etched and removed by a photolithography process to expose the silicon surface of the epitaxial layer 1 in this area.
[0075] S500, please refer to Figure 11 , grow a heteroepitaxy on the exposed silicon surface by using an epitaxial growth technique, and fill the source groove 11 by growing the heteroepitaxy to form the source region 12. In this embodiment, the heteroepitaxy bulges upward near the trench gate structure and extends to the upper end of the surface oxide layer 9 above the trench gate structure.
[0076] In this step, for PMOS devices, since the carriers in the conductive channel are holes, a compressive stress needs to be applied in the source-drain direction to improve the hole mobility; at this time, a material with a lattice spacing larger than that of silicon is grown by an epitaxial growth process to form the source region 12. In this embodiment, for PMOS devices, SiGe is grown epitaxially to form the source region 12, the temperature is 500°C to 800°C, and at the same time, a pentavalent element (for example: boron) is in-situ doped, and the doping concentration range is E18cm -3 ~E19cm -3 , and the formed concentration peak is at E19cm -3 ~E20cm -3 .
[0077] Since the room-temperature lattice constant of Si (silicon) is 5.43 Å and the room-temperature lattice constant of Ge (germanium) is 5.66 Å, by growing Si_(1-x)Ge_x in the source region 12 and doping Ge proportionally, the proportion of Ge is usually 10% to 30%. Since the lattice spacing of SiGe is larger than that of silicon, the silicon at the conductive channel is thus extruded. At this time, a compressive stress is applied to the conductive channel in the source-drain direction, thereby improving the hole mobility.
[0078] For NMOS devices, since the carriers in the conductive channel are electrons, a tensile stress needs to be applied in the source-drain direction to improve the electron mobility; at this time, a material with a lattice spacing smaller than that of silicon is grown by an epitaxial growth process to form the source region 12. In this embodiment, for NMOS devices, SiC is grown epitaxially to form the source region 12, the temperature is 1500°C to 1700°C; at the same time, a trivalent element (for example: phosphorus) is in-situ doped, and the doping concentration range is E18cm -3 ~E19cm -3 , and the formed concentration peak is at E19cm -3 ~E20cm -3Of course, since the temperature required for growing SiC by conventional epitaxial growth process is relatively high, in order to reduce the process temperature, SiC can also be epitaxially grown by atomic layer deposition process to form the source region 12 at a temperature of 580°C to 620°C.
[0079] Since the lattice constant of Si at room temperature is 5.43 Å and the lattice constant of C (carbon) at room temperature is 3.567 Å, by growing Si_(1-x)C_x in the source region 12 and doping C proportionally, the proportion of C is usually 1% to 2% (the substitutional atomic solubility of C in silicon is low). Since the lattice spacing of SiC is smaller than that of silicon, a tensile stress is formed on the silicon at the conductive channel. At this time, a tensile stress is applied to the conductive channel in the source-drain direction, thereby improving the electron mobility.
[0080] S600. Fabricate a source region 12 contact that penetrates the source region 12 and extends into the body region 10, and form an ohmic contact region 15 at the bottom of the source region 12 contact. This step may include the following sub-steps:
[0081] S610. Refer to Figure 12 , and form a silicon dioxide dielectric layer 13 on the epitaxial layer 1 by chemical vapor deposition.
[0082] S620. Refer to Figure 13 , use photoresist to define the pattern of the source region contact hole 14, and form the source region contact hole 14 by dry etching the silicon dioxide dielectric layer 13 and the epitaxial layer 1.
[0083] S630. Refer to Figure 14 , dope high-concentration impurities into the bottom of the source region contact hole 14 by ion implantation to form an ohmic contact region 15 at the bottom of the source region contact hole 14; in this step, the polarity of the impurity element implanted by ion implantation should be opposite to the polarity of the impurity element in the source region 12.
[0084] S640. Activate the impurities by rapid thermal annealing.
[0085] S650. Continue to refer to Figure 15 , deposit metallic tungsten in the source region contact hole 14 by tungsten plug 16 process, and remove the metallic tungsten outside the source region contact hole 14 by dry etching to form a tungsten plug 16 in the source region contact hole 14 as the source region 12 contact. Before depositing metallic tungsten, a metal and a nitride may also be deposited as a contact hole protection layer by physical vapor deposition process first. And form silicide by rapid thermal degradation, and the metal may include one or more of titanium, cobalt, and tantalum.
[0086] S700. Complete the subsequent manufacturing processes. The subsequent manufacturing processes generally include: depositing aluminum copper compounds above the tungsten plug 16 by physical vapor deposition, and forming circuits using photolithography and dry etching; depositing a passivation layer and etching the passivation layer using photolithography (the passivation layer generally includes silicon nitride or silicon dioxide); performing alloy annealing, etc. These are all conventional processes for manufacturing power MOSFET devices in the prior art and are not related to the improvements of this embodiment, so they will not be elaborated here.
[0087] Please refer to Figure 16 and Figure 17 , and perform TCAD simulations on PMOS devices with Figure 2 structures and PMOS devices with the structure of this embodiment. Please refer to Figure 18 . By comparing the on-current curves (PMOS) obtained from simulating the Figure 2 structure and the structure of this embodiment, it can be seen that the structure of this embodiment has an on-current increase of about 17% compared to the Figure 2 structure. Please refer to Figure 19 . By simulating the Figure 2 structure and the structure of this embodiment, it can be seen that the structure of this embodiment has a significant improvement in carrier mobility and current density at the conductive channel compared to the Figure 2 structure, meeting the optimization objectives.
[0088] In this embodiment, first, an anisotropic etching process is used to etch a source groove 11 in the region for forming the source region 12, and then the source region 12 is formed by embedding heteroepitaxy, and different types of heteroepitaxial materials are embedded according to different device types. For NMOS devices, the conduction band height is reduced by tensile stress to improve the electron mobility in the source-drain direction; for PMOS devices, the valence band height is increased by compressive stress to improve the hole mobility in the source-drain direction. Thereby, the on-resistance of the power MOSFET device can be further reduced and the power consumption can be decreased.
[0089] The present invention also discloses a power MOSFET device with heteroepitaxial embedding in the source region. The power MOSFET device can be manufactured by using the method for manufacturing a power MOSFET device with heteroepitaxial embedding in the source region according to any of the above embodiments. In this embodiment, the source region 12 of the power MOSFET device is formed by embedding heteroepitaxy. By utilizing the different elastic deformations caused by the different lattice constants of heteroepitaxy and silicon, different local stresses are applied to the silicon near the conductive channel in the source-drain direction, thereby improving the mobility of the carriers in the conductive channel and reducing the power consumption.
[0090] The above embodiments only represent the preferred embodiments of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.
Claims
1. A manufacturing method of a power MOSFET device with source region embedded heteroepitaxy, characterized in that: It includes the following steps: S100. Grow an epitaxial layer on a silicon substrate; S200. Fabricate a trench gate structure on the epitaxial layer; S300. Form a body region by implantation in the upper part of the epitaxial layer, and activate the impurities in the body region through a thermal process; during this process, the silicon in the upper part of the epitaxial layer and the trench gate structure will be oxidized to form a surface oxide layer; S400. Remove the surface oxide layer in a predetermined area, and etch to form a source groove in this area through an anisotropic etching process; S500. Fill the source groove by growing heteroepitaxy to form a source region; S600. Fabricate a source contact that penetrates the source region and extends into the body region, and form an ohmic contact region at the bottom of the source contact; S700. Complete subsequent fabrication processes.
2. The manufacturing method of the power MOSFET device with source region embedded hetero-epitaxy according to claim 1, characterized in that: Fabricating the trench gate structure includes the following sub-steps: S210. Prepare a hard mask on the epitaxial layer; S220. Etch a gate trench pattern on the hard mask through a photolithography process, and etch to form a gate trench on the epitaxial layer; S230. Remove the photoresist and the hard mask by wet etching, and perform wet cleaning; S240. Grow a layer of silicon dioxide as a sacrificial oxide layer on the sidewalls of the gate trench by a thermal oxidation process, and remove the sacrificial oxide layer by wet etching; S250. Grow a gate oxide layer on the sidewalls of the gate trench by a thermal oxidation process; S260. Deposit gate polysilicon for oxidation by low-pressure chemical vapor deposition; S270. Remove the gate polysilicon outside the gate trench by chemical mechanical polishing; S280. Adjust the morphology of the gate polysilicon on the silicon platform region by dry etching to obtain a trench gate structure.
3. The manufacturing method of the power MOSFET device with embedded heteroepitaxy in the source region according to claim 2, wherein: In the step S210, the hard mask is a silicon dioxide mask layer prepared on the epitaxial layer; or the hard mask includes a silicon dioxide cushion layer, a silicon nitride mask layer, and a silicon dioxide mask layer sequentially prepared on the epitaxial layer.
4. The manufacturing method of the power MOSFET device with source region embedded heteroepitaxy according to claim 1, characterized in that: The step S600 includes the following sub-steps: S610. Form a silicon dioxide dielectric layer on the epitaxial layer by chemical vapor deposition; S620. Define the pattern of the source contact hole using photoresist, and etch the silicon dioxide dielectric layer and the epitaxial layer by dry etching to form a source contact hole; S630. Form an ohmic contact region at the bottom of the source contact hole by ion implantation; S640. Activate the impurities by rapid thermal annealing; S650. Deposit metallic tungsten in the source contact hole by a tungsten plug process, and remove the metallic tungsten outside the source contact hole by dry etching to form a tungsten plug in the source contact hole as the source contact.
5. The manufacturing method of the source region embedded heteroepitaxial power MOSFET device according to claim 1, wherein: In the step S400, when removing the surface oxide layer in a predetermined area, use a mask and etch to remove the surface oxide layer in this area through a photolithography process to expose the silicon surface.
6. The manufacturing method of the power MOSFET device with source region embedded heteroepitaxy as described in claim 1, characterized in that: In the step S500, the heteroepitaxy bulges upward near the trench gate structure and extends to the upper end of the surface oxide layer above the trench gate structure.
7. The manufacturing method of the power MOSFET device with source region embedded heteroepitaxy according to any one of claims 1 to 6, characterized in that: When the power MOSFET device is a PMOS device, in the step S500, a source region is formed by epitaxially growing a material with a lattice spacing larger than that of silicon; when the power MOSFET device is an NMOS device, in the step S500, a source region is formed by epitaxially growing a material with a lattice spacing smaller than that of silicon.
8. The method for fabricating a source-region-embedded heteroepitaxial power MOSFET device according to claim 7, wherein: When the power MOSFET device is a PMOS device, in the step S500, SiGe is epitaxially grown to form a source region at a temperature of 500 °C to 800 °C. When the power MOSFET device is an NMOS device, in the step S500, SiC is epitaxially grown to form a source region at a temperature of 1500 °C to 1700 °C; or SiC is formed by atomic layer deposition to form a source region at a temperature of 580 °C to 620 °C.
9. The method for fabricating a source region-embedded heteroepitaxial power MOSFET device according to claim 7, wherein: When the power MOSFET device is a PMOS device, during the process of forming the source region by growing heteroepitaxy, a pentavalent element is doped in-situ; when the power MOSFET device is an NMOS device, during the process of forming the source region by growing heteroepitaxy, a trivalent element is doped in-situ; the doping concentration range is E18cm -3 ~E19cm -3 , and the formed concentration peak is at E19cm -3 ~E20cm -3 .
10. A power MOSFET device with source region embedded heteroepitaxy, characterized in that, It is made by using the method for manufacturing a power MOSFET device with heteroepitaxial source region embedding according to any one of claims 1 to 9.