High-voltage semiconductor structure and forming method thereof

Abstract

A high voltage semiconductor structure includes a substrate having a first conductive pattern, a gate structure on the substrate, a source drift region and a drain drift region in the substrate at both sides of the gate structure, respectively, where the source drift region and the drain drift region are disposed in the substrate at both sides of the gate structure from a top view. Each of the source drift region and the drain drift region comprises a first part and a second part, the width of the first part is smaller than that of the second part, the first part is directly connected with the second part, and the source drift region and the drain drift region are T-shaped from a top view; the source drift region and the drain drift region have a second conductive type.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly, to a field drift metal oxide semiconductor (FDMOS) device. Background Art

[0002] Since the power consumption of a metal oxide semiconductor (MOS) transistor is lower than that of a conventional transistor and it can be fabricated with high density, it is widely used in the semiconductor industry. When an appropriate voltage is applied, the MOS transistor can be used as a switch to control the current flowing through the device. In high-voltage circuits, such as the input and output terminals of electronic devices, field drift metal oxide semiconductor (FDMOS) transistors are commonly used because they can withstand heavy loads.

[0003] However, the prior art FDMOS devices have several disadvantages. For example, a conventional FDMOS device may have a parasitic field device that conducts when the operating voltage exceeds about 10V, resulting in instability of the circuit model. With the development of integrated circuits, improving the field drift metal oxide semiconductor (FDMOS) transistor has become an increasingly important issue. Summary of the Invention

[0004] The main object of the present invention is to provide an improved high-voltage semiconductor structure to solve the above-mentioned deficiencies and disadvantages of the prior art.

[0005] The present invention provides a high-voltage semiconductor structure, comprising a substrate having a first conductivity type, a gate structure located on the substrate, a source drift region and a drain drift region respectively located in the substrate on both sides of the gate structure, wherein, when viewed from a top view, the source drift region and the drain drift region each comprise a first portion and a second portion, a width of the first portion is smaller than a width of the second portion, the first portion is directly connected to the second portion, and the source drift region and the drain drift region present a T-shaped configuration when viewed from a top view, and the source drift region and the drain drift region have a second conductivity type.

[0006] The present invention further provides a method for forming a high-voltage semiconductor structure, which includes providing a substrate having a first conductivity type, forming a gate structure on the substrate, and forming a source drift region and a drain drift region in the substrate on both sides of the gate structure respectively. From a top view, the source drift region and the drain drift region each include a first part and a second part, the width of the first part is smaller than the width of the second part, the first part is directly connected to the second part, and the source drift region and the drain drift region present a T-shaped configuration from the top view. The source drift region and the drain drift region have a second conductivity type.

[0007] The present invention is characterized in that a high-voltage semiconductor structure and a manufacturing method thereof are provided. The source drift region and the drain drift region included therein have a shape similar to a T or have a cut-off corner from a top view. Due to the existence of the cut-off corner, the effective channel length between the source drift region and the drain drift region becomes longer at the boundary part parallel to the gate doping region. In this way, the kink effect can be reduced without forming an additional doping region, and the stability of the high-voltage semiconductor structure and the manufacturing process yield can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] To make the following text easier to understand, the accompanying drawings and their detailed written descriptions can be referred to simultaneously when reading the present invention. Through specific embodiments herein and with reference to the corresponding accompanying drawings, the specific embodiments of the present invention are explained in detail, and the principle of action of the specific embodiments of the present invention is expounded. In addition, for clarity, the features in the drawings may not be drawn according to actual proportions, so the sizes of some features in certain drawings may be deliberately enlarged or reduced.

[0009] Figure 1 is a top view layout schematic diagram of the high-voltage semiconductor structure shown in the first embodiment of the present invention;

[0010] Figure 2 is Figure 1 a schematic cross-sectional view of the high-voltage semiconductor structure taken along the section line A-A';

[0011] Figure 3 is a layout schematic diagram of the high-voltage semiconductor structure shown in the second embodiment of the present invention;

[0012] Figure 4 is Figure 3 a schematic cross-sectional view of the high-voltage semiconductor structure taken along the section line B-B';

[0013] Figure 5 is Figure 3 a schematic cross-sectional view of the high-voltage semiconductor structure taken along the section line C-C'.

[0014] Symbol Explanation

[0015] 1: High-voltage semiconductor structure

[0016] 2: High-voltage semiconductor structure

[0017] 100: Substrate

[0018] 102: Gate structure

[0019] 111: Source heavily doped region

[0020] 112: Drain heavily doped region

[0021] 120: Gate doped region

[0022] 130: Annular ion trap

[0023] 131: Heavily doped region

[0024] 140: Additional doped region

[0025] C: Corner

[0026] D: Drain terminal

[0027] DF: Drain drift region

[0028] E1: First boundary

[0029] E2: Second boundary

[0030] E3: Upper boundary

[0031] E4: Lower boundary

[0032] G: Gate terminal

[0033] GE: Gate electrode

[0034] GI: Gate dielectric layer

[0035] L1: Distance (channel length)

[0036] L2: Distance (effective channel length)

[0037] P1: First part

[0038] P2: Second part

[0039] PW: High-voltage well

[0040] S: Source terminal

[0041] SF: Source drift region

[0042] SP: Spacer wall

[0043] STI: Shallow trench isolation

[0044] W1: Width

[0045] W2: Width

[0046] W3: Width Detailed Implementation Manner

[0047] To enable those of ordinary skill in the art to which the present invention pertains to further understand the present invention, the preferred embodiments of the present invention are specifically listed below, and in conjunction with the accompanying drawings, the content and the effects to be achieved of the present invention are described in detail.

[0048] For the convenience of description, the drawings of the present invention are only schematic for easier understanding of the present invention, and their detailed proportions can be adjusted according to the design requirements. Regarding the up-and-down relationship of the relative components in the figures described in the text, those skilled in the art should understand that it refers to the relative positions of the objects, so they can all be flipped to present the same components, and this should all fall within the scope disclosed in this specification. This is hereby stated first.

[0049] Although the present invention uses terms such as first, second, third, etc. to describe elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and / or section from another element, component, region, layer, and / or section, and they do not inherently imply and represent any previous ordinal numbers of the elements, nor do they represent the arrangement order of one element and another element, or the order in the manufacturing method. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below can also be referred to by the term of the second element, component, region, layer, or section.

[0050] The terms "about" or "substantially" mentioned in the present invention generally mean within 20% of a given value or range, such as within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities, that is, even without specifically stating "about" or "substantially", the meaning of "about" or "substantially" can still be implied.

[0051] The terms "coupled", "coupled to", and "electrically connected" mentioned in the present invention include any direct and indirect electrical connection means. For example, if it is described in the text that the first component is coupled to the second component, it means that the first component can be directly electrically connected to the second component, or indirectly electrically connected to the second component through other devices or connection means.

[0052] Although the following describes the invention of the present invention through specific embodiments, the inventive concept of the present invention can also be applied to other embodiments. In addition, in order not to obscure the spirit of the present invention, specific details will be omitted, and the omitted details are within the knowledge scope of those of ordinary skill in the art.

[0053] Please refer to Figures 1 to 2 , in which, Figure 1 is a layout schematic diagram of a high-voltage semiconductor structure shown according to an embodiment of the present invention, Figure 2 and Figure 1 is a cross-sectional schematic diagram taken along the tangent line A-A' (channel length direction) in

[0054] As Figures 1 to 2 shown, a high-voltage semiconductor structure 1 is provided, for example, a field-drift metal oxide semiconductor (FDMOS) transistor, which includes a substrate 100, for example, a silicon substrate. In this embodiment, the substrate 100 has a first conductivity type, for example, P-type. In the substrate 100, a high-voltage well PW is provided, where in this embodiment, the high-voltage well PW has a first conductivity type, for example, P-type. According to an embodiment of the present invention, a source drift region SDF and a drain drift region DF are provided in the high-voltage well PW, where both the source drift region SDF and the drain drift region DF have a second conductivity type, for example, N-type. However, the conductivity types of the above-mentioned components are only one example of the present invention, and the present invention is not limited thereto.

[0055] In addition, a gate structure 102 is further included on the substrate 100. The gate structure 102 may include a gate electrode GE, a gate dielectric layer GI located below the gate electrode, and a spacer SP surrounding the gate electrode GE. In Figure 1 , for the simplicity of the drawings, the gate structure 102 represents the sum of the gate electrode GE, the gate dielectric layer GI, and the spacer SP. In addition, the gate structure 102 is connected to a gate terminal G for controlling the opening or closing of the gate of the high-voltage semiconductor structure 1.

[0056] The range of the substrate 100 directly below the gate structure 102 is, for example, a P-type doped region. Here, the doped region directly below the gate structure 102 is defined as a gate doped region 120. From a top view, the range of the gate doped region 120 is rectangular, and the position of the gate doped region 120 partially overlaps with the source drift region SDF and the drain drift region DF. In particular, the four corners C of the gate doped region 120 overlap with the source drift region SDF or the drain drift region DF. In some embodiments, the gate doped region 120 can also be regarded as a part of the high-voltage well PW. In this embodiment, both the gate doped region 120 and the high-voltage well PW have a first conductivity type (P-type).

[0057] In the source drift region SDF and the drain drift region DF, a source heavily doped region 111 and a drain heavily doped region 112 are respectively included. Among them, the source heavily doped region 111 and the drain heavily doped region 112 can be N+ doped regions. In addition, a source terminal S and a drain terminal D are included and are electrically connected to the source heavily doped region 111 and the drain heavily doped region 112 respectively. Additionally, in this embodiment, the distance between the source drift region SDF and the drain drift region DF is defined as L1, which represents the channel length of the high-voltage semiconductor device.

[0058] In addition, a plurality of shallow trench isolations STI are provided in the substrate 100 for isolating components or defining the positions of the drift regions or doped regions. The distribution of the shallow trench isolations STI can be referred to Figure 2 as shown. A part of the shallow trench isolations STI are located in the source drift region SDF and the drain drift region DF. The function of the shallow trench isolations STI located in the source drift region SDF and the drain drift region DF here is to extend the current path. More specifically, the operating voltage of the high-voltage semiconductor structure 1 of the present invention is relatively large (usually greater than 10 volts). Therefore, a relatively large electric field is likely to be generated around the gate structure 102 during operation. At this time, the current may pass through the gate dielectric layer GI and thus affect the gate structure 102. Therefore, the shallow trench isolations STI located in the source drift region SDF and the drain drift region DF here have the function of extending the current path (enabling the current to pass under the shallow trench isolations STI to avoid directly passing through the gate dielectric layer GI). Additionally, for the purpose of simplicity of the drawings, Figure 1 the positions of the shallow trench isolations STI are not drawn.

[0059] In addition, a ring ion trap 130 is included in this embodiment. Among them, the ring ion trap 130 has a first conductivity type. For example, it is a P-type. A heavily doped region 131 provided in the ring ion trap 130 is also included. According to the embodiment of the present invention, 131 can be a P+ doped region. The ring ion trap 130 surrounds components such as the above-mentioned source drift region SDF, drain drift region DF, and gate structure 102. The ring ion trap 130 described here can be regarded as a guard ring, and its main function is to connect a signal (such as a stable signal or a ground signal) to achieve the effects of absorbing the noise of the high-voltage semiconductor structure 1 and stabilizing the voltage.

[0060] In operation, when the source extreme S and the drain extreme D are connected to a signal (such as a voltage source) and a critical voltage (Vth) is applied to the gate extreme G, it will cause current to flow from the source extreme S through the channel region (not shown in the figure) under the gate structure 102 to the drain extreme D. The above behavior is called turning on the high-voltage semiconductor structure 1. However, in the actual operating state, due to the relatively high applied voltage of the high-voltage semiconductor structure 1, at the channel boundary of the gate doping region 120 of the high-voltage semiconductor structure 1, the kink effect may occur. The so-called kink effect means that at a high drain voltage, carriers near the drain extreme will multiply, causing the drain current to increase rapidly with the drain voltage. This will cause current to possibly flow from the drain extreme D to the source extreme S before the gate extreme G reaches the critical voltage. The kink effect is particularly common at the boundary of the doping region (channel boundary), for example Figure 1 near the upper boundary E3 and the lower boundary E4 of the shown gate doping region 120, the kink effect is likely to occur, causing the high-voltage semiconductor structure to turn on unexpectedly at the channel boundary. To clearly represent the features of the present invention, in the following paragraphs, the region adjacent to the upper boundary E3 or the lower boundary E4 of the gate doping region 120 is defined as the "channel boundary region R1".

[0061] The main reason for the occurrence of the above kink effect is that the doping concentration of the gate doping region 120 in the channel boundary region R1 is insufficient and the thickness of the gate dielectric layer GI is relatively thin. To solve the problem of the kink effect, in this embodiment, an additional doping region 140 is formed again at the positions adjacent to the upper boundary E3 and the lower boundary E4 of the gate doping region 120 (i.e., the channel boundary region R1). The additional doping region 140 also has a first conductivity type, such as P-type. In this embodiment, the doping concentration of the additional doping region 140 may be similar to or the same as that of the annular ion trap 130, and the depth of the additional doping region 140 is deeper than the bottom surface of the shallow trench isolation STI. The additional doping region 140 is provided in the channel boundary region R1 of the doped pole doping region 120, which can supplement the doping concentration of the channel boundary region R1 and prevent the kink effect from occurring in the channel boundary region R1 (i.e., at the upper boundary E3 and the lower boundary E4 of the gate doping region 120), that is, the occurrence probability of the kink effect can be reduced.

[0062] However, although forming the additional doping region 140 can reduce the kink effect, the additional doping region 140 occupies a certain area of the overall high-voltage semiconductor structure. With the progress of semiconductor manufacturing processes, the sizes of various components are getting smaller and smaller. That is to say, when the area of the high-voltage semiconductor structure 1 becomes smaller and smaller, it becomes more difficult to form the additional doping region 140. In addition, the applicant has found that forming the additional doping region 140 will affect the critical voltage and turn-on current of the gate terminal G, and when the area of the high-voltage semiconductor structure 1 is smaller, the change in the critical voltage of the gate terminal G is particularly obvious. Through experiments by the applicant, the change range of the critical voltage can reach approximately 50%. Therefore, forming the additional doping region 140 will introduce variables to the critical voltage of the gate terminal G, which is not conducive to maintaining the yield of semiconductor manufacturing processes.

[0063] Therefore, in another embodiment of the present invention, an improved high-voltage semiconductor structure is provided to solve the above problems such as the decrease in manufacturing process yield caused by forming the additional doping region 140 on both sides of the gate doping region 120. Details are as shown in the following paragraphs.

[0064] The following will describe different implementation modes of the high-voltage semiconductor structure and its manufacturing method of the present invention. For simplicity of description, the following description mainly details the differences of each embodiment, and the same parts will not be repeated. In addition, the same components in each embodiment of the present invention are labeled with the same reference numerals to facilitate comparison between embodiments.

[0065] Please refer to Figures 3 to 5 , wherein, Figure 3 is a layout schematic diagram of the high-voltage semiconductor structure shown according to the second embodiment of the present invention, Figure 4 is a cross-sectional schematic diagram of the high-voltage semiconductor structure according to Figure 3 along the section line B-B', Figure 5 is a cross-sectional schematic diagram of the high-voltage semiconductor structure according to Figure 3 along the section line C-C'. As Figures 3 to 5 shows, a high-voltage semiconductor structure 2 is provided. Most of the components in the high-voltage semiconductor structure 2 are the same as the corresponding components in the high-voltage semiconductor structure 1 in the above first embodiment, such as the substrate 100, the high-voltage well PW, the source drift region SDF, the drain drift region DF, the source heavily doped region 111, the drain heavily doped region 112, the gate structure 102, the shallow trench isolation STI, the annular ion trap 130, and the heavily doped region 131, etc. Among them, if these components are not specifically mentioned, they have the same or similar material compositions as those components described in the above first preferred embodiment and can be formed by the same manufacturing processes. Therefore, these repeated components will not be elaborated here.

[0066] The difference between this embodiment and the above-described first embodiment is that there is no additional doping region 140 in the first embodiment beside the gate doping region 120, and the shapes of the source drift region SDF and the drain drift region DF in this embodiment are different from those in the above-described first embodiment. More specifically, as Figure 1 shown, in the first embodiment, the source drift region SDF and the drain drift region DF are rectangular in shape and have four corners C. However, as Figure 3 shown, in this embodiment, two of the corners of the source drift region SDF and the drain drift region DF are retracted inward, so that the source drift region SDF and the drain drift region DF exhibit a shape similar to a T shape. Since the source drift region SDF and the drain drift region DF are symmetric in shape, only the drain drift region DF will be described below, and the source drift region SDF will not be repeated due to its symmetric shape.

[0067] As Figure 3 shown, the drain drift region DF has a shape similar to a T shape and can be divided into a first part P1 and a second part P2, where the first part P1 and the second part P2 are in direct contact. In addition, the width W1 of the first part P1 is smaller than the width W2 of the second part P2 (the widths W1 and W2 described here refer to the lengths along the Y direction, as Figure 3 shown). A first boundary E1 is defined on the first part P1, and a second boundary E2 is defined on the second part P2, where the first boundary E1 extends along the X direction, the second boundary E2 extends along the Y direction, the first boundary E1 is directly adjacent to the second boundary E2, and the first boundary E1 is preferably perpendicular to the second boundary E2. In some embodiments, the length of the first boundary E1 is from 0.2 micrometers to 1.6 micrometers, and the length of the second boundary E2 is between 0.2 micrometers and 1.2 micrometers. Therefore, from another perspective, after cutting off a rectangle with the length and width of the second boundary E2 and the first boundary E1 respectively from two of the corners of the rectangular drain drift region DF described in the first embodiment, the shape of the drain drift region DF in this embodiment can be obtained.

[0068] It should be noted that, viewed from the top view, the gate doping region 120 is also rectangular and has four corners C. Another feature of this embodiment is that, viewed from the top view, the drain drift region DF and the source drift region SDF have a T shape and do not overlap with the four corners of the gate doping region 120. In contrast, the drain drift region DF and the source drift region SDF in the first embodiment of the present invention will overlap with the four corners C of the gate doping region 120 (as Figure 1 shown).

[0069] In actual operation, two corners of the drain drift region DF and the source drift region SDF of this embodiment are retracted inward. Therefore, near the boundary of the gate doping region 120 (corresponding to the upper boundary E3 and the lower boundary E4 of the gate doping region 120), the distance between the drain drift region DF and the source drift region SDF becomes longer. Please also refer to Figure 4 and Figure 5 , where Figure 4 is a schematic cross-sectional view of the high-voltage semiconductor structure according to Figure 3 along the section line B-B', Figure 5 is a schematic cross-sectional view of the high-voltage semiconductor structure according to Figure 3 along the section line C-C'. It can be seen from Figure 3 that in this embodiment, in the direction horizontally aligned with the upper boundary E3 in the top view, the distance between the drain drift region DF and the source drift region SDF is defined as L2, where L2 can also be regarded as the effective channel length at the boundary. The length L2 is greater than Figure 1 the length L1 shown.

[0070] As Figure 5 shown, at the section line C-C', that is, corresponding to the direction aligned with the upper boundary E3 in the top view, the boundary of the drain drift region DF (corresponding to Figure 3 the second boundary E4) and the boundary of the source drift region SDF are located directly below the shallow trench isolation STI. Therefore, at the section line C-C' of the high-voltage semiconductor structure 2 of this embodiment, the distance between the drain drift region DF and the source drift region SDF is relatively far, resulting in a longer effective channel length at this location. Therefore, at a high operating voltage, it is not easy for current to directly penetrate from the drain drift region DF to the source drift region SDF (or vice versa) in the region near the boundary of the gate doping region 120. That is to say, the occurrence probability of the above-mentioned kink effect can be reduced.

[0071] In this embodiment, by changing the shapes of the drain drift region DF and the source drift region SDF, the distance between the drain drift region DF and the source drift region SDF in the boundary region of the gate doping region 120 becomes longer, thereby actively reducing the kink effect. Therefore, in this embodiment, it is not necessary to form the additional doping region 140 described in the first embodiment. In this way, the disadvantages of the above-mentioned first embodiment can also be avoided, such as forming the additional doping region 140 will increase the manufacturing process difficulty and affect the threshold voltage, etc.

[0072] In summary of the above specification and drawings, the present invention provides a high-voltage semiconductor structure 2, which includes a substrate 100 having a first conductivity type (e.g., P-type), a gate structure located on the substrate 100, a source drift region SF and a drain drift region DF respectively located in the substrate 100 on both sides of the gate structure 102. From a top view, the source drift region SF and the drain drift region DF each include a first portion P1 and a second portion P2. The width W1 of the first portion P1 is smaller than the width W2 of the second portion P2. The first portion P1 is directly connected to the second portion P2, and the source drift region SF and the drain drift region DF present a T-shaped from a top view. The source drift region SF and the drain drift region DF have a second conductivity type (e.g., N-type).

[0073] In some embodiments of the present invention, the first portion P1 of the source drift region SF is close to the gate structure 102, while the second portion P2 of the source drift region SF is far from the gate structure 102 (from a top view).

[0074] In some embodiments of the present invention, a gate doping region 120 is further included in the substrate below the gate structure 102. From a top view, the gate doping region 120 is rectangular and has four corners C, and the gate doping region 120 has a first conductivity type (e.g., P-type).

[0075] In some embodiments of the present invention, from a top view, the four corners C of the gate doping region 120 do not overlap with the source drift region SF and the drain drift region DF (as shown, the T-shaped source drift region SF and drain drift region DF do not overlap with the four corners C of the gate doping region 120). Figure 3 shown, the T-shaped source drift region SF and drain drift region DF do not overlap with the four corners C of the gate doping region 120).

[0076] In some embodiments of the present invention, the source drift region SF, the gate structure 102, and the drain drift region DF are arranged along a first direction (X direction), and a second direction (Y direction) is defined perpendicular to the first direction.

[0077] In some embodiments of the present invention, from a top view, the first portion P1 of the drain drift region DF has a first boundary E1 extending along the first direction (X direction). The first boundary E1 is directly adjacent to the second portion P2 of the drain drift region DF, and the length of the first boundary E1 is from 0.2 micrometers to 1.6 micrometers.

[0078] In some embodiments of the present invention, the second part P2 of the drain drift region DF has a second boundary E2 extending along the second direction (Y direction), and the second boundary E2 is directly adjacent to the first part P1 of the drain drift region DF, where the length of the second boundary P2 is from 0.2 micrometers to 1.2 micrometers.

[0079] In some embodiments of the present invention, a shallow trench isolation STI is further included in the substrate 100, and from a cross-sectional view, the second boundary of the second part of the source drift region SF is located below the shallow trench isolation.

[0080] In some embodiments of the present invention, an annular ion trap surrounds the gate structure 102, the source drift region SF, and the drain drift region DF, and the annular ion trap 130 has a first conductivity type (e.g., P type).

[0081] In some embodiments of the present invention, the gate doping region 120 includes a third boundary (upper boundary E3) adjacent to the annular ion trap 130, and the third boundary E3 extends along the first direction. Along the second direction (Y direction), there is no other doping region in the substrate 100 between the third boundary E3 and the annular ion trap 130 (that is, in the second embodiment of the present invention, no additional doping region needs to be formed beside the upper boundary E3, so there is no other doping region between the upper boundary E3 and the nearest annular ion trap 130).

[0082] In some embodiments of the present invention, from a top view, a part of the first part P1 of the source drift region SF overlaps with the gate doping region 120 (near the central channel).

[0083] In some embodiments of the present invention, from a top view, an area of the gate doping region 120 is smaller than an area of the gate structure 102.

[0084] In some embodiments of the present invention, from a top view, the width W1 of the first part P1 of the drain drift region SF is smaller than a width W3 of the gate structure 102, and the width of the second part of the drain drift region is greater than the width of the gate structure.

[0085] In some embodiments of the present invention, a source heavily doped region 111 is further included on the source drift region SF, and a drain heavily doped region 112 is included on the drain drift region DF. The source heavily doped region 111 and the drain heavily doped region 112 have a second conductivity type (e.g., N type).

[0086] The present invention also provides a method for forming a high-voltage semiconductor structure, which includes providing a substrate 100 having a first conductivity type (e.g., P-type), forming a gate structure 102 on the substrate 100, forming a source drift region SF and a drain drift region DF in the substrate 100 on both sides of the gate structure 102 respectively. From a top view, the source drift region SF and the drain drift region DF each include a first part P1 and a second part P2. A width W1 of the first part P1 is smaller than a width W2 of the second part P2. The first part P1 is directly connected to the second part P2, and the source drift region SF and the drain drift region DF present a T-shaped from a top view. The source drift region SF and the drain drift region DF have a second conductivity type (e.g., N-type).

[0087] The feature of the present invention is to provide a high-voltage semiconductor structure and a manufacturing method thereof. The source drift region and the drain drift region included therein have a shape similar to a T or have a missing corner from a top view. Due to the existence of the missing corner, the effective channel length between the source drift region and the drain drift region becomes longer at the boundary part parallel to the gate doping region. In this way, the kink effect can be reduced without forming an additional doping region, and the stability of the high-voltage semiconductor structure and the manufacturing process yield can be improved.

[0088] The above are only the preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention shall fall within the scope covered by the present invention.

Claims

1. A high-voltage semiconductor structure, comprising: a substrate having a first conductivity type; a gate structure located on the substrate; a source drift region and a drain drift region, respectively located in the substrate on both sides of the gate structure. From a top view, the source drift region and the drain drift region each include a first portion and a second portion. The width of the first portion is smaller than that of the second portion. The first portion is directly connected to the second portion, and the source drift region and the drain drift region present a T-shaped configuration from a top view. The source drift region and the drain drift region have a second conductivity type.

2. The high-voltage semiconductor structure according to claim 1, wherein the first portion of the drain drift region is close to the gate structure, and the second portion is away from the gate structure.

3. The high-voltage semiconductor structure according to claim 1, further comprising a gate doping region located in the substrate below the gate structure. From a top view, the gate doping region is rectangular and has four corners, and the gate doping region has the first conductivity type.

4. The high-voltage semiconductor structure according to claim 3, wherein the four corners of the gate doping region do not partially overlap with the source drift region and the drain drift region from a top view.

5. The high-voltage semiconductor structure according to claim 3, wherein the source drift region, the gate structure, and the drain drift region are arranged along a first direction (X direction), and a second direction (Y direction) is defined to be perpendicular to the first direction.

6. The high-voltage semiconductor structure according to claim 5, wherein the first portion of the drain drift region has a first boundary extending along the first direction, and the first boundary is directly adjacent to the second portion of the drain drift region. The length of the first boundary is from 0.2 micrometers to 1.6 micrometers.

7. The high-voltage semiconductor structure according to claim 5, wherein the second portion of the drain drift region has a second boundary extending along the second direction, and the second boundary is directly adjacent to the first portion of the drain drift region. The length of the second boundary is from 0.2 micrometers to 1.2 micrometers.

8. The high-voltage semiconductor structure according to claim 7, further comprising a shallow trench isolation located in the substrate. From a cross-sectional view, the second boundary of the second portion of the source drift region is located below the shallow trench isolation.

9. The high-voltage semiconductor structure according to claim 5, further comprising a ring-shaped ion trap surrounding the gate structure, the source drift region, and the drain drift region. The ring-shaped ion trap has the first conductivity type.

10. The high-voltage semiconductor structure according to claim 9, wherein the gate doping region includes a third boundary adjacent to the ring-shaped ion trap, and the third boundary extends along the first direction. Along the second direction, there is no other doping region in the substrate between the third boundary and the ring-shaped ion trap.

11. The high-voltage semiconductor structure according to claim 3, wherein the first portion of the source drift region partially overlaps with the gate doping region from a top view.

12. The high-voltage semiconductor structure as claimed in claim 3, wherein, when viewed from a top view, the area of the gate doping region is smaller than the area of the gate structure.

13. The high-voltage semiconductor structure as claimed in claim 1, wherein, when viewed from a top view, the width of the first part of the drain drift region is smaller than the width of the gate structure, and the width of the second part of the drain drift region is greater than the width of the gate structure.

14. The high-voltage semiconductor structure as claimed in claim 1, further comprising a source heavily doped region located on the source drift region and a drain heavily doped region located on the drain drift region, wherein the source heavily doped region and the drain heavily doped region have the second conductivity type.

15. A method for forming a high-voltage semiconductor structure, comprising: providing a substrate having a first conductivity type; forming a gate structure on the substrate; forming a source drift region and a drain drift region respectively in the substrate on two sides of the gate structure, wherein, when viewed from a top view, the source drift region and the drain drift region each comprise a first part and a second part, the width of the first part is smaller than the width of the second part, the first part and the second part are directly connected, and the source drift region and the drain drift region present a T-shaped configuration when viewed from a top view, and the source drift region and the drain drift region have a second conductivity type.

16. The method for forming a high-voltage semiconductor structure as claimed in claim 15, wherein the first parts of the source drift region and the drain drift region are close to the gate structure, and the second parts of the source drift region and the drain drift region are far from the gate structure.

17. The method for forming a high-voltage semiconductor structure as claimed in claim 15, further comprising forming a gate doping region in the substrate under the gate structure, wherein, when viewed from a top view, the gate doping region is rectangular and has four corners, and the gate doping region has the first conductivity type.

18. The method for forming a high-voltage semiconductor structure as claimed in claim 17, wherein, when viewed from a top view, the four corners of the gate doping region do not overlap partially with the source drift region and the drain drift region.

19. The method for forming a high-voltage semiconductor structure as claimed in claim 15, wherein, when viewed from a top view, the width of the first part of the source drift region is smaller than the width of the gate structure, and the width of the second part of the source drift region is greater than the width of the gate structure.

20. The method for forming a high-voltage semiconductor structure as claimed in claim 15, further comprising forming an annular ion trap surrounding the gate structure, the source drift region and the drain drift region, and the annular ion trap has the first conductivity type.

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