Fin field effect transistor and preparation method thereof

Abstract

The invention discloses a fin field effect transistor and a preparation method thereof, and belongs to the technical field of semiconductors. The fin field effect transistor comprises a substrate; the fin type semiconductor structure is located on the substrate; the fin type semiconductor structure comprises a source electrode region, a body region, a drain electrode region, a drift region and a first buried layer region, the drift region, the body region and the source electrode region are sequentially connected in the first direction, and the first buried layer region and the drift region are connected in the second direction. The first buried layer region and the drift region are symmetrically arranged along a plane perpendicular to the second direction, the doping type of the first buried layer region is opposite to that of the drift region, and the drain region is located on the drift region and the first buried layer region; and the gate structure covers the upper surface of the body region and the two side surfaces distributed along the second direction, and extends to the upper surface of the substrate. According to the invention, the source-drain breakdown voltage can be improved, and the high-voltage electric field is optimized.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to a fin field-effect transistor and a preparation method thereof. Background Art

[0002] Modern power electronics technology requires the chip system to develop towards high frequency, integration, and intelligence. The BCD (Bipolar-CMOS-DMOS) process is the key to realizing this trend. The BCD process can fabricate bipolar, CMOS, and DMOS devices on the same chip, greatly reducing the chip area. Among them, DMOS is the key to improving the power and integration of BCD chips. Common DMOS devices include LDMOS and VDMOS devices. Regardless of the direction of the conduction current flow, the gate oxide layer of LDMOS and VDMOS processes is a planarized design similar to CMOS. To improve the current passing ability, it is necessary to increase the channel width, thus occupying a larger wafer area and increasing the manufacturing cost.

[0003] The fin field-effect transistor of advanced processes changes the transistor conductive channel from a two-dimensional planar structure to a three-dimensional structure, improving the current passing ability. With the same source-drain spacing, the on-resistance of the device can be reduced by increasing the fin height and density, and there is no need to separately increase the fin width. However, the source-drain breakdown voltage of the fin field-effect transistor in related technologies is insufficient, which limits its application in the BCD process. Summary of the Invention

[0004] This application aims to solve at least one of the technical problems existing in the prior art. For this purpose, this application provides a fin field-effect transistor and a preparation method thereof, which can improve the source-drain breakdown voltage and optimize the high-voltage electric field.

[0005] In a first aspect, this application provides a fin field-effect transistor, including:

[0006] A substrate;

[0007] A fin semiconductor structure located on the substrate; the fin semiconductor structure includes a source region, a body region, a drain region, a drift region, and a first buried layer region. The drift region, the body region, and the source region are connected in sequence along a first direction. The first buried layer region and the drift region are connected along a second direction, and the first buried layer region and the drift region are symmetrically arranged along a plane perpendicular to the second direction. The doping types of the first buried layer region and the drift region are opposite, and the drain region is located on the drift region and the first buried layer region; the first direction is perpendicular to the second direction;

[0008] A gate structure covering the upper surface of the body region and both side surfaces distributed along the second direction and extending to the upper surface of the substrate.

[0009] For the fin field-effect transistor according to the present application, by providing a drift region between the drain region and the body region, the source-drain breakdown voltage is increased. By providing a first buried layer region connected to the drift region along a second direction, and the doping type of the first buried layer region is opposite to that of the drift region, to assist the depletion of the drift region, optimize the high-voltage electric field, and further increase the source-drain breakdown voltage.

[0010] According to an embodiment of the present application, the fin semiconductor structure further includes a second buried layer region;

[0011] The second buried layer region is located at the bottom of the drift region, and the second buried layer region is connected to the first buried layer region along the second direction, and the doping type of the second buried layer region is the same as that of the drift region.

[0012] According to an embodiment of the present application, the drift region includes two drift sub-regions symmetrically arranged with respect to a plane perpendicular to the second direction, and the two drift sub-regions are respectively located on both sides of the first buried layer region distributed along the second direction;

[0013] The second buried layer region includes two second buried layer sub-regions, the two second buried layer sub-regions are respectively located on both sides of the first buried layer region distributed along the second direction, and the two second buried layer sub-regions are respectively located at the bottoms of the two drift sub-regions.

[0014] According to an embodiment of the present application, the first buried layer region includes two first buried layer sub-regions symmetrically arranged with respect to a plane perpendicular to the second direction, and the two first buried layer sub-regions are respectively located on both sides of the drift region and the second buried layer region distributed along the second direction.

[0015] According to an embodiment of the present application, the doping types of the drain region, the second buried layer region, and the drift region are the same, and the doping concentrations of the drain region, the second buried layer region, and the drift region decrease in sequence.

[0016] According to an embodiment of the present application, the fin field-effect transistor further includes:

[0017] A field plate, located on the drift region and the first buried layer region, and between the body region and the drain region.

[0018] According to an embodiment of the present application, the gate structure also covers the upper surface and the two side surfaces distributed along the second direction of part of the field plate, and extends to the upper surface of the substrate.

[0019] According to an embodiment of the present application, the gate structure includes a gate oxide layer and a gate;

[0020] The gate oxide layer covers the upper surface of the body region and the two side surfaces distributed along the second direction; the gate covers the gate oxide layer and extends to the upper surface of the substrate.

[0021] According to an embodiment of the present application, the fin field-effect transistor further includes:

[0022] A protective layer that covers the upper surface of the fin semiconductor structure and the two side surfaces distributed along the second direction, and covers the gate structure.

[0023] According to an embodiment of the present application, the fin field-effect transistor further includes:

[0024] An isolation structure that is located on the substrate and is disposed around the peripheral side of the fin semiconductor structure.

[0025] According to an embodiment of the present application, the fin field-effect transistor further includes:

[0026] A drain metal electrode that is located on the drain region and is connected to the drain region;

[0027] A source metal electrode that is located on the source region and is connected to the source region;

[0028] A gate metal electrode that is located on the gate structure and is connected to the gate structure.

[0029] According to an embodiment of the present application, the substrate includes a substrate and a spacer layer;

[0030] The spacer layer is located on the substrate, the fin semiconductor structure is located on the spacer layer, the gate structure covers the upper surface of the body region and the two side surfaces distributed along the second direction, and extends to the upper surface of the spacer layer.

[0031] In a second aspect, the present application provides a method for manufacturing a fin field-effect transistor, including:

[0032] Providing a substrate;

[0033] Forming a fin semiconductor structure on the substrate;

[0034] Forming a first buried layer region, a drift region, and a body region in the fin semiconductor structure, the drift region and the body region are connected along a first direction, the first buried layer region and the drift region are connected along a second direction, and the first buried layer region and the drift region are symmetrically disposed along a plane perpendicular to the second direction, the doping types of the first buried layer region and the drift region are opposite; the second direction is perpendicular to the first direction;

[0035] Cover a gate structure on the upper surface of the body region and on both side surfaces distributed along the second direction, and the gate structure extends to the upper surface of the substrate;

[0036] Form a source region and a drain region in the fin-type semiconductor structure, the source region is located on one side of the body region away from the drift region, and the drain region is located on the drift region and the first buried layer region.

[0037] According to an embodiment of the present application, the method further includes:

[0038] Form a second buried layer region in the fin-type semiconductor structure, the second buried layer region is located at the bottom of the drift region, and the second buried layer region is connected to the first buried layer region along the second direction, and the doping type of the second buried layer region is the same as that of the drift region.

[0039] According to an embodiment of the present application, the method further includes:

[0040] Etch a groove on the fin-type semiconductor structure, and the groove is located between the drain region and the body region;

[0041] Fill a field plate in the groove.

[0042] One or more of the above technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0043] By setting a drift region between the drain region and the body region, the source-drain breakdown voltage is increased. By setting a first buried layer region connected to the drift region, and the doping type of the first buried layer region is opposite to that of the drift region, to assist the drift region to deplete, optimize the high-voltage electric field, and further increase the source-drain breakdown voltage. Moreover, the fin-type field effect transistor adopts a three-dimensional conductive channel design, making the device have a higher power density and transistor density.

[0044] The additional aspects and advantages of the present application will be partially given in the following description, partially will become obvious from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The above and / or additional aspects and advantages of the present application will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, in which:

[0046] Figure 1 is one of the structural schematic diagrams of the fin-type field effect transistor provided by the embodiment of the present application;

[0047] Figure 2 is one of the cross-sectional schematic diagrams of the fin-type field effect transistor provided by the embodiment of the present application;

[0048] Figure 3It is the second cross-sectional schematic diagram of the fin field-effect transistor provided by the embodiment of the present application;

[0049] Figure 4 It is the third cross-sectional schematic diagram of the fin field-effect transistor provided by the embodiment of the present application;

[0050] Figure 5 It is the fourth cross-sectional schematic diagram of the fin field-effect transistor provided by the embodiment of the present application;

[0051] Figure 6 It is the second structural schematic diagram of the fin field-effect transistor provided by the embodiment of the present application;

[0052] Figure 7 It is the fifth cross-sectional schematic diagram of the fin field-effect transistor provided by the embodiment of the present application;

[0053] Figure 8 It is the sixth cross-sectional schematic diagram of the fin field-effect transistor provided by the embodiment of the present application;

[0054] Figure 9 It is the seventh cross-sectional schematic diagram of the fin field-effect transistor provided by the embodiment of the present application;

[0055] Figure 10 It is the eighth cross-sectional schematic diagram of the fin field-effect transistor provided by the embodiment of the present application;

[0056] Figure 11 It is the process schematic diagram of the preparation method of the fin field-effect transistor provided by the embodiment of the present application. Detailed implementation manners

[0057] The embodiments of the present application will be described in detail below. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions from beginning to end. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and should not be construed as a limitation of the present application.

[0058] The fin field-effect transistor and its preparation method provided by the embodiment of the present application will be described below with reference to the accompanying drawings.

[0059] Figure 1 and Figure 6 is the structural schematic diagram of the fin field-effect transistor provided by the embodiment of the present application. Among them, the fin field-effect transistor can be a fin high-voltage DMOS device.

[0060] As Figure 1 shown, the fin field-effect transistor provided by the embodiment of the present application includes a substrate 1, a fin semiconductor structure 2, and a gate structure 3.

[0061] The fin-type semiconductor structure 2 is located on the substrate 1, that is, the fin-type semiconductor structure 2 is located on one side of the substrate 1 along the thickness direction X. The fin-type semiconductor structure 2 extends along the first direction Y on the substrate 1, and the first direction Y is perpendicular to the thickness direction X. The fin-type semiconductor structure 2 constitutes a fin-type active region.

[0062] Combined Figure 3 with Figure 7 shown, Figure 3 it is Figure 1 a cross-sectional schematic diagram at the dashed line B1B1' in Figure 7 and is Figure 6 a cross-sectional schematic diagram at the dashed line A2A2' in. The fin-type semiconductor structure 2 includes a drain region 21, a source region 22, a drift region 23, a first buried layer region 24, and a body region 25. The drift region 23, the body region 25, and the source region 22 are connected in sequence along the first direction Y, that is, the body region 25 is located between the drift region 23 and the source region 22, and the body region 25 is in contact with the drift region 23 and the source region 22 respectively.

[0063] The source region 22 can extend from the upper surface of the fin-type semiconductor structure 2 (that is, the surface of the fin-type semiconductor structure 2 facing away from the substrate 1) along the thickness direction X to the lower surface of the fin-type semiconductor structure 2 (that is, the surface of the fin-type semiconductor structure 2 close to the substrate 1), that is, the height of the source region 22 along the thickness direction H is the same as the height of the fin-type semiconductor structure 2 along the thickness direction H, and the width of the source region 22 along the second direction Z is the same as the width of the fin-type semiconductor structure 2 along the second direction Z. The body region 25 can extend from the upper surface of the fin-type semiconductor structure 2 along the thickness direction X to the lower surface of the fin-type semiconductor structure 2, that is, the height of the body region 25 along the thickness direction H is the same as the height of the fin-type semiconductor structure 2 along the thickness direction H, and the width of the body region 25 along the second direction Z is the same as the width of the fin-type semiconductor structure 2 along the second direction Z. The second direction Z is perpendicular to the first direction Y and the thickness direction X respectively.

[0064] Among them, the source region 22 has a first doping type, and the first doping type can be N-type or P-type. The body region 25 has a second doping type, and the second doping type can be N-type or P-type. The first doping type is opposite to the second doping type, that is, the doping type of the body region 25 is opposite to the doping type of the source region 22. The drift region 23 has a first doping type, that is, the doping type of the drift region 23 is opposite to the doping type of the body region 25.

[0065] It should be noted that the fin-type field-effect transistor can be an N-type field-effect transistor or a P-type field-effect transistor. When the fin-type field-effect transistor is an N-type field-effect transistor, the first doping type is N-type and the second doping type is P-type; when the fin-type field-effect transistor is a P-type field-effect transistor, when the first doping type is P-type, the second doping type is N-type.

[0066] The first buried layer region 24 and the drift region 23 are connected along the second direction Z. The drift region 23 and the first buried layer region 24 are arranged and in contact with each other along the second direction Z, and the arrangement order of the drift region 23 and the first buried layer region 24 along the second direction Z is not specifically limited. Combining Figure 2 and Figure 8 as shown, Figure 2 is Figure 1 a cross-sectional schematic diagram at the dashed line A1A1' in Figure 8 is Figure 6 a cross-sectional schematic diagram at the dashed line B2B2' in . The length of the first buried layer region 24 along the first direction Y can be less than or equal to the length of the drift region 23 along the first direction Y. The first buried layer region 24 can extend along the first direction Y to the body region 25 and be in contact with the body region 25, or the first buried layer region 24 can also not extend to the body region 25 and be arranged at an interval from the body region 25. The height of the drift region 23 along the thickness direction H can be less than or equal to the height of the fin semiconductor structure 2 along the thickness direction H, and the width of the drift region 23 along the second direction Z can be less than or equal to the width of the fin semiconductor structure 2 along the second direction Z. The height of the first buried layer region 24 along the thickness direction H can be less than or equal to the height of the fin semiconductor structure 2 along the thickness direction H, and the width of the first buried layer region 24 along the second direction Z can be less than or equal to the width of the fin semiconductor structure 2 along the second direction Z.

[0067] The first buried layer region 24 and the drift region 23 are symmetrically arranged respectively along a plane perpendicular to the second direction Z to maintain the uniformity of the electric field distribution. The first buried layer region 24 has a second doping type, that is, the doping type of the first buried layer region 24 is opposite to the doping type of the drift region 23, so that a PN heterojunction is formed between the first buried layer region 24 and the drift region 23.

[0068] The drain region 21 is located on the drift region 23 and the first buried layer region 24, and the drain region 21 is arranged close to the upper surface of the fin semiconductor structure 2. The drain region 21 and the body region 25 are arranged at an interval along the first direction Y, and the drift region 23 and the first buried layer region 24 are provided between the drain region 21 and the body region 25. The width of the drain region 21 along the second direction Z is the same as the width of the fin semiconductor structure 2 along the second direction Z. The drain region 21 has a first doping type, that is, the doping type of the drift region 23 is the same as that of the drain region 21.

[0069] Combining Figure 4 and Figure 9 as shown, Figure 4 is Figure 1 a cross-sectional schematic diagram at the dashed line C1C1' in Figure 9 is Figure 6A schematic cross-sectional view at the dashed line C2C2' in the middle. The gate structure 3 covers the upper surface of the body region 25 (i.e., the surface of the body region 25 facing away from the substrate 1) and the two side surfaces of the body region 25 distributed along the second direction Z, and extends to the upper surface of the substrate 1 (i.e., the surface of the substrate 1 close to the fin structure 2), that is, the gate structure 3 also covers a part of the upper surface of the substrate 1.

[0070] In this embodiment, a drift region 23 is added between the drain region 21 and the body region 25 to increase the breakdown voltage between the source and the drain. Moreover, a first buried layer region 24 is provided. The first buried layer region 24 is connected to the drift region 23 along the second direction Z. The doping types of the first buried layer region 24 and the drift region 23 are opposite, forming a PN heterojunction to assist in the depletion of the drift region, optimize the high-voltage electric field, and further increase the source-drain breakdown voltage and robustness of the device. Moreover, the fin field-effect transistor adopts a three-dimensional conductive channel design, enabling the device to have a higher power density and transistor density.

[0071] In some embodiments, the fin semiconductor structure further includes a second buried layer region 26. The second buried layer region 26 is located at the bottom of the drift region 23, that is, the second buried layer region 26 is located on the side of the drift region 23 close to the substrate 1, and the second buried layer region 26 is in contact with the drift region 23. The length of the second buried layer region 26 along the first direction Y can be the same as the length of the drift region 23 along the first direction Y, that is, the second buried layer region 26 can extend along the first direction Y to the body region 25 and be in contact with the body region 25. The width of the second buried layer region 26 along the second direction Z can be the same as the width of the drift region 23 along the second direction Z.

[0072] The second buried layer region 26 is connected to the first buried layer region 24 along the second direction Z, that is, the second buried layer region 26 is arranged and in contact with the first buried layer region 24 along the second direction. The second buried layer region 26 has a first doping type, that is, the doping type of the second buried layer region 26 is the same as the doping type of the drift region 23.

[0073] In this embodiment, a second buried layer region 26 is provided at the bottom of the drift region 23, and the doping type of the second buried layer region 26 is the same as that of the drift region 23 to reduce the on-resistance of the device.

[0074] In some embodiments, the doping types of the drain region 21, the second buried layer region 26, and the drift region 23 are the same, and the doping concentrations of the drain region 21, the second buried layer region 26, and the drift region 23 decrease in sequence, that is, the doping concentration of the drain region 21 is greater than the doping concentration of the second buried layer region 26, and the doping concentration of the second buried layer region 26 is greater than the doping concentration of the drift region 23.

[0075] In this embodiment, the doping concentrations of the drain region 21, the second buried layer region 26, and the drift region 23 decrease in sequence to modulate the on-resistance of the drift region 212, thereby reducing the on-resistance of the device.

[0076] In some embodiments, such asFigure 1 and Figure 5 as shown, Figure 5 is Figure 1 a schematic cross-sectional view at the dashed line D1D1' in. The drift region 23 includes two drift sub-regions 23a and 23b symmetrically arranged along a plane perpendicular to the second direction Z. The two drift sub-regions 23a and 23b are respectively located on both sides of the first buried layer region 24 distributed along the second direction Z, and the two drift sub-regions 23a and 23b are respectively in contact with the first buried layer region 24.

[0077] The drain region 21 is located on the first buried layer region 24 and the two drift sub-regions 23a and 23b. The first buried layer region 24 and the two drift sub-regions 23a and 23b are provided between the drain region 21 and the body region 25 to increase the source-drain breakdown voltage, and the first buried layer region 24 forms PN heterojunctions with the two drift sub-regions 23a and 23b respectively to assist the depletion of the two drift sub-regions 23a and 23b, optimize the high-voltage electric field, and further increase the source-drain breakdown voltage.

[0078] When the fin-type semiconductor structure 2 further includes a second buried layer region 26, the second buried layer region 26 includes two second buried layer sub-regions 26a and 26b. The two second buried layer sub-regions 26a and 26b can be symmetrically arranged along a plane perpendicular to the second direction Z. The two second buried layer sub-regions 26a and 26b are respectively located on both sides of the first buried layer region 24 distributed along the second direction Z, and the two second buried layer sub-regions 26a and 26b are respectively in contact with the first buried layer region 24. The two second buried layer sub-regions 26a and 26b are respectively located at the bottoms of the two drift sub-regions 23a and 23b, and the two second buried layer sub-regions 26a and 26b are respectively in contact with the bottoms of the two drift sub-regions 23a and 23b.

[0079] The total height of the drift region 23 and the second buried layer region 26 in the thickness direction X can be less than the height of the first buried layer region 24 in the thickness direction X. As Figure 3 shown, the bottom of the second buried layer region 26 has the first buried layer region 24, and the bottom of the second buried layer region 26 is in contact with the first buried layer region 24.

[0080] In some embodiments, as Figure 6 and Figure 10 shown, Figure 10 is Figure 6 a schematic cross-sectional view at the dashed line D2D2' in. The first buried layer region 24 includes two first buried layer sub-regions 24a and 24b symmetrically arranged along a plane perpendicular to the second direction Z. The two first buried layer sub-regions 24a and 24b are respectively located on both sides of the drift region 23 distributed along the second direction, and the two first buried layer sub-regions 24a and 24b are respectively in contact with the drift region 23.

[0081] The drain region 21 is located on the drift region 23 and two first buried sub-regions 24a and 24b. A drift region 23 and two first buried sub-regions 24a and 24b are provided between the drain region 21 and the body region 25 to increase the source-drain breakdown voltage, and the drift region 23 forms PN heterojunctions with the two first buried sub-regions 24a and 24b respectively to assist in the depletion of the drift region 23, optimize the high-voltage electric field, and further increase the source-drain breakdown voltage.

[0082] When the fin semiconductor structure 2 further includes a second buried region 26, the two first buried sub-regions 24a and 24b are also respectively located on both sides of the second buried region 26 along the second direction Z, that is, the two first buried sub-regions 24a and 24b are respectively located on both sides of the drift region 23 and the second buried region 26 along the second direction Z. The two first buried sub-regions 24a and 24b are respectively in contact with the second buried region 26. The second buried region 26 is located at the bottom of the drift region 23, and the second buried region 26 is in contact with the bottom of the drift region 23.

[0083] In some embodiments, the fin field-effect transistor further includes a field plate 4. The field plate 4 is located on the drift region 23 and the first buried region 24. A groove may be provided on the upper surface of the fin semiconductor structure 2, and the field plate 4 is located in the groove. The upper surface of the field plate 4 may be flush with the upper surface of the drain region 21. The field plate 4 is located between the body region 25 and the drain region 21. The field plate 4 may be in contact with the drain region 21, the field plate 4 and the body region 25 are spaced apart, and there is a drift region 23 and a first buried region 24 between the field plate 4 and the body region 25. Among them, the field plate 4 may include insulating dielectric materials such as SiO2, Si3N4, and SiC.

[0084] In this embodiment, a field plate 4 is provided between the drain region 21 and the body region 25, which can reduce the surface electric field and further increase the source-drain breakdown voltage.

[0085] In some embodiments, the gate structure 3 also covers the upper surface and the two side surfaces along the second direction Z of a part of the field plate 4 and extends to the upper surface of the substrate 1.

[0086] The gate structure 3 may cover the upper surface of the body region 25, the upper surface of the drift region 23 (and the first buried region 24) between the body region 25 and the field plate 4, and the upper surface of a part of the field plate 4 (a part of the structure of the field plate 4 close to the body region 25), and along the two side surfaces of the fin semiconductor structure 2 along the second direction Z, and extends to the upper surface of the substrate 1.

[0087] In this embodiment, the gate structure 3 also covers a part of the field plate 4, which can use the gate voltage to balance the high voltage at the drain end and improve the voltage withstand characteristics of the device.

[0088] In some embodiments, the gate structure 3 includes a gate oxide layer 31 and a gate 32. The gate oxide layer 31 covers the upper surface of the body region 25 and the two side surfaces of the body region 25 distributed along the second direction Z. The gate 32 covers the gate oxide layer 31 and extends to the upper surface of the substrate 1, that is, the gate 32 completely covers the gate oxide layer 31 and also covers a part of the upper surface of the substrate 1. Among them, the gate oxide layer 31 may include dielectric materials such as SiO2, SiON, HfO2, etc. The gate 32 may include polysilicon or metal, etc.

[0089] In some embodiments, as Figures 2 to 5 and Figures 7 to 10 shown, the fin field-effect transistor further includes a protective layer 5. The protective layer 5 covers the upper surface of the fin semiconductor structure 2 and the two side surfaces of the fin semiconductor structure 2 distributed along the second direction Z, and covers the gate structure 3 to protect the fin structure 2 and the gate structure 3.

[0090] In the case where the fin field-effect transistor further includes a field plate 4, the protective layer 5 also covers the field plate 4 to protect the field plate 4. Among them, the protective layer 5 may include Si3N4, etc.

[0091] In some embodiments, as Figure 4 , Figure 5 , Figure 9 and Figure 10 shown, the fin field-effect transistor further includes an isolation structure 6. The isolation structure 6 is located on the substrate 1 and is disposed around the peripheral side of the fin semiconductor structure 2. The isolation structure 6 is used to isolate the fin field-effect transistor from other transistors. Among them, the isolation structure 6 may include BPSG (Boro-Phospho-Silicate Glass).

[0092] In some embodiments, as Figures 2 to 4 and Figures 7 to 9 shown, the fin field-effect transistor further includes a drain metal electrode 71, a source metal electrode 72, and a gate metal electrode 73. The drain metal electrode 71, the source metal electrode 72, and the gate metal electrode 73 may be located on the same side of the fin semiconductor structure 2 (that is, the side of the fin semiconductor structure 2 facing away from the substrate 1). The drain metal electrode 71 is located on the drain region 21 and is connected to the drain region 21. The source metal electrode 72 is located on the source region 22 and is connected to the source region 22. The gate metal electrode 73 is located on the gate structure 3 and is connected to the gate structure 3. Among them, the gate metal electrode 73 is located on the gate 32 in the gate structure 3 and is connected to the gate 32.

[0093] In the case where the fin field-effect transistor further includes a protective layer 5, the drain metal electrode 71, the source metal electrode 72, and the gate metal electrode 73 are respectively located on the side of the protective layer 5 away from the substrate 1. The drain metal electrode 71 penetrates through the protective layer 5 and is connected to the drain region 21. The source metal electrode 72 penetrates through the protective layer 5 and is connected to the source region 22. The gate metal electrode 73 penetrates through the protective layer 5 and is connected to the gate 32 in the gate structure 3.

[0094] Among them, the drain metal electrode 71, the source metal electrode 72, and the gate metal electrode 73 can all include metal materials such as tungsten.

[0095] In some embodiments, as Figure 1 and Figure 6 shown, the substrate 1 includes a substrate 11 and a spacer layer 12. The spacer layer 12 is located on the substrate 1, the fin semiconductor structure 2 is located on the spacer layer 12, the gate structure 3 covers the upper surface of the body region 25 and the two side surfaces of the body region 25 distributed along the second direction Z, and extends to the upper surface of the spacer layer 12 (the surface of the spacer layer 12 close to the fin semiconductor structure side). Among them, the gate oxide layer 31 in the gate structure 3 can cover the upper surface of the body region 25 and the two side surfaces of the body region 25 distributed along the second direction Z, and the gate 32 in the gate structure 3 can cover the gate oxide layer 31 and extend to the upper surface of the spacer layer 12. The isolation structure 6 can be located on the spacer layer 12 and is arranged around the peripheral side of the fin structure 2.

[0096] Among them, the substrate 11 can be a silicon substrate or silicon-on-insulator (SOI), or can also be a semiconductor substrate including other elements. The substrate 11 has a second doping type. The spacer layer 12 can include silicon oxide, etc.

[0097] According to the fin field-effect transistor provided by the embodiments of the present application, by providing a drift region 23 between the drain region 21 and the body region 25, the source-drain breakdown voltage is increased. By providing a first buried layer region 24 connected to the drift region 23, and the doping type of the first buried layer region 24 is opposite to that of the drift region 23, to assist the depletion of the drift region and optimize the high-voltage electric field, further increasing the source-drain breakdown voltage. A second buried layer region 26 is provided at the bottom of the drift region 23, and the doping type of the second buried layer region 26 is the same as that of the drift region 23, to reduce the on-resistance of the device. A field plate 4 is provided between the drain region 21 and the body region 25, further increasing the source-drain breakdown voltage. Moreover, the fin field-effect transistor adopts a three-dimensional conductive channel design, making the device have a higher power density and transistor density. Compared with conventional DMOS devices, this embodiment enhances the current passing ability and can realize the BCD process integration of advanced process nodes.

[0098] Correspondingly, the embodiments of the present application also provide a preparation method of a fin field-effect transistor, which can fabricate the fin field-effect transistor in the above embodiments.

[0099] As Figure 11 shown, the method for manufacturing a fin field effect transistor provided by an embodiment of the present application includes steps 110 to 150.

[0100] Step 110: Provide a substrate.

[0101] In some embodiments, as Figure 1 and Figure 6 shown, the substrate 1 includes a substrate 11 and a spacer layer 12, and the spacer layer 12 is located on the substrate 11. For example, by using a thin film deposition process, the spacer layer 12 is formed on the substrate 11.

[0102] Among them, the substrate 11 may be a silicon substrate or a silicon-on-insulator (SOI), or may also be a semiconductor substrate including other elements. The substrate 11 has a second doping type, and the second doping type may be a P-type or an N-type.

[0103] Step 120: Form a fin semiconductor structure on the substrate.

[0104] As Figure 1 and Figure 6 shown, a fin semiconductor structure 2 is epitaxially grown on the substrate 1, and the fin semiconductor structure 2 constitutes a fin active region.

[0105] Step 130: Form a first buried layer region, a drift region, and a body region in the fin semiconductor structure. The drift region and the body region are connected along a first direction, the first buried layer region and the drift region are connected along a second direction, and the first buried layer region and the drift region are symmetrically arranged with respect to a plane perpendicular to the second direction, and the doping types of the first buried layer region and the drift region are opposite; the second direction is perpendicular to the first direction.

[0106] As Figure 1 and Figure 6 shown, a first buried layer region 24 is formed in the fin semiconductor structure 2 by ion implantation (Implantation, IMP). The first buried layer region 24 has a second doping type.

[0107] In some embodiments, the method for manufacturing the fin field effect transistor further includes:

[0108] Form a second buried layer region in the fin semiconductor structure. The second buried layer region is located at the bottom of the drift region, and the second buried layer region is connected to the first buried layer region along the second direction, and the doping types of the second buried layer region and the drift region are the same.

[0109] As Figure 1 and Figure 6As shown, after forming the first buried layer region 24, the second buried layer region 26 can be formed in the fin-type semiconductor structure 2 by ion implantation. The second buried layer region 26 has a first doping type, and the first doping type is N-type or P-type. The first doping type is opposite to the second doping type.

[0110] It should be noted that the fin-type field effect transistor can be an N-type field effect transistor or a P-type field effect transistor. When the fin-type field effect transistor is an N-type field effect transistor, the first doping type is N-type and the second doping type is P-type; when the fin-type field effect transistor is a P-type field effect transistor, when the first doping type is P-type, the second doping type is N-type.

[0111] Then, as Figure 1 and Figure 6 shown, the drift region 23 is formed in the fin-type semiconductor structure 2 by ion implantation. The drift region 23 has the first doping type. Then, as Figure 3 and Figure 7 shown, the body region 25 is formed in the fin-type semiconductor structure 2 by ion implantation. The body region 25 has the second doping type.

[0112] The drift region 23 and the body region 25 are connected along the first direction Y, the first buried layer region 24 and the drift region 23 are connected along the second direction Z, and the first buried layer region 24 and the drift region 23 are symmetrically arranged along the plane perpendicular to the second direction Z respectively. The second buried layer region 26 is located at the bottom of the drift region 23, and the second buried layer region 26 is connected to the first buried layer region 24 along the second direction Z.

[0113] In some embodiments, the doping types of the drain region 21, the second buried layer region 26, and the drift region 23 are the same, and the doping concentrations of the drain region 21, the second buried layer region 26, and the drift region 23 decrease in sequence to modulate the on-resistance of the drift region 212, thereby reducing the on-resistance of the device.

[0114] In some embodiments, as Figure 1 and Figure 5 shown, the drift region 23 includes two drift sub-regions 23a and 23b that are symmetrically arranged along the plane perpendicular to the second direction Z. The two drift sub-regions 23a and 23b are respectively located on both sides of the first buried layer region 24 distributed along the second direction Z. The second buried layer region 26 includes two second buried layer sub-regions 26a and 26b. The two second buried layer sub-regions 26a and 26b are respectively located on both sides of the first buried layer region 24 distributed along the second direction Z, and the two second buried layer sub-regions 26a and 26b are respectively located at the bottoms of the two drift sub-regions 23a and 23b.

[0115] In some embodiments, as Figure 6 and Figure 10As shown, the first buried layer region 24 includes two first buried layer sub-regions 24a and 24b symmetrically arranged along a plane perpendicular to the second direction Z. The two first buried layer sub-regions 24a and 24b are respectively located on both sides of the drift region 23 distributed along the second direction. The two first buried layer sub-regions 24a and 24b are also respectively located on both sides of the second buried layer region 26 distributed along the second direction Z, that is, the two first buried layer sub-regions 24a and 24b are respectively located on both sides of the drift region 23 and the second buried region 26 distributed along the second direction Z.

[0116] Step 140 : Covering the upper surface of the body region and two side surfaces distributed along the second direction with a gate structure, and the gate structure extends to the upper surface of the substrate.

[0117] like Figure 4 and Figure 9 As shown, the gate structure 3 covers the upper surface of the body region 25 and two side surfaces of the body region 25 distributed along the second direction Z, and extends to the upper surface of the substrate 1 , that is, the gate structure 3 also covers part of the upper surface of the substrate 1 .

[0118] In some embodiments, the gate structure 3 may include a gate oxide layer 31 and a gate 32. A thin film deposition process is used to cover the gate oxide layer 31 on the upper surface of the body region 25 and the two side surfaces of the body region 25 distributed along the second direction Z. Then, a thin film deposition process is used to form a gate 32 on the gate oxide layer 31. The gate 32 covers the gate oxide layer 31 and extends to the upper surface of the substrate 1. Among them, the gate oxide layer 31 may also include dielectric materials such as SiO2, SiON, and HfO2. The gate 32 may include polysilicon or metal, etc. It should be noted that when the gate 32 is polysilicon, after the gate 32 is formed, the gate 32 needs to be heavily doped.

[0119] Step 150 : forming a source region and a drain region in the fin-type semiconductor structure, wherein the source region is located on a side of the body region away from the drift region, and the drain region is located on the drift region and the first buried layer region.

[0120] like Figure 1 and Figure 6 As shown, ion implantation is used to form a source region 22 and a drain region 21 in the fin-type semiconductor structure 2. The source region 22 and the drain region 21 have a first doping type.

[0121] The drift region 23, the body region 25 and the source region 22 are sequentially connected along the first direction Y, that is, the body region 25 is located between the drift region 23 and the source region 22, and the body region 25 is in contact with the drift region 23 and the source region 22 respectively. The drain region 21 is located on the drift region 23 and the first buried region 24. The drain region 21 and the body region 25 are spaced apart along the first direction Y, and the drift region 23 and the first buried region 24 are provided between the drain region 21 and the body region 25.

[0122] In this embodiment, a drift region 23 is provided between the drain region 21 and the body region 25 to increase the source-drain breakdown voltage. By providing a first buried layer region 24 connected to the drift region 23, and the doping type of the first buried layer region 24 is opposite to that of the drift region 23, to assist the depletion of the drift region, optimize the high-voltage electric field, and further increase the source-drain breakdown voltage. A second buried layer region 26 is provided at the bottom of the drift region 23, and the doping type of the second buried layer region 26 is the same as that of the drift region 23, to reduce the on-resistance of the device.

[0123] In some embodiments, the method for manufacturing the fin field-effect transistor further includes:

[0124] Etching a groove in the fin semiconductor structure, and the groove is located between the drain region and the body region;

[0125] Forming a field plate in the groove.

[0126] As Figure 1 and Figure 6 shown, after forming the body region 25, the upper surface of the fin semiconductor structure 2 can be etched to form a groove. The groove is located between the drain region 21 and the body region 25, and the groove can be adjacent to the drain region 21 and is spaced apart from the body region 25. A field plate 4 is formed in the groove, so that the field plate 4 is located between the drain region 21 and the body region 25, and the field plate 4 is in contact with the drain region 21 and is spaced apart from the body region 25.

[0127] In this embodiment, a field plate 4 is provided between the drain region 21 and the body region 25, which can reduce the surface electric field and further increase the source-drain breakdown voltage.

[0128] In some embodiments, the method for manufacturing the fin field-effect transistor further includes:

[0129] Forming a protective layer that covers the upper surface of the fin semiconductor structure, the two side surfaces of the fin semiconductor structure distributed along the second direction, and covers the gate structure.

[0130] As Figures 2 to 5 and Figures 7 to 10 shown, by using a thin film deposition process and an etching process, a protective layer 5 is formed on the upper surface of the fin semiconductor structure 2, the two side surfaces of the fin semiconductor structure 2 distributed along the second direction Z, and the surface of the gate structure 3 to protect the fin semiconductor structure 2 and the gate structure 3. Among them, the protective layer 5 can include Si3N4, etc.

[0131] It should be noted that openings need to be reserved in the protective layer 5 to expose the drain region 21, the source region 22, and the gate structure 3.

[0132] In some embodiments, the method for manufacturing the fin field-effect transistor further includes:

[0133] A drain metal electrode connected to the drain region is formed on the drain region, a source metal electrode connected to the source region is formed on the source region, and a gate metal electrode connected to the gate structure is formed on the gate structure.

[0134] As Figures 2 to 4 and Figures 7 to 9 shown, using a thin film deposition process, a drain metal electrode 71 connected to the drain region 21, a source metal electrode 72 connected to the source region 22, and a gate metal electrode 73 connected to the gate 32 in the gate structure 3 are respectively formed on the drain region 21, the source region 22, and the gate structure 3. Among them, the drain metal electrode 71, the source metal electrode 72, and the gate metal electrode 73 can all include metal materials such as tungsten.

[0135] In some embodiments, the method for manufacturing the fin field-effect transistor further includes:

[0136] An isolation structure is formed on the substrate, and the isolation structure is disposed around the peripheral side of the fin semiconductor structure.

[0137] As Figure 4 , Figure 5 , Figure 9 and Figure 10 shown, using a thin film deposition process, an isolation structure 6 disposed around the peripheral side of the fin semiconductor structure 2 is formed on the substrate 1. The isolation structure 6 is used to isolate the fin field-effect transistor from other transistors. Among them, the isolation structure 6 can include BPSG.

[0138] It should be noted that the subsequent back-end metal interconnect process can continue, which will not be elaborated in detail here.

[0139] According to the method for manufacturing the fin field-effect transistor provided by the embodiments of the present application, by providing a drift region 23 between the drain region 21 and the body region 25, the source-drain breakdown voltage is increased. By providing a first buried layer region 24 connected to the drift region 23, and the doping type of the first buried layer region 24 is opposite to that of the drift region 23, to assist the depletion of the drift region and optimize the high-voltage electric field, further increasing the source-drain breakdown voltage. A second buried layer region 26 is disposed at the bottom of the drift region 23, and the doping type of the second buried layer region 26 is the same as that of the drift region 23, to reduce the on-resistance of the device. A field plate 4 is disposed between the drain region 21 and the body region 25, further increasing the source-drain breakdown voltage. Moreover, the fin field-effect transistor adopts a three-dimensional conductive channel design, enabling the device to have a higher power density and transistor density. Compared with conventional DMOS devices, this embodiment enhances the current passing ability and can achieve the BCD process integration of advanced process nodes.

[0140] The terms "first", "second", etc. in the description and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances so that the embodiments of this application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same type and do not limit the number of objects. For example, the first object can be one or more.

[0141] In the description of this application, "a plurality" means two or more.

[0142] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0143] Although the embodiments of this application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of this application, and the scope of this application is defined by the claims and their equivalents.

Claims

1. A fin field-effect transistor, characterized in that, Comprising: A substrate; A fin-type semiconductor structure located on the substrate; The fin-type semiconductor structure includes a source region, a body region, a drain region, a drift region, and a first buried layer region. The drift region, the body region, and the source region are sequentially connected in a first direction. The first buried layer region and the drift region are connected in a second direction, and the first buried layer region and the drift region are symmetrically disposed with respect to a plane perpendicular to the second direction. The doping types of the first buried layer region and the drift region are opposite to each other, and the drain region is located on the drift region and the first buried layer region; the first direction is perpendicular to the second direction; A gate structure covering the upper surface of the body region and both side surfaces distributed along the second direction and extending to the upper surface of the substrate.

2. The fin field effect transistor according to claim 1, characterized in that The fin-type semiconductor structure further includes a second buried layer region; The second buried layer region is located at the bottom of the drift region, and the second buried layer region is connected to the first buried layer region in the second direction. The doping type of the second buried layer region is the same as that of the drift region.

3. The fin field-effect transistor according to claim 2, characterized in that The drift region includes two drift sub-regions symmetrically disposed with respect to a plane perpendicular to the second direction, and the two drift sub-regions are respectively located on both sides of the first buried layer region distributed in the second direction; The second buried layer region includes two second buried layer sub-regions, the two second buried layer sub-regions are respectively located on both sides of the first buried layer region distributed in the second direction, and the two second buried layer sub-regions are respectively located at the bottoms of the two drift sub-regions.

4. The fin field effect transistor according to claim 2, wherein The first buried layer region includes two first buried layer sub-regions symmetrically disposed with respect to a plane perpendicular to the second direction, and the two first buried layer sub-regions are respectively located on both sides of the drift region and the second buried layer region distributed in the second direction.

5. The fin field effect transistor according to claim 2, characterized in that The doping types of the drain region, the second buried layer region, and the drift region are the same, and the doping concentrations of the drain region, the second buried layer region, and the drift region decrease in sequence.

6. The fin field effect transistor according to claim 1, wherein The fin-type field effect transistor further includes: A field plate located on the drift region and the first buried layer region and between the body region and the drain region.

7. The fin field effect transistor according to claim 6, characterized in that, The gate structure further covers the upper surface of a part of the field plate and both side surfaces distributed along the second direction and extends to the upper surface of the substrate.

8. The fin field effect transistor according to claim 1, wherein The gate structure includes a gate oxide layer and a gate; The gate oxide layer covers the upper surface of the body region and both side surfaces distributed in the second direction; the gate covers the gate oxide layer and extends to the upper surface of the substrate.

9. The fin field effect transistor according to claim 1, wherein The fin-type field effect transistor further includes: A protective layer covering the upper surface of the fin-type semiconductor structure and both side surfaces distributed along the second direction and covering the gate structure.

10. The fin field effect transistor according to claim 1, characterized in that, The fin-type field effect transistor further includes: An isolation structure located on the substrate and disposed around the peripheral side of the fin-type semiconductor structure.

11. The fin field effect transistor according to claim 1, characterized in that, The fin-type field effect transistor further includes: A drain metal electrode located on the drain region and connected to the drain region; A source metal electrode located on the source region and connected to the source region; A gate metal electrode located on the gate structure and connected to the gate structure.

12. The fin field-effect transistor according to any one of claims 1-11, characterized in that, The substrate includes a substrate and a spacer layer; The spacer layer is located on the substrate, the fin-type semiconductor structure is located on the spacer layer, and the gate structure covers the upper surface of the body region and two side surfaces distributed along the second direction and extends to the upper surface of the spacer layer.

13. A method for manufacturing a fin field effect transistor, characterized in that, include: providing a substrate; forming a fin semiconductor structure on the substrate; A first buried region, a drift region and a body region are formed in the fin-type semiconductor structure, wherein the drift region and the body region are connected along a first direction, the first buried region and the drift region are connected along a second direction, and the first buried region and the drift region are symmetrically arranged along a plane perpendicular to the second direction, respectively, and the first buried region and the drift region have opposite doping types; and the second direction is perpendicular to the first direction; A gate structure is covered on the upper surface of the body region and two side surfaces distributed along the second direction, and the gate structure extends to the upper surface of the substrate; A source region and a drain region are formed in the fin-type semiconductor structure. The source region is located on a side of the body region away from the drift region, and the drain region is located on the drift region and the first buried layer region.

14. The manufacturing method of the fin field effect transistor according to claim 13, characterized in that, The method further comprises: A second buried region is formed in the fin-type semiconductor structure, the second buried region is located at the bottom of the drift region, the second buried region is connected to the first buried region along the second direction, and the second buried region and the drift region have the same doping type.

15. The method for manufacturing a fin field effect transistor according to claim 13 or 14, characterized in that, The method further comprises: Etching a groove on the fin-type semiconductor structure, wherein the groove is located between the drain region and the body region; A field plate is filled in the groove.

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