Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. The semiconductor device comprises a semiconductor body which comprises a first surface and a second surface which are oppositely arranged; the semiconductor body further comprises a well region and a first region; the well region is connected with the first side surface of the first region, and the well region extends to the first bottom surface of the first region and is connected with the first bottom surface; wherein the first bottom surface is opposite to the first surface; the isolation structure is located on the first surface and extends into the first area from the first surface, and the isolation structure and the first side face are arranged in a spaced mode. According to the invention, the breakdown voltage of the semiconductor device can be improved on the premise of not increasing the epitaxial growth time. And the breakdown voltage of the semiconductor device is improved on the premise of not increasing the epitaxial growth time.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) made of third-generation wide-bandgap semiconductors such as silicon carbide or gallium nitride have characteristics such as a large critical breakdown electric field strength, a high thermal conductivity, a large bandgap width, and a high electron saturation drift velocity. This makes third-generation wide-bandgap semiconductor materials such as silicon carbide or gallium nitride become a research hotspot for power semiconductor devices. In high-power application scenarios, such as high-speed railways, hybrid electric vehicles, and intelligent high-voltage DC power transmission, high expectations have been placed on silicon carbide devices.

[0003] An important parameter of a semiconductor device is the breakdown voltage. The pressure-bearing area of a semiconductor device with a planar gate structure is the epitaxial layer. Therefore, at present, for a semiconductor device with a planar gate structure to increase the breakdown voltage, a relatively thick epitaxial layer is required, which brings problems such as an increase in epitaxial growth time and an increase in defects. That is to say, current semiconductor devices cannot meet the two requirements of a relatively short epitaxial growth time and a relatively large breakdown voltage at the same time. Summary of the Invention

[0004] The present invention provides a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle to increase the breakdown voltage of the semiconductor device without increasing the epitaxial growth time.

[0005] According to an aspect of the present invention, a semiconductor device is provided, including:

[0006] A semiconductor body, including a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region and a first region; the first region is set to a first conductivity type and is located on the first surface, and the well region is set to a second conductivity type and is located on the first surface; the well region is in contact with a first side surface of the first region, and the well region extends to a first bottom surface of the first region and is in contact with the first bottom surface; wherein, the first bottom surface is opposite to the first surface;

[0007] An isolation structure, located on the first surface and extending from the first surface into the first region, and the isolation structure is spaced apart from the first side surface;

[0008] A gate, located on the first surface;

[0009] The source electrode is located on the first surface, and the portion of the source electrode in contact with the first surface is located on the side of the isolation structure away from the first side surface.

[0010] Optionally, the first surface is further provided with an isolation groove, the isolation groove extends from the first surface into the first region, the isolation groove is spaced from the first side surface, and the isolation structure is located in the isolation groove.

[0011] Optionally, the semiconductor body further includes a second region, the second region is set to a first conduction type and is located on the first surface, the second region includes a second bottom surface opposite to the first surface, the second region is located on the side of the isolation groove away from the first side surface, and the first region is in contact with the second bottom surface, and the ion concentration of the first region is less than the ion concentration of the second region; the isolation groove is spaced from the second region.

[0012] Optionally, the semiconductor device further includes a first insulating layer;

[0013] The first insulating layer is located on the first surface;

[0014] The gate electrode is located on the side of the first insulating layer away from the first surface;

[0015] The second region further includes a second side surface close to the isolation groove; along the thickness direction of the semiconductor device, the second side surface is flush with the side surface of the first insulating layer.

[0016] Optionally, the depth of the isolation groove is greater than the thickness of the second region.

[0017] Optionally, along the thickness direction of the semiconductor device, the thickness of the first region is 80% - 90% of the maximum thickness of the well region.

[0018] Optionally, along the thickness direction of the semiconductor device, the depth of the isolation groove is 30% - 70% of the maximum thickness of the well region.

[0019] Optionally, the material of the isolation structure includes at least one of silicon dioxide and silicon nitride.

[0020] Optionally, the semiconductor device further includes a drain electrode, and the drain electrode is located on the second surface.

[0021] Optionally, the semiconductor body further includes a third region, the third region is set to a second conduction type and is located on the first surface, and the ion concentration of the third region is greater than the ion concentration of the well region; the third region is located on the side of the first region away from the well region.

[0022] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising:

[0023] Providing a semiconductor body, the semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body further including a well region and a first region; the first region is of a first conductivity type and is located on the first surface, the well region is of a second conductivity type and is located on the first surface; the well region is adjacent to a first side surface of the first region, and the well region extends to a first bottom surface of the first region and is in contact with the first bottom surface; wherein, the first bottom surface is opposite to the first surface;

[0024] Forming an isolation structure, wherein the isolation structure is located on the first surface and extends from the first surface into the first region, and the isolation structure is spaced apart from the first side surface;

[0025] Forming a gate on the first surface;

[0026] Forming a source on the first surface, and a portion of the source in contact with the first surface is located on a side of the isolation structure away from the first side surface.

[0027] Optionally, providing the semiconductor body includes:

[0028] Forming an isolation groove on the first surface of the semiconductor body, the isolation groove extending from the first surface into the first region, and the isolation groove is spaced apart from the first side surface;

[0029] The forming of the isolation structure includes:

[0030] Forming the isolation structure in the isolation groove.

[0031] Optionally, providing the semiconductor body includes:

[0032] Forming the well region on the first surface of the semiconductor body;

[0033] Forming the first region on the first surface of the semiconductor body;

[0034] Forming the isolation groove on the first surface of the semiconductor body.

[0035] Optionally, providing the semiconductor body includes:

[0036] Providing the semiconductor body further including a third region, the third region being of a second conductivity type and located on the first surface, the ion doping concentration of the third region being greater than that of the well region; the third region is located on a side of the first region away from the well region.

[0037] According to another aspect of the present invention, there is provided a power module including a substrate and at least one semiconductor device as described above, and the substrate is used to carry the semiconductor device.

[0038] According to another aspect of the present invention, there is provided a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction;

[0039] The power conversion circuit includes a circuit board and at least one semiconductor device as described above, and the semiconductor device is electrically connected to the circuit board.

[0040] According to another aspect of the present invention, there is provided a vehicle including a load and a power conversion circuit as described above, and the power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

[0041] The technical solution of the embodiment of the present invention uses a semiconductor device including a semiconductor body having a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region and a first region; the first region is of a first conductivity type and is located on the first surface, and the well region is of a second conductivity type and is located on the first surface; the well region is in contact with a first side surface of the first region, and the well region extends to a first bottom surface of the first region and is in contact with the first bottom surface; wherein the first bottom surface is opposite to the first surface; an isolation structure located on the first surface and extending from the first surface into the first region, and the isolation structure is spaced apart from the first side surface; a gate located on the first surface; a source located on the first surface, and a portion of the source in contact with the first surface is located on a side of the isolation structure away from the first side surface. The breakdown voltage is increased by configuring the path of the current in the first region, without the need to extend the path in the epitaxial layer to increase the breakdown voltage. The semiconductor device of this embodiment does not need to increase the thickness of the epitaxial layer in the semiconductor body to increase the breakdown voltage of the semiconductor device.

[0042] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Description of the Drawings

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0044] Figure 1Schematic diagram of a semiconductor device provided by an embodiment of the present invention;

[0045] Figure 2 is Figure 1 Current path diagram of the semiconductor device in;

[0046] Figure 3 Schematic diagram of another semiconductor device provided by an embodiment of the present invention;

[0047] Figure 4 Flowchart of a manufacturing method of a semiconductor device provided by an embodiment of the present invention;

[0048] Figures 5 - 9 Schematic diagram of the product structure corresponding to the main steps of the manufacturing method of the semiconductor device provided by an embodiment of the present invention. Detailed implementation manners

[0049] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0050] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0051] Figure 1 Schematic diagram of a semiconductor device provided by an embodiment of the present invention, referring to Figure 1. The semiconductor device includes: a semiconductor body 100, an isolation structure 200, a gate 302, and a source 400. The semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite to each other; the semiconductor body 100 further includes a well region 103 and a first region 104; the first region 104 is of a first conduction type and is located on the first surface 101, and the well region 103 is of a second conduction type and is located on the first surface 101; the well region 103 is adjacent to a first side surface 1041 of the first region 104, and the well region 103 extends to a first bottom surface 1042 of the first region 104 and is adjacent to the first bottom surface 1042; wherein, the first bottom surface 1042 is opposite to the first surface 101; the isolation structure 200 is located on the first surface 101 and extends from the first surface 101 into the first region 104, and the isolation structure 200 is spaced apart from the first side surface 1041; the gate 302 is located on the first surface 101; the source 400 is located on the first surface 101, and a portion of the source 400 in contact with the first surface 101 is located on a side of the isolation structure 200 away from the first side surface 1041.

[0052] Specifically, the semiconductor device is, for example, a MOSFET device, and the semiconductor device can be an N-type device or a P-type device. If the semiconductor device is an N-type device, the first conduction type is N-type (i.e., N-type doping), and the second conduction type is P-type (i.e., P-type doping). If the semiconductor device is a P-type device, the first conduction type is P-type, and the second conduction type is N-type. In this embodiment, the semiconductor device is taken as an example of an N-type device for illustration. The semiconductor body 100 includes, for example, a substrate 10 and an epitaxial layer 20. The substrate 10 is, for example, an N+ substrate, such as an N+ silicon carbide substrate or an N+ gallium nitride substrate, etc. The epitaxial layer 20 is an N-epitaxial layer, for example, an N-silicon carbide epitaxial layer or an N-gallium nitride epitaxial layer, etc. The surface of the epitaxial layer 20 away from the substrate 10 is the first surface 101 of the semiconductor body 100, and the surface of the substrate 10 away from the epitaxial layer 20 is the second surface 102 of the semiconductor body 100. The well region 103 is, for example, a P-type well region, that is, the well region 103 can be understood as a PW region. P-type ion implantation can be performed in the region of the epitaxial layer 20 where the well region 103 needs to be formed to form the well region 103. The P-type ions can be aluminum ions or boron ions, etc., and the ion concentration can be 10 14 ~10 18 / cm 3The first region 104 is of the first conductivity type. For example, the first region 104 is an N-type region. The second region 106 is of the first conductivity type. For example, the second region 106 is an N-type region. The N-type region is a region formed by performing N-type ion implantation. The N-type ions are, for example, phosphorus ions or nitrogen ions. The ion concentration of the first region 104 is less than that of the second region 106. For example, the first region 104 is an N- region, and the second region 106 is an N+ region. Both the first region 104 and the second region 106 have conductivity. Since the ion concentration of the first region 104 is less than that of the second region 106, the resistance per unit length of the first region 104 is less than that of the second region 106. The second region 106 can form an ohmic contact with the source electrode 400, thereby transmitting current to the source electrode 400.

[0053] The first side surface 1041 and the first bottom surface 1042 of the first region 104 are in contact with the well region 103. During the manufacturing process of the semiconductor body 100, P-type ion implantation can be first performed at the positions corresponding to the well region 103, the first region 104, and the second region 106 to form a P-type region, and then N- ion implantation and N+ ion implantation are sequentially performed in the P-type region, thereby forming the well region 103, the first region 104, and the second region 106.

[0054] In addition, an isolation structure 200 is further provided on the first surface 101. The isolation structure 200 is made of an insulating material. The isolation structure 200 is spaced apart from the first side surface 1041, that is, the isolation structure 200 is not in contact with the first side surface 1041, and there is a part of the first region 104 between the two. As Figure 2 shown, Figure 2 is Figure 1Current path diagram of a semiconductor device. After the current in the semiconductor body 100 enters the well region 103, it first enters the first region 104, then goes around to the bottom surface of the isolation structure 200, and is transmitted from the bottom surface of the isolation structure 200 to the position where the source electrode 400 contacts the first surface 101 and then transmitted to the source electrode. Compared with the current semiconductor device, on the one hand, the first region 104 is provided, and the resistance per unit length of the first region 104 is relatively large. The current is more resistant when it passes through the first region 104 from the well region 103 and then enters the source electrode than when it directly enters the source electrode from the well region 103, so that the breakdown voltage of the semiconductor device is higher. On the other hand, by providing the isolation structure 200, after the current enters the first region 104 from the well region 103, it is transmitted along a broken line around the isolation structure 200, that is, the current transmission path is longer, and thus the resistance is greater, making the breakdown voltage of the semiconductor device higher. In summary, the breakdown voltage is increased by configuring the path of the current in the first region 104 without extending the path in the epitaxial layer 20 to increase the breakdown voltage. It can be seen from the above that the semiconductor device of this embodiment does not need to increase the thickness of the epitaxial layer 20 in the semiconductor body to increase the breakdown voltage of the semiconductor device.

[0055] The technical solution of this embodiment uses a semiconductor device including a semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region and a first region; the first region is set to a first conduction type and is located on the first surface, and the well region is set to a second conduction type and is located on the first surface; the well region is connected to the first side surface of the first region, and the well region extends to the first bottom surface of the first region and is connected to the first bottom surface; wherein, the first bottom surface is opposite to the first surface; the semiconductor body further includes an isolation structure; the isolation structure is located on the first surface and extends from the first surface into the first region, and the isolation structure is spaced apart from the first side surface; a gate, located on the first surface; a source electrode, located on the first surface, and the part of the source electrode in contact with the first surface is located on the side of the isolation structure away from the first side surface. The breakdown voltage is increased by configuring the path of the current in the first region without extending the path in the epitaxial layer to increase the breakdown voltage. The semiconductor device of this embodiment does not need to increase the thickness of the epitaxial layer in the semiconductor body to increase the breakdown voltage of the semiconductor device.

[0056] Optionally, the semiconductor body 100 further includes an isolation groove 105; the isolation groove 105 is located on the first surface 101 and extends from the first surface 101 into the first region 104, and the isolation groove 105 is spaced apart from the first side surface 1041; the isolation structure 200 is located in the isolation groove 105. When manufacturing the semiconductor device, the isolation groove 105 can be formed on the first surface first, and then the isolation structure 200 is filled in the isolation groove 105. The isolation structure 200 can completely fill the isolation groove 105; in some other embodiments, a part of the isolation groove can also be filled.

[0057] Optionally, the semiconductor body further includes a second region 106. The second region 106 is of a first conduction type and is located on the first surface 101. The second region 106 includes a second bottom surface 1061 opposite to the first surface 101. The second region 106 is located on a side of the isolation groove 105 away from the first side surface 1041, and the first region 104 covers the second bottom surface 1061. The ion concentration of the first region 104 is less than that of the second region 106. The source electrode 400 is located on the first surface 101 and is in contact with the second region 106. By providing the second region 106, the on-resistance of the semiconductor device can be reduced.

[0058] Optionally, continue to refer to Figure 1 , the isolation groove 105 and the second region 106 are arranged at intervals.

[0059] Specifically, in this embodiment, the isolation groove 105 is not in contact with the second region 106, and the two are separated by the first region 104. That is to say, the side surface of the second region 106 away from the first side surface 1041 is also in contact with the first region 104, so that current can enter the second region 106 through more paths, which is beneficial to increasing the current.

[0060] Optionally, Figure 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention. Refer to Figure 3 . In this embodiment, the isolation groove 105 is connected to the second region 106. That is to say, the isolation groove 105 is directly in contact with the second region 106, and the two are not separated by the first region 104, which is beneficial to reducing the radial size of the semiconductor device.

[0061] Optionally, continue to refer to Figure 1 , the semiconductor device further includes a first insulating layer 301; the first insulating layer 301 is located on the first surface 101; the gate electrode 302 is located on a side of the first insulating layer 301 away from the first surface 101; the second region 106 further includes a second side surface 1062 close to the isolation groove 105. Along the thickness direction X of the semiconductor device, the second side surface 1062 is flush with the side surface of the first insulating layer 301.

[0062] Specifically, the first insulating layer 301 serves to isolate the gate 302 and the epitaxial layer 20. The side surface of the first insulating layer 301 is flush with the second side surface 1062 of the second region 106. The semiconductor device is an annular device, that is to say, the first insulating layer 301 is located inside the annular structure surrounded by the second side surface 1062. The vertical projection of the second region 106 on the second surface 102 does not overlap with the vertical projection of the first insulating layer 301 on the second surface 102. The second region 106 does not affect the thickness of the first insulating layer 301, thereby ensuring the stability of the performance of the semiconductor device. In addition, along the radial direction Y of the semiconductor device, the distance between the second region 106 and the well region 103 is relatively close, which is more conducive to forming a current channel between the second region 106 and the well region 103, and can reduce the threshold voltage of the semiconductor device.

[0063] Optionally, continuing to refer to Figure 1 , the depth of the isolation groove 105 is greater than the thickness of the second region 106. Thus, it can be ensured that in the radial direction Y, the current entering the first region 104 from the well region 103 does not directly enter the second region 106, but must bypass the isolation groove 105, that is, it can ensure to extend the path of the current, thereby increasing the breakdown voltage of the semiconductor device.

[0064] Optionally, continuing to refer to Figure 1 , along the thickness direction X of the semiconductor device, the thickness of the first region 104 is 80% - 90% of the maximum thickness of the well region 103.

[0065] Specifically, the maximum thickness of the well region 103 is the depth of ion implantation on the first surface 101 when manufacturing the well region 103. If the thickness of the first region 104 is too thick, the thickness of the well region 103 near the second surface 102 in the first region 104 is relatively thin, affecting the establishment of the conductive channel. If the first region 104 is too thin, the isolation groove 105 will be too thin, or the part of the first region 104 between the isolation groove 105 and the second bottom surface 1061 will be too thin, which will also make the current in the first region 104 too small, affecting the performance of the semiconductor device. In this embodiment, the thickness of the first region 104 is 80% - 90% of the maximum thickness of the well region 103, which can not only ensure that the part of the well region 103 near the second surface 102 in the first region 104 has an appropriate thickness, but also ensure that the second region 106 and the part of the first region 104 between the isolation groove 105 and the second bottom surface 1061 have appropriate thicknesses, thereby ensuring that the semiconductor device has better performance.

[0066] Further optionally, continuing to refer to Figure 1 , along the thickness direction X of the semiconductor device, the depth of the isolation groove 105 is 30% - 70% of the maximum thickness of the well region 103.

[0067] Specifically, since the depth of the isolation groove 105 is greater than the thickness of the second region 106, if the depth of the isolation groove 105 is too small, the thickness of the second region 106 will be too small, affecting the formation of the conductive channel. If the depth of the isolation groove 105 is too large, the distance between the isolation groove 105 and the first bottom surface 1042 will be too close, that is, the first region 104 between the isolation groove 105 and the first bottom surface 1042 will be too thin, and its impedance will be too large, affecting the establishment of the conductive channel.

[0068] Optionally, the material of the isolation structure 200 includes at least one of silicon dioxide and silicon nitride. Both silicon dioxide and silicon nitride have good insulation properties; during the manufacturing process of semiconductor devices, silicon dioxide and silicon nitride are more likely to fill the isolation groove 105, and it is easier to etch back to make the isolation structure 200 flush with the first surface 101. Of course, in some other embodiments, the isolation structure 200 can also use other insulating materials.

[0069] Optionally, continuing to refer to Figure 1 , the semiconductor body 100 further includes a third region 107, the third region 107 is set to the second conduction type and is located on the first surface 101, and the ion concentration of the third region 107 is greater than the ion concentration of the well region 103; the third region 107 is located on the side of the first region 104 away from the well region 103.

[0070] Specifically, the third region 107 is, for example, a P+ region. The third region 107 is used to improve the conductivity of the semiconductor device and form a good contact region, thereby improving the performance of the semiconductor device.

[0071] Optionally, continuing to refer to Figure 1 , the semiconductor device further includes a drain 800, and the drain 800 is located on the second surface 102. The material of the drain 800 can be titanium, titanium nitride, aluminum, or the like.

[0072] Optionally, continuing to refer to Figure 1 , the semiconductor device further includes a packaging structure, and the packaging structure includes a passivation layer 600 and a protective layer 700. The passivation layer 600 is located on the side of the source 400 away from the first surface 101. The protective layer 700 is located on the side of the passivation layer 600 away from the first surface 101. The protective layer 700 covers the passivation layer 600 and the sidewalls of the passivation layer 600 away from the edge of the semiconductor device. Among them, the region not encapsulated by the packaging structure is the lead region of the gate 302, and the lead region can electrically connect the gate 302 to the outside. The material of the passivation layer 600 can be silicon dioxide and / or silicon nitride. The material of the protective layer 700 can be, for example, polyimide.

[0073] Optionally, continuing to refer to Figure 1 , an interlayer dielectric layer 500 is further provided between the gate 302 and the source 400.

[0074] Based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device for manufacturing the semiconductor device provided in any embodiment of the present invention. As Figure 4 shown, Figure 4 is a flowchart of a method for manufacturing a semiconductor device provided in an embodiment of the present invention, and the manufacturing method includes:

[0075] Step S101, providing a semiconductor body, the semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region and a first region; the first region is set to a first conduction type and is located on the first surface, the well region is set to a second conduction type and is located on the first surface; the well region is in contact with a first side surface of the first region, and the well region extends to a first bottom surface of the first region and is in contact with the first bottom surface; wherein, the first bottom surface is opposite to the first surface;

[0076] Specifically, as Figure 1 shown, the semiconductor body 100 may include a substrate 10 and an epitaxial layer 20. If the semiconductor device is an N-type device, the first conduction type is N-type and the second conduction type is P-type; if the semiconductor device is a P-type device, the first conduction type is P-type and the second conduction type is N-type. The well region 103 is, for example, a P-type well region, and the second region 106 is an N-type region. The first surface 101 is further provided with an isolation groove 105. After the current in the semiconductor body 100 enters the well region 103, it first enters the first region 104. Since it cannot pass through the isolation groove 105, it will bypass to the bottom surface of the isolation groove 105 and be transmitted from the bottom surface of the isolation groove 105 to the bottom surface of the second region 106, and then enter the second region 106.

[0077] Step S102, forming an isolation structure, wherein the isolation structure is located on the first surface and extends from the first surface into the first region, and the isolation structure is spaced apart from the first side surface;

[0078] Specifically, the surface of the isolation structure 200 can be set to be flush with the first surface 101, and the isolation structure has insulating properties to prevent current from flowing through.

[0079] Step S103, forming a gate on the first surface;

[0080] Specifically, the gate 302 is located on the side of the first surface 101 away from the second surface 102.

[0081] Step S104, forming a source on the first surface, and the portion of the source in contact with the first surface is located on the side of the isolation structure away from the first side surface.

[0082] Specifically, the source 400 is in contact with the first surface, so that a current channel is formed between the first region 104 and the source 400.

[0083] The technical solution of this embodiment is a manufacturing method of a semiconductor device. The manufactured semiconductor device improves the breakdown voltage by configuring the path of the current in the first region, without extending the path in the epitaxial layer to improve the breakdown voltage. The semiconductor device of this embodiment does not need to increase the thickness of the epitaxial layer in the semiconductor body to improve the breakdown voltage of the semiconductor device.

[0084] Optionally, providing a semiconductor body includes: forming an isolation groove on the first surface of the semiconductor body, the isolation groove extending from the first surface into the first region, and the isolation groove being spaced apart from the first side surface; forming an isolation structure includes: forming an isolation structure in the isolation groove.

[0085] Specifically, the isolation groove can be formed by etching, and then the isolation structure is filled in the isolation groove. Subsequently, back-etching is performed so that the surface of the isolation structure 200 is flush with the first surface 101.

[0086] Optionally, Figures 5 - 9 is a schematic diagram of the product structure corresponding to the main steps of the manufacturing method of the semiconductor device provided by the embodiment of the present invention. Refer to Figures 5 - 9 , providing a semiconductor body includes:

[0087] forming a well region on the first surface of the semiconductor body; forming a first region on the first surface of the semiconductor body; forming a second region on the first surface of the semiconductor body.

[0088] Specifically, as Figure 5 shown, a substrate 10 and an epitaxial layer 20 can be provided first. Then, ion implantation corresponding to the well region, ion implantation corresponding to the first region, and ion implantation corresponding to the second region are sequentially performed on the first surface 101, so as to form a well region 103, a first region 104, and a second region 106. As Figure 5 shown, providing a semiconductor body includes: providing a semiconductor body further including a third region, the third region being set to a second conduction type and located on the first surface, and the ion doping concentration of the third region being greater than the ion doping concentration of the well region; the third region is located on one side of the first region away from the well region. For example, ion implantation corresponding to the third region can be performed before ion implantation of the well region, that is, P+ ion implantation is performed to form the third region.

[0089] Subsequently, as Figure 6 shown, an isolation groove is formed on the first surface of the semiconductor body. The isolation groove 105 can be formed by etching.

[0090] Subsequently, as Figure 7 shown, the isolation groove 105 is filled with the isolation structure 200, and then back-etching is performed so that the surface of the isolation structure 200 is flush with the first surface 101.

[0091] Subsequently, asFigure 8 As shown, a first insulating layer 301 and a gate 302 are prepared. The gate 302 is, for example, polysilicon.

[0092] Subsequently, as Figure 1 shown, an interlayer dielectric layer 500 is prepared, and then the first insulating layer 301 is etched to expose a second region 106 and a third region 107. Subsequently, a source electrode 400, a passivation layer 600, a protective layer 700, and a drain electrode 800 are prepared.

[0093] An embodiment of the present invention provides a power module, including a substrate and at least one semiconductor device as described in any of the embodiments of the present invention, and the substrate is used to carry the semiconductor device. Therefore, the beneficial effects of the semiconductor device as described in any of the embodiments of the present invention included in this power module will not be elaborated herein.

[0094] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device as described in any of the embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0095] Therefore, the beneficial effects of the semiconductor device as described in any of the embodiments of the present invention included in this power conversion circuit will not be elaborated herein.

[0096] An embodiment of the present invention further provides a vehicle, including a load and a power conversion circuit as in any of the embodiments of the present invention, and the power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load. Therefore, the beneficial effects of the power conversion circuit as described in any of the embodiments of the present invention included in this vehicle will not be elaborated herein.

[0097] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitations are imposed herein.

[0098] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub - combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: A semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region and a first region; the first region is of a first conductivity type and is located on the first surface, the well region is of a second conductivity type and is located on the first surface; the well region is adjacent to a first side surface of the first region, and the well region extends to a first bottom surface of the first region and is in contact with the first bottom surface; wherein, the first bottom surface is opposite to the first surface; An isolation structure located on the first surface and extending from the first surface into the first region, the isolation structure being spaced apart from the first side surface; A gate located on the first surface; A source located on the first surface, and a portion of the source in contact with the first surface is located on a side of the isolation structure away from the first side surface.

2. The semiconductor device according to claim 1, wherein The first surface is further provided with an isolation groove extending from the first surface into the first region, the isolation groove being spaced apart from the first side surface, and the isolation structure is located in the isolation groove.

3. The semiconductor device according to claim 2, wherein The semiconductor body further includes a second region, the second region is of a first conductivity type and is located on the first surface, the second region includes a second bottom surface opposite to the first surface, the second region is located on a side of the isolation groove away from the first side surface, and the first region is in contact with the second bottom surface, and the ion concentration of the first region is less than the ion concentration of the second region; the isolation groove is spaced apart from the second region.

4. The semiconductor device according to claim 3, characterized in that, The semiconductor device further includes a first insulating layer; The first insulating layer is located on the first surface; The gate is located on a side of the first insulating layer away from the first surface; The second region further includes a second side surface close to the isolation groove; along the thickness direction of the semiconductor device, the second side surface is flush with a side surface of the first insulating layer.

5. The semiconductor device according to claim 3, wherein, The depth of the isolation groove is greater than the thickness of the second region.

6. The semiconductor device according to claim 2, wherein, Along the thickness direction of the semiconductor device, the thickness of the first region is 80% - 90% of the maximum thickness of the well region; along the thickness direction of the semiconductor device, the depth of the isolation groove is 30% - 70% of the maximum thickness of the well region.

7. The semiconductor device according to claim 1, wherein The material of the isolation structure includes at least one of silicon dioxide and silicon nitride.

8. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a semiconductor body, the semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region and a first region; the first region is of a first conductivity type and is located on the first surface, the well region is of a second conductivity type and is located on the first surface; the well region is adjacent to a first side surface of the first region, and the well region extends to a first bottom surface of the first region and is in contact with the first bottom surface; wherein, the first bottom surface is opposite to the first surface; Forming an isolation structure, wherein the isolation structure is located on the first surface and extends from the first surface into the first region, the isolation structure being spaced apart from the first side surface; Forming a gate on the first surface; A source electrode is formed on the first surface, and a portion of the source electrode in contact with the first surface is located on a side of the isolation structure away from the first side surface.

9. The manufacturing method of the semiconductor device according to claim 8, characterized in that, Provided is a semiconductor body including: An isolation groove is formed on the first surface of the semiconductor body, the isolation groove extends from the first surface into the first region, and the isolation groove is spaced apart from the first side surface. The forming of the isolation structure includes: Forming the isolation structure in the isolation groove.

10. The manufacturing method of the semiconductor device according to claim 9, characterized in that, Provided is a semiconductor body including: Forming the well region on the first surface of the semiconductor body; Forming the first region on the first surface of the semiconductor body; Forming the isolation groove on the first surface of the semiconductor body.

11. A power module, characterized in that, Including a substrate and at least one semiconductor device according to any one of claims 1-7, the substrate being used to carry the semiconductor device.

12. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1-7, the semiconductor device being electrically connected to the circuit board.

13. A vehicle, characterized in that, Including a load and the power conversion circuit according to claim 12, the power conversion circuit is used for converting alternating current to direct current, converting alternating current to alternating current, converting direct current to direct current, or converting direct current to alternating current and then inputting it to the load.

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