Gallium nitride photoelectric double-control device with double-gate structure and manufacturing method of gallium nitride photoelectric double-control device
By introducing a double gate structure of a single crystal silicon layer into the GaN/AIN superlattice structure, the performance bottleneck of traditional silicon-based devices and the lattice mismatch problem in GaN epitaxial growth is solved, and the photoelectric dual-controlled devices with high electron mobility, high voltage withstand voltage and low leakage are realized to meet the needs of high-frequency communication and high-power applications.
Patent Information
- Application Number
- CN202510266262.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-07
- Publication Date
- 2025-07-08
AI Technical Summary
Traditional silicon-based devices have problems such as large signal delay, high loss, low breakdown voltage and large on-resistance in high-frequency communication and high-power applications. There are lattice mismatch problems in epitaxial growth of GaN materials. Traditional GaN devices have limitations in carrier regulation and photocontrol capabilities.
The double gate structure with GaN/AIN superlattice structure is adopted, combined with a single crystal silicon layer, to achieve high electron mobility, high voltage withstand voltage and low leakage, and device manipulation is carried out through a combination of light control and electronic control. The GaN/AlN superlattice structure and single crystal silicon layer are used to achieve light control and electronic control in the dual gate mode.
It improves the electronic mobility and voltage resistance of the device, reduces leakage current, enhances the stability and reliability of the device, meets the needs of high-frequency communication and high-power applications, and realizes flexible device handling.
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Abstract
Description
Technical Field
[0001] The invention relates to a gallium nitride photoelectric dual-control device with a dual-gate structure and a manufacturing method thereof, belonging to the technical field of semiconductor devices. Background Art
[0002] In the continuous development of semiconductor technology, traditional silicon-based devices, as core components of the electronics industry, have played a vital role in promoting the advancement of information technology. However, with the rapid development of science and technology, especially in the fields of high-frequency communications and high-power applications, traditional silicon-based devices have gradually encountered performance bottlenecks. In high-frequency communication scenarios, silicon-based devices exhibit significant signal delays and large signal losses due to their relatively low electron mobility. This feature makes it difficult for silicon-based devices to meet the stringent requirements of 5G and future higher-speed communication systems, limiting the rate and efficiency of data transmission. In the field of high-power applications, silicon-based devices also face the problems of low breakdown voltage and high on-resistance. These two factors directly affect the efficiency and stability of the power conversion system, making it difficult for silicon-based devices to perform at their best in power electronic equipment and energy conversion systems.
[0003] In order to solve the above problems, gallium nitride (GaN) materials have become a research hotspot in the semiconductor field due to their unique wide bandgap and high electron saturation velocity. The application of GaN materials is expected to significantly improve the electron mobility of devices, reduce signal delay and loss, while increasing the breakdown voltage and reducing the on-resistance, thereby meeting the needs of high-frequency communications and high-power applications. However, despite the many advantages of GaN materials, the lattice mismatch problem in its epitaxial growth process is a difficult problem that needs to be solved urgently. Lattice mismatch will lead to the generation of a large number of crystal defects, thereby reducing electron mobility and affecting the reliability and service life of the device.
[0004] In addition, the single-gate structure of traditional GaN devices has limitations in carrier regulation and is difficult to adapt to complex and changing working conditions. With the continuous emergence of emerging technologies, semiconductor devices need to have not only efficient electrical control capabilities, but also optical control capabilities to meet the needs of optoelectronic integration and optically controlled electronic systems.
[0005] In summary, in order to overcome the performance bottleneck of traditional silicon-based devices, solve the lattice mismatch problem in the epitaxial growth of GaN materials, and break through the limitations of traditional GaN devices in carrier regulation and light control capabilities, a new type of semiconductor device design is urgently needed. Summary of the invention
[0006] To solve the above problems, the present invention provides a gallium nitride optoelectronic dual-control device with a double-gate structure and a manufacturing method thereof. The present invention uses a double-gate structure based on a GaN / AIN superlattice structure and utilizes single-crystalline silicon to achieve the optical control operation of the device. The present invention utilizes the GaN / AlN superlattice structure to achieve high electron mobility, high breakdown voltage, and low leakage current, and achieves optical control and electrical control in the double-gate mode with the help of a single-crystalline silicon layer, opening up a new path for high-performance semiconductor devices.
[0007] In a first aspect, the present invention provides a gallium nitride optoelectronic dual-control device with a double-gate structure, including a substrate, a nucleation layer, a buffer layer, a GaN layer, a GaN / AIN superlattice layer, and a passivation layer arranged in sequence from bottom to top. The passivation layer is provided with a first source electrode, a first p-GaN layer, a second p-GaN layer, and a second source electrode. A single-crystalline silicon layer is arranged on the first p-GaN layer, a first gate electrode is arranged on the single-crystalline silicon layer, and a second gate electrode is arranged on the second p-GaN layer; the first source electrode and the second source electrode respectively form ohmic contacts with the GaN / AIN superlattice layer, the first gate electrode forms a Schottky contact with the single-crystalline silicon layer, and the second gate electrode forms a Schottky contact with the second p-GaN layer.
[0008] In an embodiment of the present invention, the materials of the nucleation layer and the buffer layer are one or more combinations of AlN, GaN, AlGaN, and InGaN; the thickness of the nucleation layer is 1-1000 nm; the thickness of the buffer layer is 1-4000 nm.
[0009] In an embodiment of the present invention, the materials of the first source electrode, the second source electrode, the first gate electrode, and the second gate electrode are one or more combinations of Ti, Al, Ni, and Au.
[0010] In an embodiment of the present invention, the material of the substrate is one or more combinations of silicon, sapphire, and silicon carbide.
[0011] In an embodiment of the present invention, the thickness of the GaN layer is 1-5000 nm.
[0012] In an embodiment of the present invention, the thickness of the GaN / AIN superlattice layer is 1-1000 nm.
[0013] In an embodiment of the present invention, the passivation layer is a silicon nitride passivation layer, the thickness of the passivation layer is 1-1000 nm; the thickness of the single-crystalline silicon layer is 1-500 nm; the thicknesses of the first p-GaN layer and the second p-GaN layer are 1-1000 nm.
[0014] In a second aspect, the present invention provides a manufacturing method of the gallium nitride optoelectronic dual-control device with the double-gate structure described above, including the following steps:
[0015] Step 1: Provide a substrate;
[0016] Step 2: Sequentially grow a nucleation layer, a buffer layer, a GaN layer, a GaN / AIN superlattice layer, and a passivation layer on the substrate;
[0017] Step 3: Etch the regions corresponding to the first source electrode and the second source electrode on the passivation layer. When etching reaches the GaN / AIN superlattice layer, stop etching;
[0018] Step 4: Etch the regions corresponding to the first p-GaN layer and the second p-GaN layer on the passivation layer. When etching reaches the GaN / AIN superlattice layer, further etch a groove with a depth of 1 - 100 nm downward;
[0019] Step 5: Deposit the first source electrode and the second source electrode in the regions obtained by etching in Step 3. The first source electrode and the second source electrode respectively form ohmic contacts with the GaN / AIN superlattice layer;
[0020] Step 6: Epitaxially grow the first p-GaN layer and the second p-GaN layer in the regions obtained in Step 4;
[0021] Step 7: Grow a single-crystalline silicon layer above the first p-GaN layer obtained in Step 6;
[0022] Step 8: Deposit a first gate in the upper region of the single-crystalline silicon layer obtained in Step 7. The first gate forms a Schottky contact with the single-crystalline silicon layer; deposit a second gate in the upper region of the second p-GaN layer obtained in Step 6. The second gate forms a Schottky contact with the second p-GaN layer.
[0023] In an embodiment of the present invention, Step 1 further includes:
[0024] Clean the substrate. First, place the substrate in a 1% ammonium fluoride buffer solution to remove the surface oxide layer and inorganic impurities; then clean the substrate with pure water; then soak the substrate in acetone and isopropyl alcohol in sequence, and clean it with ultrasonic waves for 3 - 5 minutes; finally, rinse the substrate with pure water and dry the substrate with an ammonia gun;
[0025] In Step 2, the material of the nucleation layer is AlN, and the organic chemical vapor deposition method is used with a growth temperature of 200 °C and a thickness of 50 nm; the material of the buffer layer is GaN, and the organic chemical vapor deposition method is used with a growth temperature of 800 °C and a thickness of 1000 nm; the GaN layer uses the organic chemical vapor deposition method with a growth temperature of 1000 °C and a thickness of 2000 nm; the GaN / AlN superlattice layer uses the organic chemical vapor deposition method with a thickness of 100 nm; the material of the passivation layer is Si3N4, and plasma-enhanced chemical vapor deposition is used with a growth temperature of 300 °C and a thickness of 50 nm.
[0026] In an embodiment of the present invention, in Step 3 and Step 4, dry etching is performed using Cl2 or BCl3 and doped with O2 or SF6; in Step 2, the GaN / AlN superlattice layer is grown in a metal organic chemical vapor deposition (MOCVD) device; in Step 7, the single crystal silicon layer is grown in a molecular beam epitaxy (MBE) device with a growth temperature of 500 °C and a thickness of 16 nm.
[0027] The beneficial effects of the present invention are as follows:
[0028] 1. A gallium nitride optoelectronic dual-control device with a double-gate structure and its manufacturing method provided by the present invention utilize a GaN / AlN superlattice structure to achieve high electron mobility, high breakdown voltage, and low leakage current. The present invention uses single crystal silicon to achieve light control operation. Based on the modulation of the Schottky barrier by photo-generated carriers, when illuminated, the single crystal silicon and p-GaN materials absorb photons to generate electron-hole pairs, change the Schottky barrier height, and affect carrier transport, thereby achieving light control of the electrical characteristics of the device. The light control function of the first gate cooperates with the electrical control function of the second gate to achieve more powerful and flexible device manipulation.
[0029] 2. The substrate of the present invention, as a basic support structure, selects materials such as silicon, sapphire, or silicon carbide to provide a stable platform for the growth of subsequent layers. The nucleation layer and the buffer layer use materials such as AlN, GaN, AlGaN, and InGaN. The nucleation layer can improve the lattice matching degree between the substrate and the subsequent growth layer, reduce the lattice mismatch degree, and reduce the generation of crystal defects. The buffer layer further alleviates stress, enabling the subsequent grown GaN layer and GaN / AlN superlattice layer to grow in a better environment, enhancing the integrity and quality of the overall crystal structure. Description of the Drawings
[0030] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.
[0031] Figure 1 It is a schematic structural diagram of a gallium nitride optoelectronic dual-control device with a double-gate structure provided by the present invention.
[0032] Figure 2 It is a comparative curve graph of the leakage current performance of the AlGaN / GaN and GaN / AIN superlattice structures provided by the present invention.
[0033] Figure 3 It is a comparative curve graph of the breakdown voltage performance of the AlGaN / GaN and GaN / AIN superlattice structures provided by the present invention.
[0034] Figure 4 It is a switching performance curve graph of the gallium nitride optoelectronic dual-control device provided by the present invention under different single-crystalline silicon thicknesses.
[0035] Figure 5 It is a light absorption coefficient curve graph of the gallium nitride optoelectronic dual-control device provided by the present invention under different single-crystalline silicon thicknesses.
[0036] Figure 6 It is a leakage current characteristic curve graph of the gallium nitride optoelectronic dual-control device provided by the present invention under different single-crystalline silicon thicknesses.
[0037] In the figure: 1. Substrate; 2. Nucleation layer; 3. Buffer layer; 4. GaN layer; 5. GaN / AIN superlattice layer; 6. Passivation layer; 7. First source electrode; 8. First p-GaN layer; 9. Second p-GaN layer; 10. Second source electrode; 11. Single-crystalline silicon layer; 12. First gate electrode; 13. Second gate electrode. Detailed implementation manners
[0038] The following will clearly and completely describe the technical solutions of the present invention with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the protection scope of the present invention.
[0039] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation on the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance. Among them, the terms "first position" and "second position" are two different positions.
[0040] Embodiment 1
[0041] This embodiment provides a gallium nitride optoelectronic dual-control device with a double-gate structure, which includes a substrate 1, a nucleation layer 2, a buffer layer 3, a GaN layer 4, a GaN / AIN superlattice layer (SLs) 5, and a passivation layer 6 arranged in sequence from bottom to top. The passivation layer 6 is provided with a first source electrode 7, a first p-GaN layer 8, a second p-GaN layer 9, and a second source electrode 10. A single-crystalline silicon layer 11 is arranged on the first p-GaN layer 8, and a first gate 12 is arranged on the single-crystalline silicon layer 11. The second p-GaN layer 9 is provided with a second gate 13; the first source electrode 7 and the second source electrode 10 respectively form ohmic contacts with the GaN / AIN superlattice layer 5, the first gate 12 forms a Schottky contact with the single-crystalline silicon layer 11, and the second gate 13 forms a Schottky contact with the second p-GaN layer 9.
[0042] Optionally, the material of the substrate 1 is one or a combination of silicon, sapphire, and silicon carbide.
[0043] Optionally, the materials of the nucleation layer 2 and the buffer layer 3 are one or a combination of AlN, GaN, AlGaN, and InGaN.
[0044] Optionally, the thickness of the nucleation layer 2 is 1 - 1000 nm.
[0045] Optionally, the thickness of the buffer layer 3 is 1 - 4000 nm.
[0046] Optionally, the thickness of the GaN layer 4 is 1 - 5000 nm.
[0047] Optionally, the thickness of the GaN / AIN superlattice layer 5 is 1 - 1000 nm.
[0048] Optionally, the passivation layer 6 is a silicon nitride passivation layer, and the thickness of the passivation layer 6 is 1 - 1000 nm.
[0049] Optionally, the thicknesses of the first p-GaN layer 8 and the second p-GaN layer 9 are 1 - 1000 nm.
[0050] Optionally, the thickness of the single-crystalline silicon layer 11 is 1 - 500 nm.
[0051] Optionally, the materials of the first source electrode 7, the second source electrode 10, the first gate electrode 12, and the second gate electrode 13 are one or more combinations of Ti, Al, Ni, and Au.
[0052] The present invention uses a double-gate structure based on a GaN / AIN superlattice structure, and uses single-crystalline silicon to achieve optical control operation of the device. The present invention utilizes the GaN / AlN superlattice structure to achieve high electron mobility, high breakdown voltage, and low leakage current, and achieves optical control and electrical control in a double-gate mode with the help of the single-crystalline silicon layer, opening up a new path for high-performance semiconductor devices.
[0053] Embodiment 2
[0054] This embodiment provides a manufacturing method of a gallium nitride optoelectronic double-control device with a double-gate structure according to Embodiment 1, including the following steps:
[0055] Step 1: Provide a substrate 1;
[0056] Step 2: Sequentially grow a nucleation layer 2, a buffer layer 3, a GaN layer 4, a GaN / AIN superlattice layer 5, and a passivation layer 6 on the substrate 1;
[0057] Step 3: Etch the regions corresponding to the first source electrode 7 and the second source electrode 10 on the passivation layer 6, and stop etching when reaching the GaN / AIN superlattice layer 5;
[0058] Step 4: Etch the regions corresponding to the first p-GaN layer 8 and the second p-GaN layer 9 on the passivation layer 6, and then etch a groove with a depth of 1 - 100 nm downward when reaching the GaN / AIN superlattice layer 5;
[0059] Step 5: Deposit the first source electrode 7 and the second source electrode 10 in the regions obtained by etching in Step 3, and the first source electrode 7 and the second source electrode 10 respectively form ohmic contacts with the GaN / AIN superlattice layer 5;
[0060] Step 6: Epitaxially grow the first p-GaN layer 8 and the second p-GaN layer 9 in the regions obtained in Step 4;
[0061] Step 7: Grow a single-crystalline silicon layer 11 above the first p-GaN layer 8 obtained in Step 6;
[0062] Step Eight: Deposit a first gate 12 in the upper region of the monocrystalline silicon layer 11 obtained in Step Seven, and form a Schottky contact between the first gate 12 and the monocrystalline silicon layer 11; deposit a second gate 13 in the upper region of the second p-GaN layer 9 obtained in Step Six, and form a Schottky contact between the second gate 13 and the second p-GaN layer 9.
[0063] Optionally, grow the GaN / AIN superlattice layer 5 in a metalorganic chemical vapor deposition (MOCVD) apparatus in Step Two.
[0064] Optionally, grow the monocrystalline silicon layer 11 in a molecular beam epitaxy (MBE) apparatus in Step Seven.
[0065] Optionally, use Cl2 or BCl3 for dry etching in Steps Three and Four, and introduce O2 or SF6.
[0066] Embodiment Three
[0067] This embodiment provides a manufacturing method of a gallium nitride optoelectronic dual-control device with a dual-gate structure according to Embodiment 1, including the following steps:
[0068] Step One: Provide a substrate 1; clean the substrate 1. The substrate 1 is a silicon substrate. First, place the silicon wafer in a 1% ammonium fluoride buffer solution (BOE) to remove the surface oxide layer and inorganic impurities; then clean the substrate 1 with pure water; then soak the substrate 1 in acetone and isopropyl alcohol in sequence, and perform ultrasonic cleaning for 3 - 5 minutes; finally, rinse the substrate 1 with pure water and dry the substrate 1 with an ammonia gun.
[0069] Step Two: Sequentially grow a nucleation layer 2, a buffer layer 3, a GaN layer 4, a GaN / AIN superlattice layer 5, and a passivation layer 6 on the substrate 1.
[0070] Among them, the material of the nucleation layer 2 is AIN, and it is grown by metalorganic chemical vapor deposition (MOCVD) at a growth temperature of 200°C and a thickness of 50 nm; the material of the buffer layer 3 is GaN, and it is grown by metalorganic chemical vapor deposition (MOCVD) at a growth temperature of 800°C and a thickness of 1000 nm; the GaN layer 4 is grown by metalorganic chemical vapor deposition (MOCVD) at a growth temperature of 1000°C and a thickness of 2000 nm; the GaN / AIN superlattice layer 5 is grown by metalorganic chemical vapor deposition (MOCVD) with a thickness of 100 nm; the material of the passivation layer 6 is Si3N4, and it is grown by plasma-enhanced chemical vapor deposition (PECVD) at a growth temperature of 300°C and a thickness of 50 nm.
[0071] Step 3: Etch the areas corresponding to the first source electrode 7 and the second source electrode 10 in the passivation layer 6, and stop etching when reaching the GaN / AIN superlattice layer 5; wherein, dry etching or wet etching is used;
[0072] Step 4: Etch the areas corresponding to the first p-GaN layer 8 and the second p-GaN layer 9 in the passivation layer 6, and when reaching the GaN / AIN superlattice layer 5, further etch a groove with a depth of 10 nm; wherein, dry etching or wet etching is used;
[0073] Step 5: Deposit the first source electrode 7 and the second source electrode 10 in the area obtained by etching in Step 3, and the first source electrode 7 and the second source electrode 10 respectively form ohmic contacts with the GaN / AIN superlattice layer 5;
[0074] Among them, the deposited metal is one or more of Ti, Al, Ni, and Au; the protective gas is argon; the high-temperature annealing temperature is 850 °C;
[0075] Step 6: Use metalorganic chemical vapor deposition (MOCVD) to epitaxially grow the first p-GaN layer 8 and the second p-GaN layer 9 in the area obtained in Step 4, and the thickness of the first p-GaN layer 8 and the second p-GaN layer 9 is 200 nm;
[0076] Step 7: Use molecular beam epitaxy (MBE) to grow a single-crystalline silicon layer 11 above the first p-GaN layer 8 obtained in Step 6, with a growth temperature of 500 °C and a thickness of 16 nm;
[0077] Step 8: Deposit a first gate electrode 12 in the area above the single-crystalline silicon layer 11 obtained in Step 7, and the first gate electrode 12 forms a Schottky contact with the single-crystalline silicon layer 11; deposit a second gate electrode 13 in the area above the second p-GaN layer 9 obtained in Step 6, and the second gate electrode 13 forms a Schottky contact with the second p-GaN layer 9;
[0078] Among them, the deposited metal is one or more of Ti, Al, Ni, and Au; the protective gas is argon; the high-temperature annealing temperature is 500 °C.
[0079] Example 4
[0080] In this example, on the basis of Example 3, the GaN / AIN superlattice layer 5 is replaced with AlGaN with a thickness of 20 nm, and the groove etched in Step 4 has a depth of 5 nm, and the rest is the same as in Example 3.
[0081] Example 5
[0082] In this example, on the basis of Example 3, the thickness range of the single-crystalline silicon layer is changed from 0 - 30 nm.
[0083] Taking the simulation tests of the leakage performance and breakdown voltage characteristic curves of the gallium nitride device transistors formed in Example 3 and Example 4, as Figure 2 and Figure 3 shown.
[0084] Figure 2 and Figure 3 show that the GaN / AIN superlattice structure has lower leakage current and higher breakdown voltage compared with the traditional AlGaN / GaN structure, bringing more excellent comprehensive performance to the device in practical applications, and greatly enhancing the stability, reliability and working efficiency of the device.
[0085] Taking the simulation tests of the switching speed, optical absorption coefficient and leakage current characteristics of the gallium nitride transistor formed in Example 5, as Figure 4 、 Figure 5 and Figure 6 shown.
[0086] Figure 4 show that the switching speed decreases as the thickness of the single crystal silicon increases; Figure 5 show that the optical absorption coefficient increases as the thickness of the single crystal silicon increases; Figure 6 show that the leakage current decreases as the thickness of the single crystal silicon increases. A gallium nitride optoelectronic dual-control device with a double-gate structure provided by the present invention requires better switching speed, lower leakage current and better optical absorption characteristics. Therefore, according to Figure 4 、 Figure 5 and Figure 6 considering comprehensively, when the thickness of the single crystal silicon is 16nm, there are more appropriate switching speed, leakage current and optical absorption characteristics.
[0087] In this article, specific embodiments are used to elaborate the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.
Claims
1. A gallium nitride optoelectronic dual-control device with a double-gate structure, characterized in that It includes a substrate (1), a nucleation layer (2), a buffer layer (3), a GaN layer (4), a GaN / AIN superlattice layer (5), and a passivation layer (6) which are sequentially arranged from bottom to top. The passivation layer (6) is provided with a first source electrode (7), a first p-GaN layer (8), a second p-GaN layer (9), and a second source electrode (10). A single-crystalline silicon layer (11) is provided on the first p-GaN layer (8), and a first gate electrode (12) is provided on the single-crystalline silicon layer (11). The second p-GaN layer (9) is provided with a second gate electrode (13); the first source electrode (7) and the second source electrode (10) respectively form ohmic contacts with the GaN / AIN superlattice layer (5), the first gate electrode (12) forms a Schottky contact with the single-crystalline silicon layer (11), and the second gate electrode (13) forms a Schottky contact with the second p-GaN layer (9).
2. The gallium nitride optoelectronic dual-control device with a double-gate structure according to claim 1, wherein The materials of the nucleation layer (2) and the buffer layer (3) are one or more combinations of AlN, GaN, AlGaN, and InGaN; the thickness of the nucleation layer (2) is 1 - 1000 nm; the thickness of the buffer layer (3) is 1 - 4000 nm.
3. A gallium nitride optoelectronic dual-control device with a double-gate structure according to claim 1, characterized in that, The materials of the first source electrode (7), the second source electrode (10), the first gate electrode (12), and the second gate electrode (13) are one or more combinations of Ti, Al, Ni, and Au.
4. A gallium nitride optoelectronic dual-control device with a double-gate structure according to claim 1, characterized in that, The material of the substrate (1) is one or more combinations of silicon, sapphire, and silicon carbide.
5. A gallium nitride optoelectronic dual-control device with a double-gate structure according to claim 1, characterized in that, The thickness of the GaN layer (4) is 1 - 5000 nm.
6. A gallium nitride optoelectronic dual-control device with a double-gate structure according to claim 1, characterized in that, The thickness of the GaN / AIN superlattice layer (5) is 1 - 1000 nm.
7. The gallium nitride optoelectronic dual-control device with a double-gate structure according to claim 1, characterized in that, The passivation layer (6) is a silicon nitride passivation layer, and the thickness of the passivation layer (6) is 1 - 1000 nm; the thickness of the single-crystalline silicon layer (11) is 1 - 500 nm; the thicknesses of the first p-GaN layer (8) and the second p-GaN layer (9) are 1 - 1000 nm.
8. A manufacturing method of a gallium nitride optoelectronic dual-control device with a double-gate structure according to any one of claims 1-7, characterized in that, It includes the following steps: Step 1: Provide a substrate (1); Step 2: Sequentially grow a nucleation layer (2), a buffer layer (3), a GaN layer (4), a GaN / AIN superlattice layer (5), and a passivation layer (6) on the substrate (1); Step 3: Etch the regions corresponding to the first source electrode (7) and the second source electrode (10) on the passivation layer (6), and stop etching when reaching the GaN / AIN superlattice layer (5); Step 4: Etch the regions corresponding to the first p-GaN layer (8) and the second p-GaN layer (9) on the passivation layer (6), and then etch a groove with a depth of 1 - 100 nm downward when reaching the GaN / AIN superlattice layer (5); Step 5: Deposit the first source electrode (7) and the second source electrode (10) in the regions obtained by etching in Step 3, and the first source electrode (7) and the second source electrode (10) respectively form ohmic contacts with the GaN / AIN superlattice layer (5); Step 6: Epitaxially grow the first p-GaN layer (8) and the second p-GaN layer (9) in the regions obtained in Step 4; Step Seven: Grow a single-crystalline silicon layer (11) above the first p-GaN layer (8) obtained in Step Six; Step Eight: Deposit a first gate (12) in the upper region of the single-crystalline silicon layer (11) obtained in Step Seven, and the first gate (12) forms a Schottky contact with the single-crystalline silicon layer (11); deposit a second gate (13) in the upper region of the second p-GaN layer (9) obtained in Step Six, and the second gate (13) forms a Schottky contact with the second p-GaN layer (9).
9. The manufacturing method of a gallium nitride optoelectronic dual-control device with a double-gate structure according to claim 8, characterized in that, Step One further includes: Clean the substrate (1). First, place the substrate (1) in a 1% ammonium fluoride buffer solution to remove the surface oxide layer and inorganic impurities; then clean the substrate (1) with pure water; then soak the substrate (1) in acetone and isopropyl alcohol in sequence, and clean it with ultrasonic waves for 3 - 5 minutes; finally, rinse the substrate (1) with pure water and dry the substrate (1) with an ammonia gun; In Step Two, the material of the nucleation layer (2) is AlN, and it is grown by organic chemical vapor deposition with a growth temperature of 200 °C and a thickness of 50 nm; the material of the buffer layer (3) is GaN, and it is grown by organic chemical vapor deposition with a growth temperature of 800 °C and a thickness of 1000 nm; the GaN layer (4) is grown by organic chemical vapor deposition with a growth temperature of 1000 °C and a thickness of 2000 nm; the GaN / AlN superlattice layer (5) is grown by organic chemical vapor deposition with a thickness of 100 nm; the material of the passivation layer (6) is Si3N4, and it is grown by plasma-enhanced chemical vapor deposition with a growth temperature of 300 °C and a thickness of 50 nm.
10. The manufacturing method of a gallium nitride optoelectronic dual-control device with a double-gate structure according to claim 8, characterized in that, Steps Three and Four use Cl2 or BCl3 for dry etching and incorporate O2 or SF6; in Step Two, the GaN / AlN superlattice layer (5) is grown in a metalorganic chemical vapor deposition (MOCVD) device; in Step Seven, the single-crystalline silicon layer (11) is grown in a molecular beam epitaxy (MBE) device with a growth temperature of 500 °C and a thickness of 16 nm.