Semiconductor structure and manufacturing method thereof
By forming a step structure in the semiconductor structure and pushing the gate oxide layer through anisotropic etching process, the problem of insufficient rounding of the top corner of the active region is solved, the risk of breakdown is reduced and the electrical performance and process yield are improved.
Patent Information
- Application Number
- CN202510469764.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-14
- Publication Date
- 2025-07-08
AI Technical Summary
In semiconductor structures, the sharp edges of the top angle of the active region cause concentration of electric field and mechanical stress, affecting process yield and reliability. Especially when the gate oxide layer thickness is large in high voltage semiconductor devices, it is difficult to perform sufficient top angle contour rounding.
By forming a sacrificial material layer in the initial trench, the target trench is formed, and the gate oxide layer is pushed open in the vertical direction using an anisotropic etching process to form a step structure, exposing the top angle of the active region for rounding.
It effectively improves the problem of insufficient rounding of the top corner of the active area, reduces the risk of breakdown of semiconductor structures, and improves electrical performance and process compatibility.
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Figure CN120282507A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing, and particularly to a semiconductor structure and a manufacturing method thereof. Background Art
[0002] The active region etching process is an etching process used to define the shallow trench isolation (STI) region and the active region (AA) of transistors on the surface of a semiconductor structure. During the active region etching process, sharp edges often form at the corners of the active region. The sharp corner edges are prone to problems such as electric field concentration and mechanical stress concentration, which will increase the breakdown risk of the semiconductor structure and have an adverse impact on the process yield and process uniformity of subsequent processes (such as oxidation processes or deposition processes). Therefore, it is necessary to perform corner profile rounding on the active region to improve the electrical performance, mechanical performance, and process compatibility of the semiconductor structure.
[0003] However, since the thickness of the gate oxide layer in high-voltage semiconductor devices is usually large (for example, the thickness is greater than or equal to 800 Å), it makes it difficult for the gate oxide layer to be pushed aside to both sides during the corner profile rounding process of the active region, making it difficult to fully round the corners of the active region, thus having an adverse impact on the performance and reliability of the semiconductor structure. Summary of the Invention
[0004] Based on this, the embodiments of this application provide a semiconductor structure and a manufacturing method thereof, which enable the gate oxide layer above the corners of the active region to be fully pushed aside to both sides of the target trench, facilitating the corner profile rounding process, effectively improving the problem of insufficient corner rounding of the active region in the semiconductor structure, and thus improving the electrical performance and process yield of the semiconductor structure.
[0005] In order to achieve the above-mentioned purpose, on the one hand, some embodiments of the present application provide a method for manufacturing a semiconductor structure. The manufacturing method includes: providing a substrate; the top of the substrate has an active area; the side of the substrate having the active area is formed with a gate oxide layer and a mask layer stacked in sequence from bottom to top along a first direction perpendicular to the substrate; etching the mask layer to form an initial trench in the mask layer; forming a sacrificial material layer at least at the bottom and sidewalls of the initial trench; continuing to etch the bottom of the sacrificial material layer, the gate oxide layer and the substrate along the extension direction of the initial trench to remove the sacrificial material layer at the bottom of the initial trench, and forming a sacrificial material layer at the gate oxide layer. A target groove having a target depth is formed in the mask layer and the substrate; wherein the sacrificial material layer retained on the side wall of the mask layer in the target groove corresponds to a sacrificial layer; the sacrificial layer is removed to form a first step structure between the mask layer and the gate oxide layer; based on the first step structure, the gate oxide layer on the side wall of the target groove is etched using a target process to form a second step structure between the gate oxide layer and the substrate to expose the top corner of the active area at the top of the substrate; and the top corner contour of the active area is rounded.
[0006] In some embodiments, after the bottom of the sacrificial material layer, the gate oxide layer, and the substrate are continuously etched along the extension direction of the initial trench to remove the sacrificial material layer at the bottom of the initial trench and a target trench having a target depth is formed in the gate oxide layer and the substrate, the sidewall of the gate oxide layer in the target trench is flush with the surface of the sacrificial layer facing away from the mask layer.
[0007] In some embodiments, the target process includes an anisotropic etching process.
[0008] In some embodiments, an etching rate of the target process in a first direction perpendicular to the substrate is greater than an etching rate of the target process in a second direction parallel to the substrate; the first direction intersects with the second direction.
[0009] In some embodiments, there is also a grinding protection layer between the mask layer and the gate oxide layer; the bottom of the sacrificial material layer, the gate oxide layer and the substrate are continuously etched along the extension direction of the initial groove to remove the sacrificial material layer at the bottom of the initial groove, and a target groove with a target depth is formed in the gate oxide layer and the substrate, including: the bottom of the sacrificial material layer, the grinding protection layer, the gate oxide layer and the substrate are continuously etched along the extension direction of the initial groove to remove the sacrificial material layer at the bottom of the initial groove, and a target groove with a target depth is formed in the grinding protection layer, the gate oxide layer and the substrate.
[0010] In some embodiments, the sidewalls of the polishing protection layer in the target trench, the sidewalls of the gate oxide layer, and the surface of the sacrificial layer facing away from the mask layer are flush; wherein, after removing the sacrificial layer, a first step structure is formed between the gate oxide layer, the polishing protection layer, and the mask layer.
[0011] In some embodiments, before etching the mask layer to form an initial trench in the mask layer, the method for manufacturing the semiconductor structure further includes: forming an anti-reflection layer on a side of the mask layer facing away from the gate oxide layer; forming a patterned photoresist layer on a side of the anti-reflection layer facing away from the mask layer; the patterned photoresist layer has a mask pattern for defining the initial trench.
[0012] Wherein, etching the mask layer to form an initial trench in the mask layer includes: etching the anti-reflection layer and the mask layer based on the patterned photoresist layer to form the initial trench in the anti-reflection layer and the mask layer; removing the patterned photoresist layer.
[0013] In some embodiments, after etching the gate oxide layer on the sidewall of the target trench based on the first step structure to form a second step structure between the gate oxide layer and the substrate, so as to expose the apex angle of the active region at the top of the substrate, the method for manufacturing the semiconductor structure further includes: removing the mask layer.
[0014] In some embodiments, after performing an apex angle rounding process on the apex angle of the active region, the method for manufacturing the semiconductor structure further includes: forming a seed layer on the bottom and sidewalls of the portion of the target trench located in the substrate; forming an insulating filling layer covering the seed layer and filling the target trench; at least polishing the insulating filling layer to expose the surface of the gate oxide layer facing away from the substrate, and making the insulating filling layer remaining in the target trench correspondingly constitute an isolation structure.
[0015] On the other hand, according to some embodiments, the present application further provides a semiconductor structure; this semiconductor structure is prepared by using the method for manufacturing the semiconductor structure in some of the foregoing embodiments of the present application.
[0016] The embodiments of the present application can / at least have the following advantages:
[0017] In the embodiments of the present application, an initial trench is first formed, and a sacrificial layer is formed on the sidewall of the mask layer in the initial trench. The sacrificial layer protects the sidewall of the mask layer, and during the process of continuously etching along the extension direction of the initial trench to form a target trench, a height difference is formed between the gate oxide layer and the mask layer in a direction perpendicular to the inner wall of the target trench through the sacrificial layer, so as to form a first step structure after the sacrificial layer is removed; then, based on the first step structure, the gate oxide layer on the sidewall of the target trench is etched by adopting a target process, so as to transfer the stepped structure from top to bottom in a first direction perpendicular to the substrate to the semiconductor film layer below, and a second step structure having the same or similar shape as the first step structure is formed between the gate oxide layer and the substrate. In this way, the embodiments of the present application can fully push the gate oxide layer above the top corner of the active region to both sides of the target trench, fully expose the top corner of the active region at the top of the substrate, so as to facilitate the rounding process of the top corner contour of the active region, thereby effectively improving the problems of electric field concentration and mechanical stress concentration caused by insufficient rounding of the top corner of the active region in the semiconductor structure, reducing the breakdown risk of the semiconductor structure, and improving the process compatibility and process yield of semiconductor manufacturing.
[0018] Details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present application will become apparent from the specification, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0020] Figure 1 It is a schematic flowchart of a method for manufacturing a semiconductor structure provided in some embodiments;
[0021] Figure 2 It is a schematic flowchart of another method for manufacturing a semiconductor structure provided in some embodiments;
[0022] Figure 3 It is a schematic flowchart of yet another method for manufacturing a semiconductor structure provided in some embodiments;
[0023] Figure 4 It is a schematic flowchart of yet another method for manufacturing a semiconductor structure provided in some embodiments;
[0024] Figure 5 It is a schematic flowchart of yet another method for manufacturing a semiconductor structure provided in some embodiments;
[0025] Figure 6 Schematic diagram of the structure of a substrate provided in some embodiments;
[0026] Figure 7 Schematic diagram of the structure obtained after forming an initial trench provided in some embodiments;
[0027] Figure 8 Schematic diagram of the structure obtained after removing a patterned photoresist layer provided in some embodiments;
[0028] Figure 9 Schematic diagram of the structure obtained after forming a sacrificial material layer provided in some embodiments;
[0029] Figure 10 Schematic diagram of the structure obtained after forming a target trench and a sacrificial layer provided in some embodiments;
[0030] Figure 11 Schematic diagram of the structure obtained after removing the sacrificial layer and forming a first step structure provided in some embodiments;
[0031] Figure 12 Schematic diagram of the structure obtained after forming a second step structure provided in some embodiments;
[0032] Figure 13 Schematic diagram of the structure obtained after performing rounding processing on the top corner profile provided in some embodiments;
[0033] Figure 14 Schematic diagram of the structure obtained after forming a seed layer provided in some embodiments;
[0034] Figure 15 Schematic diagram of the structure obtained after forming an insulating filling layer provided in some embodiments;
[0035] Figure 16 Schematic diagram of the structure obtained after forming an isolation structure provided in some embodiments.
[0036] Description of reference numerals:
[0037] 1 - Substrate, AA - Active region, 2 - Gate oxide layer, 3 - Mask layer, 4 - Anti - reflection layer, P - Patterned photoresist layer, 51 - Sacrificial material layer, 52 - Sacrificial layer, 6 - Grinding protection layer, S1 - First step structure, S2 - Second step structure, G1 - Initial trench, G2 - Target trench, C - Top corner of the active region, 71 - Seed layer, 72 - Insulating filling layer, STI - Isolation structure. Detailed implementation manners
[0038] To facilitate understanding of the present application, the present application will be described more comprehensively below with reference to the relevant accompanying drawings. Preferred embodiments of the present application are shown in the accompanying drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.
[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0040] It should be understood that when an element or layer is referred to as "on", "adjacent to", or "connected to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or parts, these elements, components, regions, layers, doping types, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or part from another element, component, region, layer, doping type, or part. Thus, without departing from the teachings of this application, the first element, component, region, layer, doping type, or part discussed below may be referred to as the second element, component, region, layer, or part.
[0041] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, the presence of the described features, integers, steps, operations, elements, and / or components can be determined, but one or more other features, integers, steps, operations, elements, components, and / or groups may not be excluded. At the same time, as used herein, the term "and / or" includes any and all combinations of the related listed items.
[0042] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application, and such variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present application.
[0043] An embodiment of the present application provides a semiconductor structure and a method for manufacturing the same, so that the gate oxide layer above the top corner of the active area is fully pushed to both sides of the target trench to facilitate the rounding of the top corner contour, effectively improving the problem of insufficient rounding of the top corner of the active area in the semiconductor structure, thereby improving the electrical performance and process yield of the semiconductor structure.
[0044] In some embodiments, see Figure 1 , the manufacturing method of the semiconductor structure includes the following steps S100~S700.
[0045] S100, providing a substrate; the top of the substrate has an active area; a gate oxide layer and a mask layer are formed on one side of the substrate having the active area, which are sequentially stacked from bottom to top along a first direction perpendicular to the substrate.
[0046] S200 , etching the mask layer to form an initial trench in the mask layer.
[0047] S300 , forming a sacrificial material layer at least on the bottom and sidewalls of the initial trench.
[0048] S400, continuing to etch the bottom of the sacrificial material layer, the gate oxide layer and the substrate along the extension direction of the initial trench to remove the sacrificial material layer at the bottom of the initial trench and form a target trench with a target depth in the gate oxide layer and the substrate; wherein the sacrificial material layer retained on the side wall of the mask layer in the target trench corresponds to a sacrificial layer.
[0049] S500, removing the sacrificial layer to form a first step structure between the mask layer and the gate oxide layer.
[0050] S600, based on the first step structure, etching the gate oxide layer on the sidewall of the target trench by using a target process to form a second step structure between the gate oxide layer and the substrate to expose the top corner of the active region on the top of the substrate.
[0051] S700, performing a rounding process on the top corners of the active area.
[0052] It should be noted that, in some examples, after executing step S400 , the sidewall of the gate oxide layer in the target trench is flush with the surface of the sacrificial layer facing away from the mask layer.
[0053] In the embodiments of the present application, an initial trench is first formed, and a sacrificial layer is formed on the sidewall of the mask layer in the initial trench. The sacrificial layer protects the sidewall of the mask layer, and during the process of continuously etching along the extending direction of the initial trench to form a target trench, a height difference is formed between the gate oxide layer and the mask layer in a direction perpendicular to the inner wall of the target trench through the sacrificial layer, so as to form a first stepped structure after the sacrificial layer is removed; then, based on the first stepped structure, the gate oxide layer on the sidewall of the target trench is etched by adopting a target process, so as to transfer the stepped structure from top to bottom in a first direction perpendicular to the substrate to the underlying semiconductor film layer, and a second stepped structure having the same or similar shape as the first stepped structure is formed between the gate oxide layer and the substrate. In this way, the embodiments of the present application can fully push the gate oxide layer above the top corner of the active region to both sides of the target trench, fully expose the top corner of the active region at the top of the substrate, so as to facilitate the rounding process of the top corner contour of the active region, thereby effectively improving the problems of electric field concentration and mechanical stress concentration caused by insufficient rounding of the top corner of the active region in the semiconductor structure, reducing the breakdown risk of the semiconductor structure, and improving the process compatibility and process yield of semiconductor manufacturing.
[0054] In some embodiments, the target process includes an anisotropic etching process.
[0055] In some embodiments, the etching rate of the target process in a first direction perpendicular to the substrate is greater than its etching rate in a second direction parallel to the substrate; the first direction intersects with the second direction.
[0056] In the embodiments of the present application, the gate oxide layer on the sidewall of the target trench is etched by using an anisotropic etching process. Since the etching rate of the anisotropic etching process in a first direction perpendicular to the substrate is greater than its etching rate in a second direction parallel to the substrate, the surface shape of the semiconductor film layer can be accurately transferred from top to bottom in a direction perpendicular to the substrate, and the first stepped structure formed between the mask layer and the gate oxide layer is accurately transferred to the underlying semiconductor film layer, so that a second stepped structure having the same or similar shape as the first stepped shape is formed between the gate oxide layer and the substrate, which is beneficial to fully pushing the gate oxide layer above the top corner of the active region to both sides of the target trench and fully exposing the top corner of the active region at the top of the substrate, so as to facilitate the rounding process of the top corner contour of the active region.
[0057] In some embodiments, please refer to Figure 2 , there is also a polishing protection layer between the mask layer and the gate oxide layer; step S400 includes the following steps S410.
[0058] S410, continue etching the bottom of the sacrificial material layer, the grinding protection layer, the gate oxide layer and the substrate along the extension direction of the initial trench to remove the sacrificial material layer at the bottom of the initial trench, and form a target trench with a target depth in the grinding protection layer, the gate oxide layer and the substrate.
[0059] The sacrificial material layer retained on the sidewall of the mask layer in the target trench correspondingly constitutes a sacrificial layer.
[0060] In the implementation of the present application, by forming a grinding protection layer above the gate oxide layer, when the semiconductor structure is planarized in the subsequent preparation steps, the grinding plane can be accurately stopped above the gate oxide layer, thereby avoiding damage to the gate oxide layer caused by the grinding process, thereby improving the process yield of semiconductor manufacturing.
[0061] In some embodiments, the sidewalls of the polishing protection layer, the sidewalls of the gate oxide layer, and the surface of the sacrificial layer facing away from the mask layer in the target trench are all flush.
[0062] Accordingly, after the sacrificial layer is removed in step S500 , a first step structure is formed between the gate oxide layer, the grinding protection layer and the mask layer.
[0063] In some embodiments, see Figure 3 Before step S200, the method for manufacturing the semiconductor structure further includes the following steps S201-S202.
[0064] S201, forming an anti-reflection layer on a side of the mask layer away from the gate oxide layer.
[0065] S202, forming a patterned photoresist layer on a side of the anti-reflection layer away from the mask layer; the patterned photoresist layer has a mask pattern for defining an initial groove.
[0066] Accordingly, please continue to refer to Figure 3 , step S200 includes the following steps S210~S220.
[0067] S210 , etching the anti-reflection layer and the mask layer based on the patterned photoresist layer to form initial grooves in the anti-reflection layer and the mask layer.
[0068] S220, removing the patterned photoresist layer.
[0069] In some embodiments, see Figure 4 After step S600, the method for manufacturing the semiconductor structure further includes the following step S610.
[0070] S610, removing the mask layer.
[0071] In some embodiments, see Figure 5, after step S700, the method for manufacturing a semiconductor structure further includes the following steps S810 to S830.
[0072] S810, form a seed layer on the bottom and sidewalls of the portion of the target trench located within the substrate.
[0073] S820, form an insulating filling layer that covers the seed layer and fills the target trench.
[0074] S830, at least polish the insulating filling layer to expose the surface of the gate oxide layer facing away from the substrate, and make the insulating filling layer remaining within the target trench correspondingly constitute an isolation structure.
[0075] It should be understood that although Figures 1 - 5 the steps in the flowchart are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, Figures 1 - 5 at least a part of the steps in
[0076] may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential either, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.
[0076] To more clearly illustrate the method for manufacturing a semiconductor structure in some of the above embodiments, please refer to the following some embodiments in combination with Figures 6 - 16 for understanding.
[0077] In some embodiments, the method for manufacturing a semiconductor structure includes the following steps S100 to S700.
[0078] In step S100, please refer to Figure 6 , provide a substrate 1; the top of the substrate 1 has an active region AA; on one side of the substrate 1 having the active region AA, a gate oxide layer 2 and a mask layer 3 are sequentially stacked from bottom to top along a first direction perpendicular to the substrate 1 (for example, the Y direction).
[0079] In some embodiments, the semiconductor structure includes, but is not limited to, high-voltage semiconductor devices.
[0080] Exemplarily, the semiconductor structure can be, for example, a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), a power metal-oxide-semiconductor field-effect transistor (Power MOSFET), a thyristor, a gallium nitride (GaN) power device, a silicon carbide (SiC) power device, or the like.
[0081] Exemplarily, the substrate 1 can be composed of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 1 can be a single-layer structure or a multi-layer structure. For example, the substrate 1 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate 1 can be a layered substrate including, for example, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of the substrate 1 should not limit the protection scope of this application.
[0082] Exemplarily, the material of the gate oxide layer 2 (Gate oxide, abbreviated as GOX) includes, but is not limited to, insulating materials; the material of the gate oxide layer 2 can be, for example, silicon dioxide (SiO2), etc.
[0083] In some embodiments, the dimension of the gate oxide layer 2 in the first direction perpendicular to the substrate 1 (for example, the Y direction) is greater than or equal to 800 Å.
[0084] Exemplarily, the dimension of the gate oxide layer 2 in the first direction perpendicular to the substrate 1 (for example, the Y direction) can be, for example, 800 Å, 1000 Å, 1200 Å, 1500 Å, 2000 Å, 2500 Å, or 3000 Å, etc.
[0085] In some examples, the mask layer 3 includes, but is not limited to, an advanced patterning film (Advanced Patterning Film, abbreviated as APF).
[0086] It should be noted that using the advanced patterning film (APF) as the mask layer 3 can effectively improve the resolution and accuracy of the etching process, improve the uniformity and stability of the etching process, and reduce pattern defects.
[0087] In some embodiments, there is also a polishing protection layer 6 between the mask layer 3 and the gate oxide layer 2.
[0088] Exemplarily, the material of the polishing protection layer 6 includes but is not limited to nitrides; for example, the material of the polishing protection layer 6 can be silicon nitride (SiN), etc.
[0089] In some embodiments, before step S200, the manufacturing method of the semiconductor structure further includes the following steps S201 to S202.
[0090] In step S201, please continue to refer to Figure 6 , an anti-reflection layer 4 is formed on the side of the mask layer 3 away from the gate oxide layer 2.
[0091] Exemplarily, the anti-reflection layer 4 can be, for example, a bottom anti-reflection coating (BARC for short).
[0092] Exemplarily, the material of the anti-reflection layer 4 includes but is not limited to silicon oxynitride (SiON), silicon nitride (Si3N4), silicon carbide (SiC), or polyimide (PI), etc.
[0093] Exemplarily, the formation process of the anti-reflection layer 4 includes but is not limited to deposition processes, etc.
[0094] In step S202, please continue to refer to Figure 6 , a patterned photoresist layer P is formed on the side of the anti-reflection layer 4 away from the mask layer 3; the patterned photoresist layer P has a mask pattern for defining the initial trench G1.
[0095] Exemplarily, step S202 can include the following steps: forming a photoresist material layer on the side of the anti-reflection layer 4 away from the mask layer 3; using a photolithography process to etch the photoresist material layer to form a mask pattern for defining the initial trench G1 on the photoresist material layer, thereby obtaining the patterned photoresist layer P.
[0096] Exemplarily, the formation process of the photoresist material layer includes but is not limited to a coating process, for example, it can be a spin-on PR coating process.
[0097] It should be noted that by providing the anti-reflection layer 4 under the patterned photoresist layer P, the reflected light can be reduced, the pattern resolution can be improved, and the standing wave effect can be suppressed, thereby improving the uniformity of the light intensity distribution in the patterned photoresist layer P during the etching process, improving the resolution and edge clarity of the etched pattern (such as the initial trench G1), and enhancing the stability of the etching process.
[0098] In step S200, please refer to Figure 7 , etch the mask layer 3 to form an initial trench G1 in the mask layer 3.
[0099] Exemplarily, the etching process for forming the initial trench G1 includes, but is not limited to, photolithography and the like.
[0100] In some examples, step S200 includes the following step S210.
[0101] In step S210, please continue to refer to Figure 7 , etch the anti-reflection layer 4 and the mask layer 3 based on the patterned photoresist layer P to form an initial trench G1 in the anti-reflection layer 4 and the mask layer 3.
[0102] In some examples, please continue to refer to Figure 7 , the initial trench G1 penetrates through the anti-reflection layer 4 and the mask layer 3, the sidewalls of the initial trench G1 expose opposite sidewalls of the anti-reflection layer 4 in the second direction (e.g., X direction) parallel to the substrate 1 and opposite sidewalls of the mask layer 3 in the second direction (e.g., X direction) parallel to the substrate 1, and the bottom of the initial trench G1 exposes a partial surface of the polishing protection layer 6 that is away from the gate oxide layer 2 in the first direction (e.g., Y direction) perpendicular to the substrate 1.
[0103] In step S220, please refer to Figure 8 , remove the patterned photoresist layer P.
[0104] Exemplarily, the removal process of the patterned photoresist layer P includes, but is not limited to, a debonding process.
[0105] In step S300, please refer to Figure 9 , form a sacrificial material layer 51 at least on the bottom and sidewalls of the initial trench G1.
[0106] In some examples, please continue to refer to Figure 9 , the sacrificial material layer 51 can also be a whole-layer structure that conformally covers the bottom and sidewalls of the initial trench G1 and the surface of the anti-reflection layer 4 facing away from the mask layer 3.
[0107] Exemplarily, the material of the sacrificial material layer 51 includes, but is not limited to, an insulating material; the material of the sacrificial material layer 51 can be, for example, an oxide.
[0108] Exemplarily, the formation process of the sacrificial material layer 51 includes, but is not limited to, a deposition process; the formation process of the sacrificial material layer 51 can be, for example, an atomic layer deposition process (Atomic Layer Deposition, abbreviated as ALD).
[0109] In step S400, please refer to Figure 10, continue to etch the bottom of the sacrificial material layer 51, the gate oxide layer 2, and the substrate 1 along the extension direction of the initial trench G1 (for example, the Y direction) to remove the sacrificial material layer 51 at the bottom of the initial trench G1, and form a target trench G2 with a target depth in the gate oxide layer 2 and the substrate 1; wherein, the sacrificial material layer 51 on the sidewall of the mask layer 3 remaining in the target trench G2 correspondingly constitutes the sacrificial layer 52.
[0110] Exemplarily, the etching process for forming the target trench G2 includes, but is not limited to, photolithography and the like.
[0111] In some examples, there is also a polishing protection layer 6 between the mask layer 3 and the gate oxide layer 2; step S400 includes the following step S410.
[0112] In step S410, please continue to refer to Figure 10 , continue to etch the bottom of the sacrificial material layer 51, the polishing protection layer 6, the gate oxide layer 2, and the substrate 1 along the extension direction of the initial trench G1 to remove the sacrificial material layer 51 at the bottom of the initial trench G1, and form a target trench G2 with a target depth in the polishing protection layer 6, the gate oxide layer 2, and the substrate 1.
[0113] Exemplarily, please continue to refer to Figure 10 , the target trench G2 penetrates through the polishing protection layer 6 and the gate oxide layer 2 and extends into the substrate 1 along the extension direction of the initial trench G1.
[0114] In some examples, please continue to refer to Figure 10 , after performing step S400, the sidewall of the gate oxide layer 2 in the target trench G2 is flush with the surface of the sacrificial layer 52 facing away from the mask layer 3.
[0115] In some examples, the semiconductor structure further includes a mask protection layer; the sidewalls of the polishing protection layer 6 and the gate oxide layer 2 in the target trench G2 are both flush with the surface of the sacrificial layer 52 facing away from the mask layer 3.
[0116] It should be explained that the target trench G2 is etched along the sidewall of the sacrificial layer 52 facing away from the mask layer 3, and the sidewalls of the polishing protection layer 6 and the gate oxide layer 2 in the target trench G2 are both flush with the surface of the sacrificial layer 52 facing away from the mask layer 3; in this way, the sacrificial layer 52 can play a protective role for the sidewall of the mask layer 3 during the etching process of the target trench G2, so that a height difference is formed between the mask layer 3 and the polishing protection layer 6 and the gate oxide layer 2 in the direction perpendicular to the inner wall of the target trench G2.
[0117] In step S500, please refer to Figure 11 , remove the sacrificial layer 52 to form a first step structure S1 between the mask layer 3 and the gate oxide layer 2.
[0118] Exemplarily, the process for removing the sacrificial layer 52 includes, but is not limited to, a wet etching process (Wet Etch).
[0119] In some examples, the semiconductor structure further includes a polishing protection layer 6; after removing the sacrificial layer 52 in step S500, a first step structure S1 is formed between the gate oxide layer 2, the polishing protection layer 6, and the mask layer 3.
[0120] In step S600, refer to Figure 12 , based on the first step structure S1, the gate oxide layer 2 on the sidewall of the target trench G2 is etched using a target process, so that a second step structure S2 is formed between the gate oxide layer 2 and the substrate 1 to expose the active region apex angle C at the top of the substrate 1.
[0121] In some embodiments, the shape of the second step structure S2 is the same as or similar to the shape of the first step structure S1.
[0122] In some embodiments, the vertical edges of the second step structure S2 and the vertical edges of the first step structure S1 are in the same plane in a direction perpendicular to the substrate 1.
[0123] In some embodiments, the step width of the second step structure S2 is equal to the step width of the first step structure S1.
[0124] It should be noted that the "step width" of the step structure refers to the dimension of the step structure in the second direction parallel to the substrate 1 (for example, the X direction).
[0125] It should be explained that, please continue to refer to Figure 12 , the "active region apex angle C" refers to the geometric angle at the top edge of the active region AA at the opening of the target trench G2 after the formation of the target trench G2. Before sufficient corner profile rounding treatment, the profile shape of the active region apex angle C usually presents a sharp geometric shape.
[0126] In some embodiments, the target process includes an anisotropic etching process.
[0127] Exemplarily, the target process can be, for example, a reactive ion etching (RIE) process, a deep reactive ion etching (DRIE) process, an ion beam etching (IBE), a plasma etching (PE), a chemically assisted ion beam etching (CAIBE), an inductively coupled plasma etching (ICP), or an electron cyclotron resonance etching (ECR), etc.
[0128] In some embodiments, the etching rate of the target process in a first direction perpendicular to the substrate 1 (e.g., the Y direction) is greater than its etching rate in a second direction parallel to the substrate 1 (e.g., the X direction); the first direction (e.g., the Y direction) intersects with the second direction (e.g., the X direction).
[0129] It should be noted that, in the target process (e.g., an anisotropic etching process), the etching rate in the first direction perpendicular to the substrate 1 (e.g., the Y direction) is greater than the etching rate in the second direction parallel to the substrate 1 (e.g., the X direction), that is, the anisotropic etching process mainly proceeds in the first direction (e.g., the Y direction). Therefore, this characteristic enables the target process to accurately transfer the surface shape of the semiconductor film layer; for example, in the embodiments of the present application, the target process can accurately transfer the first step structure S1 between the gate oxide layer 2, the polishing protection layer 6, and the mask layer 3 to between the gate oxide layer 2 and the substrate 1 and form a second step structure S2, and can make the vertical edges of the first step structure S1 and the vertical edges of the second step structure S2 be in the same plane. Thus, it is beneficial to fully push the gate oxide layer 2 above the active region apex C to both sides of the target trench G2, fully exposing the active region apex C at the top of the substrate 1, so as to facilitate the apex profile rounding process for the active region apex C.
[0130] In some embodiments, after step S600, the manufacturing method of the semiconductor structure further includes the following step S610.
[0131] In step S610, please refer to Figure 13 , and remove the mask layer 3.
[0132] Exemplarily, the process for removing the mask layer 3 includes but is not limited to a grinding process; the process for removing the mask layer 3 can be, for example, a Chemical Mechanical Polishing (CMP) process.
[0133] In step S700, please continue to refer to Figure 13 , and perform a corner profile rounding process on the top corner C of the active region.
[0134] Exemplarily, the processes used for the corner profile rounding process include but are not limited to a Thermal Oxidation Rounding process, a Chemical Mechanical Polishing (CMP) process, a Wet Etch Rounding process, or a Plasma Treatment Rounding process, etc.
[0135] It should be noted that the corner profile rounding process is a process of transforming the top corner C of the active region in a semiconductor structure into a smooth profile through chemical or physical methods.
[0136] Exemplarily, after sufficient corner profile rounding process, please continue to refer to Figure 13 , the profile shape of the top corner C of the active region presents a smooth arc.
[0137] In the embodiment of the present application, the top corner C of the active region at the top of the substrate 1 is fully exposed through the steps of the foregoing manufacturing method, facilitating the sufficient corner profile rounding process of the top corner C of the active region in this step, thereby effectively improving the problems of electric field concentration and mechanical stress concentration caused by insufficient rounding of the top corner C of the active region in the semiconductor structure, reducing the breakdown risk of the semiconductor structure, and improving the process compatibility and process yield of semiconductor manufacturing.
[0138] In some embodiments, after step S700, the method for manufacturing a semiconductor structure further includes the following steps S810 to S830.
[0139] In step S810, please refer to Figure 14 , and form a seed layer 71 on the bottom and side walls of the portion of the target trench G2 located in the substrate 1.
[0140] Exemplarily, the material of the seed layer 71 includes but is not limited to an insulating material; the material of the seed layer 71 can be, for example, an oxide.
[0141] In some embodiments, the seed layer 71 covers the top corner C of the active region.
[0142] It should be noted that by fully rounding the corners of the active region C, the coverage of the seed layer 71 on the surface of the active region corner C can be effectively improved, thereby improving the deposition uniformity and consistency of the semiconductor film layer, and effectively improving the process yield and process compatibility.
[0143] In step S820, please refer to Figure 15 , an insulating filling layer 72 is formed to cover the seed layer 71 and fill the target trench G2.
[0144] It should be noted that please continue to refer to Figure 15 , the insulating filling layer 72 and the seed layer 71 are made of the same material, and the insulating filling layer 72 and the seed layer 71 can be an integral structure.
[0145] Exemplarily, the material of the insulating filling layer 72 includes but is not limited to insulating materials; the material of the insulating filling layer 72 can be, for example, an oxide.
[0146] Exemplarily, the formation process of the insulating filling layer 72 includes but is not limited to deposition processes; the formation process of the insulating filling layer 72 can be, for example, a Chemical Vapor Deposition (CVD) process.
[0147] In some examples, please continue to refer to Figure 15 , the insulating filling layer 72 also covers the sidewalls and the surface of the sidewalls of the gate oxide layer 2 and the polishing protection layer 6.
[0148] In step S830, please refer to Figure 16 , at least the insulating filling layer 72 is polished to expose the surface of the gate oxide layer 2 facing away from the substrate 1, and the insulating filling layer 72 remaining in the target trench G2 correspondingly forms an isolation structure STI.
[0149] In some embodiments, please continue to refer to Figure 16 , while polishing the insulating filling layer 72, the polishing protection layer 6 is also polished synchronously and the polishing protection layer 6 is removed synchronously. In this way, the polishing protection layer 6 can accurately stop the polishing plane above the gate oxide layer 2, avoiding damage to the gate oxide layer 2 caused by the polishing process, thereby improving the process yield of semiconductor manufacturing.
[0150] Exemplarily, the isolation structure STI can be, for example, a Shallow Trench Isolation (STI) structure.
[0151] Exemplarily, the polishing process of the insulating filling layer 72 includes but is not limited to a Chemical Mechanical Polishing (CMP) process.
[0152] According to some embodiments, the present application also provides a semiconductor structure, which can be prepared by the manufacturing method of the semiconductor structure in the above-mentioned some embodiments. The semiconductor structure also has all the technical advantages of the manufacturing method of the foregoing semiconductor structure. It should be noted that for the same or corresponding parts as those in the above embodiments, reference may be made to the corresponding descriptions of the foregoing embodiments, and details will not be described in the following.
[0153] In some embodiments, the semiconductor structure includes, but is not limited to, high-voltage semiconductor devices.
[0154] Exemplarily, the semiconductor structure can be, for example, a bipolar junction transistor (BJT), an insulated gate bipolar transistor (IGBT), a power metal oxide semiconductor field effect transistor (Power MOSFET), a thyristor, a gallium nitride (GaN) power device, or a silicon carbide (SiC) power device, etc.
[0155] In the description of this specification, the description with reference to terms such as "some embodiments", "some examples", "exemplarily", etc. means that the specific features, structures, materials, or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.
[0156] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.
[0157] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that, include: providing a substrate; The top of the substrate has an active area; a gate oxide layer and a mask layer are formed on one side of the substrate having the active area, which are sequentially stacked from bottom to top along a first direction perpendicular to the substrate; etching the mask layer to form an initial trench in the mask layer; forming a sacrificial material layer at least on the bottom and sidewalls of the initial trench; Continue etching the bottom of the sacrificial material layer, the gate oxide layer and the substrate along the extension direction of the initial trench to remove the sacrificial material layer at the bottom of the initial trench and form a target trench with a target depth in the gate oxide layer and the substrate; wherein the sacrificial material layer retained on the side wall of the mask layer in the target trench correspondingly constitutes a sacrificial layer; removing the sacrificial layer to form a first step structure between the mask layer and the gate oxide layer; Based on the first step structure, the gate oxide layer on the sidewall of the target trench is etched by a target process to form a second step structure between the gate oxide layer and the substrate to expose the top corner of the active area on the top of the substrate; The top corner of the active area is rounded.
2. The manufacturing method of the semiconductor structure according to claim 1, wherein, After continuing to etch the bottom of the sacrificial material layer, the gate oxide layer and the substrate along the extension direction of the initial groove to remove the sacrificial material layer at the bottom of the initial groove and forming a target groove with a target depth in the gate oxide layer and the substrate, the side wall of the gate oxide layer in the target groove is flush with the surface of the sacrificial layer away from the mask layer.
3. The manufacturing method of the semiconductor structure according to claim 1, wherein The target process includes an anisotropic etching process.
4. The manufacturing method of the semiconductor structure according to claim 3, characterized in that, The etching rate of the target process in a first direction perpendicular to the substrate is greater than the etching rate in a second direction parallel to the substrate; the first direction intersects with the second direction.
5. The manufacturing method of the semiconductor structure according to claim 1, wherein, A grinding protection layer is further provided between the mask layer and the gate oxide layer; the bottom of the sacrificial material layer, the gate oxide layer and the substrate are continuously etched along the extension direction of the initial trench to remove the sacrificial material layer at the bottom of the initial trench and form a target trench with a target depth in the gate oxide layer and the substrate, comprising: Continue to etch the bottom of the sacrificial material layer, the grinding protection layer, the gate oxide layer and the substrate along the extension direction of the initial groove to remove the sacrificial material layer at the bottom of the initial groove and form a target groove with a target depth in the grinding protection layer, the gate oxide layer and the substrate.
6. The manufacturing method of the semiconductor structure according to claim 5, characterized in that, The sidewalls of the grinding protection layer, the sidewalls of the gate oxide layer and the surface of the sacrificial layer away from the mask layer in the target groove are all flush; After the sacrificial layer is removed, the first step structure is formed between the gate oxide layer, the grinding protection layer and the mask layer.
7. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, Before etching the mask layer to form an initial trench in the mask layer, the method for manufacturing the semiconductor structure further includes: forming an anti-reflection layer on a side of the mask layer away from the gate oxide layer; A patterned photoresist layer is formed on a side of the antireflection layer facing away from the mask layer; the patterned photoresist layer has a mask pattern for defining the initial trench. Wherein, etching the mask layer to form an initial trench in the mask layer includes: Etching the antireflection layer and the mask layer based on the patterned photoresist layer to form the initial trench in the antireflection layer and the mask layer; Removing the patterned photoresist layer.
8. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, After etching the gate oxide layer on the sidewall of the target trench based on the first step structure to form a second step structure between the gate oxide layer and the substrate to expose the top corner of the active region at the top of the substrate, the manufacturing method of the semiconductor structure further includes: Removing the mask layer.
9. The manufacturing method of the semiconductor structure according to claim 1, wherein, After performing a rounding process on the top corner of the active region, the manufacturing method of the semiconductor structure further includes: Forming a seed layer on the bottom and sidewall of the portion of the target trench located in the substrate; Forming an insulating filling layer covering the seed layer and filling the target trench; At least grinding the insulating filling layer to expose the surface of the gate oxide layer facing away from the substrate, and making the insulating filling layer remaining in the target trench correspondingly constitute an isolation structure.
10. A semiconductor structure, characterized in that, Prepared and formed by using the manufacturing method of the semiconductor structure according to any one of claims 1 to 9.