Semiconductor structure and preparation method thereof, and semiconductor device
By adopting a multi-layer epitaxial structure and floating-type doped region design in the semiconductor structure, the problem of low operating frequency of traditional epitaxial chip preparation semiconductor devices is solved, and faster device shutdown and higher operating frequency are achieved.
Patent Information
- Application Number
- CN202510384714.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-28
- Publication Date
- 2025-07-08
AI Technical Summary
The existing semiconductor devices prepared based on traditional epitaxial chips have the problem of low operating frequency.
A multi-layer epitaxial structure is adopted, including at least two layers of the first conductive type epitaxial layer and at least one second conductive type doped region, the doped region is located between adjacent epitaxial layers and includes relatively arranged first and second doped regions, the depth of the doped region is smaller than the thickness of the epitaxial layer, forming a floating-type doped region with the opposite conductivity type to increase the device shutdown speed.
By shortening the life of minority carriers, the operating frequency of semiconductor devices is improved.
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Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure, a method for manufacturing the same, and a semiconductor device. Background Art
[0002] Currently, when manufacturing semiconductor devices, it is mostly necessary to first grow an epitaxial wafer and then fabricate a semiconductor structure based on the epitaxial wafer. However, semiconductor devices fabricated based on traditional epitaxial wafers have the problem of low operating frequency. Summary of the Invention
[0003] Based on this, it is necessary to provide a semiconductor structure, a method for manufacturing the same, and a semiconductor device that can operate at high frequencies.
[0004] In a first aspect, this application provides a semiconductor structure, including:
[0005] A substrate;
[0006] At least two epitaxial layers of a first conductivity type,
[0007] At least one doping region of a second conductivity type, where the first conductivity type is opposite to the second conductivity type;
[0008] The doping region is located between adjacent epitaxial layers and includes a first doping region and a second doping region that are oppositely arranged. The first doping region is located in the one of the adjacent epitaxial layers that is closer to the substrate, and the second doping region is located in the one of the adjacent epitaxial layers that is farther from the substrate. Moreover, the depths of both the first doping region and the second doping region are less than the thickness of the epitaxial layer in which they are located.
[0009] In one embodiment, in the same doping region, the depth of the first doping region is greater than the depth of the second doping region.
[0010] In one embodiment, in a direction parallel to the substrate, a plurality of the doping regions are arranged at intervals.
[0011] In one embodiment, the semiconductor structure further includes an auxiliary layer of a first conductivity type, and the auxiliary layer is located between the substrate and the epitaxial layer.
[0012] In a second aspect, this application also provides a method for manufacturing a semiconductor structure, including:
[0013] Providing a substrate;
[0014] Forming at least two epitaxial layers of a first conductivity type and at least one doping region of a second conductivity type on the substrate respectively;
[0015] Wherein, the first conductivity type is opposite to the second conductivity type; the doping region is located between adjacent epitaxial layers and includes a first doping region and a second doping region which are oppositely arranged. The first doping region is located in one of the adjacent epitaxial layers closer to the substrate, and the second doping region is located in one of the adjacent epitaxial layers farther from the substrate. The depths of both the first doping region and the second doping region are less than the thickness of the epitaxial layer where they are located.
[0016] In one embodiment, forming at least two epitaxial layers of the first conductivity type and at least one doping region of the second conductivity type on the substrate respectively includes:
[0017] Forming one epitaxial layer of the first conductivity type on the substrate, and forming at least one of the first doping regions on the side of the epitaxial layer away from the substrate;
[0018] Forming another epitaxial layer of the first conductivity type on the surface of the epitaxial layer after forming the first doping region, and forming the second doping region on the side of the other epitaxial layer close to the substrate. The second doping region is oppositely arranged with the first doping region.
[0019] In one embodiment, forming one epitaxial layer of the first conductivity type on the substrate and forming at least one of the first doping regions on the side of the epitaxial layer away from the substrate includes:
[0020] Adopting an epitaxial process to form one epitaxial layer of the first conductivity type on the substrate;
[0021] Adopting an ion implantation process to form at least one of the first doping regions on the side of the epitaxial layer away from the substrate.
[0022] In one embodiment, forming another epitaxial layer of the first conductivity type on the inner surface of the epitaxial layer after forming the first doping region and forming the second doping region on the side of the other epitaxial layer close to the substrate includes:
[0023] Under a preset temperature condition, forming another epitaxial layer of the first conductivity type on the inner surface of the epitaxial layer after forming the first doping region;
[0024] During the process of forming the other epitaxial layer, conductive ions in the first doping region diffuse into the other epitaxial layer to form the second doping region.
[0025] In one embodiment, before forming the epitaxial layer on the substrate, the method further includes:
[0026] Forming an auxiliary layer of the first conductivity type on the substrate.
[0027] In a third aspect, the present application also provides a semiconductor device, including the semiconductor structure provided in any of the above embodiments.
[0028] In the above semiconductor structure, its preparation method, and the semiconductor device, the semiconductor structure includes a substrate, at least two epitaxial layers of a first conductivity type, and at least one doped region of a second conductivity type. The doped region is located between adjacent epitaxial layers and includes a first doped region and a second doped region that are oppositely arranged. The first doped region is in the one of the adjacent epitaxial layers that is closer to the substrate, and the second doped region is in the one of the adjacent epitaxial layers that is farther from the substrate. Moreover, the depths of both the first doped region and the second doped region are less than the thickness of the epitaxial layer where they are located. In the present application, the epitaxial structure formed by multiple epitaxial layers can be used to form a drift region in semiconductor devices such as IGBT tubes and MOSFET tubes. Since multiple floating-type doped regions are formed in the epitaxial structure and the conductivity type of the doped region is opposite to that of the epitaxial structure, when the device is turned off, the lifetime of minority carriers is shorter, and the device can be turned off more quickly, improving the operating frequency of the device. Description of the Drawings
[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0030] Figure 1 One of the cross-sectional structure schematic diagrams of the semiconductor structure provided in an embodiment;
[0031] Figure 2 Another cross-sectional structure schematic diagram of the semiconductor structure provided in an embodiment;
[0032] Figure 3 A third cross-sectional structure schematic diagram of the semiconductor structure provided in an embodiment;
[0033] Figure 4 A flow chart of the preparation method of the semiconductor structure provided in an embodiment;
[0034] Figure 5 A flow chart of step S200 in the preparation method of the semiconductor structure provided in an embodiment;
[0035] Figure 6 A cross-sectional structure schematic diagram of the structure obtained in step S210 in the preparation method of the semiconductor structure provided in an embodiment.
[0036] Explanation of the reference numerals:
[0037] 100 - Substrate, 200 - Epitaxial layer, 210 - First epitaxial layer, 220 - Second epitaxial layer, 300 - Doped region, 310 - First doped region, 320 - Second doped region, 400 - Auxiliary layer. Detailed implementation manners
[0038] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant attached drawings. Embodiments of the present application are shown in the attached drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.
[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the description of this application in this specification are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0040] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various layers, conduction types, regions, these layers, conduction types, regions should not be limited by these terms. These terms are only used to distinguish one layer, conduction type, region from another layer, conduction type, region. Therefore, without departing from the teachings of the present invention, the first layer, conduction type, region discussed below can be referred to as the second layer, conduction type, region; for example, the first conduction type can be referred to as the second conduction type, and similarly, the second conduction type can be referred to as the first conduction type; the first conduction type and the second conduction type are different conduction types.
[0041] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. can be used herein to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. Additionally, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.
[0042] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / having" etc. specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the related listed items.
[0043] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes as illustrated are to be expected due to, for example, manufacturing techniques and / or tolerances. Thus, embodiments of the invention should not be limited to the particular shapes of regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, a doped region shown as rectangular will typically have rounded or curved features at its edges and / or an implanted concentration gradient, rather than a binary change from the doped region to the non-doped region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.
[0044] In one embodiment, the present application provides a semiconductor structure, such as Figure 1 , comprising a substrate 100, at least two epitaxial layers 200 of a first conductivity type, and at least one doped region 300 of a second conductivity type.
[0045] The material of the substrate 100 can be any suitable substrate material known in the art. For example, it can be at least one of the materials mentioned below: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, and also includes multi-layer structures composed of these semiconductors, etc. Or it can be silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). Or it can also be double-sided polished wafers (DSP), and can also be a ceramic substrate such as alumina, a quartz or glass substrate, etc. This embodiment is not limited herein.
[0046] The first conduction type is opposite to the second conduction type. Exemplarily, the first conduction type can be N-type, and the second conduction type can be P-type; the first conduction type can be P-type, and correspondingly, the second conduction type can be N-type. In some embodiments, the conduction type of the substrate 100 can be the same as the conduction type of the epitaxial layer 200.
[0047] The number of layers of the epitaxial layer 200 can be 2 layers, 3 layers, 4 layers, 5 layers or more layers, which can be determined according to the actually required thickness of the epitaxial layer. This application embodiment is not limited herein.
[0048] The doped region 300 is located between adjacent epitaxial layers 200, and includes a first doped region 310 and a second doped region 320 which are oppositely arranged. The first doped region 310 is located in the one of the adjacent epitaxial layers 200 that is closer to the substrate 100, and the second doped region 320 is located in the one of the adjacent epitaxial layers 200 that is farther from the substrate 100. And the depths of both the first doped region 310 and the second doped region 320 are less than the thickness of the epitaxial layer where they are located. The depth of the first doped region and the second doped region refers to the extension length of the first doped region 310 and the second doped region 320 in the direction perpendicular to the substrate 100. The thickness of the epitaxial layer refers to the extension length of the epitaxial layer 200 in the direction perpendicular to the substrate. Taking Figure 1 as an example, Figure 1In the first epitaxial layer 210 is the epitaxial layer close to the substrate 100, and the second epitaxial layer 220 is the epitaxial layer far from the substrate 100. The first doping region 310 is located in the first epitaxial layer 210, and the second doping region 320 is located in the second epitaxial layer 220. The depth of the first doping region 310 is less than the thickness of the first epitaxial layer 210, and the depth of the second doping region 320 is less than the thickness of the second epitaxial layer 220. The thicknesses of the first epitaxial layer 210 and the second epitaxial layer 220 may be the same or different. In addition, the doping concentration of the second doping region 320 is equal to or slightly less than the doping concentration of the first doping region 310.
[0049] When the number of epitaxial layers is greater than 2, as Figure 2 shown, in the direction perpendicular to the substrate 100, a plurality of doping regions 300 are arranged at intervals, and the first doping region 310 and the second doping region 320 located in the same epitaxial layer 200 do not contact each other.
[0050] In the embodiment of the present application, the semiconductor structure includes a substrate 100, at least two epitaxial layers 200 of the first conductivity type, and at least one doping region 300 of the second conductivity type. The doping region 300 is located between adjacent epitaxial layers 200 and includes a first doping region 310 and a second doping region 320 which are oppositely arranged. The first doping region 310 is located in the one of the adjacent epitaxial layers 200 close to the substrate 100, and the second doping region 320 is located in the one of the adjacent epitaxial layers 200 far from the substrate 100. The depths of the first doping region 310 and the second doping region 320 are both less than the thickness of the epitaxial layer 200 where they are located. In the present application, the epitaxial structure formed by the multiple epitaxial layers 200 can be used to form a drift region in semiconductor devices such as IGBT tubes and MOSFET tubes. Since a plurality of floating doping regions 300 are formed in the epitaxial structure and the doping region 300 has a conductivity type opposite to that of the epitaxial structure, the lifetime of minority carriers is shorter when the device is turned off, and the device can be turned off more quickly, improving the operating frequency of the device.
[0051] In one embodiment, please refer to Figure 1 or Figure 2 , in the same doping region 300, the depth of the first doping region 310 is greater than the depth of the second doping region 320.
[0052] In one embodiment, please refer to Figure 1 or Figure 2 , in the direction parallel to the substrate 100, a plurality of doping regions 300 are arranged at intervals. It can be understood that the number of doping regions 300 between adjacent epitaxial layers 200 can be 1, 2, 3, 4 or more, and the embodiments of the present application do not limit this here.
[0053] In one embodiment, as Figure 3As shown, the semiconductor structure further includes an auxiliary layer 400 of a first conductivity type, and the auxiliary layer 400 is located between the substrate 100 and the epitaxial layer 200. The material of the auxiliary layer 400 may be the same as that of the epitaxial layer 200.
[0054] Based on the same inventive concept, the present application also provides a method for manufacturing a semiconductor structure, as Figure 4 shown, including steps S100 - S200.
[0055] S100, providing a substrate.
[0056] The material of the substrate 100 may be any suitable substrate material well known in the art. For example, it may be at least one of the materials mentioned below: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, and also includes multilayer structures composed of these semiconductors, etc. Or it may be silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S - SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). Or it may also be a double - side polished wafer (DSP), or a ceramic substrate such as alumina, a quartz or glass substrate, etc. This embodiment does not limit this here.
[0057] S200, forming at least two epitaxial layers of a first conductivity type and at least one doped region of a second conductivity type on the substrate respectively.
[0058] Please continue to refer to Figure 1 or Figure 2 , and at least two epitaxial layers 200 of a first conductivity type and at least one doped region 300 of a second conductivity type can be formed on the substrate by processes such as epitaxial process, deposition process, or ion implantation.
[0059] In an embodiment of the present application, a substrate 100 is provided, and at least two epitaxial layers 200 of a first conductivity type and at least one doping region 300 of a second conductivity type are respectively formed on the substrate 100. The doping region 300 is located between adjacent epitaxial layers 200, and includes a first doping region 310 and a second doping region 320 which are oppositely arranged. The first doping region 310 is located in one of the adjacent epitaxial layers 200 close to the substrate 100, and the second doping region 320 is located in one of the adjacent epitaxial layers 200 far from the substrate 100. Moreover, the depths of both the first doping region 310 and the second doping region 320 are less than the thickness of the epitaxial layer 200 where they are located. In the present application, the epitaxial structure formed by the multiple epitaxial layers 200 can be used to form a drift region in semiconductor devices such as IGBTs and MOSFETs. Since a plurality of floating doping regions 300 are formed in the epitaxial structure, and the doping regions 300 have a conductivity type opposite to that of the epitaxial structure, the minority carrier lifetime is shorter when the device is turned off, and the device can be turned off more quickly, improving the operating frequency of the device.
[0060] In one embodiment, as Figure 5 shown, the above step S200: respectively forming at least two epitaxial layers of a first conductivity type and at least one doping region of a second conductivity type on the substrate includes steps S210 - S220.
[0061] S210, forming an epitaxial layer of a first conductivity type on the substrate, and forming at least one first doping region on the side of the epitaxial layer far from the substrate.
[0062] For ease of description, the epitaxial layer closest to the substrate is referred to as the first epitaxial layer. In the direction away from the substrate, the epitaxial layers are successively referred to as the first epitaxial layer, the second epitaxial layer, the third epitaxial layer... As Figure 6 shown, processes such as molecular beam epitaxy process, vapor phase epitaxy process or metal organic chemical vapor deposition process can be used to form the first epitaxial layer 210 of a first conductivity type on the substrate 100. Then, an ion implantation process can be used to form at least one first doping region 310 on the side of the first epitaxial layer 210 far from the substrate 100. Exemplarily, when the first conductivity type is N type and the second conductivity type is P type, the first doping region 310 may include trivalent ions such as boron ions, aluminum ions or indium ions; when the first conductivity type is P type and the second conductivity type is N type, the first doping region 310 may include pentavalent ions such as phosphorus ions, arsenic ions or antimony ions.
[0063] S220, forming another epitaxial layer of a first conductivity type on the surface of the epitaxial layer after forming the first doping region, and forming a second doping region on the side of the other epitaxial layer close to the substrate, with the second doping region being oppositely arranged to the first doping region.
[0064] More specifically, under a preset temperature condition, another epitaxial layer of a first conductivity type is formed on the inner surface of the epitaxial layer after the formation of the first doped region; during the formation of the other epitaxial layer, the conductive ions in the first doped region diffuse into the other epitaxial layer to form a second doped region.
[0065] The preset temperature condition can be 1000°C - 1200°C. For example, it can be 1000°C, 1050°C, 1100°C, 1150°C, 1200°C or a value therebetween. Please continue to refer to Figure 1 , under the preset temperature condition, a second epitaxial layer 220 of the first conductivity type can be formed on the surface of the first epitaxial layer 210 after the formation of the first doped region 310 by processes such as molecular beam epitaxy process, vapor phase epitaxy process or metalorganic chemical vapor deposition process. During the formation of the second epitaxial layer 220, the conductive ions in the first doped region 310 undergo diffusion movement and diffuse into the newly formed second epitaxial layer 220 to form a second doped region 320. The doping concentration of the second doped region 320 is less than or equal to the doping concentration of the first doped region 310, and the depth of the second doped region 320 is less than the depth of the first doped region 310.
[0066] Optionally, after the formation of the second epitaxial layer 220, a new first doped region can also be formed on the side of the second epitaxial layer away from the substrate, a new epitaxial layer can be formed on the second epitaxial layer, and the steps of ion implantation and formation of a new epitaxial layer can be repeatedly executed until the number of layers or the total depth of the epitaxial layer meets the requirements.
[0067] In one embodiment, before forming the epitaxial layer on the substrate, the preparation method of the semiconductor structure of the present application further includes the step of forming an auxiliary layer of a first conductivity type on the substrate. Specifically, an auxiliary layer 400 of the first conductivity type can be formed on the substrate 100 by processes such as a deposition process or an epitaxial process, and the material of the auxiliary layer 400 can be the same as the material of the epitaxial layer 200.
[0068] In one embodiment, the present application further provides a semiconductor device, which includes the semiconductor structure provided in any of the above embodiments.
[0069] It should be understood that although the steps in the above flowcharts are shown in sequence according to the indications in the figures, these steps are not necessarily executed in the order indicated by the figures. Unless there is a clear description in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the figures may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.
[0070] In the description of this specification, the description referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or features described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.
[0071] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.
[0072] The above-described embodiments only represent several implementation manners of the present application, and the description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.
Claims
1. A semiconductor structure, characterized in that, Comprising: A substrate; At least two epitaxial layers of a first conductivity type, At least one doped region of a second conductivity type, the first conductivity type being opposite to the second conductivity type; The doped region is located between adjacent epitaxial layers and includes a first doped region and a second doped region which are oppositely arranged. The first doped region is located in one of the adjacent epitaxial layers close to the substrate, and the second doped region is located in one of the adjacent epitaxial layers far from the substrate. The depths of both the first doped region and the second doped region are less than the thickness of the epitaxial layer where they are located.
2. The semiconductor structure according to claim 1, wherein, In the same doped region, the depth of the first doped region is greater than the depth of the second doped region.
3. The semiconductor structure according to claim 1, wherein In a direction parallel to the substrate, a plurality of the doped regions are arranged at intervals.
4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure further includes an auxiliary layer of a first conductivity type, and the auxiliary layer is located between the substrate and the epitaxial layer.
5. A method for preparing a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming at least two epitaxial layers of a first conductivity type and at least one doped region of a second conductivity type on the substrate respectively; Wherein, the first conductivity type is opposite to the second conductivity type; the doped region is located between adjacent epitaxial layers and includes a first doped region and a second doped region which are oppositely arranged. The first doped region is located in one of the adjacent epitaxial layers close to the substrate, and the second doped region is located in one of the adjacent epitaxial layers far from the substrate. The depths of both the first doped region and the second doped region are less than the thickness of the epitaxial layer where they are located.
6. The method according to claim 5, wherein The forming at least two epitaxial layers of a first conductivity type and at least one doped region of a second conductivity type on the substrate respectively includes: Forming an epitaxial layer of a first conductivity type on the substrate, and forming at least one of the first doped regions on a side of the epitaxial layer far from the substrate; Forming another epitaxial layer of a first conductivity type on the surface of the epitaxial layer after forming the first doped region, and forming the second doped region on a side of the other epitaxial layer close to the substrate, the second doped region being oppositely arranged to the first doped region.
7. The method according to claim 6, wherein The forming an epitaxial layer of a first conductivity type on the substrate, and forming at least one of the first doped regions on a side of the epitaxial layer far from the substrate includes: Adopting an epitaxial process to form an epitaxial layer of a first conductivity type on the substrate; Adopting an ion implantation process to form at least one of the first doped regions on a side of the epitaxial layer far from the substrate.
8. The method according to claim 6, wherein The forming another epitaxial layer of a first conductivity type on the inner surface of the epitaxial layer after forming the first doped region, and forming the second doped region on a side of the other epitaxial layer close to the substrate includes: Under a preset temperature condition, forming another epitaxial layer of a first conductivity type on the inner surface of the epitaxial layer after forming the first doped region; During the process of forming the other epitaxial layer, conductive ions in the first doped region diffuse into the other epitaxial layer to form the second doped region.
9. The method according to claim 5, wherein Before forming the epitaxial layer on the substrate, the method further includes: Forming an auxiliary layer of a first conductivity type on the substrate.
10. A semiconductor device, characterized in that, Comprising a semiconductor structure as described in any one of claims 1-4.