Semiconductor structure and manufacturing method thereof
By using a spin-coated glass layer as a buffer layer in the metal gate process, the problem of metal residue at the edge of the wafer is solved, and the yield and process reliability of the semiconductor structure are improved.
Patent Information
- Application Number
- CN202510333647.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-20
- Publication Date
- 2025-07-08
AI Technical Summary
In the existing metal gate process, metal residues are easily generated in the wafer edge area, resulting in peeling defects and affecting yields.
A spin-coated glass layer is formed as a buffer layer on the surface of the dielectric layer between the zero layer, which raises the overall thickness and surface uniformity of the substrate, reveals the top surface of the dummy gate structure through chemical mechanical polishing, and retains the spin-coated glass buffer layer in the preset width area to protect the substrate from etching and prevent metal residue.
It effectively prevents metal residues, improves the yield of semiconductor structures, avoids peeling defects in subsequent processes, and improves the reliability of the process.
Smart Images
Figure CN120282516A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductors and relates to a semiconductor structure and a manufacturing method thereof. Background Art
[0002] Metal Gate is an important technology in semiconductor manufacturing, which uses metal materials as the gate materials of transistors. Compared with traditional polysilicon gates, metal gates have higher conductivity, lower resistivity, and can be better compatible with high-k dielectric materials (such as HfO2, HfSiON). Metal gates are mainly applied in the High-k Metal Gate (HKMG) process, and the HKMG process combines high-k dielectric materials and metal gates, which can improve the performance and power consumption performance of transistors.
[0003] The manufacturing of metal gates generally adopts the following two processes:
[0004] (1) Gate-First process: directly deposit metal gate materials above the gate dielectric layer.
[0005] (2) Gate-Last process: first form a polysilicon dummy gate, and then replace it with a metal gate.
[0006] At some technology node platforms, after chemical mechanical polishing (CMP) of the deposited metal gate materials, serious peeling defects exist at the edges of the obtained wafers. In subsequent processes, it also includes depositing a Contact Glue Layer (CTG for short), which is mainly used to enhance the adhesion between metals and semiconductor materials, reduce resistance, and prevent metal diffusion to the substrate. The contact glue layer usually consists of titanium (Ti) and titanium nitride (TiN), and these materials are selected because of their good adhesion performance. For example, before tungsten deposition, a contact glue layer composed of Ti and TiN (Ti / TiN) is used to enhance adhesion, reduce resistance, and prevent tungsten diffusion to the substrate. However, the aforementioned defects still exist during the subsequent deposition of CTG, seriously affecting the yield.
[0007] Therefore, how to improve the process flow of metal gates to reduce the residue after the deposition of metal gate materials and improve the yield has become an important technical problem that needs to be solved urgently by those skilled in the art.
[0008] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention
[0009] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a semiconductor structure and a manufacturing method thereof, which are used to solve the problem that metal residues are easily generated in the wafer edge region during the process of the existing metal gate, resulting in peeling defects.
[0010] To achieve the above object and other related objects, the present invention provides a manufacturing method of a semiconductor structure, including the following steps:
[0011] Provide a substrate, and form a dummy gate structure on the substrate, the dummy gate structure includes a dummy polysilicon gate and sidewalls located on both sides of the dummy polysilicon gate;
[0012] Form a zero-layer interlayer dielectric layer covering the dummy gate structure on the substrate. In a preset width region at the edge of the substrate, the thickness of the zero-layer interlayer dielectric layer gradually decreases first and then gradually increases in the direction from the center of the substrate to the edge of the substrate;
[0013] Form a spin-on glass layer on the surface of the zero-layer interlayer dielectric layer;
[0014] Perform a first chemical mechanical polishing to expose the top surface of the dummy gate structure. The spin-on glass layer remains in the preset width region after the first chemical mechanical polishing and serves as a spin-on glass buffer layer;
[0015] Remove the dummy polysilicon gate to obtain a gate trench defined by the sidewalls;
[0016] Deposit a metal gate material to fill the gate trench, and perform a second chemical mechanical polishing to remove the metal gate material outside the gate trench, so as to obtain a metal gate located in the gate trench;
[0017] Form a capping dielectric layer and a contact layer. The capping dielectric layer covers the surface of the zero-layer interlayer dielectric layer and the spin-on glass buffer layer, and has a contact hole opened above the metal gate. The contact layer covers the surface of the capping dielectric layer and fills into the contact hole to be electrically connected to the metal gate.
[0018] Optionally, the range of the preset width is 0.4 mm to 1.1 mm.
[0019] Optionally, the top surface of the spin-on glass buffer layer is not higher than the top surface of the metal gate.
[0020] Optionally, the material of the metal gate includes Al, and the thickness range of the metal gate is 1000 to 3000 angstroms.
[0021] Optionally, the capping dielectric layer includes a TEOS layer, and the contact layer includes at least one of a Ti layer and a TiN layer.
[0022] The present invention also provides a semiconductor structure, including:
[0023] a substrate;
[0024] a metal gate located on the substrate;
[0025] a zero - layer interlayer dielectric layer covering the substrate and having a top surface not higher than the top surface of the metal gate. In a preset width region at the edge of the substrate, the thickness of the zero - layer interlayer dielectric layer shows a trend of gradually decreasing first and then gradually increasing in the direction from the center of the substrate to the edge of the substrate;
[0026] a spin - on glass buffer layer located on the surface of the zero - layer interlayer dielectric layer in the preset width region;
[0027] a covering dielectric layer covering the surfaces of the zero - layer interlayer dielectric layer and the spin - on glass buffer layer and having a contact hole above the metal gate;
[0028] a contact layer covering the surface of the covering dielectric layer and filling into the contact hole to be electrically connected to the metal gate.
[0029] Optionally, the range of the preset width is 0.4 mm to 1.1 mm.
[0030] Optionally, the top surface of the spin - on glass buffer layer is not higher than the top surface of the metal gate.
[0031] Optionally, the material of the metal gate includes Al, and the thickness range of the metal gate is 1000 to 3000 angstroms.
[0032] Optionally, the covering dielectric layer includes a TEOS layer, and the contact layer includes at least one of a Ti layer and a TiN layer.
[0033] As described above, in the manufacturing method of the semiconductor structure of the present invention, after forming the zero - layer interlayer dielectric layer covering the pseudo - gate structure, a spin - on glass layer is newly added on the surface of the zero - layer interlayer dielectric layer, which can increase the overall thickness and surface uniformity of the substrate. Thus, in the process of the first chemical mechanical polishing to expose the top surface of the pseudo - gate structure, the thinner region of the zero - layer interlayer dielectric layer in the edge region of the substrate will not be lost due to chemical mechanical polishing, and after the first chemical mechanical polishing, the spin - on glass layer still remains in the preset width region. This remaining spin - on glass layer serves as a spin - on glass buffer layer, which can protect the substrate from being etched during the subsequent process of removing the pseudo - polysilicon gate. Further, due to the existence of the spin - on glass buffer layer, the thinner region of the zero - layer interlayer dielectric layer in the edge region of the substrate is filled, and after depositing the metal gate material and performing the second chemical mechanical polishing, there is no metal residue in this region, thus cutting off the generation of peeling defects at the source, not affecting the subsequent processes, and ultimately contributing to the improvement of the yield. Description of the Drawings
[0034] Figure 1 A schematic diagram of the structure obtained after chemical mechanical polishing of the interlayer dielectric layer of the zero-th layer during the formation of Al metal residue.
[0035] Figure 2 A schematic diagram of the structure obtained after removing the pseudo-polysilicon gate through etching during the formation of Al metal residue.
[0036] Figure 3 A schematic diagram of the structure obtained after depositing Al metal gate material and performing chemical mechanical polishing during the formation of Al metal residue.
[0037] Figure 4 A schematic diagram of the structure obtained after forming the dielectric capping layer and the contact layer during the formation of Al metal residue.
[0038] Figure 5 A process flow diagram of the manufacturing method of the semiconductor structure of the present invention.
[0039] Figure 6 A schematic diagram of the structure obtained after forming a pseudo-gate structure on a substrate in the manufacturing method of the semiconductor structure of the present invention.
[0040] Figure 7 A schematic diagram of the structure obtained after forming the interlayer dielectric layer of the zero-th layer covering the pseudo-gate structure on a substrate in the manufacturing method of the semiconductor structure of the present invention.
[0041] Figure 8 A schematic diagram of the structure obtained after forming a spin-on glass layer on the surface of the interlayer dielectric layer of the zero-th layer in the manufacturing method of the semiconductor structure of the present invention.
[0042] Figure 9 A schematic diagram of the structure obtained after performing the first chemical mechanical polishing to expose the top surface of the pseudo-gate structure in the manufacturing method of the semiconductor structure of the present invention.
[0043] Figure 10 A schematic diagram of the structure obtained after removing the pseudo-polysilicon gate to obtain a gate trench defined by sidewalls in the manufacturing method of the semiconductor structure of the present invention.
[0044] Figure 11 A schematic diagram of the structure obtained after depositing metal gate material and performing the second chemical mechanical polishing to remove the metal gate material outside the gate trench in the manufacturing method of the semiconductor structure of the present invention.
[0045] Figure 12 A schematic diagram of the structure obtained after forming the capping dielectric layer and the contact layer in the manufacturing method of the semiconductor structure of the present invention.
[0046] Description of Reference Numerals
[0047] 101 Zeroth interlayer dielectric layer
[0048] 102 Substrate
[0049] 103 Side Wall
[0050] 104 Pseudo polysilicon gate
[0051] 105 Gate trench
[0052] 106 substrate groove
[0053] 107 Metal Grid
[0054] 108 Metal Residues
[0055] 109 Defective Area
[0056] 110 Dielectric Cover
[0057] 111 Contact layer
[0058] 112 Contact hole
[0059] Steps S1 to S7
[0060] 201 Substrate
[0061] 202 Pseudo polysilicon gate
[0062] 203 Side Wall
[0063] 204 Interface layer
[0064] 205 Zeroth interlayer dielectric layer
[0065] 206 Spin-on glass layer
[0066] 206a Spin-on glass buffer layer
[0067] 207 Gate Trench
[0068] 208 Metal Grid
[0069] 209 Covering dielectric layer
[0070] 210 Contact layer
[0071] 211 Contact hole
[0072] M Preset width area DETAILED DESCRIPTION
[0073] The inventors of this application analyzed the formation mechanism of the peeling defects existing at the wafer edge: First, by analyzing the peeled-off matter through elemental analysis, it was found that it contained Al / Ti. After further in-depth analysis, it was determined that the reason for the generation of the peeled-off matter was that when depositing the bottom layer, the interlayer dielectric layer 0 (ILD0) through the High Aspect Ratio Process (HARP), due to the gradual decrease of the reaction gas concentration from the wafer center region to the wafer edge region, the thickness of the interlayer dielectric layer 0 also gradually decreased from the wafer center region to the wafer edge region. And after chemical mechanical polishing, the thickness of the oxide layer deposited by HARP showed a process of thinning → disappearing → thickening from the wafer center region to the wafer edge region. That is to say, there were areas on the upper surface of the substrate without the protection of the HARP oxide layer after CMP. These areas would be over-etched to form relatively deep grooves after the etching process of Dummy Poly Remove (DPR), resulting in Al metal residues generated at the grooves after the deposition of the metal gate material, and the subsequent metal CMP could not cover the metal Al in the grooves. Due to the large difference in the thermal expansion coefficients between metal Al and SiO2, these Al metal residues were prone to peeling in the subsequent process, leading to the formation of abnormal patterns during CTG deposition.
[0074] As an example, please refer to Figures 1 to 4 , showing the formation process of Al metal residues, where Figure 1 shows a schematic diagram of the structure obtained after chemical mechanical polishing of the bottom layer, interlayer dielectric layer 101. Among them, the bottom layer, interlayer dielectric layer 101 originally covered the dummy polycrystalline silicon gate 104 with sidewalls 103 on the substrate 102. After chemical mechanical polishing, the bottom layer, interlayer dielectric layer 101 was thinned to expose the top surface of the dummy polycrystalline silicon gate 104, and in some areas between the dummy polycrystalline silicon gate 104 and the wafer edge, there was no coverage of the bottom layer, interlayer dielectric layer 101. Figure 2 shows a schematic diagram of the structure obtained after removing the dummy polycrystalline silicon gate 104 by etching. Among them, while the dummy polycrystalline silicon gate 104 was removed to obtain the gate trench 105, the substrate in the area without the coverage of the bottom layer, interlayer dielectric layer 101 between the dummy polycrystalline silicon gate 104 and the wafer edge was etched through to form a substrate groove 106. Figure 3 shows a schematic diagram of the structure obtained after depositing the Al metal gate material and chemical mechanical polishing. Among them, when the Al metal gate material filled the gate trench 105 to obtain the metal gate 107, it also filled the substrate groove 106, resulting in the formation of metal residues 108. The area with the metal residues 108 was the defect area 109. The defect area 109 was located at the wafer edge and had a width of approximately 0.7 mm. Figure 4Shown is a schematic diagram of the structure obtained after forming the dielectric capping layer 110 and the contact layer 111. Among them, the dielectric capping layer 110 covers the surface of the zero-th interlayer dielectric layer 101, and a contact hole 112 is formed in the metal gate 107. The contact layer 111 covers the surface of the dielectric capping layer 110 and fills into the contact hole 112 to be electrically connected to the metal gate 107.
[0075] Regarding the formation mechanism of the peeling defect, through a large number of studies, the inventors of the present application proposed an improvement method. After depositing the zero-th interlayer dielectric layer (ILD0), a spin-on glass layer is formed as a buffer layer by using a spin coating process, thereby increasing the overall thickness and surface uniformity of the wafer. After the ILD0 CMP stops at the pseudo gate polysilicon, only the spin-on glass layer in a preset width region at the edge of the wafer is retained as the buffer layer, thus avoiding the risk of substrate penetration during the subsequent removal of the pseudo polysilicon gate, cutting off the metal residue defect after the deposition of the metal gate material from the source, and improving the peeling defect problem.
[0076] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0077] It should be emphasized that the term "comprising / including" when used herein refers to the presence of features, whole things, steps or components, but does not exclude the presence or addition of one or more other features, whole things, steps or components.
[0078] Features described and / or shown for one implementation manner can be used in the same or similar manner in one or more other implementation manners, combined with the features in other implementation manners, or replace the features in other implementation manners.
[0079] When detailing the embodiments of the present invention, for the convenience of description, the schematic diagrams showing the device structure will be enlarged locally not in accordance with the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention herein. In addition, in actual production, three-dimensional spatial dimensions including length, width and depth should be included.
[0080] For ease of description, spatial relationship terms such as "below", "beneath", "lower", "under", "above", "on" may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relationship terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation depicted in the drawings. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there can be one or more intervening layers.
[0081] In the context of the present application, the structure in which the first feature is "above" the second feature as described may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
[0082] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0083] The present invention provides a method for manufacturing a semiconductor structure. Please refer to Figure 5 , shown as a process flow diagram of the method, including the following steps:
[0084] S1: Provide a substrate, and form a dummy gate structure on the substrate. The dummy gate structure includes a dummy polysilicon gate and sidewalls located on both sides of the dummy polysilicon gate;
[0085] S2: Form a zero-th interlayer dielectric layer covering the dummy gate structure on the substrate. In a preset width region at the edge of the substrate, the thickness of the zero-th interlayer dielectric layer gradually decreases first and then gradually increases in the direction from the center of the substrate to the edge of the substrate;
[0086] S3: Form a spin-on glass layer on the surface of the zero-th interlayer dielectric layer;
[0087] S4: Perform a first chemical mechanical polishing to expose the top surface of the dummy gate structure. The spin-on glass layer remains in the preset width region after the first chemical mechanical polishing and serves as a spin-on glass buffer layer;
[0088] S5: Remove the dummy polysilicon gate to obtain a gate trench defined by the sidewalls;
[0089] S6: Deposit a metal gate material to fill the gate trench, and perform a second chemical mechanical polishing to remove the metal gate material outside the gate trench, thereby obtaining a metal gate located in the gate trench;
[0090] S7: Form a capping dielectric layer and a contact layer. The capping dielectric layer covers the surface of the zero-th interlayer dielectric layer and the spin-on glass buffer layer, and has a contact hole formed above the metal gate. The contact layer covers the surface of the capping dielectric layer and fills into the contact hole to be electrically connected to the metal gate.
[0091] The above steps will be described in detail below in conjunction with the structural diagrams.
[0092] First, please refer to Figure 6 , and perform the step S1: Provide a substrate 201, and form a dummy gate structure on the substrate 201. The dummy gate structure includes a dummy polysilicon gate 202 and sidewalls 203 located on both sides of the dummy polysilicon gate 202.
[0093] As an example, the substrate 201 is a Si substrate, a silicon germanium substrate, a silicon carbide substrate, a III-V compound substrate, or other suitable substrates.
[0094] As an example, the surface of the substrate 201 further has an interface layer 204, and the interface layer 204 may be, for example, a silicon nitride layer, which is generated by a front-layer stress engineering process and helps to improve device performance.
[0095] In some embodiments, a pre-formed high-k dielectric layer (not shown) is further provided between the dummy polysilicon gate 202 and the substrate 201. The high-k dielectric layer may be, for example, HfO2, HfSiO, HfSiON, HfTaO, Al2O3, or other suitable high-k materials.
[0096] Refer to Figure 7 again, and perform the step S2: Form a zero-th interlayer dielectric layer 205 covering the dummy gate structure on the substrate 201. In a preset width region M at the edge of the substrate 201, the thickness of the zero-th interlayer dielectric layer 205 gradually decreases first and then gradually increases in the direction from the center of the substrate to the edge of the substrate. For example Figure 7 in, the thickness of the dielectric layer at B is less than the thicknesses of the dielectric layers at A and C.
[0097] As an example, the zero-th interlayer dielectric layer 205 is deposited by a High Aspect Ratio Process (HARP). Among them, a thermal chemical reaction of ozone (O3) and tetraethyl orthosilicate (TEOS) is used to form an oxide film, that is, a HARP film. This process does not involve the use of plasma, so damage to the semiconductor structure or substrate caused by plasma can be avoided. Moreover, the aspect ratios of the recessed areas on both sides of the pseudo-gate structure are relatively high, and the HARP process can better fill these high-aspect-ratio structural gaps and can provide a pore-free thin film.
[0098] Specifically, since the concentration of the reaction gas gradually decreases from the center region of the wafer to the edge region of the wafer, the thickness of the zero-th interlayer dielectric layer 205 also shows a gradually decreasing trend from the center region of the wafer to the edge region of the wafer. And due to factors such as the arc shape of the wafer edge, the thickness of the zero-th interlayer dielectric layer 205 gradually increases again after decreasing to the lowest value, so that in a preset width region M at the edge of the substrate 201, the thickness of the zero-th interlayer dielectric layer 205 shows a trend of first gradually decreasing and then gradually increasing in the direction from the center of the substrate to the edge of the substrate.
[0099] Specifically, the "preset width region at the edge of the substrate" defined in the present invention refers to a region that starts from the edge of the wafer and extends a preset width in the direction pointing to the center of the wafer.
[0100] As an example, the range of the preset width is 0.4 mm to 1.1 mm, for example, about 0.7 mm.
[0101] Please refer to Figure 8 again, and perform the step S3: form a spin-on glass layer 206 on the surface of the zero-th interlayer dielectric layer 205.
[0102] As an example, forming the spin-on glass layer 206 includes the following steps:
[0103] (1) Drop a spin-on glass material (for example, it can be a silica-based silicate liquid compound or other suitable materials) at a preset position on the wafer, such as the center of the wafer, and then quickly rotate the wafer to evenly coat the solution on the surface of the wafer by centrifugal force to form a uniform liquid film.
[0104] (2) After spin coating is completed, perform soft baking to remove the solvent. This step transforms the spin-on glass from a liquid state to a semi-solid state, and at the same time uses the fluidity and capillary action of the spin-on glass to fill the gaps and depressions on the surface of the wafer to achieve local planarization;
[0105] (3) After soft baking, the wafer is placed in a high-temperature environment (e.g., 200 °C) for further curing. At high temperature, the organic groups in the spin-on glass undergo a cross-linking reaction to form a solid glass layer, ultimately forming a dielectric material close to silicon dioxide (SiO2).
[0106] It should be noted that, in order to achieve an increase in the overall thickness of the wafer and good uniformity, single-layer deposition or multi-layer deposition can be employed as needed. For example, when the pseudo-gate structure is relatively high, multi-layer deposition can be used, such as by performing multiple spin-coatings and step-by-step curing.
[0107] Refer again to Figure 9 and perform step S4: perform a first chemical mechanical polishing to expose the top surface of the pseudo-gate structure. The spin-on glass layer 206 remains in the preset width region after the first chemical mechanical polishing and serves as the spin-on glass buffer layer 206a.
[0108] Specifically, due to the presence of the spin-on glass layer 206, the overall thickness of the substrate and the surface uniformity are increased, which is beneficial to improving the uniformity of the first chemical mechanical polishing. Moreover, due to the protective effect of the spin-on glass layer 206, the thinner regions of the zero-layer interlayer dielectric layer in the edge region of the substrate will not be damaged due to chemical mechanical polishing.
[0109] Specifically, after the first chemical mechanical polishing, the spin-on glass layer 206 remains in the thinner regions of the zero-layer interlayer dielectric layer in the edge region of the substrate, such as the region below the sidewall 203. This remaining spin-on glass layer serves as the spin-on glass buffer layer 206a.
[0110] In some embodiments, the spin-on glass buffer layer 206a only exists on the surface of the preset width region M.
[0111] Refer again to Figure 10 and perform step S5: remove the pseudo-polysilicon gate 202 to obtain the gate trench 207 defined by the sidewall 203.
[0112] As an example, the pseudo-polysilicon gate 202 can be removed by wet etching, dry etching, a combination thereof, or other suitable methods. For example, in some embodiments, a dry etching of the polysilicon is performed using a mixed gas of HBr and O2 to remove the pseudo-polysilicon gate 202. Among them, silicon reacts with bromine to form a weakly volatile silicon bromide by-product, thereby achieving a high selectivity of polysilicon to silicon dioxide. In other embodiments, CF4 or NF3 is used as the etching gas. In still other embodiments, a wet etching of the polysilicon is performed using a chemical solution such as tetramethylammonium hydroxide (TMAH) to remove the pseudo-polysilicon gate 202.
[0113] Specifically, due to the presence of the spin-on glass buffer layer 206a, during the process of removing the pseudo-polysilicon gate 202, the substrate 201 will not be etched because it is protected.
[0114] Please refer to Figure 11 again, and perform the step S6: depositing a metal gate material to fill the gate trench 207, and performing a second chemical mechanical polishing to remove the metal gate material outside the gate trench 207, so as to obtain a metal gate 208 located in the gate trench 207.
[0115] As an example, the material of the metal gate 208 includes Al or other suitable materials, and the thickness range of the metal gate 208 is 1000 - 3000 angstroms, such as 2000 angstroms.
[0116] As an example, the top surface of the spin-on glass buffer layer 206a is not higher than the top surface of the metal gate 208.
[0117] Specifically, since the spin-on glass buffer layer 206a fills the thinner region of the zero-th interlayer dielectric layer 205 in the substrate edge region, after depositing the metal gate material and performing the second chemical mechanical polishing, there is no metal residue in this region, thus cutting off the generation of peeling defects at the source, not affecting the subsequent processes, and ultimately contributing to the improvement of the yield.
[0118] Please refer to Figure 12 again, and perform the step S7: forming a capping dielectric layer 209 and a contact layer 210. The capping dielectric layer 209 covers the surface of the zero-th interlayer dielectric layer 205 and the spin-on glass buffer layer 206a, and a contact hole 211 is formed above the metal gate 208. The contact layer 210 covers the surface of the capping dielectric layer 209 and fills into the contact hole 211 to be electrically connected to the metal gate 208.
[0119] As an example, the capping dielectric layer includes a TEOS layer or other suitable insulating material layer, and the contact layer 210 includes at least one of a Ti layer and a TiN layer.
[0120] So far, a semiconductor structure is fabricated, which includes a substrate 201, a metal gate 208, a zero-th layer of interlayer dielectric 205, a spin-on glass buffer layer 206a, a capping dielectric layer 209, and a contact layer 210. Among them, the metal gate 208 is located on the substrate 201, the zero-th layer of interlayer dielectric 205 covers the substrate 201 and its top surface is not higher than the top surface of the metal gate 208. In a preset width region at the edge of the substrate 201, the thickness of the zero-th layer of interlayer dielectric 205 shows a trend of first gradually decreasing and then gradually increasing in the direction from the center of the substrate 201 to the edge of the substrate 201. The spin-on glass buffer layer 206a is located on the surface of the zero-th layer of interlayer dielectric 205 in the preset width region. The capping dielectric layer 209 covers the surfaces of the zero-th layer of interlayer dielectric 205 and the spin-on glass buffer layer 206a, and a contact hole is formed above the metal gate 208. The contact layer 210 covers the surface of the capping dielectric layer 209 and fills into the contact hole to be electrically connected to the metal gate 208.
[0121] As an example, the range of the preset width is 0.4 mm to 1.1 mm.
[0122] As an example, the top surface of the spin-on glass buffer layer is not higher than the top surface of the metal gate.
[0123] As an example, the material of the metal gate includes Al, and the thickness range of the metal gate is 1000 to 3000 angstroms.
[0124] As an example, the capping dielectric layer includes a TEOS layer, and the contact layer includes at least one of a Ti layer and a TiN layer.
[0125] In summary, after forming the zero-th layer of interlayer dielectric covering the pseudo-gate structure in the manufacturing method of the semiconductor structure of the present invention, a spin-on glass layer is newly added on the surface of the zero-th layer of interlayer dielectric, which can increase the overall thickness and surface uniformity of the substrate. Thus, in the process of the first chemical mechanical polishing to expose the top surface of the pseudo-gate structure, the thinner region of the zero-th layer of interlayer dielectric in the edge region of the substrate will not be damaged due to the chemical mechanical polishing. And after the first chemical mechanical polishing, the spin-on glass layer still remains in the preset width region. This remaining spin-on glass layer serves as a spin-on glass buffer layer, which can protect the substrate from being etched during the subsequent process of removing the pseudo-polysilicon gate. Further, due to the existence of the spin-on glass buffer layer, the thinner region of the zero-th layer of interlayer dielectric in the edge region of the substrate is filled. After depositing the metal gate material and performing the second chemical mechanical polishing, there is no metal residue in this region, thus cutting off the generation of peeling defects at the source and not affecting the subsequent processes, ultimately contributing to the improvement of the yield. Therefore, the present invention effectively overcomes various drawbacks in the prior art and has high industrial utilization value.
[0126] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A manufacturing method of a semiconductor structure, characterized in that, Including the following steps: Providing a substrate, forming a dummy gate structure on the substrate, the dummy gate structure including a dummy polysilicon gate and sidewalls located on both sides of the dummy polysilicon gate; Forming a zero-th interlayer dielectric layer covering the dummy gate structure on the substrate. In a preset width region at the edge of the substrate, the thickness of the zero-th interlayer dielectric layer shows a trend of gradually decreasing first and then gradually increasing in the direction from the center of the substrate to the edge of the substrate; Forming a spin-on glass layer on the surface of the zero-th interlayer dielectric layer; Performing a first chemical mechanical polishing to expose the top surface of the dummy gate structure. The spin-on glass layer remains in the preset width region after the first chemical mechanical polishing and serves as a spin-on glass buffer layer; Removing the dummy polysilicon gate to obtain a gate trench defined by the sidewalls; Depositing a metal gate material to fill the gate trench, and performing a second chemical mechanical polishing to remove the metal gate material outside the gate trench, obtaining a metal gate located in the gate trench; Forming a capping dielectric layer and a contact layer. The capping dielectric layer covers the surface of the zero-th interlayer dielectric layer and the spin-on glass buffer layer and has a contact hole above the metal gate. The contact layer covers the surface of the capping dielectric layer and fills into the contact hole to be electrically connected to the metal gate.
2. The manufacturing method of the semiconductor structure according to claim 1, characterized in that: The range of the preset width is 0.4 mm to 1.1 mm.
3. The manufacturing method of the semiconductor structure according to claim 1, characterized in that: The top surface of the spin-on glass buffer layer is not higher than the top surface of the metal gate.
4. The manufacturing method of the semiconductor structure according to claim 1, characterized in that: The material of the metal gate includes Al, and the thickness range of the metal gate is 1000 to 3000 angstroms.
5. The manufacturing method of the semiconductor structure according to claim 1, characterized in that: The capping dielectric layer includes a TEOS layer, and the contact layer includes at least one of a Ti layer and a TiN layer.
6. A semiconductor structure, characterized in that, Including: A substrate; A metal gate, located on the substrate; A zero-th interlayer dielectric layer, covering the substrate and having a top surface not higher than the top surface of the metal gate. In a preset width region at the edge of the substrate, the thickness of the zero-th interlayer dielectric layer shows a trend of gradually decreasing first and then gradually increasing in the direction from the center of the substrate to the edge of the substrate; A spin-on glass buffer layer, located on the surface of the zero-th interlayer dielectric layer in the preset width region; A capping dielectric layer, covering the surface of the zero-th interlayer dielectric layer and the spin-on glass buffer layer and having a contact hole above the metal gate; A contact layer, covering the surface of the capping dielectric layer and filling into the contact hole to be electrically connected to the metal gate.
7. The semiconductor structure according to claim 6, wherein: The range of the preset width is 0.4 mm to 1.1 mm.
8. The semiconductor structure according to claim 6, wherein: The top surface of the spin-on glass buffer layer is not higher than the top surface of the metal gate.
9. The semiconductor structure according to claim 6, wherein: The material of the metal gate includes Al, and the thickness range of the metal gate is 1000 to 3000 angstroms.
10. The semiconductor structure according to claim 6, wherein: The capping dielectric layer includes a TEOS layer, and the contact layer includes at least one of a Ti layer and a TiN layer.