Semiconductor structure with multiple threshold voltages and manufacturing method thereof
By combining multiple conductivity-type ion implantation and threshold voltage regulation photocoats in the semiconductor layer, the problem of high cost and complex process preparation of multiple threshold voltage semiconductor devices in the prior art is solved, and a low-cost and efficient preparation of multiple threshold voltage devices is achieved, which improves the device's leakage protection performance and application range.
Patent Information
- Application Number
- CN202410022543.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-05
- Publication Date
- 2025-07-08
AI Technical Summary
The prior art is costly and complex in preparing a variety of semiconductor devices with different threshold voltages, making it difficult to provide more types of products without adding a photocoat.
By employing a combination of multiple conductivity type ion implantation and threshold voltage regulation photocoats in the semiconductor layer, a semiconductor structure with multiple threshold voltages is formed, including making MOS transistors with different threshold voltages on the same semiconductor layer.
It is realized that semiconductor devices with multiple threshold voltages are prepared without adding a mask, reducing costs, simplifying processes, improving the leakage resistance of the device, and expanding the application range.
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Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor technology, and relates to a semiconductor structure with multiple threshold voltages and a manufacturing method thereof. Background Art
[0002] The threshold voltage refers to the voltage value at which, in a semiconductor device, when the voltage of an input signal reaches a certain threshold, the device begins to respond or switch states. This threshold voltage is usually defined as the critical point from the non-responsive state to the responsive state.
[0003] The threshold voltage is one of the important electrical parameters characterizing the performance of semiconductor devices, and semiconductor devices corresponding to different threshold voltages have different applications. Taking core devices and input / output devices (I / O devices) as an example, due to different application scenarios, in order to enable the two types of devices to have different threshold voltages and functions, currently in the semiconductor industry, first, the same photomask is used to perform well region ion implantation on the regions corresponding to the two types of devices, and then another photomask is used to perform an additional threshold voltage Vt ion implantation in the core device region, while matching different gate oxide thicknesses and lightly doped source / drain ion implantation conditions, etc., so as to fabricate two semiconductor devices with different threshold voltages.
[0004] In recent years, with the continuous improvement of modern integrated circuit manufacturing technology, semiconductor devices are increasingly widely used in various products, and different requirements are also put forward for the threshold voltages of different semiconductor devices. Usually, if more types of products are to be provided on the basis of the original process, new processes need to be restarted, such as re-opening photomasks and re-formulating new process steps, wasting a large amount of time and cost. In addition, as the node gradually decreases, the requirements for device performance gradually increase, and the probability of source / drain punch-through of MOS transistors becomes larger, which poses higher requirements and difficulties for the new processes.
[0005] Therefore, how to form products with better performance and more types at the least cost on the basis of being able to provide the original devices has become an important technical problem that needs to be urgently solved by those skilled in the art.
[0006] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention
[0007] In view of the above-mentioned disadvantages of the prior art, the object of the present invention is to provide a semiconductor structure with multiple threshold voltages and a manufacturing method thereof, which is used to solve the problems of high cost and complex process required for preparing semiconductor devices with different threshold voltages in the same semiconductor structure in the prior art.
[0008] To achieve the above object and other related objects, the present invention provides a manufacturing method of a semiconductor structure with multiple threshold voltages, including the following steps:
[0009] Provide a semiconductor layer, and the semiconductor layer includes a first core device region, a second core device region, a first input / output device region, and a second input / output device region that are distributed according to a preset rule along the plane where the semiconductor layer is located;
[0010] Based on the first well region mask, perform first-conductivity-type ion implantation with a first depth and a first dose, second-conductivity-type ion implantation with a second depth and a second dose, and third-conductivity-type ion implantation with a third depth and a third dose in sequence to form a first-conductivity-type well region in the semiconductor layer. The first depth, the second depth, and the third depth become shallower in sequence. The first dose is higher than a first reference dose, and the first-conductivity-type well region is distributed in the first core device region, the second core device region, the first input / output device region, and the second input / output device region;
[0011] Based on the first threshold voltage adjustment mask, perform first-conductivity-type ion implantation at the third depth to form a first-conductivity-type adjustment region. The first-conductivity-type adjustment region includes a first sub-adjustment region on the upper surface layer of the first-conductivity-type well region in the first core device region and a second sub-adjustment region on the upper surface layer of the first-conductivity-type well region in the second core device region;
[0012] Based on the second well region mask, perform second-conductivity-type ion implantation to form a second-conductivity-type well region in the semiconductor layer. The second-conductivity-type well region and the first-conductivity-type well region are located in different regions of the plane where the semiconductor layer is located;
[0013] Based on the second threshold voltage adjustment mask, perform second-conductivity-type ion implantation with a fourth dose at the third depth to form a second-conductivity-type adjustment region in the semiconductor layer. The second-conductivity-type adjustment region includes a third sub-adjustment region on the upper surface layer of the second-conductivity-type well region, a fourth sub-adjustment region on the upper surface layer of the first-conductivity-type well region in the second core device region, and a fifth sub-adjustment region on the upper surface layer of the first-conductivity-type well region in the second input / output device region;
[0014] Form a first MOS transistor in the first core device region, form a second MOS transistor in the second core device region, form a third MOS transistor in the first input / output device region, and form a fourth MOS transistor in the second input / output device region. The channels of the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all of the second conduction type. The second MOS transistor has a first reference threshold voltage, the threshold voltage of the first MOS transistor is higher than the first reference threshold voltage, the fourth MOS transistor has a second reference threshold voltage, and the threshold voltage of the third MOS transistor is higher than the second reference threshold voltage.
[0015] Optionally, the fourth dose is equal to the difference between the first dose and the first reference dose, the second dose is higher than the second reference dose, and the third dose is higher than the third reference dose.
[0016] Optionally, the first conduction type is P-type, the second conduction type is N-type, and the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all NMOS transistors; or the first conduction type is N-type, the second conduction type is P-type, and the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all PMOS transistors.
[0017] Optionally, forming the first conduction type well region includes the following steps:
[0018] Form a first photoresist layer on the semiconductor layer;
[0019] Pattern the first photoresist layer based on the first well region mask to expose the first core device region, the second core device region, the first input / output device region, and the second input / output device region;
[0020] Using the patterned first photoresist layer as a mask, perform first conduction type ion implantation with a first dose at a first depth, first conduction type ion implantation with a second dose at a second depth, and first conduction type ion implantation with a third dose at a third depth on the semiconductor layer in sequence;
[0021] Perform annealing.
[0022] Optionally, forming the first conduction type adjustment region includes the following steps:
[0023] Form a second photoresist layer on the semiconductor layer;
[0024] Pattern the second photoresist layer based on the first threshold voltage mask to expose the first core device region and the second core device region, and the patterned second photoresist layer still covers the first input / output device region and the second input / output device region;
[0025] Use the patterned second photoresist layer as a mask to perform first-conductivity-type ion implantation on the semiconductor layer to the third depth;
[0026] Perform annealing.
[0027] Optionally, forming the second-conductivity-type well region includes the following steps:
[0028] Form a third photoresist layer on the semiconductor layer;
[0029] Pattern the third photoresist layer based on the second well region mask to expose the region where the second-conductivity-type well region is to be formed, and the patterned third photoresist layer still covers the first core device region, the second core device region, the first input / output device region, and the second input / output device region;
[0030] Use the patterned third photoresist layer as a mask to perform second-conductivity-type ion implantation on the semiconductor layer;
[0031] Perform annealing.
[0032] Optionally, forming the second-conductivity-type adjustment region includes the following steps:
[0033] Form a fourth photoresist layer on the semiconductor layer;
[0034] Pattern the fourth photoresist layer based on the second threshold voltage adjustment mask to expose the second core device region and the second input / output device region, and the patterned fourth photoresist layer still covers the first core device region and the first input / output device region;
[0035] Use the patterned fourth photoresist layer as a mask to perform second-conductivity-type ion implantation on the semiconductor layer to the third depth with a fourth dose;
[0036] Perform annealing.
[0037] Optionally, the first MOS transistor and the second MOS transistor have pocket doping regions and lightly doped source / drain regions, and the third MOS transistor and the fourth MOS transistor have lightly doped source / drain regions.
[0038] Optionally, the gate dielectric layer thickness of the third MOS transistor and the fourth MOS transistor is greater than the gate dielectric layer thickness of the first MOS transistor and the second MOS transistor.
[0039] The present invention also provides a semiconductor structure having multiple threshold voltages, comprising:
[0040] A semiconductor layer, including a first core device region, a second core device region, a first input / output device region, and a second input / output device region distributed according to a preset rule along the plane where the semiconductor layer is located;
[0041] A first-conductivity-type well region, located in the semiconductor layer, and the first-conductivity-type well region is distributed in the first core device region, the second core device region, the first input / output device region, and the second input / output device region;
[0042] A first-conductivity-type adjustment region, including a first sub-adjustment region on the upper surface layer of the first-conductivity-type well region in the first core device region and a second sub-adjustment region on the upper surface layer of the first-conductivity-type well region in the second core device region;
[0043] A second-conductivity-type well region, located in the semiconductor layer, and the second-conductivity-type well region and the first-conductivity-type well region are located in different regions of the plane where the semiconductor layer is located;
[0044] A second-conductivity-type adjustment region, located in the semiconductor layer, and the second-conductivity-type adjustment region includes a third sub-adjustment region on the upper surface layer of the second-conductivity-type well region, a fourth sub-adjustment region on the upper surface layer of the first-conductivity-type well region in the second core device region, and a fifth sub-adjustment region on the upper surface layer of the first-conductivity-type well region in the second input / output device region;
[0045] A first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, where the first MOS transistor is located in the first core device region, the second MOS transistor is located in the second core device region, the third MOS transistor is located in the first input / output device region, and the fourth MOS transistor is located in the second input / output device region;
[0046] Wherein, the channels of the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all of the second conductivity type, the second MOS transistor has a first reference threshold voltage, the threshold voltage of the first MOS transistor is higher than the first reference threshold voltage, the fourth MOS transistor has a second reference threshold voltage, and the threshold voltage of the third MOS transistor is higher than the second reference threshold voltage.
[0047] As described above, the method for fabricating a semiconductor structure with multiple threshold voltages of the present invention fabricates a second MOS transistor located in the core device region and having a first reference threshold voltage and a fourth MOS transistor located in the input / output device region and having a second reference threshold voltage. At the same time, without adding a photomask, a first MOS transistor located in the core device region and a third MOS transistor located in the input / output device region are additionally fabricated based on the same semiconductor layer. Among them, the threshold voltage of the first MOS transistor is higher than the first reference threshold voltage, and the threshold voltage of the third MOS transistor is higher than the second reference threshold voltage. In an alternative embodiment of the present invention, the second dose can be further made higher than the second reference dose, and the third dose can be made higher than the third reference dose. That is, by increasing the well ion implantation concentration deep in the device, the possibility of source-drain punch-through is reduced, the leakage problem is improved, and the means adopted is compatible or synchronized with the addition of a new threshold voltage, with low cost and simple process. In short, the present invention can use the least cost (only the combination of ion implantation steps in different process steps) to form a product with better anti-leakage performance and more types (one more type of device in both the core device region and the input / output device region) on the basis of being able to provide MOS transistors with reference threshold voltages, expanding the application range of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0048] Figure 1 It shows a schematic diagram of combining P-well ion implantation in a method for fabricating a semiconductor structure.
[0049] Figure 2 It shows a schematic diagram of performing P-type ion implantation in a method for fabricating a semiconductor structure to adjust the threshold voltage of the core device region.
[0050] Figure 3 It shows a schematic diagram of the structure obtained after removing the second photoresist layer in a method for fabricating a semiconductor structure.
[0051] Figure 4 It shows a process flow diagram of the method for fabricating a semiconductor structure with multiple threshold voltages of the present invention.
[0052] Figure 5 It shows a schematic diagram of the structure of the semiconductor layer provided by the method for fabricating a semiconductor structure with multiple threshold voltages of the present invention.
[0053] Figure 6 It shows a schematic diagram of the structure obtained after forming a well region of the first conductivity type in the method for fabricating a semiconductor structure with multiple threshold voltages of the present invention.
[0054] Figure 7Schematic diagram of the structure obtained after forming a first-conductivity-type adjustment region in the manufacturing method of a semiconductor structure with multiple threshold voltages according to the present invention.
[0055] Figure 8 Schematic diagram of the structure obtained after forming a second-conductivity-type well region in the manufacturing method of a semiconductor structure with multiple threshold voltages according to the present invention.
[0056] Figure 9 Schematic diagram of the structure obtained after forming a second-conductivity-type adjustment region in the manufacturing method of a semiconductor structure with multiple threshold voltages according to the present invention.
[0057] Figure 10 Schematic diagram of the structure obtained after forming the gate structures of the first, second, third, and fourth MOS transistors in the manufacturing method of a semiconductor structure with multiple threshold voltages according to the present invention.
[0058] Figure 11 Schematic diagram of the structure obtained after forming the lightly doped source / drain regions of the third and fourth MOS transistors in the manufacturing method of a semiconductor structure with multiple threshold voltages according to the present invention.
[0059] Figure 12 Schematic diagram of the structure obtained after forming the lightly doped source / drain regions and pocket doping regions of the first and second MOS transistors in the manufacturing method of a semiconductor structure with multiple threshold voltages according to the present invention.
[0060] Figure 13 Schematic diagram of the structure obtained after forming the heavily doped source / drain regions of the first, second, third, and fourth MOS transistors in the manufacturing method of a semiconductor structure with multiple threshold voltages according to the present invention.
[0061] Description of reference numerals
[0062] 101 Semiconductor layer
[0063] 102 Isolation structure
[0064] 103 Core device region
[0065] 104 Input / output device region
[0066] 105 First photoresist layer
[0067] 106 First ion implantation window
[0068] 107 Core region P well
[0069] 108 I / O region P well
[0070] 109 Second photoresist layer
[0071] 110 Second ion implantation window
[0072] Steps S1 to S6
[0073] 201 Semiconductor layer
[0074] A First core device region
[0075] B Second core device region
[0076] C First input / output device region
[0077] D Second input / output device region
[0078] 202 Isolation structure
[0079] 203 First conductivity type well region
[0080] 204 First photoresist layer
[0081] 205 First conductivity type adjustment region
[0082] 2051 First sub-adjustment region
[0083] 2052 Second sub-adjustment region
[0084] 206 Second photoresist layer
[0085] 207 Third photoresist layer
[0086] 208 Second conductivity type adjustment region
[0087] 2081 Fourth sub-adjustment region
[0088] 2082 Fifth sub-adjustment region
[0089] 209 Fourth photoresist layer
[0090] 210 First MOS transistor
[0091] 211 Second MOS transistor
[0092] 212 Third MOS transistor
[0093] 213 Fourth MOS transistor
[0094] 214 Gate dielectric layer
[0095] 215 Gate conductive layer
[0096] 216 Fifth photoresist layer
[0097] 217 Lightly doped source / drain region
[0098] 218 Zero-layer sidewall
[0099] 219 Sixth photoresist layer
[0100] 220 Lightly doped source / drain regions
[0101] 221 Pocket doping regions
[0102] 222 Sidewalls
[0103] 223 The seventh photoresist layer
[0104] 224 Heavily doped source / drain regions Detailed implementation manners
[0105] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0106] Please refer to Figures 1 to 13 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.
[0107] Please refer to Figures 1 to 3 , which shows a schematic diagram of the structures presented in each step of a method for fabricating a semiconductor structure.
[0108] Specifically, as Figure 1 shown, it shows a schematic diagram of performing combined P-well ion implantation. Among them, the object to be ion implanted is a semiconductor layer 101, and in this semiconductor layer 101, there are a core device region 103 and an input / output device region 104 separated by an isolation structure 102. Before performing ion implantation, a first photoresist layer 105 is first formed on the semiconductor layer 101, and the first photoresist layer 105 is patterned based on a first mask using a photolithography process to obtain a first ion implantation window 106. Then, using the patterned first photoresist layer 105 as a mask, P-type ion implantation is performed on the semiconductor layer 101 to obtain a core region P-well 107 in the core device region 103 and an I / O region P-well 108 in the input / output device region 104.
[0109] It should be pointed out that Figure 1Only partial regions of the core device region 103 and the input / output device region 104 are shown. In the actual manufacturing process, P-well ion implantation is not performed on all regions of the core device region 103 and the input / output device region 104. In one embodiment, both the core device and the input / output device include PMOS transistors and NMOS transistors. Therefore, both the core device region 103 and the input / output device region 104 are defined with P-well formation regions and N-well formation regions arranged according to a preset rule. Subsequently, NMOS transistors will be fabricated in the P-well formation regions, and PMOS transistors will be fabricated in the N-well formation regions. Figures 1 - 3 Taking the NMOS transistors in the core device region / input / output device region as an example for illustration.
[0110] As Figure 2 shown, it is a schematic diagram showing P-type ion implantation to adjust the threshold voltage of the core device region 103. Among them, before ion implantation, a second photoresist layer 109 is first formed on the semiconductor layer 101, and the second photoresist layer 109 is patterned based on a second photomask by a photolithography process to obtain a second ion implantation window 110. Then, using the patterned second photoresist layer 109 as a mask, P-type ion implantation is performed on the semiconductor layer 101 to increase the doping concentration on the surface layer of the core region P-well 107.
[0111] As Figure 3 shown, it is a schematic diagram of the structure obtained after removing the second photoresist layer 109. Subsequently, the fabrication of the gate structure, source / drain regions, etc. of the NMOS transistor can be continued. That is to say, by using the first photomask and the second photomask, NMOS transistors with different surface layer concentrations in different regions of the semiconductor layer 101 can be fabricated based on the semiconductor layer 101. Among them, the NMOS transistors in the core device region have a first reference threshold voltage, and the NMOS transistors in the input / output device region have a second reference threshold voltage.
[0112] In order to fabricate more devices with different threshold voltages based on the same semiconductor layer without increasing the photomask, so that the semiconductor structure can meet more application requirements, the inventors of the present application, through a large number of experimental studies and practices, proposed a method for fabricating a semiconductor structure with multiple threshold voltages. Please refer to Figure 4 , which shows a process flow chart of the method, including the following steps:
[0113] S1: Provide a semiconductor layer, and the semiconductor layer includes a first core device region, a second core device region, a first input / output device region, and a second input / output device region distributed according to a preset rule along the plane where the semiconductor layer is located;
[0114] S2: Based on the first well region mask, perform first-conductivity-type ion implantation with a first dose at a first depth, first-conductivity-type ion implantation with a second dose at a second depth, and first-conductivity-type ion implantation with a third dose at a third depth to form a first-conductivity-type well region in the semiconductor layer. The first depth, the second depth, and the third depth gradually become shallower. The first dose is higher than a first reference dose. The first-conductivity-type well region is distributed in the first core device region, the second core device region, the first input / output device region, and the second input / output device region;
[0115] S3: Based on the first threshold voltage adjustment mask, perform first-conductivity-type ion implantation at the third depth to form a first-conductivity-type adjustment region. The first-conductivity-type adjustment region includes a first sub-adjustment region on the upper surface layer of the first-conductivity-type well region in the first core device region and a second sub-adjustment region on the upper surface layer of the first-conductivity-type well region in the second core device region;
[0116] S4: Based on the second well region mask, perform second-conductivity-type ion implantation to form a second-conductivity-type well region in the semiconductor layer. The second-conductivity-type well region and the first-conductivity-type well region are located in different regions of the plane where the semiconductor layer is located;
[0117] S5: Based on the second threshold voltage adjustment mask, perform second-conductivity-type ion implantation with a fourth dose at the third depth to form a second-conductivity-type adjustment region in the semiconductor layer. The second-conductivity-type adjustment region includes a third sub-adjustment region on the upper surface layer of the second-conductivity-type well region, a fourth sub-adjustment region on the upper surface layer of the first-conductivity-type well region in the second core device region, and a fifth sub-adjustment region on the upper surface layer of the first-conductivity-type well region in the second input / output device region;
[0118] S6: Form a first MOS transistor in the first core device region, form a second MOS transistor in the second core device region, form a third MOS transistor in the first input / output device region, and form a fourth MOS transistor in the second input / output device region. The channels of the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all of the second conductivity type. The second MOS transistor has a first reference threshold voltage. The threshold voltage of the first MOS transistor is higher than the first reference threshold voltage. The fourth MOS transistor has a second reference threshold voltage. The threshold voltage of the third MOS transistor is higher than the second reference threshold voltage.
[0119] First, please refer to Figure 5, perform the step S1: Provide a semiconductor layer 201, which includes a first core device region A, a second core device region B, a first input / output device region C, and a second input / output device region D that are distributed according to a preset rule in the plane where the semiconductor layer 201 is located.
[0120] As an example, the semiconductor layer 201 can be a separate semiconductor substrate or an epitaxial layer grown on a semiconductor substrate.
[0121] As an example, an isolation structure 202 is pre-formed in the semiconductor layer 201. The isolation structure 202 can be a shallow trench isolation (STI) structure or other suitable isolation structures. Different device regions or different transistors in the same device region are isolated from each other through the isolation structure 202.
[0122] Please refer to Figure 6 , perform the step S2: Based on the first well region mask, perform first-conductivity-type ion implantation with a first dose at a first depth, first-conductivity-type ion implantation with a second dose at a second depth, and first-conductivity-type ion implantation with a third dose at a third depth in sequence to form a first-conductivity-type well region 203 in the semiconductor layer 201. The first depth, the second depth, and the third depth become shallower in sequence. The first dose is higher than a first reference dose. The first-conductivity-type well region 203 is distributed in the first core device region A, the second core device region B, the first input / output device region C, and the second input / output device region D.
[0123] In some embodiments of the present invention, the first conductivity type is P-type, the second conductivity type is N-type, and the subsequent first MOS transistor, second MOS transistor, third MOS transistor, and fourth MOS transistor are all NMOS transistors. In some other embodiments of the present invention, the first conductivity type can also be N-type, the second conductivity type correspondingly is P-type, and the subsequent first MOS transistor, second MOS transistor, third MOS transistor, and fourth MOS transistor are all PMOS transistors.
[0124] Specifically, the formation of the first-conductivity-type well region 203 includes three ion implantations. Among them, the first ion implantation with relatively high energy and relatively large dose is first performed to implant ions to a relatively deep depth, then the second ion implantation with medium energy and medium dose is performed to implant ions to a medium depth, and finally the third ion implantation with relatively low energy and relatively small dose is performed to implant ions into the upper surface layer of the semiconductor layer. In this way, long-time high-temperature driving-in is not required, and the place with the highest ion concentration is not on the surface, and the lateral diffusion is relatively small.
[0125] It should be noted that the object of the present invention is, without additional photomasks, to fabricate not only the original devices but also more devices with different threshold voltages. For example, based on the solution corresponding to Figures 1 - 3 not only fabricate NMOS transistors with a first reference threshold voltage in the core device region and NMOS transistors with a second reference threshold voltage in the input / output device region, but also fabricate NMOS transistors in the core device region with a threshold voltage higher than the first reference threshold voltage and NMOS transistors in the input / output device region with a threshold voltage higher than the second reference threshold voltage. When Figures 1 - 3 in the corresponding solution, the P-well is also subjected to three ion implantations from deep to shallow, the dose of the first ion implantation can be defined as the first reference dose, the dose of the second ion implantation can be defined as the second reference dose, and the dose of the third ion implantation can be defined as the third reference dose. In the present invention, the first dose is higher than the first reference dose to obtain MOS transistors with a higher threshold voltage. In a preferred embodiment of the present invention, the second dose is also higher than the second reference dose, and the third dose is also higher than the third reference dose, that is, the well ion implantation concentration in the deep part of the device is increased, which helps to reduce the possibility of source-drain punch-through and improve the leakage problem.
[0126] As an example, forming the first-conductivity-type well region 203 includes the following steps:
[0127] (1) Form a first photoresist layer 204 on the semiconductor layer 201;
[0128] (2) Provide a first well region photomask, and pattern the first photoresist layer 204 based on the first well region photomask by photolithography to expose the first core device region A, the second core device region B, the first input / output device region C, and the second input / output device region D;
[0129] (3) Using the patterned first photoresist layer 204 as a mask, perform first-conductivity-type ion implantation with a first depth and a first dose, second-conductivity-type ion implantation with a second depth and a second dose, and third-conductivity-type ion implantation with a third depth and a third dose on the semiconductor layer 201 in sequence;
[0130] (4) Perform annealing.
[0131] It should be noted that in the step of forming the first-conductivity-type well region based on the first well region photomask, the ion species, dose, implantation angle, and energy of each ion implantation can be adjusted according to the electrical requirements such as the threshold voltage of the actual device. For example, when the first conductivity type is P-type, P-type elements such as B (boron) can be implanted, and when the first conductivity type is N-type, N-type elements such as P (phosphorus) can be implanted. No specific limitation is made in the present invention.
[0132] Please refer to again Figure 7 and perform step S3: Based on the first threshold voltage adjustment mask, perform first-conductivity-type ion implantation at the third depth to form a first-conductivity-type adjustment region 205. The first-conductivity-type adjustment region 205 includes a first sub-adjustment region 2051 on the upper surface layer of the first-conductivity-type well region 203 in the first core device region A and a second sub-adjustment region 2052 on the upper surface layer of the first-conductivity-type well region 203 in the second core device region B.
[0133] As an example, forming the first-conductivity-type adjustment region 205 includes the following steps:
[0134] (1) Form a second photoresist layer 206 on the semiconductor layer 201;
[0135] (2) Provide a first threshold voltage adjustment mask, and pattern the second photoresist layer 206 based on the first threshold voltage adjustment mask using a photolithography process to expose the first core device region A and the second core device region B. The patterned second photoresist layer 206 still covers the first input / output device region C and the second input / output device region D;
[0136] (3) Use the patterned second photoresist layer 206 as a mask to perform first-conductivity-type ion implantation at the third depth on the semiconductor layer 201;
[0137] (4) Perform annealing.
[0138] Specifically, the function of the first-conductivity-type adjustment region 205 is to increase the doping concentration on the upper surface layer of the first-conductivity-type well region 203 in the first core device region A and the second core device region B, so that part of the first-conductivity-type well region 203 has different upper surface layer doping concentrations in the core device region and the input / output device region, and at the same time, different gate oxide thicknesses and lightly doped source / drain ion implantation conditions are combined to meet the respective threshold voltage requirements of the core device region and the input / output device region. In the present invention, no specific limitation is imposed on the dose used for performing first-conductivity-type ion implantation at the third depth based on the first threshold voltage adjustment mask to form the first-conductivity-type adjustment region 205, and it can be set according to actual needs.
[0139] Please refer to again Figure 8 and perform step S4: Based on the second well region mask, perform second-conductivity-type ion implantation to form a second-conductivity-type well region (not shown) in the semiconductor layer 201. The second-conductivity-type well region and the first-conductivity-type well region 203 are located in different regions of the plane where the semiconductor layer is located.
[0140] As an example, different types of well regions with different conduction types are used to form MOS transistors with channels of different conduction types. For example, a P-well is used to form an NMOS transistor, and an N-well is used to form a PMOS transistor.
[0141] As an example, forming the well region of the second conduction type includes the following steps:
[0142] (1) Form a third photoresist layer 207 on the semiconductor layer 201;
[0143] (2) Provide a second well region mask, and pattern the third photoresist layer 207 based on the second well region mask by a lithography process to expose the region where the well region of the second conduction type is to be formed. The patterned third photoresist layer 207 still covers the first core device region A, the second core device region B, the first input / output device region C, and the second input / output device region D;
[0144] (3) Use the patterned third photoresist layer 207 as a mask to perform ion implantation of the second conduction type on the semiconductor layer 201;
[0145] (4) Perform annealing.
[0146] Please refer to again Figure 9 , and execute the step S5: Perform ion implantation of the second conduction type with the third depth and the fourth dose based on the second threshold voltage adjustment mask to form a second conduction type adjustment region 208 in the semiconductor layer 201. The second conduction type adjustment region 208 includes a third sub-adjustment region (not shown) on the upper surface layer of the well region of the second conduction type (not shown), a fourth sub-adjustment region 2081 on the upper surface layer of the well region 203 of the first conduction type in the second core device region B, and a fifth sub-adjustment region 2082 on the upper surface layer of the well region 203 of the first conduction type in the second input / output device region D.
[0147] Specifically, the fourth dose is equal to the difference between the first dose and the first reference dose. That is, after the first-conductivity-type ion implantation with the third depth and the third dose is performed on the first core device region A, the second core device region B, the first input / output device region C, and the second input / output device region D in the step S2, the dose by which the first dose is increased relative to the first reference dose in some regions (the second core device region B and the second input / output device region D) will be neutralized in this step, so that the original devices or the original devices with better anti-leakage performance can be manufactured in the second core device region B and the second input / output device region D subsequently, that is, the MOS transistor with the first reference threshold voltage located in the second core device region B and the MOS transistor with the second reference threshold voltage located in the second input / output device region D. At the same time, since the second-conductivity-type ion implantation with the third depth and the fourth dose is only directed at the second core device region B and the second input / output device region D, the doped ions that increase relative to the reference ion implantation dose on the upper surface of the first-conductivity-type well region 203 in the first core device region A and the first input / output device region C will not be neutralized in the step S2.
[0148] As an example, forming the second-conductivity-type adjustment region 208 includes the following steps:
[0149] (1) Form a fourth photoresist layer 209 on the semiconductor layer 201;
[0150] (2) Provide a second threshold voltage adjustment mask, and pattern the fourth photoresist layer 209 based on the second threshold voltage adjustment mask by photolithography to expose the second core device region B and the second input / output device region D, and the patterned fourth photoresist layer 209 still covers the first core device region A and the first input / output device region C;
[0151] (3) Use the patterned fourth photoresist layer 209 as a mask to perform the second-conductivity-type ion implantation with the third depth and the fourth dose on the semiconductor layer 201;
[0152] (4) Perform annealing.
[0153] It should be noted that according to different process requirements, the annealing mentioned in the above steps S2 - S5 can be performed separately or some of them can be combined, which is not limited here. The purpose of annealing is to make the ions diffuse to the desired positions.
[0154] Please refer to again Figures 10 to 13, perform the step S6: form a first MOS transistor 210 in the first core device region A, form a second MOS transistor 211 in the second core device region B, form a third MOS transistor 212 in the first input / output device region C, and form a fourth MOS transistor 213 in the second input / output device region D. The channels of the first MOS transistor 210, the second MOS transistor 211, the third MOS transistor 212, and the fourth MOS transistor 213 are all of the second conduction type. The second MOS transistor 211 has a first reference threshold voltage, the threshold voltage of the first MOS transistor 210 is higher than the first reference threshold voltage, the fourth MOS transistor 213 has a second reference threshold voltage, and the threshold voltage of the third MOS transistor 212 is higher than the second reference threshold voltage.
[0155] In some embodiments, the first MOS transistor 210 located in the first core device region A and the second MOS transistor 211 located in the second core device region B have pocket (PKT) doping regions and lightly doped source / drain regions. The third MOS transistor 212 located in the first input / output device region C and the fourth MOS transistor 213 located in the second input / output device region D have lightly doped source / drain regions but do not have pocket doping regions. The gate dielectric layer thickness of the third MOS transistor 212 and the fourth MOS transistor 213 is greater than the gate dielectric layer thickness of the first MOS transistor 210 and the second MOS transistor 211.
[0156] It should be noted that the "lightly doped source / drain region" mentioned here and in other parts is the LDD (Lightly Doped Drain), which is a lightly doped source / drain region set near the heavily doped source / drain region in the MOS transistor channel. Letting this lightly doped source / drain region also bear part of the voltage helps prevent the hot electron degradation effect. The pocket doping region is formed by tilted angle ion implantation, which helps improve the short channel effect.
[0157] Specifically, as Figure 10 shown, first form the gate structures of the first MOS transistor 210, the second MOS transistor 211, the third MOS transistor 212, and the fourth MOS transistor 213. The gate structures of the first MOS transistor 210, the second MOS transistor 211, the third MOS transistor 212, and the fourth MOS transistor 213 all include a gate dielectric layer 214 and a gate conductive layer 215 located on the gate dielectric layer. The material of the gate dielectric layer 214 can be silicon oxide or other suitable materials, and the gate conductive layer 215 can be polysilicon or other suitable materials.
[0158] As Figure 11 shown, based on the patterned fifth photoresist layer 216, the semiconductor layer 201 is subjected to ion implantation of the second conductivity type to obtain the lightly doped source / drain regions 217 of the third MOS transistor 212 and the fourth MOS transistor 213.
[0159] As Figure 12 shown, after forming zero-layer spacers 218 on both sides of the gate structure, based on the patterned sixth photoresist layer 219, the semiconductor layer 201 is subjected to ion implantation of the second conductivity type to obtain the lightly doped source / drain regions 220 of the first MOS transistor 210 and the second MOS transistor 211, and the semiconductor layer 201 is subjected to inclined ion implantation of the first conductivity type to obtain the pocket doping regions 221 of the first MOS transistor 210 and the second MOS transistor 211.
[0160] As Figure 13 shown, after forming spacers 222 on both sides of the gate structure, based on the patterned seventh photoresist layer 223, the semiconductor layer 201 is subjected to ion implantation of the second conductivity type to obtain the heavily doped source / drain regions 224 of the first MOS transistor 210, the second MOS transistor 211, the third MOS transistor 212, and the fourth MOS transistor 213.
[0161] So far, a semiconductor structure has been fabricated. The semiconductor structure includes a semiconductor layer, a well region of a first conductivity type, an adjustment region of the first conductivity type, a well region of a second conductivity type, an adjustment region of the second conductivity type, a first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor. Among them, the semiconductor layer includes a first core device region, a second core device region, a first input / output device region, and a second input / output device region that are distributed according to a preset rule in the plane where the semiconductor layer is located. The well region of the first conductivity type is located in the semiconductor layer and is distributed in the first core device region, the second core device region, the first input / output device region, and the second input / output device region. The adjustment region of the first conductivity type includes a first sub-adjustment region on the upper surface layer of the well region of the first conductivity type in the first core device region and a second sub-adjustment region on the upper surface layer of the well region of the first conductivity type in the second core device region. The well region of the second conductivity type is located in the semiconductor layer and is in a different region from the well region of the first conductivity type in the plane where the semiconductor layer is located. The adjustment region of the second conductivity type is located in the semiconductor layer and includes a third sub-adjustment region on the upper surface layer of the well region of the second conductivity type, a fourth sub-adjustment region on the upper surface layer of the well region of the first conductivity type in the second core device region, and a fifth sub-adjustment region on the upper surface layer of the well region of the first conductivity type in the second input / output device region. The first MOS transistor is located in the first core device region, the second MOS transistor is located in the second core device region, the third MOS transistor is located in the first input / output device region, and the fourth MOS transistor is located in the second input / output device region. Among them, the channels of the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all of the second conductivity type. The second MOS transistor has a first reference threshold voltage, the threshold voltage of the first MOS transistor is higher than the first reference threshold voltage, the fourth MOS transistor has a second reference threshold voltage, and the threshold voltage of the third MOS transistor is higher than the second reference threshold voltage.
[0162] In summary, the manufacturing method of the semiconductor structure with multiple threshold voltages according to the present invention fabricates the second MOS transistor located in the core device region and having a first reference threshold voltage and the fourth MOS transistor located in the input / output device region and having a second reference threshold voltage. At the same time, without adding a mask, the first MOS transistor located in the core device region and the third MOS transistor located in the input / output device region are additionally fabricated based on the same semiconductor layer. Among them, the threshold voltage of the first MOS transistor is higher than the first reference threshold voltage, and the threshold voltage of the third MOS transistor is higher than the second reference threshold voltage. In an alternative embodiment of the present invention, the second dose can be further made higher than the second reference dose, and the third dose can be made higher than the third reference dose. That is, by increasing the well ion implantation concentration deep in the device, the possibility of source-drain punch-through is reduced, the leakage problem is improved, and the means adopted is compatible or synchronized with adding a new threshold voltage, with low cost and simple process. In short, the present invention can use the least cost (only the combination of ion implantation steps in different process steps) to form a product with better anti-leakage performance and more types (one more type of device in both the core device region and the input / output device region) on the basis of being able to provide MOS transistors with reference threshold voltages, expanding the application scope of the semiconductor structure. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.
[0163] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A method for fabricating a semiconductor structure having multiple threshold voltages, characterized in that, The method includes the following steps: Providing a semiconductor layer, which includes a first core device region, a second core device region, a first input / output device region, and a second input / output device region that are distributed according to a preset rule in the plane where the semiconductor layer is located; Based on a first well mask, performing first-conductivity-type ion implantation with a first depth and a first dose, first-conductivity-type ion implantation with a second depth and a second dose, and first-conductivity-type ion implantation with a third depth and a third dose in sequence to form a first-conductivity-type well region in the semiconductor layer. The first depth, the second depth, and the third depth become shallower in sequence. The first dose is higher than a first reference dose. The first-conductivity-type well region is distributed in the first core device region, the second core device region, the first input / output device region, and the second input / output device region; Based on a first threshold voltage adjustment mask, performing first-conductivity-type ion implantation with the third depth to form a first-conductivity-type adjustment region. The first-conductivity-type adjustment region includes a first sub-adjustment region on the upper surface layer of the first-conductivity-type well region in the first core device region and a second sub-adjustment region on the upper surface layer of the first-conductivity-type well region in the second core device region; Based on a second well mask, performing second-conductivity-type ion implantation to form a second-conductivity-type well region in the semiconductor layer. The second-conductivity-type well region and the first-conductivity-type well region are located in different regions in the plane where the semiconductor layer is located; Based on a second threshold voltage adjustment mask, performing second-conductivity-type ion implantation with the fourth dose and the third depth to form a second-conductivity-type adjustment region in the semiconductor layer. The second-conductivity-type adjustment region includes a third sub-adjustment region on the upper surface layer of the second-conductivity-type well region, a fourth sub-adjustment region on the upper surface layer of the first-conductivity-type well region in the second core device region, and a fifth sub-adjustment region on the upper surface layer of the first-conductivity-type well region in the second input / output device region; Forming a first MOS transistor in the first core device region, forming a second MOS transistor in the second core device region, forming a third MOS transistor in the first input / output device region, and forming a fourth MOS transistor in the second input / output device region. The channels of the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all of the second conductivity type. The second MOS transistor has a first reference threshold voltage. The threshold voltage of the first MOS transistor is higher than the first reference threshold voltage. The fourth MOS transistor has a second reference threshold voltage. The threshold voltage of the third MOS transistor is higher than the second reference threshold voltage.
2. The manufacturing method of the semiconductor structure with multiple threshold voltages according to claim 1, wherein: The fourth dose is equal to the difference between the first dose and the first reference dose. The second dose is higher than a second reference dose. The third dose is higher than a third reference dose.
3. The manufacturing method of the semiconductor structure with multiple threshold voltages according to claim 1, characterized in that: The first conduction type is P-type, the second conduction type is N-type, and the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all NMOS transistors; or the first conduction type is N-type, the second conduction type is P-type, and the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all PMOS transistors.
4. The manufacturing method of the semiconductor structure with multiple threshold voltages according to claim 1, characterized in that, Forming the first conduction type well region includes the following steps: Forming a first photoresist layer on the semiconductor layer; Patterning the first photoresist layer based on the first well region mask to expose the first core device region, the second core device region, the first input / output device region, and the second input / output device region; Using the patterned first photoresist layer as a mask to perform first conduction type ion implantation with a first depth and a first dose, first conduction type ion implantation with a second depth and a second dose, and first conduction type ion implantation with a third depth and a third dose on the semiconductor layer in sequence; Performing annealing.
5. The manufacturing method of a semiconductor structure having multiple threshold voltages according to claim 1, characterized in that Forming the first conduction type adjustment region includes the following steps: Forming a second photoresist layer on the semiconductor layer; Patterning the second photoresist layer based on the first threshold voltage adjustment mask to expose the first core device region and the second core device region, and the patterned second photoresist layer still covers the first input / output device region and the second input / output device region; Using the patterned second photoresist layer as a mask to perform the first conduction type ion implantation with the third depth on the semiconductor layer; Performing annealing.
6. The manufacturing method of the semiconductor structure with multiple threshold voltages according to claim 1, characterized in that, Forming the second conduction type well region includes the following steps: Forming a third photoresist layer on the semiconductor layer; Patterning the third photoresist layer based on the second well region mask to expose the region where the second conduction type well region is to be formed, and the patterned third photoresist layer still covers the first core device region, the second core device region, the first input / output device region, and the second input / output device region; Using the patterned third photoresist layer as a mask to perform second conduction type ion implantation on the semiconductor layer; Performing annealing.
7. The manufacturing method of the semiconductor structure with multiple threshold voltages according to claim 1, characterized in that, Forming the second conduction type adjustment region includes the following steps: Forming a fourth photoresist layer on the semiconductor layer; Patterning the fourth photoresist layer based on the second threshold voltage adjustment mask to expose the second core device region and the second input / output device region, and the patterned fourth photoresist layer still covers the first core device region and the first input / output device region; Using the patterned fourth photoresist layer as a mask to perform the second conduction type ion implantation with the third depth and a fourth dose on the semiconductor layer; Performing annealing.
8. The manufacturing method of the semiconductor structure having multiple threshold voltages according to claim 1, wherein: The first MOS transistor and the second MOS transistor have pocket doping regions and lightly doped source / drain regions, and the third MOS transistor and the fourth MOS transistor have lightly doped source / drain regions.
9. The manufacturing method of the semiconductor structure with multiple threshold voltages according to claim 1, characterized in that: The gate dielectric layer thickness of the third MOS transistor and the fourth MOS transistor is greater than that of the first MOS transistor and the second MOS transistor.
10. A semiconductor structure with multiple threshold voltages, characterized in that, Comprising: A semiconductor layer including a first core device region, a second core device region, a first input / output device region, and a second input / output device region distributed in a preset rule along the plane where the semiconductor layer is located; A first conductivity type well region located in the semiconductor layer, and the first conductivity type well region is distributed in the first core device region, the second core device region, the first input / output device region, and the second input / output device region; A first conductivity type adjustment region including a first sub-adjustment region on the upper surface layer of the first conductivity type well region in the first core device region and a second sub-adjustment region on the upper surface layer of the first conductivity type well region in the second core device region; A second conductivity type well region located in the semiconductor layer, and the second conductivity type well region and the first conductivity type well region are located in different regions of the plane where the semiconductor layer is located; A second conductivity type adjustment region located in the semiconductor layer, and the second conductivity type adjustment region includes a third sub-adjustment region on the upper surface layer of the second conductivity type well region, a fourth sub-adjustment region on the upper surface layer of the first conductivity type well region in the second core device region, and a fifth sub-adjustment region on the upper surface layer of the first conductivity type well region in the second input / output device region; A first MOS transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, where the first MOS transistor is located in the first core device region, the second MOS transistor is located in the second core device region, the third MOS transistor is located in the first input / output device region, and the fourth MOS transistor is located in the second input / output device region; Wherein, the channels of the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are all of the second conductivity type, the second MOS transistor has a first reference threshold voltage, the threshold voltage of the first MOS transistor is higher than the first reference threshold voltage, the fourth MOS transistor has a second reference threshold voltage, and the threshold voltage of the third MOS transistor is higher than the second reference threshold voltage.