Semiconductor device, electronic equipment and preparation method of semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device, electronic equipment and a preparation method of the semiconductor device. Relates to the technical field of semiconductors. A semiconductor device capable of overvoltage protection of a transistor gate is provided. The semiconductor device comprises a substrate, and a transistor and a protection device which are arranged on the substrate, the protection device comprises a channel layer, a barrier layer, a first electrode and a second electrode, the channel layer is formed on the substrate, the barrier layer is formed on the channel layer, the first electrode and the second electrode are both arranged on the barrier layer, the first electrode and the second electrode are electrically isolated, the barrier layer corresponds to the first electrode in position, and the barrier layer is formed on the channel layer. The barrier layer is electrically isolated from the barrier layer corresponding to the position of the second electrode; the gate of the transistor is electrically connected to the first electrode, and the source or drain of the transistor is electrically connected to the second electrode. A Schottky diode is formed through the barrier heights of the electrode, the channel layer and the barrier layer, and a channel of leakage current is formed through a diode formed by the channel layer and the barrier layer, so that the transistor is protected.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly to a semiconductor device, an electronic device including the semiconductor device, and a method for manufacturing the semiconductor device. Background Art

[0002] With the development of communication technology, the radio frequency communication field has put forward higher requirements for semiconductor devices in terms of higher frequency, higher voltage, higher output power and efficiency.

[0003] Semiconductor devices made of compound semiconductor materials, such as gallium nitride (GaN)-based high electron mobility transistors (HEMTs), are increasingly widely used in high-power radio frequency devices, high-voltage withstand switching devices and other fields due to their excellent physical properties such as wide bandgap, high electron drift rate, radiation resistance, and high temperature resistance. For example, they are widely used in systems such as radar, wireless communication, navigation, satellite communication, and electronic countermeasure equipment.

[0004] The reliability of GaN HEMT semiconductor devices is relatively low. The gate of GaN HEMT semiconductor devices is extremely vulnerable to overvoltage damage. For example, electrostatic discharge (ESD) has the characteristics of high potential (up to tens of thousands of volts or even hundreds of thousands of volts) and short action time, which is extremely destructive to semiconductor devices. Therefore, it is necessary to provide a structure for protecting GaN HEMT semiconductor devices. Summary of the Invention

[0005] The present application provides a semiconductor device, an electronic device including the semiconductor device, and a method for manufacturing the semiconductor device. The purpose is to provide a semiconductor device that can protect the transistor gate from overvoltage.

[0006] To achieve the above object, the embodiments of the present application adopt the following technical solutions:

[0007] On the one hand, the present application provides a semiconductor device. The semiconductor device includes a transistor, and the transistor can be a high electron mobility transistor HEMT.

[0008] The semiconductor device includes a substrate, a transistor and a protection device disposed on the substrate, and the protection device is used for overvoltage protection of the transistor gate; the protection device includes: a first channel layer, a first barrier layer, a first electrode and a second electrode. The first channel layer is formed on the substrate, the first barrier layer is formed on the first channel layer, the first electrode and the second electrode are both disposed on the first barrier layer, and the first electrode and the second electrode are electrically isolated from each other. The first barrier layer corresponding to the position of the first electrode and the first barrier layer corresponding to the position of the second electrode are electrically isolated from each other; and, the gate of the transistor is electrically connected to the first electrode, and the source or drain of the transistor is electrically connected to the second electrode.

[0009] In the protection device for overvoltage protection of the transistor gate given in this application, the first electrode and the first barrier layer can form a Schottky diode SBD1, and the barrier between the first barrier layer corresponding to the position of the first electrode and the first channel layer can be regarded as a diode D1. The second electrode and the first barrier layer can form a Schottky diode SBD2, and the barrier between the first barrier layer corresponding to the position of the second electrode and the first channel layer can be regarded as a diode D2.

[0010] For example, when the first electrode is connected to a high potential and the second electrode is connected to a low potential, both the Schottky diode SBD1 and the diode D1 are forward-conducted and in an on state, and the Schottky diode SBD2 and the diode D2 are in a reverse cut-off state; when the voltage exceeds a certain threshold, due to the increased kinetic energy of the electrons in the channel, the kinetic energy of some electrons is large enough to overcome the barriers of the diode D2 and the Schottky diode SBD2, so that the electrons escape to the second electrode, forming a current path to protect the transistor.

[0011] In a possible implementation manner, a second channel layer is further formed on the substrate, and the second channel layer is electrically isolated from the first channel layer; a second barrier layer is formed on the second channel layer, and the second barrier layer is electrically isolated from the first barrier layer; the source and drain of the transistor are both in ohmic contact with the second channel layer.

[0012] In some examples, the transistor can be a high electron mobility transistor HEMT. In this example, the high electron mobility transistor HEMT and the protection device are integrated on the same substrate, and the device formed in this way can be called device-level on-chip protection, which can effectively reduce the damage of components caused by electrostatic discharge during the device packaging process.

[0013] In a possible implementation manner, the first channel layer and the second channel layer are located in the same channel layer, and the first barrier layer and the second barrier layer are located in the same barrier layer.

[0014] In a possible implementation, the gate of the transistor is located on the side of the second barrier layer away from the second channel layer; the gate, the first electrode, and the second electrode of the transistor are located in the same metal layer.

[0015] Since the channel layer of the protection device and the channel layer of the transistor are in the same layer, and the barrier layer of the protection device and the barrier layer of the transistor are in the same layer, then when fabricating this semiconductor device, the transistor and the protection device can be fabricated simultaneously using a front-end process, and the fabrication process of the protection device is fully compatible with the GaN HEMT device.

[0016] In a possible implementation, there are multiple first electrodes and multiple second electrodes; the multiple first electrodes and the multiple second electrodes are arranged alternately in the first direction.

[0017] By using multiple first electrodes and multiple second electrodes arranged alternately, the length dimensions of the first electrode and the second electrode can be increased, thereby improving the current-carrying capacity of this protection device and enhancing the protection performance for the transistor.

[0018] In a possible implementation, the spacing S between the first electrode and the second electrode satisfies 0.5μm ≤ S ≤ 20μm.

[0019] The size of the spacing S between the first electrode and the second electrode can determine the turn-on voltage V of the protection device. ON 。

[0020] In a possible implementation, the width d of the first electrode and / or the second electrode satisfies 2μm ≤ d ≤ 20μm.

[0021] In a possible implementation, the length dimension of the first electrode is not equal to the length dimension of the second electrode.

[0022] For example, the length dimension of the first electrode is greater than the length dimension of the second electrode.

[0023] In this way, different turn-on voltages in the forward and reverse directions of the protection device can be achieved to adapt to protection devices with different turn-on voltage levels.

[0024] In a possible implementation, there is a dielectric layer between the first electrode and the second electrode; there is a dielectric layer between the first barrier layer corresponding to the position of the first electrode and the first barrier layer corresponding to the position of the second electrode.

[0025] In some process methods, a groove can be etched between the first electrode and the second electrode, and the groove is made to penetrate through to the channel layer, and then a dielectric material is filled to electrically isolate the two electrodes, and the barrier layers below the two electrodes are switched so that the barrier layer forms two electrically isolated parts.

[0026] In a possible implementation, the material of the first barrier layer includes Al x Ga 1-x N, where 0.2 ≤ x ≤ 0.4.

[0027] In a possible implementation, the thickness h of the first barrier layer satisfies 10 nm ≤ h ≤ 30 nm.

[0028] In the examples of this application, by defining the composition and thickness dimensions of the barrier layer, the turn-on voltage of the protection device can be controlled.

[0029] In a possible implementation, the turn-on voltage V of the protection device ON , satisfies 5 V ≤ V ON ≤ 100 V.

[0030] Since the turn-on voltage of the protection device given in this application is 5 V ≤ V ON ≤ 100 V, then when the normal operating voltage range of the gate of the transistor to be protected is relatively high, the gate overvoltage of the transistor can still be protected.

[0031] In a possible implementation, the off-state leakage current I of the protection device satisfies I ≤ 10 -2 mA / mm.

[0032] The protection device provided in this application has a low off-state leakage current, low static power consumption, and a low parasitic capacitance, and is suitable for high-frequency circuit applications.

[0033] In a possible implementation, on the side of the transistor and the protection device facing away from the substrate, there is an interconnect wiring layer; the gate of the transistor is electrically connected to the first electrode through the interconnect wiring layer; the source or drain of the transistor is electrically connected to the second electrode through the interconnect wiring layer.

[0034] That is, the transistor and the protection device can be fabricated using a front-end process, and the metal wiring of the interconnect wiring layer fabricated using a back-end process is used to electrically connect the transistor and the protection device.

[0035] On the other hand, this application provides a method for manufacturing a semiconductor device, which includes:

[0036] Fabricating a transistor and a protection device on a substrate;

[0037] Electrically connecting the gate of the transistor to the first electrode of the protection device, and the source or drain of the transistor to the second electrode of the protection device;

[0038] Fabricating the protection device on the substrate includes:

[0039] Fabricating a first channel layer on the substrate;

[0040] A first barrier layer is formed on the first channel layer;

[0041] A first electrode and a second electrode are formed on the first barrier layer. The first electrode and the second electrode are electrically isolated from each other. The first barrier layer corresponding to the position of the first electrode and the first barrier layer corresponding to the position of the second electrode are electrically isolated from each other.

[0042] In the protection device prepared by using the preparation method provided in this application, the first electrode and the first barrier layer can form a Schottky diode SBD1. The barrier between the first barrier layer corresponding to the position of the first electrode and the first channel layer can be regarded as a diode D1. The second electrode and the first barrier layer can form a Schottky diode SBD2. The barrier between the first barrier layer corresponding to the position of the second electrode and the first channel layer can be regarded as a diode D2. For example, when the first electrode is connected to a high potential and the second electrode is connected to a low potential, both the Schottky diode SBD1 and the diode D1 are forward-conducting and in an on state, while the Schottky diode SBD2 and the diode D2 are in a reverse cutoff state. When the voltage exceeds a certain threshold, due to the increased kinetic energy of the electrons in the channel, the kinetic energy of some electrons is large enough to overcome the barriers of the diode D2 and the Schottky diode SBD2, so that the electrons escape to the second electrode, forming a current path to protect the transistor gate from overvoltage.

[0043] In a possible implementation manner, forming a transistor and a protection device on a substrate includes:

[0044] A channel layer is formed on the substrate;

[0045] A barrier layer is formed on the channel layer;

[0046] The active region for forming the transistor and the region for forming the protection device are electrically isolated, so as to form a stacked first channel layer and a first barrier layer in the region of the protection device, and a stacked second channel layer and a second barrier layer in the active region. The first channel layer and the second channel layer are electrically isolated from each other, and the first barrier layer and the second barrier layer are electrically isolated from each other.

[0047] That is, the transistor and the protection device can be formed simultaneously using the previous process. The process for preparing the protection device can be compatible with the process for preparing the transistor, without posing challenges to the preparation process of the protection device.

[0048] In a possible implementation manner, after forming the barrier layer on the channel layer, the preparation method further includes:

[0049] Etch a groove in the region for forming the protection device, and the groove penetrates the barrier layer;

[0050] Form a first electrode and a second electrode on the barrier layer isolated by the groove.

[0051] After the first channel layer and the second barrier layer are fabricated, the groove can be etched to switch the two-dimensional electron gas channel of the protection device.

[0052] In a possible implementation manner, when the first electrode and the second electrode are fabricated on the first barrier layer, it further includes:

[0053] Fabricating the gate of the transistor.

[0054] The gate of the transistor, the first electrode and the second electrode of the protection device can be fabricated by using the same process. The preparation process has strong compatibility.

[0055] In a possible implementation manner, when the first electrode and the second electrode are fabricated on the first barrier layer, it includes:

[0056] A plurality of first electrodes and a plurality of second electrodes are fabricated along a first direction parallel to the surface of the substrate, and the plurality of first electrodes and the plurality of second electrodes are alternately arranged in the first direction.

[0057] In this way, first electrodes and second electrodes with larger length dimensions can be arranged per unit area to improve the current-carrying capacity of the protection device.

[0058] In a possible implementation manner, after the transistor and the protection device are fabricated on the substrate, the preparation method further includes:

[0059] An interconnection trace layer is fabricated on the side of the transistor and the protection device facing away from the substrate. The gate of the transistor is electrically connected to the first electrode through the interconnection trace layer, and the source or drain of the transistor is electrically connected to the second electrode through the interconnection trace layer.

[0060] On the other hand, the present application also provides an electronic device. The electronic device includes the semiconductor device in any of the above implementation manners, and the electronic device further includes a substrate, and the transistor is arranged on the substrate.

[0061] In the electronic device provided by the present application, since it includes the semiconductor device in any of the above implementation manners, the protection device and the protected transistor in the semiconductor device are integrated on the same substrate, that is, the on-chip integration of the protection device. Moreover, the present application uses a diode formed by a series of Schottky diodes, channel layers and barrier layers to form a current leakage path to protect the transistor gate from overvoltage. Description of the Drawings

[0062] Figure 1 It is a partial structural schematic diagram of a base station provided by an embodiment of the present application;

[0063] Figure 2 It is an exploded schematic diagram of a partial structure of a mobile phone provided by an embodiment of the present application;

[0064] Figure 3 Schematic diagram of a packaging structure of a semiconductor device provided by an embodiment of the present application;

[0065] Figure 4 Partial circuit diagram in an electronic device provided by an embodiment of the present application;

[0066] Figure 5 Partial circuit diagram in an electronic device provided by an embodiment of the present application;

[0067] Figure 6 Schematic diagram of a structure of a semiconductor device provided by an embodiment of the present application;

[0068] Figure 7 Semiconductor energy level diagram of each film layer structure in a protection device provided by an embodiment of the present application;

[0069] Figure 8 Equivalent circuit diagram of a protection device provided by an example of the present application;

[0070] Figure 9 Circuit connection relationship diagram of a transistor and a protection device provided by an example of the present application;

[0071] Figure 10 Schematic diagram of a structure of a semiconductor device provided by an embodiment of the present application;

[0072] Figure 11 Schematic diagram of a structure of a first electrode and a second electrode provided by an embodiment of the present application;

[0073] Figure 12 Schematic diagram of a structure of a first electrode and a second electrode provided by an embodiment of the present application;

[0074] Figure 13 Schematic diagram of a structure of a first electrode and a second electrode provided by an embodiment of the present application;

[0075] Figure 14 Schematic diagram of a structure of a first electrode and a second electrode provided by an embodiment of the present application;

[0076] Figure 15 Schematic diagram of a structure of a first electrode and a second electrode provided by an embodiment of the present application;

[0077] Figure 16 I-V characteristic curve diagram of a protection device provided by an embodiment of the present application;

[0078] Figure 17 Schematic diagram of the connection relationship between the electrodes of a transistor and the electrodes of a protection device provided by an embodiment of the present application;

[0079] Figure 18Flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present application;

[0080] Figures 19A to 19F During the manufacturing process of a semiconductor device provided by an embodiment of the present application, schematic diagrams of the corresponding structures after each step are completed;

[0081] Figures 20A to 20F During the manufacturing process of a semiconductor device provided by an embodiment of the present application, schematic diagrams of the corresponding structures after each step are completed;

[0082] Figure 21 Schematic diagram of a semiconductor device provided by an embodiment of the present application. Detailed implementation manners

[0083] Before introducing the embodiments related to the present application, some technical terms related to the embodiments of the present application are introduced as follows:

[0084] Heterojunction: It is a junction formed by the contact of two different semiconductor materials. The lattice constants of these two materials are different, so lattice mismatch will occur.

[0085] Semiconductor heterojunction energy band diagram: It shows the energy changes of the lowest conduction band value and the highest valence band value on both sides of the heterojunction interface.

[0086] The solutions related to the embodiments of the present application are introduced below with reference to the accompanying drawings.

[0087] An embodiment of the present application provides an electronic device, which may include a communication device (such as a base station, a mobile phone, a tablet, a wearable device, a smart screen, a wireless earphone), a wireless charging device, a medical device, a radar, a navigation device, a radio frequency (RF) plasma lighting device, an RF induction and microwave heating device, etc. The specific form of the above electronic device is not particularly limited in the embodiments of the present application.

[0088] In the above electronic devices, basically all include radio frequency semiconductor devices. For example, they include a power amplifier (PA). The main function of the PA is to amplify radio frequency signals. Taking a base station as an example, Figure 1 A simple schematic diagram of a base station is given. The base station includes a control unit. The control unit in the base station includes a radio transceiver, signal processing circuits related to antennas, etc. Among them, the control unit mainly includes four components: a cell controller, a voice channel controller, a signaling channel controller, and a multiplex terminal interface for expansion. The control unit of the base station usually controls several base transceiver stations. Through the remote commands of the transceiver station and the mobile station, the control unit of the base station is responsible for all mobile communication interface management, mainly the allocation, release, and management of wireless channels, etc.

[0089] Continue to combine Figure 1 The base station further includes a transmission unit, which is connected to the core network. Control signaling, voice calls, or data service information on the core network side is sent to the control unit of the base station through the transmission unit, and these services are processed by the control unit.

[0090] Combined with Figure 1 The base station further includes a baseband unit and a radio frequency (RF) unit. The baseband unit mainly completes functions such as baseband modulation and demodulation, radio resource allocation, call processing, power control, and soft handover. The RF unit mainly completes the conversion between the air radio frequency channel and the baseband digital channel, and then amplifies the signal through a power amplifier (PA), and then sends it to the antenna through a radio frequency feeder for transmission. Terminal devices, such as mobile phones, tablets, etc., receive the radio waves emitted by the antenna through the wireless channel, and then demodulate their own signals.

[0091] Continue to combine Figure 1 The base station further includes a power supply unit, which can be used to supply power to structures such as the transmission unit, baseband unit, and control unit.

[0092] Figure 2 The structure diagram of another electronic device is given. Taking a mobile phone as an example, the mobile phone may include a middle frame 11, a rear shell 12, and a display screen 13. The middle frame 11 includes a carrier board 111 for carrying the display screen 13, and a frame 110 around the carrier board 111. As Figure 3 shown, the radio frequency power amplifier PA is in the transmission link in the radio frequency front-end system of the intelligent terminal, and can be set on the carrier board 111. The main function of the radio frequency power amplifier PA is to amplify the modulated radio frequency signal and then transmit it externally through a filter, a switch, and an antenna.

[0093] With the development of mobile communication technology, the functional requirements for the above-mentioned radio frequency semiconductor devices are also getting higher and higher. For example, they have higher frequencies, higher voltages, higher output powers, and higher efficiencies, etc.

[0094] Among the selectable semiconductor materials, gallium nitride (GaN) has become a key material for fabricating radio frequency semiconductor devices due to its high thermal conductivity, high breakdown field strength, high saturated electron drift velocity, etc. For example, a high electron mobility transistor (HEMT) based on gallium nitride (GaN) is fabricated from a GaN epitaxial single crystal film grown on a single crystal substrate. The single crystal substrate generally uses materials such as sapphire, silicon carbide (SiC), or silicon (Si) single crystal. For instance, when the substrate uses a silicon single crystal material, the fabricated HEMT can be called a gallium nitride on silicon (GaN-on-Si) HEMT device. In some other examples, the substrate can be a composite substrate formed based on the above different materials.

[0095] As Figure 3 shown, the semiconductor device 300 including the HEMT in the above device is disposed on the substrate 400, and the semiconductor device 300 is disposed on the substrate 400 through a first electrical connection structure (such as a metal layer) 500, so that the semiconductor device 300 can perform signal interconnection with other electronic devices on the substrate 400.

[0096] The substrate 400 is further disposed on the circuit board 100 through a second electrical connection structure 200. For example, the circuit board 100 can be a printed circuit board (PCB), and the second electrical connection structure 200 here can be a ball grid array (BGA) or other electrical connection structures.

[0097] Gallium nitride high electron mobility transistor (GaN HEMT) devices have great application prospects in high-power and high-speed radio frequency fields due to the characteristics of wide bandgap and high carrier concentration. However, the electrostatic discharge (ESD) protection ability is weak. Therefore, it is necessary to add protection devices to protect the HEMT device.

[0098] As Figure 4 and Figure 5 shown, the protection device can be disposed at the input, output, or power supply pins of the device. For example, protection devices need to be configured at the pin ports of radio frequency signal input, radio frequency signal output, bias circuit input power supply, and Vdd power supply input to prevent damage to the protected device caused by external ESD pulse current.

[0099] When the protected device is operating normally, the protection device is in the off state. When the protected device encounters an ESD impact, the protection device turns on to release the ESD current, so that the protected device is protected from the ESD impact.

[0100] An embodiment of the present application provides a semiconductor device, which not only integrates a transistor, but also integrates a protection device for protecting the gate overvoltage of the transistor.

[0101] As Figure 6 , Figure 6 is a structural diagram of a semiconductor device according to an example of the present application. The semiconductor device includes a substrate 10, a transistor 20 disposed on the substrate 10, and a protection device 30.

[0102] Among them, the protection device 30 includes: a first channel layer 301 disposed on the substrate 10, a first barrier layer 302 disposed on the first channel layer 301, a first electrode 303 and a second electrode 304 disposed on the first barrier layer 302.

[0103] The first electrode 303 and the second electrode 304 are electrically isolated.

[0104] The first barrier layer 302 corresponding to the position of the first electrode 303 and the first barrier layer 302 corresponding to the position of the second electrode 304 are electrically isolated.

[0105] The gate G of the transistor is electrically connected to the first electrode 303, and the source S or drain G of the transistor is electrically connected to the second electrode 304; that is, it can be understood that: in one embodiment, as Figure 6 , the gate G of the transistor is electrically connected to the first electrode 303, and the source S of the transistor is electrically connected to the second electrode 304; in another embodiment, the gate G of the transistor is electrically connected to the first electrode 303, and the drain G of the transistor is electrically connected to the second electrode 304.

[0106] The protection device according to the example of the present application exhibits a high-resistance state under a low bias voltage and presents a low-resistance state when the bias voltage exceeds a certain threshold. When the protected transistor is operating normally, the protection device is in a high-resistance state, and the current flowing through the protection device is very small; when the external input voltage exceeds the turn-on voltage of the protection device, the protection device plays a voltage clamping role and can release a large current in a state where the voltage is almost unchanged, that is, it exhibits a low-resistance state, thereby protecting the transistor from being damaged by high-voltage static electricity.

[0107] Figure 7 is a semiconductor energy level diagram of each film layer structure in the protection device according to the example of the present application, Figure 8 is an equivalent circuit diagram of the protection device according to the example of the present application, Figure 9 is a circuit connection relationship diagram of the transistor and the protection device according to the example of the present application.

[0108] As Figure 7, showing the energy band diagrams of the first electrode 303 and the second electrode 304 containing metal materials, the energy band diagram of the first barrier layer 302 containing AlGaN material, and the energy band diagram of the first channel layer 301 containing GaN material.

[0109] In Figure 7 , the physical meanings represented by the various quantities in the energy band diagram are as follows:

[0110] E F : Fermi level. For a microscopic system composed of fermions (which can be electrons, protons, neutrons), each fermion is in its respective quantum energy state. In the energy band theory, the Fermi level can be regarded as the imaginary energy level that electrons have a 50% probability of occupying at thermodynamic equilibrium.

[0111] E C : The bottom of the conduction band shown as the bandgap width.

[0112] E V : The top of the valence band shown as the bandgap width.

[0113] qφ b : Shown as the Schottky barrier.

[0114] qV bi : Shown as the semiconductor barrier.

[0115] From Figure 7 it can be known that: In the protection device 30 shown in Figure 6 , the first electrode 303 and the first barrier layer 302 form a Schottky diode SBD1, and the first barrier layer 302 and the first channel layer 301 located below the first electrode 303 form a diode D1. As shown in Figure 8 , the Schottky diode SBD1 and the diode D1 are in series. The second electrode 304 and the first barrier layer 302 form a Schottky diode SBD2, and the first barrier layer 302 and the first channel layer 301 located below the second electrode 304 form a diode D2. As shown in Figure 8 , the Schottky diode SBD2 and the diode D2 are in series. The first channel layer 301 forms a resistor R. And the resistor R is in series between the cathodes of the diode D1 and the diode D2.

[0116] Figure 9 In the example, in the protection device 30, the first electrode of the Schottky diode SBD1 is electrically connected to the gate G of the transistor, and the second electrode of the Schottky diode SBD2 is electrically connected to the source S of the transistor.

[0117] Figure 8 and Figure 9The working principle of the exemplary protection device includes: for example, when the first electrode 303 is connected to a high potential and the second electrode 304 is connected to a low potential (for example, grounded), both the Schottky diode SBD1 and the diode D1 are forward-conducting and in an on state, and both the Schottky diode SBD2 and the diode D2 are in a reverse cut-off state. When the voltage exceeds a certain threshold, the kinetic energy of electrons in the first channel layer 301 increases, so that the kinetic energy of some electrons can overcome the barriers of the diode D2 and the Schottky diode SBD2, and thus escape to the second electrode 304, causing the protection device to form a current channel, protecting the transistor and preventing the transistor gate from overvoltage.

[0118] Conversely, when the second electrode 304 is connected to a high potential and the first electrode 303 is connected to a low potential, both the Schottky diode SBD2 and the diode D2 are forward-conducting and in an on state, and both the Schottky diode SBD1 and the diode D1 are in a reverse cut-off state. When the voltage exceeds a certain threshold, the kinetic energy of electrons in the first channel layer 301 increases, so that the kinetic energy of some electrons can overcome the barriers of the diode D1 and the Schottky diode SBD1, and thus escape to the first electrode 303, causing the protection device to form a current channel, protecting the transistor and preventing the transistor gate from overvoltage.

[0119] Return to Figure 6 Transistor 20 includes a second channel layer 201, and a second barrier layer 202 is disposed on the second channel layer 201. The second barrier layer 202 and the second channel layer 201 form a heterojunction and form a two-dimensional electron gas (2DEG) channel under the polarization effect. The source S and the drain D of the transistor 20 are both in ohmic contact with the second channel layer 201.

[0120] In some examples, such as Figure 6 , the first channel layer 301 of the protection device 30 and the second channel layer 201 of the transistor 20 are in the same channel layer, and the first channel layer 301 is electrically isolated from the second channel layer 201.

[0121] Continue to see Figure 6 , the first barrier layer 302 of the protection device 30 and the second barrier layer 202 of the transistor 20 are in the same barrier layer, and the first barrier layer 302 is electrically isolated from the second barrier layer 202.

[0122] In some embodiments, the materials of the first channel layer 301 and the second channel layer 201 in the same channel layer are the same, or the thickness dimensions are equal.

[0123] In some implementation structures, the materials of the first barrier layer 302 and the second barrier layer 202 in the same barrier layer are the same, or the thickness dimensions are equal.

[0124] In a feasible process, stacked channel layers and barrier layers can be formed on the substrate 10, and then the channel layers and barrier layers are patterned to form electrically isolated second channel layer 201 and first channel layer 301, as well as electrically isolated second barrier layer 202 and first barrier layer 302.

[0125] In some examples, the gate G of the transistor can be located in the same metal layer as the first electrode 303 and the second electrode 304 of the protection device.

[0126] For example, the gate G, the first electrode 303, and the second electrode 304 located in the same metal layer can be made of the same material. For example, at least one of Ni, Au, Pt, and Ti can be selected.

[0127] In the example of this application, the transistor 20 and the protection device 30 are integrated on the same substrate 10 to form an on-chip protection semiconductor device. In this way, it can effectively reduce the damage of components caused by electrostatic discharge during the packaging process of the semiconductor device, reduce the ESD sensitivity and failure risk of the protected GaN HEMT device during the above packaging process, improve the yield of the semiconductor device, and improve the reliability.

[0128] In addition, when manufacturing this on-chip protection semiconductor device, the protected transistor and protection device can be obtained by the front-end process. That is, the preparation process of the protection device is completely compatible with the process of the GaN HEMT device and does not pose a challenge to the process.

[0129] Furthermore, the protection device in the example of this application has a simple structure and a small occupied area, which can improve the integration density of the transistor.

[0130] In the semiconductor device of the example of this application, the protected transistor can be not only an enhancement-mode GaN HEMT device but also a depletion-mode GaN HEMT device.

[0131] In some other examples, such as Figure 10 , Figure 10 FIG. is a structural diagram of another semiconductor device including the transistor 20 and the protection device 30 given in this application. In this example, a buffer layer 40 can also be included. The buffer layer 40 is stacked on the substrate 10, and the first channel layer 301 and the second channel layer 201 are stacked on the buffer layer 40.

[0132] In still other examples, a first cap layer 305 stacked on the first barrier layer 302 and a second cap layer 205 stacked on the second barrier layer 202 can also be included, and the first cap layer 305 and the second cap layer 205 are electrically isolated.

[0133] In the achievable processes, a buffer layer 40, a channel layer, a barrier layer, and a cap layer can be sequentially formed on a substrate, and then the channel layer, the barrier layer, and the cap layer are patterned to obtain the first channel layer 301 and the second channel layer 201 which are electrically isolated as shown in Figure 10 , the first barrier layer 302 and the second barrier layer 202 which are electrically isolated, and the first cap layer 305 and the second cap layer 205 which are electrically isolated.

[0134] The buffer layer 40 includes but is not limited to a single-layer or multi-layer IIIA group nitride and a multi-element IIIA group nitride, or a superlattice structure composed of them. The buffer layer is used to buffer the stress between the substrate and the channel layer and improve the quality of the epitaxial growth of the channel layer.

[0135] The first channel layer 301 and the second channel layer 201 can include gallium nitride (GaN) material. Any one of the first channel layer 301 and the second channel layer 201 can include a single channel layer, or can include at least two phases of stacked channel layers.

[0136] The first barrier layer 302 and the second barrier layer 202 can include but are not limited to IIIA group nitrides and multi-element IIIA group nitrides.

[0137] The first cap layer 305 and the second cap layer 205 can include but are not limited to grown nitride or oxide layers. For example, a grown GaN single crystal layer can be selected in some embodiments, and for another example, a polycrystalline SiNx layer can be selected in some embodiments.

[0138] In some examples, an isolation layer can also be stacked between the first channel layer 301 and the first barrier layer 302, and an isolation layer can be stacked between the second channel layer 201 and the second barrier layer 202, and the two isolation layers are also electrically isolated.

[0139] In still other examples, the gate G of the transistor can be stacked on the gate dielectric layer, and the gate dielectric layer is stacked on the cap layer.

[0140] As Figure 11 , Figure 11 shows the structures of the first electrode 303 and the second electrode 304. In this example, the first electrode 303 and the second electrode 304 are in a strip structure, and the spacing S between the first electrode 303 and the second electrode 304.

[0141] The spacing S between the first electrode 303 and the second electrode 304 can affect the turn-on voltage V of this protection device ON .

[0142] Exemplarily, 0.5μm ≤ S ≤ 20μm. For example, 1μm ≤ S ≤ 20μm; or, 10μm ≤ S ≤ 20μm; or, 15μm ≤ S ≤ 20μm.

[0143] The shapes of the first electrode 303 and the second electrode 304 are diverse.

[0144] For example Figure 11 , both the first electrode 303 and the second electrode 304 can be strip-shaped structures.

[0145] For example Figure 12 , the first electrode 303 and the second electrode 304 can be in a bent structure. In some examples, the bending angle of the first electrode 303 and the second electrode 304 can be close to 90°.

[0146] For example Figure 13 , the first electrode 303 can be in a circular structure, and the second electrode 304 can be in an annular structure. The second electrode 304 surrounds the periphery of the first electrode 303.

[0147] For example Figure 14 , the first electrode 303 can be in an annular structure, and the second electrode 304 can be in an annular structure. The second electrode 304 surrounds the periphery of the first electrode 303.

[0148] For example Figure 15 , there are multiple first electrodes 303 and multiple second electrodes 304; the multiple first electrodes 303 and the multiple second electrodes 304 are arranged alternately in the first direction, and the first direction is parallel to the surface of the substrate. For example Figure 15 The multiple first electrodes 303 and the multiple second electrodes 304 shown are arranged at intervals along the P direction parallel to the substrate.

[0149] When adopting Figure 15 the electrode layout method shown, the length dimensions of the first electrode 303 and the second electrode 304 can be increased. In this way, the current-carrying capacity of the protection device can be increased.

[0150] In some examples, for the length dimension L of at least one of the first electrode 303 and the second electrode 304, 100 μm ≤ L ≤ 1000 μm. For example, 500 μm ≤ L ≤ 1000 μm; or, 500 μm ≤ L ≤ 800 μm; or, 800 μm ≤ L ≤ 1000 μm.

[0151] For example Figure 13 , Figure 13 The length dimensions of the exemplary first electrode 303 and second electrode 304 can be understood as: the length dimension of the first electrode 303 is the perimeter of the first electrode 303, and the length dimension of the second electrode 304 is the perimeter of the outer ring of the second electrode 304.

[0152] For example Figure 14 , Figure 14The length dimensions of the first electrode 303 and the second electrode 304 in the example can be understood as follows: The length dimension of the first electrode 303 is the circumference of the outer ring of the first electrode 303, and the length dimension of the second electrode 304 is the circumference of the outer ring of the second electrode 304.

[0153] In some examples, the width dimensions of the first electrode 303 and the second electrode 304 can affect the current-carrying capacity of the protection device.

[0154] The width d of the first electrode 303 and / or the second electrode 304 satisfies 2μm ≤ d ≤ 20μm. For example, 10μm ≤ d ≤ 20μm; for another example, 10μm ≤ d ≤ 15μm; for yet another example, 10μm ≤ d ≤ 18μm.

[0155] Such as Figure 11 、 Figure 12 and Figure 15 For, the width dimension of the first electrode 303 is the dimension in the direction perpendicular to the extension direction. In Figure 13 it is the diameter of the first electrode 303, and the width dimension of the second electrode 304 is the difference between the outer ring diameter and the inner ring diameter. In Figure 14 it is the difference between the outer ring diameter and the inner ring diameter, and the width dimension of the second electrode 304 is the difference between the outer ring diameter and the inner ring diameter.

[0156] In the example of this application, returning to Figure 10 the thickness dimension of the first barrier layer 302 can affect the turn-on voltage V ON of the protection device. In some examples, the larger the thickness dimension of the first barrier layer 302, the larger the turn-on voltage V ON . The thickness h of the first barrier layer 302 given in this application satisfies 10nm ≤ h ≤ 30nm. For example, 20nm ≤ h ≤ 30nm; or 15nm ≤ h ≤ 30nm; 18nm ≤ h ≤ 30nm.

[0157] The composition of the first barrier layer 302 can also affect the turn-on voltage V ON of the protection device. In some examples, the material of the first barrier layer 302 includes Al x Ga 1-x N, where 0.2 ≤ x ≤ 0.4. The content of Al in Al x Ga 1-x N can affect the turn-on voltage V ON of the protection device. For example, 0.3 ≤ x ≤ 0.4, or 0.2 ≤ x ≤ 0.3, or 0.3 ≤ x ≤ 0.35.

[0158] For the protection device provided by this application, the turn-on voltage V ONis relatively large, for example, 5V ≤ V ON ≤ 100V, or, 50V ≤ V ON ≤ 100V, 80V ≤ V ON ≤ 100V; 50V ≤ V ON ≤ 90V; 20V ≤ V ON ≤ 90V. In this way, when the operating voltage of the protected transistor is relatively high, overvoltage protection can still be provided for the transistor gate. Moreover, the structure of the protection device is simple and does not occupy a large area, improving the integration density of the protected transistor.

[0159] For the protection device exemplified in this application, not only is the turn-on voltage V ON relatively large, but the off-state leakage current is also relatively small. For example, the off-state leakage current I of the protection device satisfies I ≤ 10 -2 mA / mm.

[0160] As Figure 16 , Figure 16 shown is the I-V characteristic curve of the protection device exemplified in this application, that is, the current-voltage characteristic curve. The abscissa of curve 1 in the curve graph represents voltage, and the ordinate represents current density. The abscissa of curve 2 represents voltage, and the ordinate represents current. From this Figure 16 it can be known that: the turn-on voltage of the protection device is 34V, the off-state leakage current is on the order of 0.1 mA, and the off-state leakage current is very small.

[0161] In the semiconductor device exemplified in this application, multiple protected transistors are integrated. Each transistor can be arranged in an array on the substrate. Each transistor has a gate G, a source S, and a drain D. As Figure 17 shown, Figure 17 exemplarily shows the layout of six protected transistors, and the layout of multiple gates G, multiple sources S, and multiple drains D included in the six transistors. Among them, multiple gates G, multiple sources S, and multiple drains D can be arranged along a direction parallel to the substrate. Multiple gates G are interconnected, multiple sources S are interconnected, and multiple drains D are interconnected.

[0162] The first electrode 303 in the protection device can be electrically connected to the interconnected gates G through the metal trace 1, and the second electrode 304 can be electrically connected to the interconnected sources S through the metal trace 2. The transistors and the protection devices for transistor gate overvoltage protection exemplified in this application can be fabricated through front-end processes. As Figure 17 shown, the metal trace 1 and the metal trace 2 can be fabricated in the interconnect layer through back-end processes.

[0163] That is, the fabrication of the protection device can be completed in the previous process, providing ESD protection for the GaN HEMT device during the subsequent process to module packaging, reducing the ESD sensitivity and failure risk of the protected GaN HEMT device during the above process, and improving the reliability of the device.

[0164] The embodiment of the present application also provides a method for manufacturing a semiconductor device, as Figure 18 shown, Figure 18 The flowchart of the manufacturing method is exemplified. The manufacturing method includes:

[0165] S1: Fabricate a transistor and a protection device on a substrate;

[0166] Fabricating a protection device on a substrate includes:

[0167] Fabricate a first channel layer on the substrate; fabricate a first barrier layer on the first channel layer; fabricate a first electrode and a second electrode on the first barrier layer. The first electrode and the second electrode are electrically isolated from each other, and the first barrier layer corresponding to the position of the first electrode and the first barrier layer corresponding to the position of the second electrode are electrically isolated from each other.

[0168] S2: Electrically connect the gate of the transistor to the first electrode of the protection device, and electrically connect the source or drain of the transistor to the second electrode of the protection device.

[0169] In the protection device fabricated by the method exemplified in the present application, a Schottky diode SBD1 formed by the first electrode and the first barrier layer, a diode D1 formed between the first barrier layer corresponding to the position of the first electrode and the first channel layer, and a Schottky diode SBD2 formed by the second electrode and the first barrier layer, and a diode D2 formed between the first barrier layer corresponding to the position of the second electrode and the first channel layer are included.

[0170] The Schottky diode SBD1 and the diode D1 are connected in series, and the Schottky diode SBD2 and the diode D2 are connected in series, and are coupled between the gate and the source (or drain) of the transistor.

[0171] For example, when the protected transistor is at the normal operating voltage, both the Schottky diode SBD1 and the diode D1 are forward-conducting and in the on state, and the Schottky diode SBD2 and the diode D2 are in the reverse cutoff state. However, when the gate of the transistor is over-voltage and the voltage exceeds a certain threshold, due to the increase in the electron kinetic energy in the channel, the kinetic energy of a part of the electrons overcomes the barriers of the diode D2 and the Schottky diode SBD2, and escapes to the second electrode, becoming an electron leakage channel to prevent the transistor from being impacted by high voltage.

[0172] In addition, the protection device provided in this application and the transistor to be protected are integrated on the same substrate to form an on-chip integrated protection device. In this way, during subsequent packaging processes of the semiconductor device, for example, ESD protection can be provided to reduce the ESD sensitivity of the transistor to be protected and even the risk of failure.

[0173] In some implementable processes, the protection device and the transistor to be protected can be fabricated using a front-end process. For example, the channel layer in the protection device and the channel layer in the transistor can be fabricated simultaneously using the same process; the barrier layer in the protection device and the barrier layer in the transistor can be fabricated simultaneously using the same process; the first electrode and the second electrode of the protection device can be fabricated simultaneously with the gate of the transistor using the same process. This makes the fabrication process of the protection device compatible with that of the transistor and facilitates process implementation.

[0174] The following introduces the specific process flows involved in the fabrication method of the above semiconductor device with reference to the accompanying drawings.

[0175] Figures 19A to 19F The process structure after each step in the process of fabricating a semiconductor device according to an embodiment of this application is given.

[0176] As Figure 19A shown, a buffer layer, a channel layer, a barrier layer, and a cap layer are sequentially fabricated on the substrate.

[0177] In some other examples, an isolation layer can also be formed between the channel layer and the barrier layer.

[0178] The substrate can be silicon, silicon carbide, aluminum oxide, or a composite substrate formed based on the above substrates.

[0179] The buffer layer can be a Group III nitride, such as AlN or AlGaN, which is used to buffer the stress between the substrate and the channel layer and improve the quality of epitaxial growth of the channel layer.

[0180] The barrier layer includes an aluminum gallium nitride (AlGaN) material. For example, the Group III nitride barrier layer is disposed on top of the Group III nitride channel layer. The Group III nitride barrier layer is used to cooperate with the Group III nitride channel layer to generate a 2DEG through polarization in the region where the Group III nitride channel layer and the Group III nitride barrier layer are in contact, thereby providing a channel for conducting current.

[0181] As Figure 19B shown, the active region and the protection region of the semiconductor device are isolated. The active region in the example of this application can be understood as the region where the transistor is disposed, and the protection region is the region where the protection device is disposed.

[0182] In an implementable solution, the channel layer of the active region and the channel layer of the protection region can be cut off by forming a physical etching groove. The etching method can be at least one of reactive ion etching (RIE), inductively coupled plasma-reactive ion etching (ICP-RIE), wet potassium hydroxide (KOH) solution, wet etching after thermal oxidation, and photo-assisted electrochemical etching.

[0183] In another implementable solution, the channel layer of the active region and the channel layer of the protection region can be isolated by shallow trench isolation (STI) process.

[0184] In Figure 19B the example, the active region and the protection region are isolated by etching a groove, and the groove penetrates from the cap layer to the buffer layer.

[0185] As Figure 19C shown, the groove is etched. The groove etching in this step can be performed by at least one of reactive ion etching (RIE), inductively coupled plasma-reactive ion etching (ICP-RIE), wet potassium hydroxide (KOH) solution, wet etching after thermal oxidation, and photo-assisted electrochemical etching.

[0186] The bottom termination position of the groove can be the surface of the channel layer, or it can be ±0.5 nm away from the surface of the channel layer.

[0187] In some realizable processes, after etching the groove, the root mean square (RMS) surface roughness of the trench layer is less than or equal to 0.3 nm, or close to the surface roughness of the epitaxially grown cap layer.

[0188] As Figure 19D shown, in Figure 19C the etched groove of the active region, a source electrode S and a drain electrode D that are ohmic contact with the channel layer are formed.

[0189] In an implementable manner, the source electrode S and the drain electrode D of the ohmic contact are formed by a method of full-surface sputtering or evaporation deposition followed by etching or stripping. The optional implementation schemes for the source electrode S and the drain electrode D include high-temperature annealing, ion implantation, or secondary epitaxy.

[0190] For example, when fabricating the source electrode S and the drain electrode D of the ohmic contact by high-temperature annealing, at least one of the materials Ti, Al, Ni, and Au can be selected, and the ohmic metal is subjected to high-temperature annealing treatment in a nitrogen atmosphere at 800 °C - 900 °C to obtain the ohmic contact of the source electrode S and the drain electrode D.

[0191] For another example, in the ion implantation ohmic contact scheme, the ohmic contact region is first subjected to ion implantation treatment, and the implanted ions can be elements such as Si or Ge, and then annealing activation treatment is performed at a high temperature above 1000 °C.

[0192] For another example, for fabricating ohmic contacts using the secondary epitaxial growth technique, epitaxial growth must be carried out under high-temperature conditions above 1000°C.

[0193] The source S or the drain D can be a single-layer structure or a stacked multi-layer structure. For example, it can be a stacked structure of Ti layer, Al layer, Ni layer, and Au layer.

[0194] Such as Figure 19E As shown, the gate G of the fabricated transistor, the first electrode and the second electrode of the protection device are obtained.

[0195] In an implementable solution, the gate G of the transistor, the first electrode and the second electrode of the protection device can be deposited and grown simultaneously or separately.

[0196] The optional schemes for depositing metals include but are not limited to at least one of Ni and Au, or at least one of Pt, Ti, Au, or at least one of W, Ti, Au, or at least one of TiN and Cu.

[0197] The gate G, the first electrode or the second electrode of the transistor can be a single-layer structure or a stacked multi-layer structure. For example, it can be a stacked structure of Ni layer and Au layer; for another example, it can be a stacked structure of Pt layer, Ti layer and Au layer; for another example, it can be a stacked structure of W layer, Ti layer and Au layer; for another example, it can be a stacked structure of TiN layer and Cu layer.

[0198] In another process step, the gate dielectric layer can be fabricated before fabricating the gate G, and then the gate G is fabricated on the gate dielectric layer.

[0199] Such as Figure 19F As shown, the interconnect wiring layer is fabricated using the back-end process. For example, by depositing metal wiring, the transistor and the protection device are electrically connected using the metal wiring. The gate G of the transistor is electrically connected to the first electrode, and the source S of the transistor is electrically connected to the second electrode.

[0200] In an implementable solution, the metal wiring can be formed by electroplating, sputtering, or evaporation, and the metal types include but are not limited to one or several of Ni, Au, Cu, Pt, Ti, and W.

[0201] In some other implementable process steps, it can also be fabricated using the Figures 20A to 20F method shown. Figures 20A to 20F The process structure after each step in another process for fabricating a semiconductor device according to an embodiment of the present application is given.

[0202] Such as Figure 20A As shown, a buffer layer, a channel layer, a barrier layer, and a cap layer are sequentially fabricated on the substrate.

[0203] As shown in Figure 20B , the photolithography mask technology is used to pattern the structure shown in Figure 20A , exposing the source electrode S and drain electrode D for which an ohmic contact is to be fabricated, as well as the groove region of the protection device. Then, the capping layer and barrier layer in these regions are etched away in sequence by dry etching, and the photolithography mask layer is removed to complete the wafer cleaning, obtaining the structure shown in Figure 20B .

[0204] In some examples, the surface roughness of the bottom of the etched groove is less than 0.3 nm.

[0205] The termination position of the etched groove is ±0.5 nm from the surface of the trench layer.

[0206] The width of the etched groove of the protection device can be 3 μm, and the length of the etched groove can be 600 μm.

[0207] As shown in Figure 20C , the source electrode S and drain electrode D of the transistor are fabricated in the groove for forming the ohmic contact layer obtained, and the etched groove of the protection device is retained. Figure 20B

[0208] As shown in Figure 20D , the regions outside the active region of the transistor and the protection device are isolated by ion implantation. For example, high-energy N ions can be used for treatment. The purpose of ion implantation is to destroy the 2DEG channel in the non-functional region, and the leakage current between the functional regions after isolation can be less than or equal to 1 nA / mm.

[0209] The leakage current between the functional regions after isolation can be less than or equal to 1 nA / mm. It can be understood that: the leakage current between the protected transistors can be less than or equal to 1 nA / mm, or the leakage current between the protected transistor and the protection device can be less than or equal to 1 nA / mm.

[0210] The functional regions in the examples of this application can be understood as the regions where transistors are arranged (the regions where the two-dimensional electron gas channel needs to be retained), and the non-functional regions can be understood as the regions where the two-dimensional electron gas channel does not need to be retained.

[0211] As shown in Figure 20E , the gate G of the transistor, the first electrode and the second electrode of the protection device can be formed by electron beam evaporation.

[0212] As shown in Figure 20F , the interconnect wiring layer is fabricated by back-end processes. For example, by depositing metal wiring, the transistor and the protection device are electrically connected using the metal wiring. The gate G of the transistor is electrically connected to the first electrode, and the source electrode S of the transistor is electrically connected to the second electrode.​

[0213] As Figure 21 shown, in the fabricated semiconductor device, a dielectric layer is filled in the groove that is formed between the first electrode and the second electrode and penetrates through to the channel layer. The dielectric layer is used to electrically isolate the first electrode and the second electrode and to switch the two-dimensional electron gas channel of the protection device.

[0214] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any one or more embodiments or examples in a suitable manner.

[0215] The above are only specific implementation manners of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: substrate; A transistor and a protection device disposed on the substrate; The protective device comprises: A first channel layer formed on the substrate; a first barrier layer formed on the first channel layer; a first electrode and a second electrode, wherein the first electrode and the second electrode are both disposed on the first barrier layer, and the first electrode and the second electrode are electrically isolated; The first barrier layer corresponding to the first electrode position is electrically isolated from the first barrier layer corresponding to the second electrode position; The gate of the transistor is electrically connected to the first electrode, and the source or drain of the transistor is electrically connected to the second electrode.

2. The semiconductor device according to claim 1, wherein: A second channel layer is also formed on the substrate, and the second channel layer is electrically isolated from the first channel layer; A second barrier layer is formed on the second channel layer, and the second barrier layer is electrically isolated from the first barrier layer; A source and a drain of the transistor are both in ohmic contact with the second channel layer.

3. The semiconductor device according to claim 2, wherein, The first channel layer and the second channel layer are located in the same channel layer, and the first barrier layer and the second barrier layer are located in the same barrier layer.

4. The semiconductor device according to claim 2 or 3, characterized in that, The gate of the transistor is located on a side of the second barrier layer away from the second channel layer; the gate of the transistor, the first electrode and the second electrode are located in the same metal layer.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: A dielectric layer is provided between the first electrode and the second electrode; The dielectric layer is located between the first barrier layer corresponding to the first electrode position and the first barrier layer corresponding to the second electrode position.

6. The semiconductor device according to any one of claims 1-5, characterized in that, There are a plurality of the first electrodes, and a plurality of the second electrodes; A plurality of the first electrodes and a plurality of the second electrodes are arranged alternately in a first direction, and the first direction is parallel to a surface of the substrate.

7. The semiconductor device according to any one of claims 1-6, characterized in that, The distance S between the first electrode and the second electrode is 0.5 μm≤S≤20 μm.

8. The semiconductor device according to any one of claims 1-7, characterized in that, The width d of the first electrode and / or the second electrode is 2 μm≤d≤20 μm.

9. The semiconductor device according to any one of claims 1-8, characterized in that, The material of the first barrier layer includes Al x Ga 1-x N, where 0.2 ≤ x ≤ 0.

4.

10. The semiconductor device according to any one of claims 1-9, characterized in that, The thickness h of the first barrier layer is 10 nm ≤ h ≤ 30 nm.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that, The turn-on voltage V of the protection device ON , 5V ≤ V ON ≤ 100V.

12. The semiconductor device according to any one of claims 1-11, characterized in that, The off-state leakage current I of the protection device, I ≤ 10 -2 mA / mm.

13. The semiconductor device according to any one of claims 1 to 12, characterized in that, The transistor and the protection device have an interconnection wiring layer on a side facing away from the substrate; The gate of the transistor is electrically connected to the first electrode through the interconnect wiring layer; The source or drain of the transistor is electrically connected to the second electrode through the interconnection wiring layer.

14. A method for manufacturing a semiconductor device, characterized in that, The preparation method comprises: Fabricating transistors and protective devices on a substrate; The gate of the transistor is electrically connected to the first electrode of the protection device, and the source or drain of the transistor is electrically connected to the second electrode of the protection device; Producing the protection device on the substrate comprises: Producing a first channel layer on the substrate; forming a first barrier layer on the first channel layer; The first electrode and the second electrode are formed on the first barrier layer, the first electrode and the second electrode are electrically isolated from each other, and the first barrier layer corresponding to the position of the first electrode is electrically isolated from the first barrier layer corresponding to the position of the second electrode.

15. The method for manufacturing a semiconductor device according to claim 14, wherein, Producing the transistor and the protection device on the substrate comprises: Producing a channel layer on the substrate; forming a barrier layer on the channel layer; The active area for making the transistor and the area for making the protective device are electrically isolated to produce the first channel layer and the first barrier layer stacked in the area of ​​the protective device, and the second channel layer and the second barrier layer stacked in the active area, the first channel layer is electrically isolated from the second channel layer, and the first barrier layer is electrically isolated from the second barrier layer.

16. The manufacturing method of the semiconductor device according to claim 15, characterized in that, After the barrier layer is formed on the channel layer, the preparation method further comprises: Etching a groove in a region for making the protection device, wherein the groove penetrates the barrier layer; The first electrode and the second electrode are formed on the barrier layer separated by the groove.

17. The method for manufacturing a semiconductor device according to any one of claims 14 to 16, characterized in that, When the first electrode and the second electrode are formed on the first barrier layer, the method further comprises: A gate of the transistor is manufactured.

18. The method for manufacturing a semiconductor device according to any one of claims 14 to 17, characterized in that, When the first electrode and the second electrode are manufactured on the first barrier layer, the method comprises: A plurality of the first electrodes and a plurality of the second electrodes are manufactured along a first direction parallel to the surface of the substrate, and the plurality of the first electrodes and the plurality of the second electrodes are alternately arranged in the first direction.

19. The method for manufacturing a semiconductor device according to any one of claims 14-18, characterized in that, After the transistor and the protection device are manufactured on the substrate, the manufacturing method further comprises: An interconnection wiring layer is formed on the side of the transistor and the protection device facing away from the substrate, the gate of the transistor is electrically connected to the first electrode through the interconnection wiring layer, and the source or drain of the transistor is electrically connected to the second electrode through the interconnection wiring layer.

20. An electronic device, characterized in that, include: substrate; The semiconductor device according to any one of claims 1 to 13, wherein the semiconductor device is arranged on the substrate.

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