Wide-bandgap ultrahigh-voltage large-current semiconductor device structure and manufacturing method thereof

Abstract

The invention provides a wide-bandgap ultrahigh-voltage large-current semiconductor device structure and a manufacturing method thereof. The device structure comprises a substrate layer and an epitaxial layer, the channel layer is arranged on the epitaxial layer, and a P-type semiconductor layer is embedded in the channel layer to form a PN junction; the N-type semiconductor layer is arranged in the P-type semiconductor layer; the gate dielectric layer grows on the channel layer; the gate electrode is deposited on the gate dielectric layer; the interlayer dielectric layer grows on the channel layer; a groove is formed in the substrate layer, the groove is filled with a transparent insulator medium, a current gain window is constructed and formed, light rays reach the substrate layer through the current gain window under the action of illumination, and the substrate layer generates a large number of photon-generated carriers due to illumination and is conductive under the action of an electric field; and the first electrode and the second electrode are respectively arranged on two sides of the stacked structure of the gate dielectric layer and the interlayer dielectric layer. According to the structure, the conversion of the working state of the gallium oxide device is realized through the additionally arranged light-operated unit, and the problem of large on-resistance caused by lack of P-type doping of the gallium oxide device is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a wide-bandgap ultra-high voltage and high-current semiconductor device structure and a manufacturing method thereof. Background Art

[0002] In recent years, power devices have been widely used in many fields, covering aspects such as mobile phones, fast charging of new energy vehicles, photovoltaic power generation, and high-voltage power grid transmission, greatly facilitating people's daily lives. With the continuous progress of technology, power devices will still play an important role in the future, further improving the quality of human life.

[0003] In power switch applications, Baliga's Figure-of-Merit (BFOM) is widely used to measure the applicability of semiconductor materials in the field of power electronics. The calculation formula of this index is: BFOM = εμE³, where ε represents the dielectric constant, μ is the mobility, and E is the breakdown electric field strength of the semiconductor. Research shows that the BFOM value is roughly positively correlated with the sixth power of the bandgap width (Eg) of the semiconductor material. Therefore, a larger bandgap width means lower power loss and higher conversion efficiency, thus achieving more excellent power electronics application performance. Among wide-bandgap semiconductor materials, Ga2O3 stands out with its 4.8 eV bandgap width, an ideal breakdown electric field strength of 8 MV / cm, and a BFOM value as high as 3400. Its BFOM value is about 4 times that of GaN and 10 times that of SiC. Thus, Ga2O3 materials have extremely important research value and broad application prospects in current power electronics applications with urgent demands for higher power density and lower power consumption.

[0004] However, although Ga2O3 performs well in n-type doping, there has been no successful report on p-type doping so far. This situation severely restricts the application of Ga2O3 in bipolar power devices. Specifically, there are three major problems in realizing p-type Ga2O3 with hole conduction: First, it is difficult to find acceptor impurities with low activation energy; second, theoretical calculations show that the maximum valence band dispersion of Ga2O3 is small, resulting in a very large effective mass, making the mobility (μ) of free holes extremely low and showing a local distribution characteristic; finally, theoretical predictions for Ga2O3 indicate that due to local lattice distortion, the energy of local self-trapping of free holes in the volume is extremely high, thus forming small polarons, which undoubtedly hinders the conduction of effective holes.

[0005] Based on this, the present invention provides a new wide-bandgap ultra-high voltage and high-current semiconductor device structure and a manufacturing method thereof. Summary of the Invention

[0006] Based on the above description, the present invention provides a wide-bandgap ultra-high voltage and high-current semiconductor device structure and device structure, aiming to solve the technical problem of difficult p-type doping in Ga2O3 materials, thereby breaking through its limitations in the application of bipolar power devices and further expanding the application scope of Ga2O3 in high-performance power electronic devices.

[0007] The technical solution of the present invention to solve the above technical problems is as follows: In the first aspect, the present invention provides a wide-bandgap ultra-high voltage and high-current semiconductor device structure, including: A substrate layer; An epitaxial layer disposed on the substrate layer; A channel layer, which is an N-type Ga2O3 layer or a GaN layer, disposed on the epitaxial layer and internally embedded with a P-type semiconductor layer, and the P-type semiconductor layer forms a heterojunction PN junction with the channel layer; An N-type semiconductor layer wrapped inside the P-type semiconductor layer; A gate dielectric layer grown on the channel layer and completely covering the gap between the N-type semiconductor layer and the P-type semiconductor layer; A gate electrode deposited on the gate dielectric layer; An interlayer dielectric layer grown on the channel layer; a groove is etched from the upper surface of the interlayer dielectric layer down to the upper surface of the substrate layer, and the groove is filled with a transparent insulator dielectric to construct a current gain window. Under the action of light, light passes through the current gain window to reach the substrate layer, and the substrate layer conducts electricity under the action of an electric field due to a large number of photo-generated carriers generated by light; A first electrode and a second electrode respectively disposed on both sides of the superposition structure of the gate dielectric layer and the interlayer dielectric layer.

[0008] Based on the above technical solution, the present invention can also be improved as follows.

[0009] Further, the size of the N-type semiconductor layer in the channel direction is smaller than the size range of the P-type semiconductor, and there is a gap between the two.

[0010] Further, the resistivity of the substrate layer is greater than , and the thickness is 300 - 600 μm; And / or, the epitaxial layer is an unintentionally doped epitaxial layer, and the doping concentration is less than 10 16 cm -3 , and the thickness is 100 - 300 nm; And / or, the channel layer is a deliberately doped high-concentration epitaxial layer, and the doping concentration is 1.0x10 18 - 1.0x10 19 cm -3, with a thickness of 100 - 300 nm.

[0011] Further, the P-type semiconductor layer is any one of P-GaN, P-NiO, P-Cu2O, P-doped SiC, P-doped Si, and P-doped diamond.

[0012] Further, when the P-type semiconductor layer is P-GaN, the doping concentration of P-GaN is 5.0x10 18 -5.0x10 19 cm -3 .

[0013] Further, both the first electrode and the second electrode are ohmic contact electrodes, with a thickness of 10 - 100 nm.

[0014] Further, the first electrode and the second electrode are the emitter electrode and the collector electrode respectively; or, the first electrode and the second electrode are the source electrode and the drain electrode respectively; or, the first electrode and the second electrode are the cathode and the anode respectively; or, the first electrode and the second electrode are the anode and the cathode respectively.

[0015] Further, the cross-sectional shape of the current gain window is bar-shaped, square, circular, or hexagonal.

[0016] Further, the substrate layer and the epitaxial layer are each one or any combination of Ga2O3, AlN, BN, SiC, GaN, and diamond.

[0017] In a second aspect, the present invention also provides a manufacturing method for manufacturing the wide bandgap ultra-high voltage high-current semiconductor device structure as described in the first aspect, including the following steps: S1: Epitaxially grow an epitaxial layer on the substrate layer, and grow an N-type Ga2O3 layer as a channel layer on the epitaxial layer; Inlay a P-type semiconductor layer on the channel layer to form a heterojunction PN junction with the N-type Ga2O3 layer; S2: Form an N-type semiconductor layer opposite to the P-type semiconductor layer in one of the heterojunction PN junctions; S3: Grow a gate dielectric layer on the surface, and at the same time open holes in the P-type semiconductor region, and the gate dielectric completely covers the gap between the N-type semiconductor layer and the P-type semiconductor layer; S4: Deposit a layer of Ti on the surface as an ohmic contact electrode and a gate electrode, and perform annealing treatment; S5: Grow an insulating dielectric layer on the surface as an interlayer dielectric layer, and at the same time open holes at the position of the ohmic contact electrode to expose the electrode; S6: Deposit a Ti / Al laminated metal on the surface as the first electrode and the second electrode of the device; S7: Selectively etch the interlayer dielectric layer, the gate dielectric layer, the channel layer, and the epitaxial layer on the surface to obtain a groove structure; S8: Fill the groove structure with a transparent insulator dielectric to obtain a current gain window, thus completing the device.

[0018] Compared with the prior art, the technical solution of the present application has the following beneficial technical effects: The wide-bandgap ultra-high voltage and high-current semiconductor device structure and its manufacturing method provided by the present invention have the following beneficial effects compared with the prior art: First, the wide-bandgap ultra-high voltage and high-current semiconductor device structure fabricated by the present invention combines a lateral IGBT device structure with a current enhancement window.

[0019] When the device operates in the forward conduction state, when the forward voltage of the heterojunction PN junction on the collector side is high enough, the heterojunction PN junction can conduct and provide electrons and holes. When the gate electrode voltage exceeds the device threshold voltage, electrons can pass through the emitter, through the N-type semiconductor and the channel, and enter the channel layer and the epitaxial layer, and finally enter the substrate layer. The substrate layer generates a large number of photo-generated carriers due to light illumination and conducts electricity under the action of an electric field. Finally, the electrons will enter the epitaxial layer and the channel layer from the substrate layer and finally enter the collector, realizing high-current transmission.

[0020] When the device operates in the reverse cut-off state, when the gate voltage turns off the channel and the light illumination is removed, the current cannot conduct due to the lack of a conduction path. At this time, the voltage across the collector and the emitter will be applied to the channel layer and the transparent insulating dielectric layer. Since there are no net charges in the insulating dielectric, the electric field distribution in the insulating dielectric presents a horizontal shape at this time. When the proportion of the insulating dielectric in the same-sized cell is large, the breakdown voltage of the device will also increase. The present invention uses the carriers generated by light illumination to solve the problem that the semi-insulating substrate cannot conduct electricity. The generated photo-generated carriers can solve the problem of fabricating high-current devices and solve the problem of high on-resistance of traditional lateral devices. The transparent insulating dielectric can allow light to penetrate the surface and enter the semi-insulating substrate on the one hand, and can withstand high voltage during reverse blocking, playing a role in high-voltage resistance.

[0021] Second, when the wide-bandgap ultra-high voltage and high-current semiconductor device is turned on, the gate voltage needs to reach the threshold voltage and light illumination is required to generate a sufficient number of photo-generated carriers. By controlling the time difference between the opening and triggering of the two, the device can operate in multiple different modes. For example, when the gate bias voltage and the photon generation trigger circuit are turned on simultaneously, the device conducts forward. When the gate bias voltage or the photon generation trigger circuit is turned off, the device stops working. When the device is in the reverse bias state, the photon trigger circuit is turned on, which will cause a large number of carriers to be generated inside the semi-insulating substrate. The carriers will generate impact ionization under high electric field strength, thereby generating a large current. At this time, the device is in a high electric field and high voltage state, so it will consume a large amount of electric power and generate heat. At this time, it is necessary to control the opening time of the photon generation circuit to form a pulse switch, and the current in the device forms a pulse current.

[0022] In summary, the present invention constructs a wide-bandgap ultra-high voltage and high-current device by combining a lateral device structure with photo-generated carriers. The lateral device structure of the present invention can easily etch the channel layer and the epitaxial layer clean and use the dielectric filling method to realize the fabrication of high-voltage devices. The mechanism of the high-current device is that photo-generated carriers are generated by irradiating light through the reserved light illumination channel to participate in conduction.

[0023] Therefore, the gallium oxide-based ultra-high voltage and high-current device structure proposed by the present invention perfectly solves the problems of low breakdown voltage of silicon-based devices and short transmission distance of photons in semiconductor materials. The working state of the gallium oxide device can be conveniently changed through the additionally added light control unit, solving the problem of large on-resistance caused by the lack of P-type doping in gallium oxide devices. At the same time, by utilizing the ultra-wide bandgap characteristic of gallium oxide, an ultra-high voltage and high-current device is fabricated. Description of the Drawings

[0024] Figure 1 is a schematic structural diagram of the wide-bandgap ultra-high voltage and high-current semiconductor device structure provided in Embodiment 1 of the present invention; Figure 2 and Figure 3 is a schematic diagram of the working principle of the wide-bandgap ultra-high voltage and high-current semiconductor device structure provided in Embodiment 1 of the present invention; Figures 4 to 7 is a schematic structural diagram of the wide-bandgap ultra-high voltage and high-current semiconductor device structure of other construction types provided in the embodiments of the present invention; Figures 8 to 11 is a schematic cross-sectional shape diagram of the current gain window of the wide-bandgap ultra-high voltage and high-current semiconductor device structure provided in the embodiments of the present invention; Figure 12 is a schematic structural diagram of the wide-bandgap ultra-high voltage and high-current semiconductor device structure provided in Embodiment 2 of the present invention; Figures 13 to 20Schematic diagram of the manufacturing method of the wide-bandgap ultra-high voltage and high-current semiconductor device structure corresponding to Embodiment 1 provided in Embodiment 3 of the present invention; In the drawings, the list of components represented by each reference numeral is as follows: 1. Substrate layer; 2. Epitaxial layer; 3. Channel layer; 4. P-type semiconductor layer; 5. N-type semiconductor layer; 6. Gate dielectric layer; 7. Gate electrode; 8. Interlayer dielectric layer; 9. Current gain window; 10. First electrode; 11. Second electrode. Detailed implementation manners

[0025] To facilitate the understanding of the present application, the present application will be described more comprehensively with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0026] Due to the advantages of the gallium oxide material properties, it has excellent characteristics such as a large bandgap width and a high critical breakdown electric field. Therefore, using the gallium oxide material to manufacture power devices has excellent performances such as a high blocking voltage, a high operating temperature, and a low leakage current. Controlling the working state of the gallium oxide high-voltage device with an optical control unit has lower switching losses, higher device response speed, and higher safety compared with traditional electrical switches. Controlling the transition of the working state of the gallium oxide high-voltage device and reducing the on-resistance of the device by controlling the light intensity and pulse time has lower delay time, lower power loss, and higher safety compared with traditional electrical switches; Heterogeneous PN junctions formed by combining different wide-bandgap semiconductors with gallium oxide combine the advantages of different wide-bandgap semiconductors. In this way, even if the p-type gallium oxide doping is not successful, the excellent characteristics of the gallium oxide material withstanding high voltage and high current can be exerted, providing a potential possibility for the marketization of the application of gallium oxide power devices.

[0027] However, in the prior art, taking the gallium oxide material as an example, there is currently no instance of coupling the switching unit of the wide-bandgap semiconductor material with the optical control unit. The existing instances are silicon-based optical control devices, and there are two technical problems. First, the silicon material is used as the voltage withstand unit of the entire device. Currently developed silicon-based high-voltage devices such as IGBT (Insulated Gate Bipolar Transistor), VDMOS (Vertical Double-Diffused Metal Oxide Semiconductor), and GTO (Thyristor) have almost reached the physical limit of the silicon material, and it is very difficult to further improve its voltage withstand. For the gallium oxide material, its critical breakdown electric field (8 MV / cm) is 26 times that of the silicon material (0.3 MV / cm), which can naturally solve the problem of withstanding high voltage; Secondly, since the optical control units of silicon-based optical control devices all work near the surface of the electrode metal material, and since silicon itself is opaque, when the optical control unit starts to work, the depth of light entering from the surface of the silicon-based device is very thin and cannot reach the position of the breakdown voltage layer of the silicon-based device. At this time, the electron-hole pairs generated by light illumination are instantaneously recombined by the existing majority carriers in the neutral region near the surface, and no positive feedback of electron-hole pairs is generated, so it has little effect on current gain.

[0028] Therefore, there are certain defects in the prior art: on the one hand, the breakdown voltage of silicon-based devices is lower than that of wide-bandgap semiconductors with the same parameters, which is not conducive to their application in ultra-high voltage circuits; on the other hand, silicon is an opaque material, the transmission path of photons in silicon is very short, and the generated electron-hole pairs will basically be recombined on the surface, resulting in a small current gain.

[0029] The following further describes in detail the embodiments of the present invention in conjunction with the drawings and examples. The following examples are used to illustrate the present invention, but cannot be used to limit the scope of the present invention.

[0030] Example 1 As Figure 1 shown, the wide-bandgap ultra-high voltage and high-current semiconductor device structure provided by this embodiment integrates the breakdown voltage unit and the optical control unit designed with gallium oxide material to form a gallium oxide-based optical control high-voltage and high-current power device, which is expected to realize the marketization of gallium oxide material applications. It specifically includes: a substrate layer 1, an epitaxial layer 2, a channel layer 3, an N-type semiconductor layer 5, a gate dielectric layer 6, a gate electrode 7, an interlayer dielectric layer 8, a current gain window 9, a first electrode 10, and a second electrode 11.

[0031] Among them, the epitaxial layer 2 is disposed on the substrate layer 1.

[0032] In an alternative embodiment, the substrate layer 1 and the epitaxial layer 2 are each one or any combination of Ga2O3, AlN, BN, SiC, GaN, diamond. In this embodiment, the substrate layer 1 and the epitaxial layer 2 are made of gallium oxide material - Ga2O3 for introduction.

[0033] Specifically preferably, the resistivity of the substrate layer 1 is greater than , and the thickness is 300 - 600 μm.

[0034] The epitaxial layer 2 is an unintentionally doped epitaxial layer 2, with a doping concentration less than 10 16 cm -3 , and the thickness is 100 - 300 nm.

[0035] The channel layer 3 is an N-type Ga2O3 layer, disposed on the epitaxial layer 2, and internally embedded with a P-type semiconductor layer 4. The P-type semiconductor layer 4 and the N-type Ga2O3 layer form a heterojunction PN junction.

[0036] Specifically and preferably, the channel layer 3 is a deliberately doped high-concentration epitaxial layer 2 with a doping concentration of 1.0×10 18 -1.0×10 19 cm -3 , and the thickness is 100 - 300 nm.

[0037] The N-type semiconductor layer 5 is disposed and wrapped inside the P-type semiconductor layer 4.

[0038] It should be noted that: the size of the N-type semiconductor layer 5 along the channel direction is smaller than the size range of the P-type semiconductor layer 4, and there is a gap between the two.

[0039] Specifically, the P-type semiconductor layer 4 is any one of P-GaN, P-NiO, P-Cu2O, P-doped SiC, P-doped Si, and P-doped diamond.

[0040] Among them, when the P-type semiconductor layer 4 is P-GaN, the doping concentration of P-GaN is 5.0×10 18 -5.0×10 19 cm -3 ; in some examples, its thickness can exceed the channel layer 3 and the epitaxial layer 2 and extend into the substrate layer 1.

[0041] The gate dielectric layer 6 is grown on the channel layer 3 and completely covers the gap between the N-type semiconductor layer 5 and the P-type semiconductor layer 4.

[0042] The gate electrode 7 is deposited on the gate dielectric layer 6.

[0043] The interlayer dielectric layer 8 is grown on the channel layer 3; a groove is etched from the upper surface of the interlayer dielectric layer 8 down to the upper surface of the substrate layer 1, and the groove is filled with a transparent insulating medium to form a current gain window 9. Under the action of light, the light passes through the current gain window 9 to reach the substrate layer 1, and the substrate layer 1 conducts electricity due to a large number of photo-generated carriers generated by light irradiation under the action of an electric field.

[0044] The first electrode 10 and the second electrode 11 are respectively disposed on both sides of the stacked structure of the gate dielectric layer 6 and the interlayer dielectric layer 8.

[0045] In an alternative embodiment, both the first electrode 10 and the second electrode 11 are ohmic contact electrodes with a thickness of 10 - 100 nm.

[0046] In an alternative example, the first electrode 10 and the second electrode 11 are respectively an emitter electrode and a collector electrode (as Figure 1 shown).

[0047] In other alternative examples, the first electrode 10 and the second electrode 11 can also be respectively a source electrode and a drain electrode (as Figure 4 shown).

[0048] In other alternative examples, the first electrode 10 and the second electrode 11 are an anode and a cathode respectively (as Figure 5 and Figure 6 shown).

[0049] That is, the lateral device structure can be various devices, such as IGBT (as Figure 1 shown), JFET (as Figure 5 shown), MOSFET (as Figure 4 shown), GTO (as Figure 6 shown), Diode (as Figure 7 shown), etc.

[0050] In an alternative embodiment, the cross-sectional shape of the current gain window 9 is bar-shaped (as Figure 11 shown), square (as Figure 9 shown), circular (as Figure 8 shown) or hexagonal (as Figure 10 shown). Similarly, it can also be a combined structure of these shapes.

[0051] The wide bandgap ultra-high voltage high current semiconductor device structure provided by this embodiment adopts a combination of a lateral IGBT device structure and a current enhancement window.

[0052] Its working principle in practice is as follows: as Figure 2 shown, when the device operates in the forward conduction state, when the forward voltage of the heterojunction PN junction on the collector side is high enough, the heterojunction PN junction conducts to provide electrons and holes. When the gate electrode voltage exceeds the device threshold voltage, electrons can pass through the emitter, through the N-type semiconductor and the channel, and enter the channel layer and the epitaxial layer, and finally enter the substrate layer. A large number of photo-generated carriers are generated in the substrate layer due to light illumination and conduct electricity under the action of the electric field. Finally, the electrons will enter the epitaxial layer and the channel layer from the substrate layer, and finally enter the collector, realizing high current transmission.

[0053] As Figure 3 shown, when the device operates in the reverse cut-off state, when the gate voltage causes the channel to turn off and the light illumination is removed, the current cannot conduct due to the lack of a conduction path. At this time, the voltage across the collector and the emitter will be applied to the channel layer and the transparent insulating dielectric layer. Since there is no net charge in the insulating dielectric, the electric field distribution in the insulating dielectric presents a horizontal shape at this time. When the proportion of the insulating dielectric in the same-sized cell is large, the breakdown voltage of the device will also increase. This structure uses the carriers generated by light illumination to solve the problem that the semi-insulating substrate cannot conduct electricity, and the generated photo-generated carriers can solve the problem of fabricating high current devices and solve the problem of high on-resistance of traditional lateral devices. The transparent insulating dielectric can allow light to enter the semi-insulating substrate through the surface on the one hand, and can withstand high voltage during reverse blocking, playing the role of high voltage resistance.

[0054] In addition, when the wide-bandgap ultra-high voltage and high-current semiconductor device provided in this embodiment is turned on, the gate voltage needs to reach the threshold voltage and light illumination is required to generate a sufficient number of photo-generated carriers. By controlling the time difference between the turn-on and trigger of the two, the device can operate in multiple different modes. For example, when the gate bias voltage and the photon generation trigger circuit are turned on simultaneously, the device conducts forward. When the gate bias voltage or the photon generation trigger circuit is turned off, the device stops working. When the device is in a reverse bias state, the photon trigger circuit is turned on, which will cause a large number of carriers to be generated inside the semi-insulating substrate. The carriers will generate impact ionization under a high electric field strength, thereby generating a large current. At this time, the device is in a high electric field and high voltage state, so it will consume a large amount of electric power and generate heat. At this time, it is necessary to control the turn-on time of the photon generation circuit to form a pulse switch, and the current in the device forms a pulse current.

[0055] In summary, the present invention constructs a wide-bandgap ultra-high voltage and high-current device by combining a lateral device structure with photo-generated carriers. The lateral device structure can easily etch the channel layer and the epitaxial layer clean and use a dielectric filling method to realize the fabrication of high-voltage devices. The mechanism of the high-current device is that photo-generated carriers are generated by irradiating light through a reserved light illumination channel to participate in conduction.

[0056] Embodiment 2 Based on the above embodiment, the difference in this embodiment is that as Figure 12 shown, the substrate layer is SiC, the epitaxial layer is unintentionally doped GaN, the channel layer is an N-type GaN layer, and the P-type semiconductor layer forms a heterojunction PN junction with the N-type GaN layer 5; the N-type semiconductor layer 5 is N++GaN, with a thickness exceeding the channel layer and the epitaxial layer and extending into the substrate layer.

[0057] This embodiment also has the beneficial effects brought by Embodiment 1. Therefore, the beneficial effects of the structure provided in this embodiment will not be elaborated here.

[0058] Embodiment 3 To facilitate the understanding of the wide-bandgap ultra-high voltage and high-current semiconductor device structure provided in Embodiment 1, as Figures 13 to 20 shown, this embodiment correspondingly provides its manufacturing method: Step S1 ( Figure 13 shown): Epitaxially grow an epitaxial layer on the substrate layer, and grow an N-type Ga2O3 layer on the epitaxial layer as the channel layer; embed a P-type semiconductor layer on the channel layer to form a heterojunction PN junction with the N-type Ga2O3 layer.

[0059] Specifically, an unintentionally doped gallium oxide epitaxial layer with a thickness of about 100 - 300 nm is epitaxially grown on a semi-insulating Ga2O3 substrate layer, and the resistivity of the semi-insulating substrate > , with a thickness of 300 - 600 um; the concentration of the unintentionally doped gallium oxide epitaxial layer is less than 10 16 cm -3 ; grow a high-concentration channel layer with a thickness of about 100 - 300 nm on the unintentionally doped gallium oxide epitaxial layer, and the doping concentration is 1.0x10 18 - 1.0x10 19 cm -3 ; embed a layer of P-GaN or other p-type semiconductors on the Ga2O3 channel layer to form a heterojunction PN junction with the N-Ga2O3 channel layer. The doping concentration of P-GaN is 5.0x10 18 - 5.0x10 19 cm -3 , and the doping concentration should be greater than that of the Ga2O3 channel layer.

[0060] Step S2 ( Figure 14 as shown): form an n-type semiconductor layer opposite to the p-type semiconductor layer in the heterojunction PN junction on one side.

[0061] Specifically, form an n-type semiconductor opposite to P-GaN in the heterojunction PN junction on one side. The n-type semiconductor can be homogeneous or heterogeneous with P-GaN; the n-type semiconductor needs to be within the package of the p-type semiconductor, and the range of the n-type semiconductor along the channel direction cannot exceed the p-type semiconductor.

[0062] Step S3 ( Figure 15 as shown): grow a gate dielectric layer on the surface, and at the same time, open holes in the p-type semiconductor region, and the gate dielectric completely covers the gap between the n-type semiconductor layer and the p-type semiconductor layer.

[0063] Specifically, grow a 10 - 100 nm thick Al2O3 as the gate dielectric on the surface of the formed structure, and at the same time, open holes in the previous p-type semiconductor region, and the remaining Al2O3 needs to completely cover the gap between the n-type semiconductor and the p-type semiconductor.

[0064] Step S4 ( Figure 16 as shown): deposit a layer of Ti metal on the surface as an ohmic contact electrode and a gate electrode, and perform annealing treatment.

[0065] Specifically, deposit a layer of 10 - 100 nm thick Ti metal on the surface of the formed structure as an ohmic contact electrode and a gate electrode, and anneal in an N2 atmosphere at 470 °C.

[0066] Step S5 ( Figure 17 as shown): grow an insulating dielectric on the surface as an interlayer dielectric layer, and at the same time, open holes at the position of the ohmic contact electrode to expose the electrode.

[0067] Specifically, a 100 - 1000 nm insulating dielectric layer is grown on the surface of the formed structure as the interlayer dielectric between the gate electrode and the emitter electrode. Meanwhile, holes are opened at the positions of the previous ohmic contact electrodes to expose the electrodes.

[0068] Among them, the interlayer dielectric layer can be Al2O3, SiO2, Si3N4, or their stacked dielectrics.

[0069] Step S6 ( Figure 18 as shown): Deposit a Ti / Al stacked metal layer on the surface as the first and second electrodes of the device.

[0070] Specifically, deposit a 1000 - 5000 nm Ti / Al stacked metal layer on the surface of the formed structure as the emitter electrode and the collector electrode of the device.

[0071] Step S7 ( Figure 19 as shown): Selectively etch the interlayer dielectric layer, the gate dielectric layer, the channel layer, and the epitaxial layer on the surface to obtain a groove structure.

[0072] Specifically, selectively etch the interlayer dielectric, the gate dielectric, the channel layer, and the epitaxial layer on the surface of the formed structure to block the current conduction path, and the etching depth should exceed the epitaxial layer.

[0073] S8 ( Figure 20 as shown): Fill the groove structure with a transparent insulating dielectric to obtain a current gain window, and that's it.

[0074] Specifically, the requirements for the transparent insulating dielectric are that it has low light absorption and needs to fill the groove completely.

[0075] The beneficial effects of this embodiment of the manufacturing method are the same as those of the wide - bandgap ultra - high - voltage and high - current semiconductor device structure provided in Embodiment 1, and will not be elaborated here.

[0076] In summary, the gallium - oxide - based ultra - high - voltage and high - current device structure proposed by the present invention perfectly solves the problems of low breakdown voltage of silicon - based devices and short photon transmission distance in semiconductor materials. Through the additional optical control unit, the working state of the gallium - oxide device can be conveniently changed, solving the problem of high on - resistance caused by the lack of P - type doping in gallium - oxide devices. At the same time, by utilizing the ultra - wide bandgap characteristic of gallium oxide, an ultra - high - voltage and high - current device is prepared.

[0077] In the description of this specification, the description with reference to terms such as "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present invention. In this specification, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A wide bandgap ultra-high voltage and high current semiconductor device structure, characterized in that, Comprising: A substrate layer; An epitaxial layer provided on the substrate layer; A channel layer, which is an N-type Ga2O3 layer or a GaN layer, provided on the epitaxial layer, and a P-type semiconductor layer is embedded therein. The P-type semiconductor layer and the channel layer form a PN junction; An N-type semiconductor layer is wrapped and provided inside the P-type semiconductor layer; A gate dielectric layer is grown on the channel layer and completely covers the gap between the N-type semiconductor layer and the P-type semiconductor layer; A gate electrode is deposited on the gate dielectric layer; An interlayer dielectric layer is grown on the channel layer; A groove is formed by etching from the upper surface of the interlayer dielectric layer down to the upper surface of the substrate layer. The groove is filled with a transparent insulator medium to construct a current gain window. Under the action of light, light passes through the current gain window to reach the substrate layer, and the substrate layer generates a large number of photogenerated carriers due to light illumination and conducts electricity under the action of an electric field; A first electrode and a second electrode are respectively provided on both sides of the superposition structure of the gate dielectric layer and the interlayer dielectric layer.

2. The wide-bandgap ultra-high voltage and high current semiconductor device structure according to claim 1, wherein The size of the N-type semiconductor layer in the channel direction is smaller than the size range of the P-type semiconductor, and there is a gap between the two.

3. The wide-bandgap ultra-high voltage and high-current semiconductor device structure according to claim 1, wherein The resistivity of the substrate layer is greater than , and the thickness is 300 - 600 μm; And / or, the epitaxial layer is an unintentionally doped epitaxial layer with a doping concentration less than 10 16 cm -3 , and has a thickness of 100 - 300 nm; And / or, the channel layer is a deliberately doped high-concentration epitaxial layer with a doping concentration of 1.0x10 18 -1.0x10 19 cm -3 , and the thickness is 100 - 300 nm.

4. The wide-bandgap ultra-high voltage and high-current semiconductor device structure according to claim 1, wherein The P-type semiconductor layer is any one of P-GaN, P-NiO, P-Cu2O, P-doped SiC, P-doped Si, and P-doped diamond.

5. The wide-bandgap ultra-high voltage and high current semiconductor device structure according to claim 4, characterized in that, When the P-type semiconductor layer is P-GaN, the doping concentration of P-GaN is 5.0x10 18 -5.0x10 19 cm -3 .

6. The wide-bandgap ultra-high voltage and high-current semiconductor device structure according to claim 1, wherein, Both the first electrode and the second electrode are ohmic contact electrodes with a thickness of 10 - 100 nm.

7. The wide bandgap ultra-high voltage and high current semiconductor device structure according to claim 6, characterized in that, The first electrode and the second electrode are respectively an emitter electrode and a collector electrode; Or, the first electrode and the second electrode are respectively a source electrode and a drain electrode; Or, the first electrode and the second electrode are respectively a cathode and an anode; Or, the first electrode and the second electrode are respectively an anode and a cathode.

8. The wide-bandgap ultra-high voltage and high-current semiconductor device structure according to claim 1, characterized in that, The cross-sectional shape of the current gain window is strip-shaped, square, circular, or hexagonal.

9. The wide-bandgap ultra-high voltage and high current semiconductor device structure according to claim 1, wherein The substrate layer and the epitaxial layer are respectively one or any combination of Ga2O3, AlN, BN, SiC, GaN, and diamond.

10. A manufacturing method for manufacturing a wide bandgap ultra-high voltage and high current semiconductor device structure as described in any one of claims 1 to 9, characterized in that, Including the following steps: S1: Epitaxially grow an epitaxial layer on the substrate layer, and grow an N-type Ga2O3 layer on the epitaxial layer as the channel layer; embed a P-type semiconductor layer in the channel layer to form a heterojunction PN junction with the N-type Ga2O3 layer; S2: Form an N-type semiconductor layer opposite to the P-type semiconductor layer in one of the heterojunction PN junctions; S3: Grow a gate dielectric layer on the surface, and at the same time open a hole in the P-type semiconductor region. The gate dielectric completely covers the gap between the N-type semiconductor layer and the P-type semiconductor layer; S4: Deposit a layer of Ti on the surface as an ohmic contact electrode and a gate electrode, and perform annealing treatment; S5: Grow an insulating dielectric on the surface as the interlayer dielectric layer, and at the same time open a hole at the position of the ohmic contact electrode to expose the electrode; S6: Deposit a Ti / Al laminated metal on the surface as the first electrode and the second electrode of the device; S7: Selectively etch the interlayer dielectric layer, the gate dielectric layer, the channel layer, and the epitaxial layer on the surface to obtain a groove structure; S8: Fill the groove structure with a transparent insulator medium to obtain a current gain window, thus obtaining the device.

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