Modulated mobile ion synapses

Abstract

A method of manufacturing a mobile ion conditioning device includes stacking a dielectric layer on a substrate. Moving ions are placed in the dielectric layer. An electrode layer is disposed on the dielectric layer. Moving ions are directed to a designated region of the dielectric layer.

Description

Background Art Technical Field

[0001] The present invention generally relates to memories in artificial intelligence (AI), and more specifically, to artificial synapses for performing weight updates in an AI network.

[0002] Description of the Related Art

[0003] Synapses in the human brain function using neurotransmitters consisting of positively moving ions such as Na+, K+, Ca+, H+. In fields such as artificial intelligence, the development of artificial synapses that operate based on actual human synapses (e.g., "biologically inspired" synapses) is a growing area of research.

[0004] In a neural network, after data is passed forward through the network, the weights associated with the neuron connections are adjusted. The update of the weights helps to reconcile the differences between the actual results and the predicted results of multiple forward passes. For the purpose of neuromorphic computing, artificial synapses are used to perform weight updates in a deep neural network. The evaluation of analog memories has been studied from the development of digital memories, such as phase change memory (PCM), resistive random access memory (RRAM), ferroelectric, floating gate, and electrochemical methods for Li+-based structures. However, symmetric updates are still challenging. For example, in semiconductors associated with AI, it is known that mobile ions in oxide or high dielectric constant (high-K) materials can cause severe instability problems in MOS capacitors, and after a specific stress (e.g., bias temperature stress (BTS)) test, mobile ions can be detected by flat band shift (DV fb ) Summary of the Invention

[0005] According to an embodiment, a computer-implemented method of manufacturing a mobile ion regulation device includes stacking one or more layers of a dielectric layer on a substrate. Mobile ions are provided in the dielectric layer. An electrode layer is disposed on the dielectric layer. The mobile ions are guided to a specified region of the dielectric layer. Arranging the mobile ions into the specified region of the dielectric layer allows for multi-level states for analog computing, and an analog synapse that can be used, for example, in a neural network. A faster and more efficient form of AI can be obtained.

[0006] In an embodiment that can be combined with the previous embodiment, the method includes forming a 3-terminal device from the mobile ion regulation device by patterning the electrode layer into one or more gates; and forming a source and a drain on the substrate. Such a 3-terminal FET can be used to regulate mobile ions and allow for symmetric updates. Symmetric diffusion can be provided to mimic a biologically plausible synapse, which can be beneficial for AI, especially in fields such as neural networks.

[0007] In one embodiment that can be combined with the previous embodiments, driving the mobile ions includes biasing the dielectric layer with a voltage. The applied voltage can direct the mobile ions to the alignment region, which overcomes the instability problem in the MOS capacitor.

[0008] In one embodiment that can be combined with the previous embodiments, the method includes providing multiple states of a 3-terminal device for analog computing by driving mobile ions to different positions in a dielectric layer. The different positions can represent different states of a more accurate neural network with increased operating speed.

[0009] In one embodiment that can be combined with the previous embodiments, the method includes providing multiple gate stacks on a substrate, the multiple gate stacks including multiple superlattice high-K (HK) stacks, and confining multilayer mobile ions. The multiple gate stacks provide a way to confine the mobile ions for more precise control and positioning.

[0010] In one embodiment, which can be combined with the previous embodiments, the method includes providing multiple gate stacks on a substrate, the multiple gate stacks including superlattice materials selected from the group consisting of replacement HK layers such as HfSiO4, HfO2, HfSiO4, HfO2, HfSiO4, HfO2, or HfSiO4. Alternatively, Hf in the HK stack can be replaced by Zr, Al, Y). The superlattice structures with different band structures improve the regulation of mobile ions.

[0011] In one embodiment that can be combined with the previous embodiments, the method includes providing multiple gate stacks, the multiple gate stacks including multiple bandgaps constructed of dielectric materials arranged alternately. The multiple bandgaps of the respective layers allow for more precise regulation of mobile ions.

[0012] In one embodiment that can be combined with the previous embodiments, the method includes performing symmetric set and reset operations by driving the same number of mobile ions in the dielectric layer in a first direction for setting an operation and in a second direction opposite to the first direction in a reset operation. Driving the mobile ions for set and reset operations increases the accuracy and speed of the 3-terminal structure and allows it to be used as an analog synapse in a neural network.

[0013] In one embodiment that can be combined with the previous embodiments, driving the mobile ions includes heating the dielectric layer. Heating the dielectric layer can increase the accuracy of the applied voltage bias or can be used without voltage to arrange the mobile ions.

[0014] In one embodiment that can be combined with the previous embodiments, driving the mobile ions includes heating the dielectric layer before or during the biasing of the electrode layer. Heating the dielectric layer in combination with the applied voltage bias makes the arrangement of mobile ions more precise and faster.

[0015] In one embodiment that can be combined with the previous embodiments, the method includes tuning the conductance in adjacent channel layers by re-applying at least one of a voltage bias or heating of the dielectric layer. This tuning provides a more precise arrangement of mobile ions.

[0016] According to one embodiment, a method of manufacturing a mobile ion regulating device includes growing a thermoelectric dielectric layer on a substrate. An embedded gate is defined in the thermoelectric dielectric layer by metallization reactive ion etching. An additional thermoelectric dielectric layer is added on the thermoelectric dielectric layer and chemical mechanical polishing (CMP) is performed. A high dielectric constant material is deposited on the thermoelectric dielectric layer and mobile ions are placed in the high dielectric constant material. A channel material is deposited on the high-k material and source and drain (S / D) contacts are defined on the channel material. The embedded gate is an alternative structure to a top gate and manufacturing is enhanced due to the use of CMOS-comparable metallization in the structure of a 3-terminal FET.

[0017] In one embodiment that can be combined with the previous embodiments, the channel material in the deposition operation of the high-k material is selected from the group consisting of an organic semiconductor, an oxide semiconductor, or a carbon nanotube. This structure allows for advanced technology nodes.

[0018] In one embodiment that can be combined with the previous embodiments, the deposition of the high-k material is arranged to form alternating layers of high-k materials having different bandgaps, and mobile ions are placed in more than one of the alternating layers of the high-k material. A more precise arrangement of mobile ions is obtained.

[0019] In one embodiment, which can be combined with the previous embodiments, the multiple gate stacks on the substrate include a superlattice material selected from the group consisting of HfSiO4, HfO2, HfSiO4, HfO2, HfSiO4, HfO2, or HfSiO4. The above materials contribute to the ability to symmetrically update and mimic biologically plausible synapses after ion diffusion.

[0020] According to one embodiment, a mobile ion regulating device includes a 3-terminal FET device structure that includes a gate stack filled with mobile ions. The gate stack includes multiple material layers arranged to confine the mobile ions. A source, a drain, and a gate are disposed on a substrate. A voltage bias is provided between at least one of the gate and the source, or between the source and the drain. Arranging the mobile ions into a specified region of the dielectric layer allows for multi-level states for analog computing, and for example, analog synapses that can be used in a neural network. A faster and more efficient form of AI can be obtained.

[0021] In one embodiment, which can be combined with the previous embodiments, the gate includes a top gate disposed above the substrate. The gate material of the gate stack includes a dielectric material layer. The gate stack confines mobile ions within the dielectric material layer. A voltage bias is configured to control the arrangement of the mobile ions within the layer. The applied voltage can direct the mobile ions to an alignment region, which overcomes the instability problem in the MOS capacitor.

[0022] In one embodiment, which can be combined with the previous embodiments, the gate is an embedded gate within a dielectric layer disposed on the substrate. The gate material of the gate stack is a high-k superlattice layer. A voltage bias is configured to control the arrangement of the mobile ions within the high-k superlattice material layer. The high-k superlattice material contributes to the ability to symmetrically update and mimic biologically plausible synapses after ion diffusion.

[0023] In one embodiment, which can be combined with the previous embodiments, the high-K superlattice material is selected from the group consisting of HfSiO4, HfO2, HfSiO4, HfO2, HfSiO4, HfO2, or HfSiO4. The above materials are particularly suitable for superlattice materials.

[0024] In one embodiment, which can be combined with the previous embodiments, a 3-terminal FET structure is configured to simulate a synapse, including a voltage bias configured to provide a resting state, an inhibitory state, an enhancing state, and a read state negative based on the respective arrangement of at least mobile ions within the 3-terminal FET device. The various states allow for use as an analog synapse in a neural network.

[0025] These and other features will become apparent from the following detailed description of the exemplary embodiments of the invention when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings are exemplary embodiments. They do not show all embodiments. In addition or as an alternative, other embodiments may be used. Details that may be apparent or unnecessary may be omitted to save space or for more effective illustration. Some embodiments may be implemented with additional components or steps and / or without all of the components or steps shown. When the same numeral appears in different drawings, it refers to the same or similar components or steps.

[0027] Figure 1A is a diagram of a 3-terminal device including a gate stack filled with mobile ions that is consistent with an exemplary embodiment.

[0028] Figure 1B is a diagram of a 3-terminal device structure having an embedded gate and a mobile ion gate stack that is consistent with an exemplary embodiment.

[0029] Figure 2 illustrates, consistent with an exemplary embodiment, such asFigure 1A and 1B Adjustment of mobile ions in a high-k stack in the 3-terminal device shown.

[0030] Figure 3 Illustrated is the operation of an analog synapse using a 3-terminal device including a gate stack with adjusted mobile ion fill in accordance with an exemplary embodiment.

[0031] Figure 4 Shown is a process flow of a stacked gate device having a mobile ion adjustment step in accordance with an exemplary embodiment.

[0032] Figure 5 Shown is a process flow of an embedded gate device having a mobile ion adjustment step in accordance with an exemplary embodiment.

[0033] Figure 6A Shown is a first part of a process flow of an embedded gate device having a high-K stack in accordance with an exemplary embodiment.

[0034] Figure 6B Shown is for an embedded gate device having a high-K stack in accordance with an exemplary embodiment Figure 6A continuation of the process flow shown.

[0035] Figure 7 is a flowchart showing the operation of a device having mobile ion adjustment in accordance with an exemplary embodiment. Detailed Description

[0036] Overview

[0037] In the following detailed description, numerous specific details are set forth by way of examples in order to provide a thorough understanding of the relevant teachings. However, it should be understood that the teachings may be practiced without these details. In other instances, well-known methods, procedures, components, and / or circuits have been described at a relatively high level without detail in order to avoid unnecessarily obscuring aspects of the teachings. It should be understood that the present disclosure is not limited to the depictions in the drawings as there may be fewer or more elements than shown and described.

[0038] Efforts have been made to remove impure mobile ions through process optimization. However, according to the present disclosure, impure mobile ions can be regulated and used in a constrained and controllable manner, which is advantageous for synaptic applications in AI.

[0039] As used herein, the term "dielectric" should be interpreted broadly and may include oxide materials such as SiO2, HfO2, ZrO2, HfSiO, and HfZrO, as well as non-oxide materials such as SiN and AlN.

[0040] Figure 1AFIG. 100A is a diagram of a three-terminal device 101 including a mobile-ion-filled gate stack 125 in accordance with an exemplary embodiment. Figure 1A The three-terminal device in Figure 1A is a FET, but it should be understood that the present invention is not limited to modulating mobile ions on a FET. The three-terminal device 101 includes a drain 105, a gate 110, and a source 115. The drain 105 and the source 115 are disposed on a substrate 120. The drain 105 and the source 115 may include a drain, an embedded source and drain, or a top source and drain with a deposited transfer channel.

[0041] Figure 1A The gate 110 shown in Figure 1A is a top gate, but as shown in Figure 1B , an embedded gate EG 130 may be used. The gate 110 may be disposed on one or more gate stacks 125 including a layer of a dielectric material (e.g., SiO2, SiN, HK, or a high-K superlattice stack (e.g., HfSiO4, HfO2, HfSiO4, HfO2, HfSiO4, HfO2, HfSiO4)). Figure 1B

[0042] The substrate 120 may be made of Si, but the present disclosure is not limited to Si. For example, the substrate may be made of any suitable substrate material, such as single-crystalline Si, silicon germanium (SiGe), aluminum gallium arsenide (AlGaAs), AlGaN, AlAs, AlIAs, AlN, GaSb, GaAlSb, GaAs, GaAsSb, GaN, InSb, InAs, InGaAs, InGaAsP, InGaN, InN, InP, and alloy combinations.

[0043] According to the present disclosure, a three-terminal device and a manufacturing method having a regulated mobile ion synapse advantageously provide improved performance. For example, the operation of a three-terminal FET is improved, and the hardware for AI applications is also improved. Using regulated mobile ions in an AI network (e.g., a neural network) provides the advantage of symmetric updates due to the symmetric diffusion mechanism. In addition, the three-terminal device provides the feasibility of mimicking biologically plausible synapses after ion diffusion in a semiconductor. The neural network can be implemented in a power-saving and computationally less burdensome manner for more precise operation at a faster speed.

[0044] Additional advantages of the devices of the present disclosure are disclosed herein.

[0045] Example of a three-terminal device having regulated mobile ions

[0046] Figure 1B Figure 1A FIG. 100B is a diagram of a three-terminal device 201 having an embedded gate and a mobile-ion gate stack in accordance with an exemplary embodiment. The device 201 includes a substrate 120, which may be Si or as described with respect to Figure 1A Figure 1AThe structure of another material disclosed for the substrate shown. The drain 105 and the source 115 are arranged on the channel 127. On top of the substrate 120, there is a layer 128 which can be composed of SiO2. An embedded gate (EG 130) in the layer 128 is shown. The EG 130 can be formed by CMOS comparable metallization and reactive ion etching (RIE), followed by depositing more oxides and chemical mechanical polishing (CMP). A plurality of gate stacks 125 are arranged above the EG 130. The gate stacks confine mobile ions (identified by plus signs). There are multiple alternating bandgaps, including a bandgap 126 alternating with the bandgap including the gate stacks 125, and a heterostructure is formed. The heterostructure enhances the confinement of mobile ions in a more ordered arrangement. The channel 129 is optional and is used to isolate materials by utilizing an HK stack to separate two heterostructures for the scalability purpose of forming a high-density synaptic array.

[0047] The channel 127 can be formed by depositing a semiconductor material or transferring a channel material (e.g., oxides / organic semiconductors, carbon nanotubes, 2D materials, etc. for advanced technology nodes).

[0048] Figure 2 Shown in 200 are such as Figure 1A and 1B the regulation of mobile ions in a high-k stack in the 3-terminal device shown in. Here, there can be a high-K superlattice serving as a gate stack or a dielectric material layer. Figure 2 The gate stack type component 101 with a top gate and the gate stack type component 201 with an embedded gate shown in have been referred to Figure 1A with 1B and shown and described. Figure 2 The possible energy band structure of a high-k superlattice for regulating mobile ions is shown. Mobile ions (shown by + signs) located in a narrow bandgap dielectric have been regulated.

[0049] The gate stack can be a superlattice composed of HfSiO4, HfO2, HfSiO4, HfO2, / HfSiO4, HfO2, HfSiO4, and only some non-limiting possible examples are given here.

[0050] Figure 3Illustrated are operations 300A - 300D of an analog synapse using a 3 - terminal device including a gate stack with regulated mobile ion filling, consistent with an exemplary embodiment. Example (a) shows a 3 - terminal device with regulated mobile ions in a resting state. Shown are mobile ions identified by a plus sign and an electronic device (identified by a minus sign) in a relatively aligned state. Example (b) shows a negative gate pulse (e.g., inhibitory) being applied to the device. There is some movement of electrons and mobile ions away from the aligned rows as shown, for example, in example (a). Example (c) shows a positive gate pulse (enhancing) being applied. Compared to example (b), an inversion of the positions of the mobile ion and electron pair directly under the gate is shown in example (c). In example (d), a read pulse is applied between the source and the drain. A negative pulse can supply electrons to attract positive mobile ions, leaving negative charges or electrons to pair with holes in the channel, which is called inhibition. Subsequently, a positive pulse provides holes to recombine with the electrons and release mobile ions to pair with electrons near the channel, which is called enhancement. The charge transferred during inhibition and enhancement can be detected from the read current in the channel between the source and the drain. Note that the analog synapse can be used with different structures (e.g., Figure 1B embedded gates in Figure 2 and incorporated with the options shown in

[0051] Example process flow

[0052] Figure 4 Illustrated is a process flow of a stacked - gate device with a mobile - ion regulation step, according to an exemplary embodiment. For simplicity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Additionally, the various tasks and process steps described herein may be incorporated into more comprehensive procedures or processes having additional steps or functionality not described in detail herein. In particular, various steps in the fabrication of semiconductor devices and semiconductor - based ICs are well known, and thus, for simplicity, many conventional steps will only be briefly mentioned herein or will be completely omitted without providing well - known process details.

[0053] The fabrication of the devices discussed herein may include, for example, a multi - step sequence of lithographic and / or chemical processing steps that facilitate the gradual creation of electron - based systems, devices, components, and / or circuits in semiconductor and / or superconducting devices (e.g., integrated circuits). For example, Figure 4The device can be fabricated on one or more substrates (e.g., silicon (Si) substrate and / or another substrate) by techniques including but not limited to the following techniques: lithography, microlithography, nanolithography, nanoimprint lithography, photomasking techniques, patterning techniques, photoresist techniques (e.g., positive photoresist, negative photoresist, hybrid color photoresist, and / or another photoresist technique), etching techniques (e.g., reactive ion etching (RIE), dry etching, wet etching, ion beam etching, plasma etching, laser ablation, and / or another etching technique), evaporation techniques, sputtering techniques, plasma ashing techniques, heat treatment (e.g., rapid thermal annealing, furnace annealing, thermal oxidation, and / or another heat treatment), chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), electrochemical deposition (ECD), chemical mechanical planarization (ALD), backgrinding techniques, and / or another technique for manufacturing integrated circuits.

[0054] The process flow shown begins with a substrate that can be made of Si (other materials can be used). A dielectric 405 is grown or deposited on the SI wafer (e.g., substrate 120), or a high-K material is disposed. If mobile ions 123 are not incorporated with the growth / deposition of the dielectric (or high-K) on the substrate 120, such mobile ions are introduced into the dielectric 405. A top conductive electrode 410 is deposited on the dielectric layer 405. Optionally, a voltage bias (shown as V+ / -) can be applied to the top electrode 410 and / or heated to drive the mobile ions 123 to the bottom or top interface. GND is connected to the substrate 120, especially when a bias is applied to the top electrode 410. The top electrode 140 can be patterned into a gate contact 110 for each transistor on the substrate 120. Finally, the source / drain (S / D) formation is completed to finish this structure. Spacers (e.g., SiO2 / SiN stack) can be included, and the process flow is completed.

[0055] Figure 5 The process flow of an embedded gate device with a mobile ion adjustment step according to an exemplary embodiment is shown. Figure 5 The process flow in Figure 4 is somewhat different because the gate is embedded. A thermodielectric 405 can be grown on the substrate 120. In a non-limiting example, the substrate 120 used can be Si, and the dielectric used can be SiO2. The embedded gate 130 can be defined by metallization and reactive ion etching (RIE), followed by deposition of more dielectric and chemical mechanical polishing (CMP). A high-K material 510 or another dielectric is grown on the Si substrate 120. Mobile ions 123 can be incorporated into the dielectric 510 simultaneously, or provided in a separate operation.

[0056] Still referring toFigure 5 , the channel material 127 can be deposited or transferred onto the dielectric layer 510. The channel material can include dielectric / organic semiconductor materials, carbon nanotubes, 2D materials, etc. Then, source 105 and drain 105 (S / D) contacts are defined on the channel material 127. A passivation scheme can be employed to define the source and drain on the channel material.

[0057] Figure 6A The first part of a process flow for an embedded gate device with a high-K stack according to an exemplary embodiment is shown. A thermal oxide, shown as SiO2 on the substrate 120. It should be understood that the present disclosure is not limited to SiO2 as the dielectric, and the substrate 120 is not limited to Si. The embedded gate (EG) is defined by performing metallization and RIE, then depositing more oxide and performing a CMP operation. Another oxide or high-K material is grown / deposited on the Si substrate 120, and mobile ions 123 can be incorporated simultaneously or in subsequent operations.

[0058] Figure 6B The continuation of the process flow for an embedded gate device with a high-K stack according to an exemplary embodiment is shown. Figure 6A is shown. Figure 6A Two process flows for growing / depositing a dielectric or high-K on a Si wafer, including or subsequently introducing mobile ions, are repeated with alternating high-K layers having different bandgaps. The next operation includes depositing or transferring the channel material 127 (e.g., oxide / organic semiconductor carbon nanotubes, 2D materials, etc.). Source 105 and drain 105 (S / D) contacts are defined. A passivation scheme can be applied.

[0059] Example method

[0060] From the foregoing overview of the example architecture, it may be helpful to now consider a high-level discussion of the example process. To that end, Figure 7 is a flowchart showing the operation of a device with mobile ion regulation consistent with an exemplary embodiment.

[0061] Figure 7 is shown as a collection of boxes in a logical order, which represents a sequence of operations that can be implemented in hardware, software, or a combination thereof. In the context of software, these boxes represent computer-executable instructions that, when executed by one or more processors, perform the recited operations. Generally, computer-executable instructions can include routines, programs, objects, components, data structures, etc. that perform functions or implement abstract data types. In each process, the order of the described operations is not intended to be construed as a limitation, and any number of the described boxes can be combined and / or executed in any order in parallel to implement the process.

[0062] In operation 702, a dielectric layer is stacked on the substrate. For example, referring toFigure 1A The dielectric layer 128 can be an oxide on the substrate 120, such as a SiO2 layer. The substrate can be a silicon substrate. However, the present disclosure is not limited to SiO2 oxides and Si substrates.

[0063] In operation 704, mobile ions are placed within the dielectric layer. For example, referring to Figure 1A , a plurality of mobile ions 123 are arranged on the gate stack layer. Referring to Figure 4 , mobile ions 123 are arranged within the dielectric layer 405.

[0064] In operation 706, an electrode layer is disposed on the dielectric layer. Figure 4 A top electrode layer 410 disposed on the dielectric layer 405 is shown.

[0065] In operation 708, the mobile ions are driven to a specified region of the dielectric layer. Figure 4 A voltage bias V+ / - and a ground node are shown. When the voltage bias is applied, the scattering distribution of the mobile ions changes to the aligned rows of mobile ions shown. Different voltage levels and / or different polarities drive the mobile ions to different regions of the dielectric layer. Different positions can be used to construct analog synapses. The method can end after operation 708.

[0066] Conclusion

[0067] Descriptions of various embodiments of the present teachings have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are chosen to best explain the principles of the embodiments, the practical application, or improvements made to the technology found in the marketplace, or to enable other ordinary skilled artisans in the art to understand the embodiments disclosed herein.

[0068] Although the best mode and / or other examples have been described above, it should be understood that various modifications can be made therein, and the subject matter disclosed herein can be implemented in various forms and examples, and the teachings can be applied to many applications, only some of which are described herein. The appended claims are intended to claim any and all applications, modifications, and variations that fall within the true scope of the present teachings.

[0069] The components, operations, steps, features, purposes, benefits, and advantages discussed herein are merely exemplary. None of them, or the discussions associated with them, are intended to limit the scope of protection. Although various advantages have been discussed herein, it will be understood that not all embodiments must include all advantages. Unless otherwise specified, all measurements, values, ratings, positions, sizes, dimensions, and other specifications set forth in this specification, including the appended claims, are approximate and not exact. They are intended to have a reasonable range consistent with the functions associated with them and the conventions of the fields to which they pertain.

[0070] Numerous other embodiments are also contemplated. These embodiments include those having fewer, additional, and / or different components, steps, features, purposes, benefits, and advantages. These also include embodiments in which the components and / or steps are arranged and / or sequenced in different ways.

[0071] The flowcharts and diagrams in the accompanying drawings herein illustrate the possible architectures, functions, and operations according to various embodiments of the present disclosure.

[0072] Although the foregoing has been described in connection with exemplary embodiments, it should be understood that the term "exemplary" merely means as an example, and not the best or optimal. In addition to what has just been stated above, whether or not stated in the claims, what has been stated or illustrated is not intended or should not be construed as causing any component, step, feature, object, benefit, advantage, or equivalent to be dedicated to the public.

[0073] It should be understood that unless a specific meaning is otherwise set forth herein, the terms and expressions used herein have a common meaning consistent with these terms and expressions in their respective fields of inquiry and study. Relative terms such as first and second may be used only to distinguish one entity or action from another, and do not necessarily require or imply any such actual relationship or order between these entities or actions. The term "comprising," "including," or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that comprises a series of elements includes not only those elements but may also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "a" or "an" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0074] A summary of the present disclosure is provided to enable a reader to quickly ascertain the nature of the technical disclosure. It should be understood that it is not intended to be used to interpret or limit the scope or meaning of the claims. Additionally, in the foregoing detailed description, it can be seen that, for the sake of fluidity of the present disclosure, various features are grouped together in various embodiments. This method of disclosure should not be construed as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. On the contrary, as reflected by the appended claims, the subject matter of the present invention lies in less than all of the features of a single disclosed embodiment. Accordingly, the following claims are hereby incorporated into the detailed description, where each claim stands on its own as a separately claimed subject matter.

Claims

1. A method of manufacturing a mobile ion regulating device, the method comprising: Stacking a dielectric layer on a substrate; Providing mobile ions within the dielectric layer; Setting an electrode layer on the dielectric layer; And Driving the mobile ions to a designated area of the dielectric layer.

2. The method according to claim 1, further comprising: Forming a 3-terminal device from the mobile ion regulating device by patterning the electrode layer into one or more gates; And Forming a source and a drain on the substrate.

3. The method according to claim 2, wherein the driving of the mobile ions comprises: Biasing the oxide layer with a voltage.

4. The method according to claim 2 further includes: Providing multiple states of the 3-terminal device for analog computing by driving the mobile ions to different positions in the dielectric layer.

5. The method according to claim 2 further comprises: Providing a plurality of gate stacks on the substrate, the plurality of gate stacks including a plurality of superlattice high-k stacks and confining multilayer mobile ions.

6. The method according to claim 2 further comprises: Providing a plurality of gate stacks on the substrate, the plurality of gate stacks including a superlattice material selected from the group consisting of HfSiO4, HfO2, HfSiO4, HfO2, HfSiO4, HfO2, or HfSiO4.

7. The method according to claim 2 further comprises: Providing a plurality of gate stacks, the plurality of gate stacks including a plurality of bandgaps constructed from dielectric materials arranged alternately.

8. The method according to claim 2 further comprises: Performing symmetric set and reset operations by driving the same number of mobile ions in the dielectric layer in a first direction for a set operation and in a second direction opposite to the first direction in a reset operation.

9. The method according to claim 1, wherein driving the mobile ions comprises: Heating the dielectric layer.

10. The method according to claim 1, wherein driving the mobile ions comprises: Heating the dielectric layer before or during the biasing of the electrode layer.

11. The method according to claim 10 further comprises: Adjusting the conductance in adjacent channel layers by reapplying at least one of the biasing or heating of the dielectric layer.

12. A method of manufacturing a mobile ion regulating device, the method comprising: Growing a thermoelectric dielectric layer on a substrate; Defining an embedded gate in the thermoelectric dielectric layer by metallization reactive ion etching; Adding additional thermoelectric dielectric on the thermoelectric dielectric layer and performing chemical mechanical polishing (CMP); Depositing a high-k material on the thermoelectric dielectric layer and placing mobile ions in the high-k material; Depositing a channel material on the high-k material; And Defining source and drain (S / D) contacts on the channel material.

13. The method according to claim 12, wherein the channel material in the deposition operation of the high-k material is selected from the group consisting of an organic semiconductor, an oxide semiconductor, or a carbon nanotube.

14. The method according to claim 12, further comprising: Repeating the deposition of the high-k material to form alternating layers of high-k materials with different bandgaps, and placing mobile ions in more than one of the alternating layers of the high-k material.

15. The method according to claim 12 further comprises: Providing a plurality of gate stacks on the substrate, the plurality of gate stacks including a superlattice material selected from the group consisting of HfSiO4, HfO2, HfSiO4, HfO2, HfSiO4, HfO2, or HfSiO4.

16. A mobile ion regulating device, comprising: A 3-terminal FET device structure including a gate stack filled with mobile ions; The gate stack including a plurality of material layers arranged to confine the mobile ions; A source, a drain, and a gate disposed on a substrate; And A voltage bias is disposed between at least one of the gate and the source, or between the source and the drain.

17. The apparatus according to claim 16, wherein: The gate includes a top gate disposed above the substrate; The gate material of the gate stack includes a dielectric material layer; The gate stack confines the mobile ions within the dielectric material layer; And The voltage bias is configured to control the arrangement of the mobile ions within the layer.

18. The apparatus according to claim 16, wherein: The gate includes an embedded gate disposed within a dielectric layer on the substrate; The gate material of the gate stack includes a high-k superlattice layer; And The voltage bias is configured to control the arrangement of the mobile ions within the high-k superlattice material layer.

19. The apparatus according to claim 16, wherein the high-K superlattice material is selected from the group consisting of HfSiO4, HfO2, HfSiO4, HfO2, HfSiO4, HfO2, or HfSiO4.

20. The apparatus according to claim 16, wherein: The three-terminal FET structure is configured to simulate a synapse; and The voltage bias is configured to provide a resting state, an inhibitory state, an enhancing state, and a read state based at least on the respective arrangement of the mobile ions within the three-terminal FET device.

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