Self-adaptive slope compensation zero-cross detection circuit

Abstract

The invention provides a self-adaptive slope compensation zero-cross detection circuit, which comprises a sampling and holding module, an offset storage module, a comparator module, a sequential logic module and a common-mode offset module, the time sequence logic module is used for controlling a switch time sequence; the common-mode imbalance module is used for generating a common-mode level difference value; the sampling and holding module obtains sampling voltage of switch node voltage and converter output voltage during the closing period of an upper tube, receives the common-mode level difference value to serve as compensation voltage of the input end of the comparator module during the closing period of a lower tube, and outputs the sampling voltage compensated by the compensation voltage; the offset storage module stores the offset voltage during the closing period of the lower tube, and transmits the sampling voltage compensated by the compensation voltage to the comparator module after the closing of the upper tube, so as to eliminate the influence of the offset voltage. According to the zero-crossing detection circuit, the compensation voltage is added through the sampling and holding module, the influence of the offset voltage is eliminated, and an accurate current zero-crossing detection point can be obtained.

Description

Technical Field

[0001] The present invention relates to the field of power management, and particularly to a zero-crossing detection circuit with adaptive slope compensation, which is applicable to BOOST converters. Background Art

[0002] Traditional zero-crossing detection circuits mostly use fixed threshold methods to determine the zero-crossing points of signals. However, the performance of this method is limited when faced with complex and changing working environments. For example, in a Boost converter (i.e., a boost circuit), when the load changes suddenly or the input and output voltages fluctuate, the fixed detection threshold may cause inaccurate adjustment of the conduction time of the switching transistor, thereby affecting the overall efficiency and stability of the converter. In addition, due to the influence of factors such as temperature drift, it is difficult to maintain the optimal state of the fixed threshold setting for a long time.

[0003] To solve these problems, the adaptive slope compensation technology has emerged. The technology aims to adapt to the changes in the input signal by dynamically adjusting the delay parameters in the detection circuit, thereby improving the accuracy of zero-crossing detection. For example, in some implementations, by real-time monitoring the frequency and amplitude of the input signal, the system can automatically adjust the size of the time window for zero-crossing detection to ensure that even when the input conditions change, the zero-crossing moment can be accurately captured. Such a design not only helps to improve the working efficiency of the Boost converter but also enhances the anti-interference ability of the system.

[0004] However, the current adaptive slope compensation schemes still face some challenges. On the one hand, how to implement complex adaptive algorithms without affecting the detection speed to meet the requirements of high-speed converters; on the other hand, how to simplify the circuit structure, reduce the design cost, and maintain good detection performance are the difficulties in current research. Therefore, developing a new circuit that can provide reliable zero-crossing detection within a wide working range and has high integration and low cost is of great significance for promoting the progress of DC-DC Boost converter technology. Summary of the Invention

[0005] Based on this, the object of the present invention is to propose a zero-crossing detection circuit with adaptive slope compensation to achieve accurate detection of the zero-crossing point of inductor current under different inductor current slopes, comparator delays, and temperature changes.

[0006] To achieve the above object, the present invention provides a zero-crossing detection circuit with adaptive slope compensation, which is used for a BOOST converter. It is characterized in that it includes a sample-and-hold module, an offset storage module, and a comparator module connected in sequence, and a timing logic module and a common-mode offset module both connected to the sample-and-hold module and the offset storage module; the timing logic module is used to control the switching timing of the sample-and-hold module, the offset storage module, and the comparator module; the common-mode offset module is used to generate a common-mode level difference; the sample-and-hold module is configured to: charge and discharge a capacitor through switching to obtain a sampled voltage of the switch node voltage and the converter output voltage during the on-time of the upper switch, and receive the common-mode level difference as a compensation voltage at the input end of the comparator module during the on-time of the lower switch, and output the sampled voltage compensated by the compensation voltage; the offset storage module is configured to store the offset voltage of the comparator module during the on-time of the lower switch, transfer the sampled voltage compensated by the compensation voltage to the comparator module after the upper switch is turned on, and eliminate the influence of the offset voltage on the input signal and the output zero-crossing signal of the comparator module during the transfer process.

[0007] The common-mode offset module is used to generate a first common-mode level and a second common-mode level, and the first common-mode level and the second common-mode level form the common-mode level difference; the first common-mode level is connected to both the sample-and-hold module and the offset storage module, and the second common-mode level is only connected to the sample-and-hold module.

[0008] The offset storage module has a first type of switch connected to the output end of the sample-and-hold module, and the timing logic module controls the switch of the first type of switch of the offset storage module connected to the output end of the sample-and-hold module to avoid mutual influence between the sample-and-hold module and the offset storage module when obtaining the first common-mode level and the second common-mode level.

[0009] The value of the compensation voltage satisfies K×R on ×t del where R on is the on-resistance of the upper switch of the BOOST converter, K is the slope of the inductor current decrease, and t del is the delay of the comparator module.

[0010] The common-mode offset module includes a first resistor, a second resistor, and a third resistor. One ends of the first resistor, the second resistor, and the third resistor are connected together to serve as the output end of the first common-mode level. The other end of the first resistor is connected to the power supply voltage. The other end of the second resistor is connected to the compensation current and serves as the output end of the second common-mode level. The other end of the third resistor is grounded, and the resistance values of the first resistor and the second resistor are the same; and the compensation current is proportional to the difference between the power supply voltage and the ground voltage.

[0011] The resistance value R” of the third resistor of the common-mode offset module is:

[0012]

[0013] Among them, K1 is the compensation current coefficient, L is the inductance, and R on is the on-resistance of the upper switch of the BOOST converter, and t del is the delay of the comparator module.

[0014] The sampling and holding module includes a first capacitor and a second capacitor; the first side of the first capacitor is connected to the converter output voltage through a parallel connection of a first type of switch and a second type of switch, the second side is the inverting output terminal of the sampling and holding module and is connected to the second common-mode level through a third type of switch; the first side of the second capacitor is connected to the converter output voltage through the second type of switch and is connected to the switch node voltage through a switch node detection condition switch and the first type of switch, the second side is the non-inverting output terminal of the sampling and holding module and is connected to the first common-mode level through a third type of switch.

[0015] The offset storage module includes a first type of switch connected between the inverting output terminal of the sampling and holding module and the inverting input terminal of the comparator module, a first type of switch connected between the non-inverting output terminal of the sampling and holding module and the non-inverting input terminal of the comparator module, a third type of switch connected between the inverting output terminal of the sampling and holding module and the first common-mode level, a third type of switch connected between the non-inverting output terminal of the sampling and holding module and the first common-mode level, a comparator third capacitor connected between the non-inverting output terminal of the pre-amplifying comparator of the comparator module and the non-inverting input terminal of the main comparator of the comparator module, a comparator fourth capacitor connected between the inverting output terminal of the pre-amplifying comparator of the comparator module and the inverting input terminal of the main comparator of the comparator module, a third type of switch connected between the first common-mode level and the non-inverting input terminal of the main comparator of the comparator module, and a third type of switch connected between the first common-mode level and the inverting input terminal of the main comparator of the comparator module.

[0016] The timing logic module is set to: when the lower switch is closed and the upper switch is open, the second type of switch and the third type of switch are closed, and the first type of switch is open; when the lower switch is open and the upper switch is closed, the first type of switch is closed, and the second type of switch and the third type of switch are open.

[0017] The comparator module is a high-speed and high-precision comparator.

[0018] The zero-crossing detection circuit is installed between the source and drain of the upper switch of a BOOST converter; the BOOST converter includes an inductor, an upper switch, and a low-side power transistor connected to the same switch node. Among them, the other node of the inductor is connected to the power supply voltage, the other node of the upper switch is connected to the converter output voltage, and the other node of the low-side power transistor is grounded. The upper switch and the low-side power transistor are connected to a logic and drive circuit.

[0019] Through reasonable timing control, the zero-crossing detection circuit with adaptive slope compensation of the present invention samples the SW voltage node of the BOOST converter by the front-stage sample-and-hold module while the offset of the post-stage comparator is stored. At this time, two different common-mode levels generated by the common-mode offset module are used to add an adaptive compensation voltage during the sampling stage, and the influence of the offset voltage is eliminated through the offset storage process, so as to obtain an accurate current zero-crossing detection point and accurately detect the zero-crossing point of the inductor current under different inductor current slopes, comparator delays and temperature changes. And the complex operations during the sampling stage will not affect the offset storage process of the post-stage comparator. The zero-crossing detection circuit with adaptive slope compensation of the present invention can obtain an accurate current zero-crossing detection point under different inductor current decreasing slopes and different comparator delays through the setting of the common-mode offset module. The comparator module can minimize the delay of the comparator and obtain the smallest delay change range and dispersion. Therefore, the proposed zero-crossing detection circuit with adaptive slope compensation can achieve a relatively accurate early zero-crossing point under process, temperature and voltage changes. Description of the Drawings

[0020] Figure 1 is the circuit diagram of the zero-crossing detection circuit with adaptive slope compensation of the present invention and the Boost converter to which it is applicable.

[0021] Figure 2 is the circuit structure diagram of a zero-crossing detection circuit with adaptive slope compensation according to an embodiment of the present invention.

[0022] Figure 3 is as Figure 2 shown, which is the circuit structure diagram of the sample-and-hold module and the offset storage module of a zero-crossing detection circuit with adaptive slope compensation, and a part of the comparator module is shown therein;

[0023] Figure 4 is as Figure 2 shown, which is the circuit diagram of the timing logic module of a zero-crossing detection circuit with adaptive slope compensation;

[0024] Figure 5 is as Figure 4 shown, which is the circuit diagram of the first low-to-high level shift circuit of the timing logic module;

[0025] Figure 6 is as Figure 4 shown, which is the circuit diagram of the first high-to-low level shift circuit of the timing logic module;

[0026] Figure 7 is as Figure 2 shown, which is the circuit diagram of the common-mode offset circuit of a zero-crossing detection circuit with adaptive slope compensation;

[0027] Figure 8 For a Figure 2 circuit diagram of a comparator module of a common-mode offset circuit of an adaptive slope compensation zero-crossing detection circuit as shown.

[0028] Reference numerals:

[0029] 1 timing logic module, 2 sample and hold module, 3 offset storage module, 4 common-mode offset circuit, 6 comparator module. Detailed implementation manners

[0030] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0032] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and is not limited by the embodiments set forth herein.

[0033] To make the above objects, features, and advantages of the present invention more obvious and understandable, the preferred embodiments are specifically given below and, in conjunction with the accompanying drawings, are described in detail as follows.

[0034] As Figure 1 shown, the zero-crossing detection circuit of the present invention is connected between the source and drain of the upper transistor UG of a BOOST converter to receive the switch node voltage VSW and the converter output voltage VBST respectively. Among them, the BOOST converter includes an inductor L, an upper transistor UG, and a low-side power transistor LG connected to the same switch node SW. Among them, the other node of the inductor L is connected to the power supply voltage VBAT, the other node of the upper transistor UG is connected to the converter output voltage VBST, and the other node of the low-side power transistor LG is grounded. The upper transistor UG and the low-side power transistor LG are connected to a logic and drive circuit D1. The converter output voltage VBST is grounded through a load RLOAD and through an output capacitor CL and an equivalent series resistance r esr to ground.

[0035] Please refer toFigures 2 to 5 As shown in the figure, the present invention provides a zero-crossing detection circuit with adaptive slope compensation. The circuit includes a sample and hold module 2, an offset storage module 3, and a comparator module 5 connected in sequence, as well as a timing logic module 1 and a common-mode offset module 4 both connected to the sample and hold module 2 and the offset storage module 3.

[0036] The timing logic module 1 is used to control the switching timing of the sample and hold module 2, the offset storage module 3, and the comparator module 5. In addition, it ensures that the sample and hold module 2 and the offset storage module 3 do not affect each other when obtaining the common-mode voltage from the common-mode offset module 4 by controlling the switching of the first type of switch S1 connected between the offset storage module 3 and the output terminal of the sample and hold module 2, so that the circuit of the present invention can form a compensation voltage for the sampling offset while storing the offset voltage V OS of the comparator.

[0037] The clock logic control module 1 is connected to at least one first type of switch S1, at least one second type of switch S2, and at least one third type of switch S3. It is configured to drive the second type of switch S2 and the third type of switch S3 to close and the first type of switch S1 to open in the first phase (when the lower transistor of the BOOST converter is closed and the upper transistor is open); in the second phase (i.e., when the lower transistor of the BOOST converter is open and the upper transistor is closed), it drives the first type of switch S1 to close and the second type of switch S2 and the third type of switch S3 to open.

[0038] As Figure 4 shown in the figure, the clock logic control module 1 includes a first high-to-low level shift circuit LS_HL1 for controlling the third type of switch S3, a first low-to-high level shift circuit LS_LH whose input terminal is connected to the gate signal of the third type of switch S3 and whose output terminal is connected to the fourth inverter inv4 and the fifth inverter inv5 in sequence to be connected to the gates of the second type of switch S2 and the first type of switch S1 respectively, and a second high-to-low level shift circuit LS_HL2 whose input terminal is connected to the gate signal of the first type of switch S1 and whose output terminal is connected to the gate of the fourth type of switch S4.

[0039] Among them, the input end of the first high-to-low level shift circuit LS_HL1 is connected to the CLK signal, and the output end is connected to the input of the first inverter inv1; the input and output of the first inverter inv1, the second inverter inv2, and the third inverter inv3 are connected end to end in sequence, and the output of the third inverter inv3 is connected to the gate of the third type of switch S3; the input end of the first low-to-high level shift circuit LS_LH is connected to the gate of the third type of switch S3, and the output end is connected to the input end of the fourth inverter inv4; the input end of the fourth inverter inv4 is connected to the output end of the first low-to-high level shift circuit LS_LH, and the output end is connected to the gate of the second type of switch S2 and the input end of the fifth inverter inv5; the input end of the fifth inverter inv5 is connected to the gate of the second type of switch S2 and the output end of the fourth inverter inv4, and the output end is connected to the gate of the first type of switch S1 and the input end of the second high-to-low level shift circuit LS_HL2; the input end of the second level shift circuit LS_HL2 is connected to the gate of the first type of switch S1 and the output end of the fifth inverter inv5, and the output end is connected to the gate of the fourth type of switch S4.

[0040] As Figure 5 shown, the first low-to-high level shift circuit LS_LH specifically includes a first group of PMOS transistors with a common source (connected to the internal power supply VDD), a first group of NMOS transistors with a drain connected to the drain of the first group of PMOS transistors and a source grounded, a second group of PMOS transistors with a common source (connected to the first voltage source VS), and a second group of NMOS transistors with a drain connected to the drain of the second group of PMOS transistors and a common source (connected to the second voltage source GS); the gate of each PMOS transistor in the first group of PMOS transistors is connected to the drain of another PMOS transistor; the gates of the two NMOS transistors in the first group of NMOS transistors are respectively connected to the double-inverted signal dina and the single-inverted signal dinb of the input signal din of the first low-to-high level shift circuit LS_LH, and the gates of each pair of PMOS transistors and NMOS transistors with their drains connected in the second group of PMOS transistors and the second group of NMOS transistors are commonly connected to the drains of another pair of PMOS transistors and NMOS transistors with their drains connected and the drain of one of the PMOS transistors in the first group of PMOS transistors, and the gates of one of the pairs of PMOS transistors and NMOS transistors with their drains connected in the second group of PMOS transistors and the second group of NMOS transistors are connected to the output signal dout of the first low-to-high level shift circuit LS_LH through an inverter. Since it is a low-to-high level shift circuit, the voltage of the first voltage source VS is greater than the voltage of the internal power supply VDD, and GS is a low-level power supply corresponding to the first voltage source VS.

[0041] The specific structure of the low-to-high level shift circuit (such as the first low-to-high level shift circuit LS_LH) is as Figure 5As shown, the structure of the high-to-low voltage level shifting circuit (such as the first high-to-low voltage level shifting circuit LS_HL1 and the second high-to-low voltage level shifting circuit LS_HL2) is as Figure 6 shown. As Figure 6 shown, taking the first high-to-low voltage level shifting circuit LS_HL1 as an example, the high-to-low voltage level shifting circuit specifically includes a third group of PMOS transistors with a common source (connected to the third voltage source VS1), a third group of NMOS transistors with a drain connected to the drain of the third group of PMOS transistors and a source grounded, a fourth group of PMOS transistors with a common source (connected to the fourth voltage source VS2), and a fourth group of NMOS transistors with a drain connected to the drain of the fourth group of PMOS transistors and a common source (grounded); the gates of the two PMOS transistors in the third group of PMOS transistors are respectively connected to the double-inverted signal dina and the single-inverted signal dinb of the input signal din of the first low-to-high voltage level shifting circuit LS_LH, and the gate of each NMOS transistor in the third group of NMOS transistors is connected to the drain of another NMOS transistor; the gates of each pair of PMOS transistors and NMOS transistors with their drains connected in the fourth group of PMOS transistors and the fourth group of NMOS transistors are commonly connected to the drains of another pair of PMOS transistors and NMOS transistors with their drains connected and the drain of one of the PMOS transistors in the first group of PMOS transistors, and the gates of one of the pairs of PMOS transistors and NMOS transistors with their drains connected in the second group of PMOS transistors and the second group of NMOS transistors are connected to the output signal dout of the first high-to-low voltage level shifting circuit LS_HL1 through an inverter. Since it is a high-to-low voltage level shifting circuit, the voltage of the third voltage source VS1 is greater than the voltage of the fourth voltage source VS2.

[0042] The common-mode offset module 4 is used to generate a first common-mode level V CM1 and a second common-mode level V CM2 , and during the sampling process, the common-mode level difference formed by the first common-mode level V CM1 and the second common-mode level V CM2 (i.e., V CM2 -V CM1 ) is used as the compensation voltage at the input end of the comparator module 5.

[0043] In this embodiment, the first common-mode level V CM1 is connected to both the sample-and-hold module 2 and the offset storage module 3, and the second common-mode level V CM2 is only connected to the sample-and-hold module 2. The common-mode offset module 4 is used to generate a first common-mode level V CM1 and a second common-mode level V CM2 , and the first common-mode level V CM1 and the second common-mode level V CM2The formed common-mode level difference is provided to the sample-and-hold module 2 as the compensation voltage at the input end of the comparator module 5, that is, the added compensation voltage is equal to the first common-mode level V CM1 - the second common-mode level V CM2 . The value of the compensation voltage satisfies K×R on ×t del , where R on is the on-resistance of the upper transistor UG of the BOOST converter, K is the slope of the inductor current drop, and t del is the delay of the comparator module 5.

[0044] As Figure 7 shown, the common-mode offset module 4 includes a first resistor R1, a second resistor R2, and a third resistor R3. One ends of the first resistor R1, the second resistor R2, and the third resistor R3 are connected together to serve as the output end of the first common-mode level V CM1 , the other end of the first resistor R1 is connected to the power supply voltage V BAT , the other end of the second resistor R2 is connected to the compensation current I COMP and serves as the output end of the second common-mode level V CM2 , the other end of the third resistor R3 is grounded, and the resistance values of the first resistor R1 and the second resistor R2 are the same.

[0045] As Figure 5 shown, the specific working principle of the common-mode offset module 4 is as follows:

[0046] The first common-mode level V CM1 and the second common-mode level V CM2 are:

[0047]

[0048] V CM2 =V CM1 +I COMP R”

[0049] where R’ is the resistance value of the first resistor R1 and the second resistor R2, R” is the resistance value of the third resistor, I COMP is the compensation current, V BAT is the power supply voltage, and V CM1 is the first common-mode level. Thus, the first common-mode level V CM1 and the second common-mode level V CM2 are obtained.

[0050] The compensation current is generated by an adaptive compensation current sampling module. The adaptive compensation current sampling module is used to output a compensation current I COMP to the comparator module 5 that is proportional to the difference between the converter output voltage VBST and the power supply voltage VBAT (i.e., VBST - VBAT)., to enter the common-mode offset module 4. There are various specific sampling methods for the adaptive compensation current sampling module, which are not described as the technical key points of the present invention.

[0051] In this embodiment, the compensation current I COMP is:

[0052] I COMP = K1(VBST - VBAT)

[0053] In the formula, K1 is the compensation current coefficient, VBST is the converter output voltage, and VBAT is the power supply voltage.

[0054] As Figure 3 shown, the sample and hold module 2 is set to: charge and discharge the capacitor through switch conversion to sample the switch node voltage VSW of the BOOST converter and the sampled voltage of the converter output voltage VBST during the closing of the upper switch, and receive the common-mode level difference sampled by the common-mode offset module 4 (i.e., the first common-mode level V CM1 and the second common-mode level V CM2 ) during the closing of the lower switch as the compensation voltage at the input end of the comparator module 5, and output the sampled voltage compensated by the compensation voltage (i.e., the voltage V + at the positive output end and the voltage V- at the negative output end of the sample and hold module 2) to the input end of the comparator module 5 for comparison.

[0055] Among them, the sample and hold module 2 includes a first capacitor C1 and a second capacitor C2. The first side of the first capacitor C1 is connected to the converter output voltage VBST through the parallel-connected first type of switch S1 and the second type of switch S2, and the second side is the negative output end of the sample and hold module 2 and is connected to the second common-mode level V CM2 through the third type of switch S3. The first side of the second capacitor C2 is connected to the converter output voltage VBST through the second type of switch S2 and is connected to the switch node voltage VSW through the switch node detection condition switch and the first type of switch S1, and the second side is the positive output end of the sample and hold module 2 and is connected to the first common-mode level V CM1 through the third type of switch S3. The control end of the switch node detection condition switch is connected to the closing signal of the upper switch UG, so that the switch node voltage VSW of the switch node SW is detected and provided to the second capacitor C2 only when the upper switch UG is closed.

[0056] The specific working principle of the sample and hold module 2 is as follows:

[0057] The first phase (i.e., the lower switch of the BOOST converter is closed and the upper switch is open): Through the drive of the timing logic module 1, the second type of switch S2 and the third type of switch S3 are closed, and the first type of switch S1 is open; Therefore, the electric charges Q1 and Q2 stored in the first capacitor C1 and the second capacitor C2 of the sample and hold module 2 are:

[0058] Q1 = (V BST1 - V CM2 )C1

[0059] Q2 = (V BST1 - V CM1 )C2

[0060] Wherein, Q1 and Q2 are the electric charges stored in the first capacitor C1 and the second capacitor C2 respectively, V BST1 is the output voltage of the converter when the lower switch is closed, V CM1 is the first common mode level, and V CM2 is the second common mode level.

[0061] The second phase (i.e., the lower switch of the BOOST converter is open and the upper switch is closed): Through the drive of the timing logic module 1, the first type of switch S1 is closed, and the second type of switch S2 and the third type of switch S3 are open; Therefore, the electric charges Q1 and Q2 stored in the first capacitor C1 and the second capacitor C2 of the sample and hold module 2 are:

[0062] Q1 = (V BST2 - V - )C1

[0063] Q2 = (V SW - V + )C2

[0064] Wherein, V BST2 is the output voltage of the converter when the upper switch is closed, and V SW is the switch node voltage when the upper switch is closed.

[0065] And, the switch node voltage V SW when the upper switch is closed is:

[0066] V SW = V BST2 + I L R ON

[0067] Wherein, I L is the inductor current, and R ON is the on-resistance of the upper switch UG of the BOOST converter.

[0068] According to the charge conservation, the voltage V + at the positive output terminal and the voltage V- at the negative output terminal of the sample and hold module 2 can be obtained:

[0069] V - = V BST2 -V BST1 +V CM2

[0070] V + = V BST2 -V BST1 +V CM1 +I L R ON

[0071] Thus, the comparison flip point of the comparator module 5 provided by the sample and hold module 2 is V + = V - , and from I L R ON = 0 it becomes I L R ON = V CM2 -V CM1 , which is equivalent to the compensation voltage being added to the input end of the comparator through the sample and hold module 2.

[0072] The offset storage module 3 is set to store the offset voltage V OS of the comparator module 5 during the closing of the lower transistor of the BOOST converter, and transfer the sampled voltage compensated by the compensation voltage (i.e., the voltage V + at the positive output end of the sample and hold module 2 and the voltage V- at the negative output end) to the comparator module 5 after the upper transistor is closed, and eliminate the offset voltage during the transfer process, that is, eliminate the influence of the offset voltage V OS on the input signal and the zero-crossing signal ZCD output of the comparator module 5.

[0073] The offset storage module 3 includes a first type of switch S1 connected between the negative output end of the sample and hold module 2 and the negative input end of the comparator module 5, a first type of switch S1 connected between the positive output end of the sample and hold module 2 and the positive input end of the comparator module 5, a third type of switch S3 connected between the negative output end of the sample and hold module 2 and the first common-mode level V CM1 , a third type of switch S3 connected between the positive output end of the sample and hold module 2 and the first common-mode level V CM1 , a comparator third capacitor C3 connected between the positive output end of the pre-amplification comparator of the comparator module 5 and the positive input end Vop of the main comparator of the comparator module, a comparator fourth capacitor C4 connected between the negative output end of the pre-amplification comparator of the comparator module 5 and the negative input end Von of the main comparator of the comparator module, and connected to the first common-mode level V CM1The third type of switch S3 between the positive-phase input terminal Vop of the main comparator of the comparator module, and the third type of switch S3 connected to the negative-phase input terminal Von of the main comparator of the comparator module. CM1 The third type of switch S3 between the negative-phase input terminal Von of the main comparator of the comparator module.

[0074] The specific working principle of the offset storage module 3 is as follows:

[0075] The first phase (i.e., the lower switch of the BOOST converter is closed and the upper switch is open): The third type of switch S3 is closed, and the first type of switch S1 is open; Therefore, the charge Q3 stored in the third capacitor C3 of the comparator of the offset storage module 3 and the charge Q4 stored in the fourth capacitor C4 of the comparator are:

[0076] Q3 = [(V CM1 - V OS )A - V CM1 C,

[0077] Q4 = [V CM1 A - V CM1 C,

[0078] In the formula, A is the amplification factor of the pre-amplification comparator of the comparator module, V CM1 is the first common-mode level, V OS is the offset voltage, and C is the capacitance value of the third capacitor and the fourth capacitor of the comparator.

[0079] The second phase (i.e., the lower switch of the BOOST converter is open and the upper switch is closed): The third type of switch S3 is open, and the first type of switch S1 is closed; Therefore, the charge Q3 stored in the third capacitor C3 of the comparator of the offset storage module 3 and the charge Q4 stored in the fourth capacitor C4 are:

[0080] Q3 = [(VN - V OS )A - V op C,

[0081] Q4 = [VP × A - V on C,

[0082] In the formula, A is the amplification factor of the pre-amplification comparator of the comparator module, VN represents the voltage of the negative-phase input terminal of the comparator module, VP represents the voltage of the positive-phase input terminal of the comparator module, V OS is the offset voltage, Vop is the positive-phase input terminal of the main comparator of the comparator module, and Von is the negative-phase input terminal of the main comparator of the comparator module.

[0083] It should be noted that Figure 3Only a part of the comparator module 5 is shown for the convenience of explaining the working principle of the offset storage module. In fact, the comparator module further includes a main comparator COMP3 with a double-to-single output connected to the non-inverting input terminal Vop of the main comparator of the comparator module and the inverting output terminal Von of the main comparator (as Figure 8 shown), and the output of this main comparator COMP3 is the zero-crossing signal ZCD.

[0084] According to the conservation of charge, we can obtain:

[0085] ΔV o =-AΔVi n ,

[0086] In the formula, ΔVo represents the difference between the non-inverting input terminal Vop of the main comparator of the comparator module and the inverting input terminal Von of the main comparator of the comparator module, which is equal to Vop - Von. ΔVin represents the difference between the forward input terminal voltage VP and the reverse input terminal voltage VN of the comparator module, which is equal to VP - VN. A is the amplification factor of the pre-amplification comparator of the comparator module.

[0087] The zero-crossing signal ZCD and ΔVo have a gain multiple relationship. When ΔVo is positive enough or negative enough, the zero-crossing signal ZCD is a logical high and low level signal output by ΔVo through a double-to-single comparator.

[0088] In this way, the offset voltage Vos is eliminated. The reverse input terminal voltage VN and the non-inverting input terminal voltage VP of the comparator module here are equal to V- and V+ in the above text, that is, the compensation voltage V CM2 -V CM1 .

[0089] The comparator module 5 is configured to receive the sampled voltage provided by the sample-and-hold module 2 and transmitted through the offset storage module 3 to obtain the zero-crossing signal ZCD.

[0090] The comparator module 5 is preferably a high-speed and high-precision comparator. It should be noted that there are also various choices for the structure of the comparator module 5 here, which is not the main content of the present invention.

[0091] The comparator module 5 includes a plurality of comparators. Such as Figure 8As shown, in this embodiment, the comparator module 5 includes: a first-stage preamplification comparator COMP1, a second-stage preamplification comparator COMP2, and a main comparator COMP3 connected in sequence, a comparator first capacitor C5 connected between the inverting output terminal of the first-stage preamplification comparator COMP1 and the non-inverting input terminal of the second-stage preamplification comparator COMP2, a comparator second capacitor C6 connected between the non-inverting output terminal of the first-stage preamplification comparator COMP1 and the inverting input terminal of the second-stage preamplification comparator COMP2, a comparator third capacitor C3 connected between the inverting output terminal of the second-stage preamplification comparator COMP2 and the non-inverting input terminal of the main comparator COMP3, and a comparator fourth capacitor C4 connected between the non-inverting output terminal of the second-stage preamplification comparator COMP2 and the inverting input terminal of the main comparator COMP3. The non-inverting input terminal and the inverting input terminal of the first-stage preamplification comparator COMP1 are the non-inverting and inverting input terminals of the comparator module 5, and the output terminal of the main comparator COMP3 serves as the output terminal of the comparator module 5 to provide a zero-crossing signal ZCD. The first-stage preamplification comparator COMP1 and the second-stage preamplification comparator COMP2 form the preamplification comparator of the comparator module, and the preamplification comparator has two output terminals.

[0092] For better understanding, the working principle of the zero-crossing detection circuit with adaptive slope compensation of the present invention will be briefly described below in conjunction with Figures 1 - 8 ,

[0093] When the lower switch of the BOOST converter is closed and the upper switch is open, the sample and hold module 2 stores the sampled voltages of (VBST - VCM1) and (VBST - VCM2) on the first capacitor C1 and the second capacitor C2, where VCM1 and VCM2 are generated by the common-mode offset module 4, and:

[0094]

[0095] V CM2 = V CM1 + I COMP R”

[0096] where R’ is the resistance value of the first resistor R1 and the second resistor R2, R” is the resistance value of the third resistor, I COMP is the compensation current, V BAT is the power supply voltage, V CM1 is the first common-mode level. Thus, the first common-mode level V CM1 and the second common-mode level V CM2 are obtained.

[0097] where the compensation current I COMP is:

[0098] ICOMP = K1(VBST - VBAT)

[0099] The falling slope K of the inductor current of the BOOST converter is:

[0100]

[0101] Therefore, the compensation voltage needs to be equal to the error caused by the change in the falling slope of the inductor current, that is, the compensation current I COMP The resistance value R” of the third resistor of the common-mode offset module 4 needs to satisfy:

[0102] I COMP × R” = K × R on × t del

[0103] where, R on is the on-resistance of the upper switch UG of the BOOST converter, K is the falling slope of the inductor current, and t del is the delay of the comparator module 5.

[0104] Therefore, according to the above calculation, the resistance value R” of the third resistor of the common-mode offset module 4 is:

[0105]

[0106] where, K1 is the compensation current coefficient, L is the inductor, and R on is the on-resistance of the upper switch UG of the BOOST converter, and t del is the delay of the comparator module 5. At this time, the compensation voltage that changes with the falling slope K of the inductor current can be realized.

[0107] As described above, the sample and hold module 2 receives the common-mode level difference sampled by the common-mode offset module 4 (i.e., V CM1 - V CM2 ) during the closing of the lower switch as the compensation voltage at the input end of the comparator module 5, and outputs the sampled voltage compensated by the compensation voltage (i.e., the voltage V + at the positive output end and the voltage V- at the negative output end of the sample and hold module 2) to the input end of the comparator module 5 for comparison.

[0108] The offset storage module 3 is connected to both the input end and the output end of the comparator module 5, and is set to store the offset voltage V OS of the comparator module 5 during the closing of the lower switch of the BOOST converter, and transfer the sampled voltage compensated by the compensation voltage (i.e., the voltage V + at the positive output end and the voltage V- at the negative output end of the sample and hold module 2) to the comparator module 5 after waiting for the upper switch to close, and eliminate the offset voltage V during the transfer process.OS Effect on the input signal of the comparator module 5 and the zero-crossing signal ZCD of the output

[0109] Thus, the present invention can achieve the function of adaptive zero-crossing under different inductor current slopes, ensuring that accurate zero-crossing detection points can be obtained under various input and output voltage conditions. At the same time, no additional upper transistor current detection circuit is required, reducing the overall area overhead.

[0110] The zero-crossing detection circuit with adaptive slope compensation of the present invention, through reasonable timing control, while the post-stage comparator stores the offset, the pre-stage sample-and-hold module simultaneously samples the SW voltage node of the BOOST converter. At this time, two different common-mode levels generated by the common-mode offset module are used to add an adaptive compensation voltage during the sampling stage, and the influence of the offset voltage is eliminated through the offset storage process; moreover, the complex operations during the sampling stage will not affect the offset storage process of the post-stage comparator. The zero-crossing detection circuit with adaptive slope compensation of the present invention can obtain accurate current zero-crossing detection points under different inductor current decreasing slopes and different comparator delays through the setting of the common-mode offset module. The comparator module can minimize the delay of the comparator, obtaining the minimum delay variation range and dispersion. Therefore, the proposed zero-crossing detection circuit with adaptive slope compensation can achieve relatively accurate early zero-crossing points under process, temperature, and voltage variations.

[0111] The above-described embodiments are only specific implementation manners of the present invention, used to illustrate the technical solutions of the present invention, rather than limiting it. The protection scope of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: Any person skilled in the art within the technical scope disclosed by the present invention can still modify the technical solutions described in the foregoing embodiments or can easily think of changes, or perform equivalent replacements on some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. An adaptive slope compensation zero-crossing detection circuit, which is used for a BOOST converter, is characterized in that It includes a sample-and-hold module, an offset storage module, and a comparator module connected in sequence, as well as a timing logic module and a common-mode offset module both connected to the sample-and-hold module and the offset storage module; The timing logic module is used to control the switching timings of the sample-and-hold module, the offset storage module, and the comparator module; The common-mode offset module is used to generate a common-mode level difference; The sample-and-hold module is configured to: charge and discharge a capacitor through switching to obtain a sampled voltage of a switching node voltage and a converter output voltage during the closing of the upper transistor, and receive the common-mode level difference as a compensation voltage at the input end of the comparator module during the closing of the lower transistor, and output the sampled voltage compensated by the compensation voltage; The offset storage module is configured to store the offset voltage of the comparator module during the closing of the lower transistor, transfer the sampled voltage compensated by the compensation voltage to the comparator module after the upper transistor is closed, and eliminate the influence of the offset voltage on the input signal and the zero-crossing signal output of the comparator module during the transfer process.

2. The zero-crossing detection circuit with adaptive slope compensation according to claim 1, wherein The common-mode offset module is used to generate a first common-mode level and a second common-mode level, and the first common-mode level and the second common-mode level form the common-mode level difference; the first common-mode level is connected to both the sample-and-hold module and the offset storage module, and the second common-mode level is only connected to the sample-and-hold module.

3. An adaptive slope compensation zero-crossing detection circuit according to claim 2, characterized in that, The offset storage module has a first type of switch connected to the output end of the sample-and-hold module, and the timing logic module avoids the mutual influence between the sample-and-hold module and the offset storage module when obtaining the first common-mode level and the second common-mode level by controlling the switching of the first type of switch of the offset storage module connected to the output end of the sample-and-hold module.

4. An adaptive slope compensation zero-crossing detection circuit according to claim 1, characterized in that, The value of the compensation voltage satisfies K × R on × t del , where R on is the on-resistance of the upper switch of the BOOST converter, K is the falling slope of the inductor current, and t del is the delay of the comparator module.

5. An adaptive slope compensation zero-crossing detection circuit according to claim 4, wherein, The common-mode offset module includes a first resistor, a second resistor, and a third resistor. One ends of the first resistor, the second resistor, and the third resistor are connected together to serve as the output end of the first common-mode level. The other end of the first resistor is connected to the power supply voltage. The other end of the second resistor is connected to a compensation current and serves as the output end of the second common-mode level. The other end of the third resistor is grounded. The resistance values of the first resistor and the second resistor are the same; and the compensation current is proportional to the difference between the power supply voltage; The resistance value R” of the third resistor of the common-mode offset module is: Among them, K1 is the compensation current coefficient, L is the inductance, and R on is the on-resistance of the upper switch of the BOOST converter, and t del is the delay of the comparator module.

6. An adaptive slope compensation zero-crossing detection circuit according to claim 1, characterized in that, The sample-and-hold module includes a first capacitor and a second capacitor; The first side of the first capacitor is connected to the converter output voltage through a parallel-connected first type of switch and a second type of switch. The second side is the inverting output end of the sample-and-hold module and is connected to the second common-mode level through a third type of switch; the first side of the second capacitor is connected to the converter output voltage through the second type of switch and is connected to the switching node voltage through a switching node detection condition switch and the first type of switch. The second side is the non-inverting output end of the sample-and-hold module and is connected to the first common-mode level through a third type of switch.

7. An adaptive slope compensation zero-crossing detection circuit according to claim 1, characterized in that, The offset storage module includes a first type of switch connected between the inverting output terminal of the sample and hold module and the inverting input terminal of the comparator module, a first type of switch connected between the non-inverting output terminal of the sample and hold module and the non-inverting input terminal of the comparator module, a third type of switch connected between the inverting output terminal of the sample and hold module and the first common-mode level, a third type of switch connected between the non-inverting output terminal of the sample and hold module and the first common-mode level, a comparator third capacitor connected between the non-inverting output terminal of the pre-amplification comparator of the comparator module and the non-inverting input terminal of the main comparator of the comparator module, a comparator fourth capacitor connected between the inverting output terminal of the pre-amplification comparator of the comparator module and the inverting input terminal of the main comparator of the comparator module, a third type of switch connected between the first common-mode level and the non-inverting input terminal of the main comparator of the comparator module, and a third type of switch connected between the first common-mode level and the inverting input terminal of the main comparator of the comparator module.

8. An adaptive slope compensation zero-crossing detection circuit according to claim 6 or 7, characterized in that The timing logic module is set such that when the lower transistor is closed and the upper transistor is open, the second type of switch and the third type of switch are closed and the first type of switch is open; when the lower transistor is open and the upper transistor is closed, the first type of switch is closed and the second type of switch and the third type of switch are open.

9. An adaptive slope compensation zero-crossing detection circuit according to claim 1, characterized in that The comparator module is a high-speed and high-precision comparator.

10. An adaptive slope compensation zero-crossing detection circuit according to claim 1, wherein, The zero-crossing detection circuit is installed between the source and drain of the upper transistor of a BOOST converter; the BOOST converter includes an inductor, an upper transistor, and a low-side power transistor connected to the same switching node, wherein the other node of the inductor is connected to the power supply voltage, the other node of the upper transistor is connected to the converter output voltage, and the other node of the low-side power transistor is grounded, and the upper transistor and the low-side power transistor are connected to a logic and drive circuit.

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