Application processor, electronic device having same, and method of operating same

Abstract

An application processor is provided. The application processor includes a phase-locked loop (PLL) circuit, a sleep control logic circuit configured to control the PLL to enter and exit a sleep mode, and a wake-up generation logic circuit configured to provide a wake-up request signal to the sleep control logic circuit to control the PLL to exit the sleep mode based on an early wake-up signal, the normally-open video timer circuit is configured to output a synchronizing signal to a display driving chip in a sleep mode section and generate the early wake-up signal; a display video timer circuit configured to receive the synchronization signal from the normally-on video timer and instruct the sleep control logic to provide an idle section; and a clock switching logic circuit configured to alternately provide one of a normally-on clock and a word clock as an operating clock of the sleep control logic.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2024 - 0004635, filed with the Korean Intellectual Property Office on January 11, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] The present disclosure relates to an application processor, an electronic device having the application processor, and a method of operating the application processor. Background art

[0004] A display can be driven using low - frequency driving. A dedicated interface and driver for low - frequency driving can be provided, and an appropriate display can be selected according to frequency, resolution, and display type. An application can send data to and control the display using communication protocols such as Serial Peripheral Interface (SPI), Inter - Integrated Circuit (I2C), Display Serial Interface (DSI), DisplayPort (DP), etc. The application can generate and process data to be displayed on the display. For example, a graphics library or image - processing algorithm can be used to create the content to be displayed. To drive the display at a low frequency, a low - frequency signal suitable for the frequency can be generated so that the pixels of the display are updated and the content is displayed on the screen. The low - frequency signal can be used to update the display and the display content. A screen effect can be obtained by setting the display update period and method. When the display is driven at a low frequency, power consumption can be reduced. When the display is not activated, energy can be saved by switching to a low - power mode. Finally, the application can test and optimize the performance of the display controls. By following these operations and considerations, the display driven by low - frequency operation can be effectively controlled in the application, and visual information can be effectively displayed in various application fields. Summary of the invention

[0005] Example embodiments provide an application processor that efficiently manages power, an electronic device having the application processor, and a method of operating the application processor.

[0006] According to an example embodiment, an application processor includes: a phase-locked loop circuit (PLL); a sleep control logic circuit configured to control the PLL to enter and exit a sleep mode; a wake-up generation logic circuit configured to provide a wake-up request signal to the sleep control logic circuit to control the PLL to exit the sleep mode based on an early wake-up signal; a always-on video timer circuit configured to output a synchronization signal to a display driver chip in a sleep mode section and generate the early wake-up signal; a display video timer circuit configured to receive the synchronization signal from the always-on video timer and instruct the sleep control logic to provide an idle section; and a clock switching logic circuit configured to alternately provide one of an always-on clock and a word clock as an operation clock of the sleep control logic. The application processor is configured to enter at least two low power states in the sleep mode section.

[0007] According to an example embodiment, a method of operating an application processor includes: determining to enter a sleep mode of a phase-locked loop circuit (PLL) based on determining that there is currently no data available for transmission; entering the sleep mode of the PLL based on the determination; requesting a wake-up of the PLL based on a need for a frame update while in the sleep mode of the PLL; exiting the sleep mode of the PLL according to the wake-up request; performing a frame count in the sleep mode; maintaining the sleep mode based on the frame count value being less than or equal to a first value; entering a first low power state based on the frame count value being greater than the first value; and entering a second low power state based on the frame count value being greater than a second value, the second value being greater than the first value.

[0008] According to an example embodiment, an electronic device includes: a panel; a display driver chip configured to control the panel according to frame data and a synchronization signal; and an application processor configured to: provide the synchronization signal and a frame to the display driver chip; and enter a sleep mode of a phase-locked loop circuit (PLL) and at least two additional low power states based on a low power mode request from the display driver chip.

[0009] According to an example embodiment, a method of operating an application processor includes: receiving a low power mode entry request signal from a display driver chip; entering a dynamic variable refresh rate mode according to the low power mode entry request signal; entering a selected low power state selected from a plurality of low power states in the dynamic variable refresh rate mode; and exiting the selected low power state based on a frame update and sending a new frame to the display driver chip according to a synchronization signal. Description of the Drawings

[0010] The above and other aspects, features, and advantages will become more apparent from the following description of example embodiments in conjunction with the drawings, in which:

[0011] Figure 1 is a diagram showing a display system according to an exemplary embodiment;

[0012] Figure 2 is a diagram showing a low power mode in a related application processor (AP);

[0013] Figure 3 is a diagram showing a step - by - step low power mode of an AP according to an exemplary embodiment.

[0014] Figure 4 is a diagram showing a power evaluation of an AP according to an exemplary embodiment;

[0015] Figure 5 is a flowchart showing the operation of an AP according to an exemplary embodiment;

[0016] Figure 6 is a diagram showing the timing of state transitions of a state machine and related signals when performing a PLL sleep operation in the video mode of an AP according to an exemplary embodiment;

[0017] Figure 7 is a diagram showing the timing when using an optical emission signal in the low power mode of an AP according to an exemplary embodiment;

[0018] Figure 8 is a ladder diagram showing the low power operation of a display system according to an exemplary embodiment;

[0019] Figure 9 is a diagram showing a mobile device according to an exemplary embodiment; and

[0020] Figure 10 is a diagram showing an electronic device according to an exemplary embodiment. Detailed Description

[0021] Hereinafter, exemplary embodiments will be described. Each exemplary embodiment provided in the following description does not exclude one or more features associated with another exemplary or another exemplary embodiment provided herein or not provided herein but consistent with the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. An expression such as "at least one of..." modifies the entire list of elements when it is before the list of elements, rather than modifying each individual element in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0022] An application processor AP, an electronic device including the application processor AP, and an operating method of the AP according to an exemplary embodiment can implement a low-power mode with a short transition delay from an ultra low power state (ULPS) to a data transmission state even in a video mode in which the AP manages video timing. Generally, in the PLL sleep mode, the PLL is inoperable and does not generate a clock signal. In addition, by stopping the screen output of the display panel and turning off the backlight in ULPS, power consumption can be minimized even when the display is not working.

[0023] The AP, the electronic device, and the operating method of the AP according to the exemplary embodiment can also add a synchronization signal using a constant video timer to continuously manage video timing even in a PLL sleep state (i.e., in the PLL sleep mode). Logic (e.g., circuitry) can also be added to control the frame start timing in consideration of the delay consumed by PLL wake-up and the emission interval of a display driver integrated circuit (DDI). Additionally, decoding can be performed to control entry into an increasing low-power state based on the interval of frame updates in the video mode. By using the PLL sleep function in a panel that supports a command mode and a panel that uses a video mode, maximum power consumption reduction can be achieved when there is no data transmission. Furthermore, frame start progress can be ensured by considering the delay required for PLL wake-up and maintaining video timing through a constant video timer to prevent image data from being delayed.

[0024] The exemplary embodiment allows the use of a low-power mode by supporting the PLL sleep function regardless of the operating mode required by the DDI, even in a video mode in which video timing needs to be managed by the AP. Additionally, by adding a low-power mode with a shorter power-on delay than ULPS, the exemplary embodiment achieves a low-power consumption effect without delaying frames.

[0025] Figure 1 FIG. is a diagram illustrating a display system 10 according to an exemplary embodiment. Refer to Figure 1 , the display system 10 may include an application processor (AP) 100, a DDI 200, and a panel 300.

[0026] The AP 100 may include circuitry for implementing an always-on clock source 101, a clock divider 102, clock switching logic 103, PLL sleep control logic 110, a PLL circuit 120, PLL wake-up generation logic 130, an always-on video timer 140, and a display video timer 150.

[0027] The always-on clock source 101 can be implemented to generate an always-on clock. The clock divider 102 can be implemented to receive the DDR clock and output a word clock based on the DDR clock, for example, by dividing the DDR clock. The clock switching logic 103 can be implemented to receive the always-on clock from the always-on clock source 101 and the word clock from the clock divider 102, and output an operation clock based on the always-on clock and the word clock. The clock switching logic 103 can switch from the word clock as the operation clock source to the always-on clock as the operation clock source, generate a sleep trigger signal based on this change, and send the generated signal to the PLL 120. When a wake-up request is received, a wake-up can be requested from the PLL 120. When the PLL wake-up is completed, the clock switching logic 103 can perform an operation to convert the output of the operation clock from the always-on clock back to the word clock.

[0028] The PLL sleep control logic 110 can be implemented to perform a PLL sleep entry or exit sequence depending on the current state and input. If the state of the display video timer 150 is idle and there are no commands to be sent or other requested operations to be performed (skew calibration, bus switching BTA, etc.), then the conditions for sleep entry are established. The PLL sleep control logic 110 can perform a PLL sleep trigger interface operation based on the conditions for sleep entry being established. The PLL sleep trigger interface operation includes providing PLL_Sleep and PLL_LOCK signals. If the PLL_Sleep signal is asserted (low to high), then a sleep entry has been requested. Conversely, if the PLL sleep signal is de-asserted (i.e., high to low), then a sleep exit has been requested. The PLL_LOCK signal is a signal provided from the PLL 120 to the PLL sleep control logic 110. When the PLL 120 is in a stable clock generation state, the PLL_LOCK signal is at a high level. When entering the sleep state, the PLL_LOCK signal is at a low level.

[0029] The PLL wake-up generation logic 130 can be implemented to perform operations for image data transmission when an early PLL wake-up signal is received from the always-on video timer 140. The AP 100 can perform a preparation operation to read the image data to be sent from the storage device and simultaneously send a PLL wake-up request signal to the PLL sleep control logic 110.

[0030] The always-on video timer 140 can be implemented to send a synchronization signal to the display video timer 150 and the DDI. The clock source for the horizontal synchronization signal can be changed in the PLL sleep state. For example, the clock source can be changed from the always-on clock to the word clock, or from the word clock to the always-on clock. As the clock source changes, the length of the horizontal lines counted by the clock can vary. By receiving the horizontal synchronization signal from the always-on video timer 140 at regular intervals and performing line counting, even when the clock source changes, the vertical video timing can be managed consistently. Additionally, an early PLL wake-up signal can be generated to complete the wake-up before frame update. The early PLL wake-up signal can be generated earlier than the maximum time delay required for wake-up determined by the PLL 120, rather than when the AP 100 actually starts frame update, thereby preventing image transfer delay.

[0031] The AP 100 according to an example embodiment can be applied to a DSI host link controller. When using dynamic variable refresh rate (VRR), the AP 100 according to an example embodiment can enter various low-power modes in a section where there is no data transmission.

[0032] The DDI 200 can be implemented to operate the control panel 300. For example, the DDI 200 can change the data sent from the AP 100 into data in a form to be sent to the panel 300, and can send the changed data to the panel 300. In an example embodiment, the DDI 200 can control the state of the control panel 300 (sleep state, display on state, display off state, etc.). The DDI 200 can be implemented without including a frame buffer (e.g., graphics random access memory GRAM) that stores the frame data received from the AP 100. The DDI 200 can be implemented to display frame data on the panel 300 in response to timing information in a low-frequency operation mode (e.g., 1 Hz or 10 Hz operation mode). In this case, the timing information can be received from the AP 100 in the low-frequency operation mode.

[0033] The panel 300 can be implemented to display image data. In an exemplary embodiment, the panel 300 can be implemented as a thin film transistor liquid crystal display (TFT-LCD) panel, a light emitting diode (LED) display panel, an organic LED (OLED) display panel, an active matrix OLED (AMOLED) display panel, a flexible display panel, etc. Specifically, the panel 300 can be implemented as a low temperature polycrystalline oxide (LTPO) panel. In addition, details regarding the LTPO panel are described in US2022-0114957, which is incorporated herein by reference in its entirety. Further, the panel 300 can include a plurality of pixels arranged in a matrix form having a plurality of rows and a plurality of columns. The plurality of pixels can be respectively connected to a plurality of data lines and a plurality of source lines. In this case, a pixel is a structure in which sub-pixels (e.g., red (R), green (G), and blue sub-pixels) are arranged adjacent to each other for a specified color display, and one pixel can include RGB sub-pixels (RGB stripe layout structure) or RGGB sub-pixels (Pentile layout structure). In this case, the arrangement structure of the RGGB sub-pixels can be replaced with an RGBG sub-pixel arrangement structure. Alternatively, the pixel can be replaced with an RGBW sub-pixel arrangement structure.

[0034] The power states presented in the MIPI D-PHY / C-PHY standard are broadly divided into different modes, including a high speed (HS) transmission mode, a low power (LP) mode, and an ultra-low power state (ULPS). The HS transmission mode is a mode for sending data as fast as possible in a differential manner. The LP mode and the ULPS mode are states for low power. The LP mode operates the lines in a single-ended form and switches or remains idle only at a low frequency of 20 MHz or lower without conversion. The ULPS mode is a mode that pays more attention to significantly reducing power consumption than the LP mode and performs an operation of lowering all levels of the lines to a low level on the receiver side.

[0035] Figure 2 is a diagram showing the low power mode in a related AP. In the case of the ULPS mode proposed in the standard, at least 1 millisecond (ms) is provided as a reference only for wake-up. In actual operation, a longer time delay is usually required, and thus it can be used only in limited cases. For example, when the frame rate is 60 frames per second (fps), the length of one frame is about 16.6 ms. Therefore, sending image data within one frame and performing ULPS entry and exit operations during the remaining time is ineffective in reducing power. Therefore, related low power technologies are mainly applied to cases where image updates are not required for several frames and thus display output is not required.

[0036] In addition, related low-power techniques use low-power features for PLL sleep, which can reduce power consumption without long wake-up latencies. In this case, PLL sleep is the function of turning off the PLL, which is the source of the serial clock for PHY serial data transmission. This has a smaller power reduction effect than ULPS, but has the advantage of being more effective than the LP mode in terms of power reduction and lower latency. The wake-up latency varies according to the PLL specifications. Generally, the wake-up latency of the PLL requires a maximum of 200 microseconds (us) or less. However, this is not suitable for applications when the porch section of the video mode is short. In the video mode, since the AP should check the video timing based on the clock and send the horizontal sync signal HSync to the DDI, problems may occur due to the clock switching caused by PLL sleep. For this reason, PLL sleep is only used in the command mode for sending image data quickly in bursts.

[0037] As the demand for dynamic variable refresh rate (VRR) in which the frame rate is adjusted according to the application grows, a video mode that can support VRR in the DDI without a frame buffer can be used as the main operation mode. Therefore, it is crucial to minimize power consumption as much as possible in the video mode. The present disclosure provides a solution to this demand.

[0038] Generally, the operation of VRR includes a normal mode and a fast mode. In the normal mode, similar to the operation of the traditional video mode, image data is sent according to the frame rate. The fast mode completes the transmission of the image data based on the maximum frame rate and remains in an idle state without data transmission for the remaining time within one frame corresponding to the actual frame rate. Generally, during these idle intervals, since there is no data transmission, the low-power mode described in the MIPI standard is maintained. Even so, the serial clock source of the PHY, that is, the PLL (phase-locked loop), remains on, continuously consuming power. The AP 100 can enter a low-power mode called PLL sleep during these idle intervals. In this case, the idle intervals are relatively long compared to the shoulder intervals of the video mode. Although the length of the idle intervals is not sufficient to enter the ultra-low power state (ULPS), this interval provides sufficient time for PLL sleep to enter and exit. Therefore, it is possible to effectively reduce power consumption by using PLL sleep during this interval.

[0039] According to an exemplary embodiment, the AP 100 can use a constant video timer (i.e., always-on video timer) 140 to solve the video timing problem caused by clock switching and support the PLL sleep function with a relatively short wake-up latency in the video mode. When operating in the video mode, the AP 100 can gradually support the low-power mode according to the frame rate based on the length of the idle intervals.

[0040] Figure 3Shows the step - by - step low - power mode of the AP 100 according to an exemplary embodiment. When VRR is applied, regardless of the actual frame rate of the panel 300, the bandwidth of image data transmission is fixed based on the maximum frequency of the AP 100, allowing the fastest possible data transmission. Therefore, it is feasible to apply low - power methods during the remaining time before frame update. For example, an AP 100 that supports a frame rate of up to 120 fps can even send image data at a 120 - fps bandwidth when operating at an actual rate of 60 fps. Thus, when operating at 60 fps, the AP 100 can send image data within 1 / 120 seconds and remain idle for the next 1 / 120 seconds.

[0041] During this 1 / 120 - second period, the AP 100 enters PLL sleep through the PLL sleep control logic 110 and the PLL wake - up generation logic 130, thus effectively reducing power by waking up before frame update. Additionally, even when clock switching occurs due to PLL sleep, the constant video timer 140 can be used to consistently maintain the synchronization interval from the AP 100 to the DDI 200. When a frame update is required, the constant video timer 140 sends an early frame start signal to the PLL wake - up generation logic 130 before frame update, initiating a wake - up sequence (PLL sleep exit sequence) to prevent delays caused by wake - up, thus maintaining the responsiveness of frame update. Additionally, for lower frame rates such as 30 fps, 10 fps, and 1 fps, the AP 100 can gradually enter ULPS or power - off states (i.e., the first - step low - power mode, the second - step low - power mode, and the third - step low - power mode), thus achieving a greater power - reduction effect.

[0042] The low - power technology according to an exemplary embodiment can be applied by classifying low - power modes based on the frame - update interval into: a PLL sleep mode, a ULPS mode with a display - chain power - down, and a PHY power - off mode. The ULPS mode can consume less power than the PLL sleep mode, and the ULPS mode can consume more power than the PHY power - off mode.

[0043] In the first - step low - power mode, i.e., the PLL sleep mode, power reduction targets only the serial - clock PLL 120. Its entry / exit sequence has the shortest time delay and is hardware - controlled. If no image transmission occurs after a frame, the hardware (i.e., the AP 100) autonomously activates the PLL sleep function when it enters the idle state.

[0044] In the second low-power mode, i.e., the ULPS mode, the logic hardware of the AP 100 for processing the image of the next display chain is powered down. This requires software intervention and has a longer wake-up latency compared to PLL sleep, so it is applied when there is no frame update for two or more frames.

[0045] In the third low-power mode, i.e., the PHY power-off mode, when the frame update interval becomes longer than the ULPS mode, the PHY is powered off to maximize power reduction.

[0046] The AP 100 can achieve the maximum power reduction effect while considering latency by applying optimized low-power methods according to different situations as described above.

[0047] Figure 4 FIG. is a diagram showing the power evaluation of the AP 100 according to an exemplary embodiment. When the display system 10 is in a low-power state, video timing and frame update responsiveness are maintained. This maintains the consistency of operation. Different from other low-power methods, the AP 100 has a PLL sleep feature that allows automatic hardware control without software intervention, and thus there is no side effect such as an increase in power consumption of other blocks in the AP100. Therefore, its application is possible without considering trade-offs.

[0048] Comparing the power reduction effects when using the LP mode and PLL sleep in the idle section, in the PLL sleep state, the idle power can be reduced by approximately 40%. When using the fast mode of VRR, as the frame rate decreases, the length of the idle section where PLL sleep is possible may become longer, resulting in a greater power reduction effect.

[0049] As Figure 4 shown, power reduction before and after PLL sleep is expected. Regardless of the frame rate, in the fast mode, data is sent at a maximum frequency of 120 fps, and the next frame is updated according to the frame rate, so power is reduced during the period when no data is sent. If these values are compared with the normal mode in which image data is sent according to the frame rate without an idle section, a much greater power reduction effect is expected.

[0050] Figure 5 FIG. is a flowchart showing the operation of the AP 100 according to an exemplary embodiment. Referring to Figures 1 to 5 , the low-power operation of the AP 100 can be performed as follows:

[0051] The AP 100 can determine whether to enter PLL sleep (S110) by checking whether there is data to be sent or whether there are no other scheduled operations. The AP 100 can enter and maintain the PLL sleep state through a PLL sleep entry handshake between the PLL 120 and the PLL sleep control logic 110 based on determining that there is no data to be sent and there are no other scheduled operations. Before PLL sleep, the clock switching logic 103 can switch the operating clock to a constant clock (i.e., can switch the operating clock from the word clock to the always-on clock) so that the display video timer 150 and the PLL sleep control logic 110 can operate even in the PLL sleep state (S120).

[0052] When a state that requires PLL wake-up occurs, such as when a frame update is needed or when command passing is needed, the AP 100 can perform a PLL sleep exit operation when receiving a PLL wake-up request (S130). If there is a PLL wake-up request, the AP 100 can enter the PLL on state through a PLL sleep exit handshake between the PLL 120 and the PLL sleep control logic 110 (S140). Once PLL on is confirmed, the clock switching logic 103 can change the source of the operating clock back to the word clock. However, if there is no PLL wake-up request, the AP 100 can perform a frame counting operation. If there is no PLL wake-up signal during a frame, the AP 100 can increment the frame count value by 1 (S150).

[0053] The application of a specific low-power mode can be determined based on the frame count value reaching certain thresholds. Until the frame count value reaches M, the AP 100 can maintain the PLL sleep state (S120). When the frame count value reaches N, the AP 100 can perform a ULPS entry operation (S160). Additionally, if the frame count value exceeds N, the AP 100 can perform a power-off entry operation (S190). The expiration values of each counter have the relationship M < N, where M and N are natural numbers determined as optimal values through power simulation specific to each application.

[0054] In operation S160, if the frame count value remains above M without any data transmission, the AP 100 can enter the ULPS state, which provides a relatively significant power reduction effect. Subsequently, it can be determined whether a ULPS wake-up operation is needed (S170). If a ULPS wake-up operation is needed, the AP 100 can perform a ULPS exit operation (S180). On the contrary, if a ULPS wake-up operation is not needed, a frame counting operation can be performed (S150).

[0055] In operation S180, the ULPS exit operation can be performed using the protocol specified in the MIPI DSI protocol. In operation S190, if the frame count value remains higher than N without any data transmission, in order to maximize the power reduction effect, the power of the display configuration within the AP can be cut off (S191). During the power-off exit, the AP 100 can initiate all initialization sequences, or depending on the situation, use retention storage to simplify the sequences. After terminating all low-power modes, the AP 100 can be ready to start a new frame (S192).

[0056] Figure 6 FIG. is a diagram showing the state transition of the state machine and the timing of related signals when performing the PLL sleep operation in the video mode of the AP 100 according to an exemplary embodiment. In the absence of image data transmission, the display video timer 150 enters the idle state. At this time (i.e., when both the display video timer state and the PLL sleep control logic state are in the idle state), the sleep entry condition can be confirmed. As Figure 6 shown, the clock switching can be performed with a normally-on clock other than the word clock. The PLL sleep signal can be declared to the PLL 120. When the PLL 120 receives the PLL sleep signal, the PLL notifies that the PLL shutdown has been completed by lowering the lock state signal to low. After that, when an image data transmission is requested and the PLL wake-up signal is received, the PLL sleep control logic 110 invalidates the PLL sleep signal. When the PLL lock state from the PLL 120 rises to high, the sleep exit operation is completed by switching back to the word clock by completing the clock switching. Then, when a frame update is required, the frame start is declared according to the vertical synchronization signal, and the next image data can be transmitted.

[0057] Figure 7 FIG. is a diagram showing the timing when using the optical emission signal in the low-power mode of the AP 100 according to an exemplary embodiment. As shown, the frame update can start at intervals of 1 frame, for example, according to the vertical synchronization signal. When using the emission synchronization function, the frame can start at the 1 / 2 frame point or the 1 / 4 or 3 / 4 frame point. This function is to subdivide the frame start point to improve the response speed when there is no image data being transmitted in the idle state and the frame should be updated in response to an input such as a user's touch or movement.

[0058] Since the panel's emission cycle should be considered if there is a frame request, the video mode controller can include a counter for managing the emission interval. The video mode PLL sleep and emission synchronization according to an exemplary embodiment can be related.

[0059] If the transmission synchronization function is not supported, since the remaining time until frame update is shorter than the wake-up latency, in the case where frame update can be performed at the next vertical synchronization timing, the frame update is delayed by at least one frame time, and thus, the response speed may be slow. In addition, assuming that the transmission synchronization function is supported and the interval of transmission synchronization is 1 / 2 frame, the response time required for frame update can be shortened to 1 / 2 frame. The shorter the interval of the transmission synchronization signal, the higher the responsiveness will be.

[0060] As Figure 7 shown, the case where the interval of the transmission synchronization signal is 1 / 4 frame is provided. From the perspective of the system, when the transmission synchronization function and the PLL sleep function are used together, the low-power effect of the exemplary embodiment can be maintained, and at the same time, the side effects of a long frame update latency can be significantly reduced.

[0061] In the case of the PLL sleep function applied to the AP 100 according to the exemplary embodiment, the target of power reduction can be only the PLL 120 and some logics of the physical layer having the PLL 120 as a clock source. In another exemplary embodiment, the low-power target can be extended by applying hardware automatic power gating to some blocks of the AP 100 in the PLL sleep state.

[0062] Through a protocol analyzer, it is possible to check what power state is maintained for each scenario and measure power according to the scenario.

[0063] Since PLL sleep can be automatically controlled by hardware without software intervention, the entry and exit sequences are simpler. Since there are no side effects such as an increase in power consumption of other blocks within the AP, its application can be promoted without considering trade-offs. In addition, a combination with the concept of an optical transmission synchronization signal is possible, and thus, the frame update delay can be significantly reduced by the wake-up latency.

[0064] Figure 8 is a ladder diagram showing the low-power operation of the display system 10 according to the exemplary embodiment. Referring Figures 1 to 8 , the step-by-step low-power operation of the display system 10 can be performed as follows.

[0065] The DDI can send a low-power request (S10) to the AP through a tearing effect (TE) signal. The AP can input a dynamic variable refresh rate (VRR) in response to the low-power request (S11). By performing the dynamic VRR operation as Figures 1 to 7 described, the optimal low-power mode can be selected according to the situation of the display system (S12). After that, the AP can send a new frame to the DDI (S13). The DDI can display the new frame on the panel (S14).

[0066] In an example embodiment, the DDI does not include a frame buffer, and in multiple low-power states, a always-on clock can be used instead of a phase-locked loop (PLL) to output a synchronization signal. In an example embodiment, the multiple low-power states may include a sleep state of the PLL. In an example embodiment, the PLL can be put to sleep or woken up in hardware without software intervention. In an example embodiment, frame counting can be performed and it can enter one of the multiple low-power states according to the frame count value.

[0067] In addition, the example embodiment can be implemented in a mobile device.

[0068] Figure 9 is a diagram showing a mobile device according to an example embodiment. Refer to Figure 9 , the mobile device 1000 may include at least one processor 1210, a subscriber identification module (SIM) card 1224, a memory 1230, a communication module 1220, a sensor module 1240, a user input device 1250, a display module 1260, an interface 1270, an audio module 1280, a camera module 1291, a power management module 1295, a battery 1296, an indicator 1297, or a motor 1298.

[0069] The processor 1210 may include at least one application processor (AP) 1211 and at least one communication processor (CP) 1213. The AP 1211 and the CP 1213 may be respectively included in different IC packages. In an example embodiment, the AP 1211 and the CP 1213 may be included in one IC package.

[0070] The AP 1211 runs an operating system / application to control multiple hardware or software components connected to the AP 1211, and may perform processing and calculation of various types of data (including multimedia data). The AP 1211 may be implemented as, for example, a system-on-chip SoC. In an example embodiment, the processor 1210 may further include a graphics processing unit GPU. The CP 1213 may manage a data link in communication between the electronic device including the mobile device 1000 and other electronic devices connected through a network, and may perform a function of converting communication protocols. The CP 1213 may be implemented as, for example, an SoC. In an example embodiment, the CP 1213 may perform at least a part of the multimedia control function. The CP 1213 may use, for example, a subscriber identification module (e.g., the SIM card 1224) to distinguish and authenticate a terminal within a communication network. In addition, the CP 1213 may provide services such as voice calls, video calls, text messages, packet data, etc. to a user. In addition, the CP 1213 may control data transmission and reception of the communication module 1220. In Figure 9In [the figure], although components such as CP 1213, power management module 1295, and memory 1230 are shown as components separate from AP 1211, in an exemplary embodiment, AP 1211 may be implemented to include at least some of the above components (e.g., CP 1213). In an exemplary embodiment, AP 1211 or CP 1213 may load commands or data received from at least one of a non-volatile memory or other components connected thereto, respectively, into a volatile memory and process the same. Additionally, AP 1211 or CP 1213 may store data received from at least one of other components or generated by at least one of other components in a non-volatile memory.

[0071] The SIM card 1224 may be a card implementing a subscriber identity module and may be inserted into a slot formed at a specified position in the electronic device, embedded in the device in the form of a chip, or may be stored as SIM information in a part of the device (e.g., eSIM, virtual SIM, or soft SIM) without a physical form. The SIM card 1224 may include unique identification information (e.g., integrated circuit card identifier ICCID) or subscriber information (e.g., international mobile subscriber identity IMSI). The SIM card 1224 may operate in conjunction with the communication module 1220.

[0072] The memory 1230 may include an internal memory 1232 or an external memory 1234. The internal memory 1232 may include, for example, at least one of a volatile memory (e.g., dynamic random access memory DRAM, static RAM SRAM, synchronous dynamic RAM SDRAM, etc.) or a non-volatile memory (e.g., one-time programmable read-only memory OTPROM, programmable ROM PROM, erasable programmable ROM EPROM, electrically erasable programmable ROM EEPROM, mask ROM, flash ROM, NAND flash, NOR flash, etc.). In an exemplary embodiment, the internal memory 1232 may take the form of a solid-state drive SSD. The external memory 1234 may also include a flash drive, such as a compact flash CF, secure digital SD, micro secure digital micro SD, mini secure digital mini SD, or extreme digital xD, memory stick, etc.

[0073] The communication module 1220 may include, for example, an RF module 1229, a cellular module 1221, a Wi-Fi module 1223, a BT module 1225, a GPS module 1226, and an NFC module 1228. For example, the communication module 1220 may use radio frequency to provide a wireless communication function. Additionally, the communication module 1220 may include a modem or a network interface (e.g., a LAN card) for connecting the mobile device 1000 to a network (e.g., the Internet, a LAN, a WAN, a telecommunications network, a cellular network, a satellite network, POTS, etc.). The RF module 1229 may be responsible for transmitting and receiving data, such as RF signals or what are called electronic signals. The RF module 1229 may include, for example, a transceiver, a power amplifier module PAM, a frequency filter, a low-noise amplifier LNA, etc. Additionally, the RF module 1229 may further include components for transmitting and receiving electromagnetic waves in free space in wireless communication, for example, including conductors, wires, etc.

[0074] The sensor module 1240 may include at least one of, for example, a gesture sensor 1240A, a gyro sensor 1240B, a barometric pressure sensor 1240C, a magnetic sensor 1240D, an acceleration sensor 1240E, a grip sensor 1240F, a proximity sensor 1240G, an RGB (red, green, blue) sensor 1240H, a biometric sensor 1240I, a temperature / humidity sensor 1240J, an illuminance sensor 1240K, and an ultraviolet UV sensor 1240M. The sensor module 1240 may measure a physical quantity or detect an operating state of the electronic device and convert the measured or detected information into an electrical signal. Additionally, the sensor module 1240 may include, for example, an olfactory sensor (electronic nose sensor), an electromyogram sensor (EMG sensor), an electroencephalogram sensor (EEG sensor), an electrocardiogram sensor (ECG sensor), a photoplethysmography sensor (PPG sensor), a heart rate monitor HRM sensor, a sweat measurement sensor (sweat), a fingerprint sensor, etc. The sensor module 1240 may also include a control circuit for controlling at least one of the sensors included therein.

[0075] The user input device 1250 may include a touch panel 1252, a (digital) pen sensor 1254, keys 1256, and an ultrasonic input device 1258. The touch panel 1252 may identify touch inputs using at least one of, for example, capacitive, resistive, infrared, or ultrasonic methods. Additionally, the touch panel 1252 may further include a controller. In the case of the capacitive type, not only direct touch but also proximity recognition is possible. The touch panel 1252 may further include a haptic layer. In this case, the touch panel 1252 may provide a haptic response to the user. For example, the pen sensor 1254 may be implemented using the same or a similar method for receiving the user's touch input or using a separate recognition sheet. As the keys 1256, for example, a keypad or touch keys may be used. The ultrasonic input device 1258 is a device that can confirm data by detecting sound waves from the terminal to a microphone (e.g., microphone 1288) via a pen that generates ultrasonic signals and is capable of wireless recognition. In an exemplary embodiment, the mobile device 1000 may receive user input from an external device (e.g., a network, a computer, or a server) connected to the communication module 1220 using the communication module 1220.

[0076] The display module 1260 may include a panel 1262, a hologram 1264, or a projector 1266. The panel 1262 may be, for example, a liquid crystal display (LCD), an active matrix organic light emitting diode (AM-OLED), etc. The panel 1262 may be implemented as, for example, flexible, transparent, or wearable. The panel 1262 may be composed of the touch panel 1252 and a module. The hologram 1264 may display a three-dimensional image in the air using light interference. In an exemplary embodiment, the display module 1260 may further include a control circuit for controlling the panel 1262 or the hologram 1264.

[0077] The interface 1270 may include, for example, HDMI 1272, USB 1274, an optical interface 1276, and D-subminiature (D-sub) 1218. Additionally, the interface 1270 may include, for example, a multimedia card (SD / MMC) or the Infrared Data Association (IrDA). The audio module 1280 may convert voice and electrical signals bidirectionally. The audio module 1280 may convert voice information input or output through, for example, a speaker 1282, a receiver 1284, headphones 1286, or a microphone 1288. The camera module 1291 is a device that can capture images and videos and may include, in an exemplary embodiment, at least one image sensor (e.g., a front lens or a rear lens), an image signal processor (ISP), or a flash LED.

[0078] The power management module 1295 can manage the power of the mobile device 1000. The power management module 1295 can include, for example, a power management integrated circuit (PMIC), a charger IC, or a battery fuel gauge. The PMIC can be mounted, for example, within an integrated circuit or an SoC semiconductor. The charging method can be divided into wired and wireless. The charger IC can charge the battery and prevent overvoltage or overcurrent from flowing in from the charger. In an exemplary embodiment, the charger IC can include a charger IC for at least one of a wired charging method or a wireless charging method. The wireless charging method includes, for example, magnetic resonance, magnetic induction, an electromagnetic wave method, etc., and additional circuits for wireless charging, such as a coil loop, a resonant circuit, and a rectifier, can be added. The battery fuel gauge can measure, for example, the remaining amount, voltage, current, or temperature of the battery 1296 during charging. The battery 1296 can generate electricity to supply power and can be, for example, a rechargeable battery. The indicator 1297 can display a specified state of the mobile device 1000 or a part thereof (e.g., the AP 1211), such as a startup state, a message state, or a charging state. For example, the startup state, the message state, or the charging state can be displayed. The motor 1298 can convert an electrical signal into mechanical vibration. The mobile device 1000 can include a processing unit (e.g., a GPU) to support mobile TV. The processing device for supporting mobile TV can process media data according to standards such as, for example, Digital Multimedia Broadcasting (DMB), Digital Video Broadcasting (DVB), or media streaming.

[0079] Each of the above components of the hardware according to various exemplary embodiments can be composed of one or more components, and the names of the components can vary according to the type of the electronic device. The hardware according to various exemplary embodiments can be configured to include at least one of the above components, and some components can be omitted or other additional components can be included. Additionally, some hardware components according to various exemplary embodiments are combined to form a single entity, such that the functions of the corresponding components before combination can be performed in the same manner.

[0080] Furthermore, the exemplary embodiments can be implemented in an electronic device having a display system.

[0081] Figure 10 is a diagram showing an electronic device 2000 according to an exemplary embodiment. Refer to Figure 10 , the electronic device 2000 can include an AP 2100, a DDI 2200, a panel 2300, and a PMIC 2400.

[0082] The AP 2100 can be implemented to control the overall operation of an electronic device. In some example embodiments, the AP 2100 may be implemented as an integrated circuit, a system-on-chip, or a mobile application processor. The AP 2100 may send data to be displayed (e.g., image data, video data, or still image data) to the DDI 2200. In an example embodiment, the data may be divided into source data SD units corresponding to horizontal (or vertical) lines of the display panel 2300. The processor 2110 may be implemented to perform low-power state transitions step by step, as Figures 1 to 8 described in

[0083] The DDI 2200 may change the data sent from the AP 2100 into a form that can be sent to the display panel 2300 and send the changed data to the display panel 2300. The source data SD may be provided in units of pixels. The first sub-channel signal DDI_INFO may be sent to the connected AP according to the judgment of the display driver chip. The first sub-channel signal DDI_INFO may be output to the AP using the tearing effect (TE) pin. The second sub-channel signal ESYNC may be the video timing of the display driver chip. The second sub-channel signal ESYNC may be sent to the DDI periodically. Additionally, a modulation function may be applied to the second sub-channel signal ESYNC for fail-safe protection. In an example embodiment, the second sub-channel signal ESYNC may be output from the AP using the error detection flag pin.

[0084] Additionally, the DDI 2200 may control the levels of the logic voltage (VDDR) / analog voltage (VLIN1) by communicating with the PMIC 2400. The processor interface may interface the signals or data exchanged between the AP 2100 and the DDI 2200. The processor interface may interface the source data (SD, row data) sent from the AP 2100 and send the data to the DDI 2200. In an example embodiment, the processor interface may be an interface related to a serial interface, such as a Mobile Industry Processor Interface MIPI, a Mobile Display Digital Interface MDDI, a DisplayPort, an Embedded DisplayPort eDP, etc. Additionally, the display panel 2300 may be implemented to display the source data SD in response to a gate signal GS by the DDI 2200. In an example embodiment, the display panel 2300 may be a low-temperature polycrystalline oxide LTPO panel.

[0085] The PMIC 2400 may be implemented to manage the power of the display device. In an example embodiment, the PMIC 2400 may include a charger IC or a battery fuel gauge. Additionally, the PMIC 2400 may have wired and / or wireless charging methods. The wireless charging methods include, for example, magnetic resonance, magnetic induction, electromagnetic wave methods, etc., and may also include additional circuits for wireless charging, such as coil loops, resonant circuits, rectifiers, etc.

[0086] In addition, the PMIC 2400 can receive commands from the AP 2100 and supply power to the corresponding parts of the display device. The PMIC 2400 can supply power to the DDI 2200 and the display panel 2300 respectively. For example, the PMIC 2400 can provide an external voltage to the DDI 2200. In this case, the external voltage can be processed and used inside the DDI 2200. The power interface can interface between the PMIC 2400 and the DDI 2200. For example, the power interface can send commands sent by the DDI 2200 to the PMIC 2400. The power interface can be provided separately from the processor interface. The DDI 2200 can be directly connected to the PMIC 2400 without passing through the AP 2100.

[0087] In addition, the PMIC 2400 can receive power setting commands from the DDI 2200 to control the power levels VDDR / VLIN1 in each part of the display device.

[0088] The above devices can be implemented with hardware components. For example, the devices and components described herein can be implemented by using a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or one or more general-purpose or special-purpose computers (such as any other device capable of executing and responding to instructions). The processing device can execute an operating system (OS) and one or more software applications running on the operating system. In addition, the processing device can access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, there are cases described as using one processing device, but those skilled in the art will understand that the processing device can include multiple processing elements or multiple types of processing elements. For example, the processing device can include multiple processors or one processor and one controller. In addition, other processing configurations such as parallel processors are also possible.

[0089] The software can include a computer program, code, instructions, or a combination of one or more of them, and can configure the processing unit to operate as needed or independently or jointly command the processing unit. The software and / or data can be embodied in any type of machine, component, physical device, virtual device, computer storage medium, or device to be interpreted by or provide instructions or data to the processing device. The software can be distributed on a networked computer system and stored or executed in a distributed manner. The software and data can be stored on one or more computer-readable recording media.

[0090] The low-power technology of the exemplary embodiment supports the PLL sleep function even in the video mode where the video timing is managed by the AP, so that the low-power scheme is applied regardless of the operation mode (video mode or command mode) required by the DDI. The low-power technology of the exemplary embodiment adds a low-power mode with a shorter power-up delay than the ULP, so as to obtain a low-power consumption effect for each frame, but there is no delay in frame update, so there is no impact on the display output on the panel. In the exemplary embodiment, the video timing within the low-power mode section can be guaranteed.

[0091] When operating in the video mode, the AP manages the video timing, and thus the horizontal synchronization packets should be sent to the DDI at each horizontal synchronization interval (*). The horizontal synchronization interval is about several μs, and the length of the PLL sleep section varies according to the application, but is several ms (horizontal synchronization interval (*): 1 (second) / fps (Hz) / vertical resolution (integer)). In the PLL sleep section, since the PLL clock used in the display interface is not provided, the data path is unavailable, so the horizontal synchronization packets cannot be sent. The always-on video timer is a video timer that uses a clock source independent of the PLL used in the display interface. This component can send the synchronization information to the DDI by sending the horizontal synchronization signal to the sideband instead of the display interface, ensuring the video timing even in the low-power section.

[0092] In the exemplary embodiment, zero-frame delay caused by the low-power mode is guaranteed. If image transfer requires PLL wake-up, the always-on video timer generates an early wake-up signal earlier than the delay required for PLL wake-up. It is determined that image transfer is needed, and the PLL wake-up delay is shorter than the time to read image data from the memory, thus ensuring that image transfer is not delayed.

[0093] In the exemplary embodiment, hardware self-control is performed. All trigger operations for PLL sleep and wake-up can be performed through hardware self-control without software intervention, so no additional CPU power consumption is required.

[0094] According to the exemplary embodiment, a method for operating a stepwise low-power mode under VRR is provided. The display system according to the exemplary embodiment includes a device for ensuring video timing while obtaining a low-power effect. The display system according to the exemplary embodiment includes a device for preventing frame delay while obtaining low power consumption. The display system according to the exemplary embodiment includes a device for entering and exiting the low-power mode through hardware control without software intervention.

[0095] As described above, the application processor, the electronic device having the application processor, and the method of operating the application processor according to the exemplary embodiment can more effectively manage the low-power mode by supporting the PLL sleep mode.

[0096] In an application processor, an electronic device having the application processor, and a method of operating the application processor according to an exemplary embodiment, when there is no data transmission through a PLL sleep function, a power reduction effect can be significantly increased.

[0097] In an application processor, an electronic device having the application processor, and a method of operating the application processor according to an exemplary embodiment, a frame start can be performed in consideration of a time delay required for PLL wake-up.

[0098] In an application processor, an electronic device having the application processor, and a method of operating the application processor according to an exemplary embodiment, a video timer that is always on can be used to ensure the maintenance of video timing without delay of image data.

[0099] Although the exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept defined by the appended claims.

Claims

1. An application processor, comprising: A phase-locked loop circuit PLL; A sleep control logic circuit configured to control the PLL to enter and exit a sleep mode; A wake-up generation logic circuit configured to provide a wake-up request signal to the sleep control logic circuit to control the PLL to exit the sleep mode based on an early wake-up signal; A normally-on video timer circuit configured to output a synchronization signal to a display driver chip in a sleep mode section and generate the early wake-up signal; A display video timer circuit configured to receive the synchronization signal from the normally-on video timer and instruct the sleep control logic to provide an idle section; And A clock switching logic circuit configured to alternately provide one of a normally-on clock and a word clock as an operating clock of the sleep control logic, wherein the application processor is configured to enter at least two low-power states in the sleep mode section.

2. The application processor according to claim 1, further comprising: A normally-on clock source circuit configured to generate the normally-on clock; And A clock divider circuit configured to generate the word clock based on the clock of the PLL.

3. The application processor according to claim 1, further comprising a logic circuit configured to control frame timing based on an interval between a delay corresponding to the wake-up of the PLL and an optical emission period.

4. The application processor according to claim 1, further comprising a decoding logic circuit configured to control the application processor to enter the at least two low-power states according to a frame update interval in a video mode.

5. The application processor according to claim 4, wherein, The at least two low-power states include a PLL sleep state, an ultra-low power state (ULPS), and a power-off state, and wherein the decoding logic circuit is further configured to: control the application processor to enter the PLL sleep state, the ultra-low power state (ULPS), and the power-off state in stages according to the frame update interval.

6. The application processor according to claim 1, wherein, The clock switching logic circuit is further configured to provide the normally-on clock as the operating clock in the sleep mode section.

7. The application processor according to claim 1, wherein, The clock switching logic circuit is further configured to: provide the word clock as the operating clock after the wake-up of the PLL is completed.

8. The application processor according to claim 1, wherein The normally-on video timer circuit is further configured to manage horizontal video timing by counting lines of a horizontal synchronization signal at regular intervals.

9. The application processor according to claim 1, wherein, The clock switching logic circuit is further configured to provide the normally-on clock as the operating clock in the idle section.

10. The application processor according to claim 1, wherein, The PLL is configured to operate in a low-power mode managed based on a panel-based transmission synchronization signal and a sleep function of the PLL.

11. A method for operating an application processor, comprising: Determining to enter a sleep mode of a phase-locked loop circuit PLL based on determining that there is currently no data available for transmission; Entering the sleep mode of the PLL based on the determination; Requesting a wake-up of the PLL based on a need for a frame update while in the sleep mode of the PLL; Exiting the sleep mode of the PLL according to the requested wake-up; Performing frame counting in the sleep mode; Maintain the sleep mode based on the frame count value being less than or equal to a first value; Enter a first low-power state based on the frame count value being greater than the first value; and Enter a second low-power state based on the frame count value being greater than a second value, the second value being greater than the first value.

12. The method according to claim 11, further comprising: Exit the first low-power state based on a request for frame update in the first low-power state; And Exit the second low-power state based on a request for frame update in the second low-power state.

13. The method according to claim 11, wherein, The first low-power state is an ultra-low power state (ULPS), and wherein the second low-power state is a power-off state.

14. The method according to claim 11 further comprises: Use a always-on clock as the operating clock in the sleep mode section.

15. The method according to claim 11 further comprises: In the sleep mode section, output a synchronization signal from the always-on clock video timer to the display driver chip.

16. An electronic device, comprising: A panel; A display driver chip configured to control the panel according to frame data and a synchronization signal; And An application processor configured to: Provide the synchronization signal and the frame to the display driver chip; And Based on a low-power mode request from the display driver chip, enter the sleep mode of a phase-locked loop circuit (PLL) and at least two additional low-power states.

17. The electronic device according to claim 16, wherein, The application processor includes an always-on clock source configured to generate an always-on clock, wherein the application processor is further configured to use the always-on clock as the operating clock when in the sleep mode of the PLL.

18. The electronic device according to claim 16, wherein, The application processor includes: A sleep control logic circuit configured to control the PLL to enter the sleep mode according to a sleep request and exit the sleep mode according to a wake-up request; and A wake-up generation logic circuit configured to generate the wake-up request based on the frame data being updated.

19. The electronic device according to claim 18, wherein, The application processor further includes: An always-on video timer circuit configured to generate an early wake-up signal and generate the synchronization signal based on the frame data being updated; and A display video timer circuit configured to receive the synchronization signal and indicate an idle section.

20. The electronic device according to claim 19, wherein, The wake-up generation logic circuit is further configured to output the wake-up request signal according to the early wake-up request signal.

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