Touch sensing display device and method of driving the same

Abstract

A touch sensing display device and a driving method thereof are disclosed. The touch sensing display device includes: a display panel configured to alternately perform display driving and touch sensing driving; and a gate driving circuit including a stage circuit for driving gate lines of the display panel, in which the gate driving circuit outputs a display scan signal generated based on a display carry clock to the display panel during a display frame defining a display driving period, and outputting a touch scan signal generated based on the touch carry clock to the display panel during a touch frame defining a touch sensing driving period, and a position at which the touch carry clock is generated during a first touch sensing frame included in the touch sensing driving period is different from a position at which the touch carry clock is generated during a second touch sensing frame included in the touch sensing driving period.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2024 - 0003376, filed on January 9, 2024, which is incorporated herein by reference in its entirety as if fully set forth herein. Technical field

[0003] The present disclosure relates to a touch - sensing display device and a driving method thereof. Background art

[0004] With the advancement of information technology, the market for display devices as a connection medium between users and information has been growing continuously. Accordingly, the use of display devices such as light - emitting display devices, quantum dot display (QDD) devices, and liquid crystal display (LCD) devices has been increasing.

[0005] The above - mentioned display device includes a display panel including a plurality of sub - pixels, a driver that outputs a driving signal for driving the display panel, and a power supply that generates power to be supplied to the display panel or the driver.

[0006] In such a display device, when a driving signal (e.g., a scan signal and a data signal) is supplied to each of the sub - pixels provided in the display panel, the selected sub - pixel can transmit light or can emit light by itself, and thus can display an image. Summary of the invention

[0007] The present disclosure can reduce the carry signal transmission time to ensure the touch - sensing time, and based on this, can enhance the sensitivity of the touch - sensing operation, can increase the touch data acquisition target (touch screen block), and can ensure the time for analyzing the coordinates of the touch - input position.

[0008] To achieve these objects and other advantages, and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a touch - sensing display device includes: a display panel configured to alternately perform display driving and touch - sensing driving; and a gate driving circuit including a stage circuit for driving gate lines of the display panel, wherein the gate driving circuit outputs a display scan signal generated based on a display carry clock to the display panel during a display frame defining a display driving period, and outputs a touch scan signal generated based on a touch carry clock to the display panel during a touch frame defining a touch - sensing driving period, and a position where the touch carry clock is generated during a first touch - sensing frame included in the touch - sensing driving period is different from a position where the touch carry clock is generated during a second touch - sensing frame included in the touch - sensing driving period.

[0009] The touch carry clock can be transmitted in a forward direction relative to the display panel during a first touch sensing frame, and can be transmitted in a reverse direction relative to the display panel during a second touch sensing frame.

[0010] The gate driving circuit can apply a forward voltage to drive the stage circuit in a forward direction during a first touch sensing frame, and can apply a reverse voltage to drive the stage circuit in a reverse direction during a second touch sensing frame.

[0011] During a first touch sensing frame, the touch carry clock can be generated from a first gate line of the display panel and can be transmitted until a gate line disposed in a central region of the display panel, and during a second touch sensing frame, the touch carry clock can be generated from a last gate line of the display panel and can be transmitted until a gate line disposed in a central region of the display panel.

[0012] During a touch sensing driving period, a first stage of the stage circuit can supply a first touch scan signal to a first gate line included in a first touch screen block of the display panel, and a second stage of the stage circuit can supply a second touch scan signal to a second gate line included in a second touch screen block of the display panel.

[0013] The touch sensing display device may further include a sensing circuit configured to sense a voltage of a source node of a representative pixel formed in a substrate of the display panel according to a touch scan signal during a touch sensing driving period, thereby sensing a touch input applied to the display panel.

[0014] The representative pixel may include a driving transistor including a source electrode connected to the source node and a gate electrode connected to a gate node. The gate node may include a first conductive pattern and a second conductive pattern. The first conductive pattern faces the source node and is one electrode of a storage capacitor, wherein there is at least one insulating layer between the first conductive pattern and the source node. The second conductive pattern is connected to the first conductive pattern through a contact hole passing through at least one insulating layer. The source node may include a third conductive pattern disposed on at least one insulating layer and being the other electrode of the storage capacitor, and the first conductive pattern may be disposed closer to the substrate than the second conductive pattern and the third conductive pattern.

[0015] In another aspect of the present disclosure, a driving method of a touch-sensing display device (the touch-sensing display device includes: a display panel that alternately performs display driving and touch-sensing driving; and a gate driving circuit that includes stage circuits for driving gate lines of the display panel) includes: outputting a display scan signal generated based on a display carry clock to the display panel during a display frame that defines a display driving period; and outputting a touch scan signal generated based on a touch carry clock to the display panel during a touch frame that defines a touch-sensing driving period, wherein a position where the touch carry clock is generated during a first touch-sensing frame included in the touch-sensing driving period is different from a position where the touch carry clock is generated during a second touch-sensing frame included in the touch-sensing driving period.

[0016] The touch carry clock may be transmitted in a forward direction with respect to the display panel during the first touch-sensing frame, and may be transmitted in a reverse direction with respect to the display panel during the second touch-sensing frame.

[0017] During the first touch-sensing frame, the touch carry clock may be generated from a first gate line of the display panel and may be transmitted until a gate line provided in a central region of the display panel, and during the second touch-sensing frame, the touch carry clock may be generated from a last gate line of the display panel and may be transmitted until a gate line provided in a central region of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this application. The drawings illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. In the drawings:

[0019] Figure 1 is a block diagram showing a touch-sensing display device according to an embodiment;

[0020] Figure 2 is a diagram showing the structure of a pixel array and a source driver integrated circuit (IC);

[0021] Figure 3 is a diagram showing the structure of a pixel and a sensing circuit;

[0022] Figure 4 and Figure 5 is a diagram showing the concept of sensing a change in the source node voltage of a pixel based on a touch input;

[0023] Figure 6 is a diagram showing a cross-sectional structure of a pixel capable of performing touch sensing;

[0024] Figure 7is a diagram showing voltage changes in each of the gate node and the source node of a driving transistor when a touch input is applied;

[0025] Figure 8 and Figure 9 is a diagram showing an example of implementing display driving and touch sensing driving based on time division;

[0026] Figure 10 and Figure 11 is a diagram schematically showing the stage structure of a gate driving circuit;

[0027] Figure 12 is a diagram showing the structure of the nth stage circuit included in the gate driving circuit;

[0028] Figure 13 is a diagram for schematically describing a carry signal transmission method for ensuring a touch scan time according to an embodiment;

[0029] Figure 14 is a diagram for more detailedly describing a carry signal transmission method for ensuring a touch scan time according to an embodiment;

[0030] Figure 15 is a block diagram for describing signal relationships transmitted and received between stages when the driving condition of the gate driving circuit is set to forward;

[0031] Figure 16 is shown in Figure 15 Under the conditions of, a waveform diagram of a carry clock and a scan clock applied to the gate driving circuit during the first display frame;

[0032] Figure 17 is shown in Figure 15 Under the conditions of, a waveform diagram of a carry clock and a scan clock applied to the gate driving circuit during the first touch frame;

[0033] Figure 18 is a block diagram for describing signal relationships transmitted and received between stages when the driving condition of the gate driving circuit is set to reverse;

[0034] Figure 19 is shown in Figure 18 Under the conditions of, a waveform diagram of a carry clock and a scan clock applied to the gate driving circuit during the second display frame;

[0035] Figure 20 is shown in Figure 18 Under the conditions of, a waveform diagram of a carry clock and a scan clock applied to the gate driving circuit during the second touch frame;

[0036] Figure 21It is a diagram for describing the differences between the touch scanning method of the comparative example and the touch scanning method according to the embodiment. Detailed Embodiment

[0037] Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings that illustrate exemplary embodiments of the present disclosure. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present disclosure to those skilled in the art.

[0038] The display device according to the present disclosure can be applied to a television (TV), a video player, a personal computer (PC), a home theater, an electronic device for a vehicle, and a smart phone, but is not limited thereto. The display device according to the present disclosure can be implemented as a light-emitting display device, a quantum dot display (QDD) device, or a liquid crystal display (LCD) device. Hereinafter, for convenience of description, for example, a light-emitting display device that emits light by using an inorganic light-emitting diode or an organic light-emitting diode will be described.

[0039] In the following description, the scan signal (or gate signal) applied to the pixel may swing between a gate-on voltage and a gate-off voltage. The gate-on voltage may be set to a voltage higher than the threshold voltage of the transistor, and the gate-off voltage may be set to a voltage lower than the threshold voltage of the transistor. The transistor may be turned on in response to the gate-on voltage and may be turned off in response to the gate-off voltage. In an N-channel transistor, the gate-on voltage may be a gate high voltage (VGH), and the gate-off voltage may be a gate low voltage (VGL). In a P-channel transistor, the gate-on voltage may be a gate low voltage (VGL), and the gate-off voltage may be a gate high voltage (VGH).

[0040] Figure 1 It is a block diagram showing a touch-sensing display device according to an embodiment, Figure 2 It is a diagram showing the configuration of a pixel array and a source driver integrated circuit (IC).

[0041] As Figure 1 and Figure 2 shown, the touch-sensing display device according to an embodiment may include a display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, and a sensing circuit SU. The sensing circuit SU may be embedded in the data driving circuit 12, but the embodiment is not limited thereto.

[0042] In a screen for displaying an input image on the display panel 10, a first signal line 14 extending in the column direction (or vertical direction) may intersect a second signal line 15 extending in the row direction (or horizontal direction), and a plurality of pixels P may be respectively disposed in a plurality of intersection regions and may be arranged in a matrix type to construct a pixel array. The first signal line 14 may include a plurality of data lines 14A through which a data voltage is supplied and a plurality of reference voltage lines 14B through which a reference voltage is supplied. The reference voltage line 14B may connect the pixel P to the sensing circuit SU and may be referred to as a sensing line. The second signal line 15 may be a gate line through which a scan signal is supplied.

[0043] The pixel array may include a plurality of pixel clusters PL. Here, the pixel cluster PL may not represent a physical signal line, but may be defined as a set of pixels of a row of pixels arranged adjacent to each other in the horizontal direction, or as a pixel block of a row of pixels. The pixels P may be grouped into a plurality of groups and may implement various colors. When a pixel group for implementing a color is defined as a unit pixel UPXL, one unit pixel UPXL may include a red (R) pixel, a green (G) pixel, a blue (B) pixel, and a white (W) pixel. The pixels constructing one unit pixel UPXL may be arranged adjacent to each other in the horizontal direction and may be designed to share the same reference voltage line 14B, and thus, the pixel array may be simplified.

[0044] The timing controller 11 may convert a non-touch driving mode into a touch driving mode or vice versa based on whether there is a touch input, mode selection information about the user, and distance information between the display device and the user. The non-touch driving mode may be a driving mode for performing a display operation and an external compensation operation. The touch driving mode may be a driving mode for further performing a touch sensing operation in addition to the display operation and the external compensation operation.

[0045] In the non-touch driving mode, all frames may be display frames for display driving. On the other hand, in the touch driving mode, a display frame for display driving and a touch frame for touch sensing driving may be alternately executed at a specific time period. Here, the specific time may be one frame time, and in this case, one display frame may be arranged between adjacent touch frames. However, the inventive concept is not limited thereto. The specific time may be several frame times, and in this case, a plurality of display frames may be arranged between adjacent touch frames.

[0046] One frame may include a vertical active period for scanning (or refreshing or updating) new image data DATA and a vertical blank period during which the scanning of the image data DATA is not performed. The display driving may be performed during the vertical active period of the display frame, and the touch sensing driving may be performed during the vertical active period of the touch frame. The external compensation driving may be performed during the vertical blank period of each of the display frame and the touch frame. The external compensation driving may be used to sense device characteristic values of the pixel P (threshold voltage and electron mobility of the driving transistor and threshold voltage of the light emitting device).

[0047] The timing controller 11 may correct the digital video data input from the host system by using a compensation value based on the pixel sensing value according to the external compensation driving, and then may supply the corrected image data DATA to the data driving circuit 12. The timing controller 11 may receive timing signals such as a vertical sync signal Vsync, a horizontal sync signal Hsync, a data enable signal DE, and a dot clock DCLK from the host system to generate a gate timing control signal GDC for controlling the operation timing of the gate driving circuit 13 and a data timing control signal DDC for controlling the operation timing of the data driving circuit 12.

[0048] The timing controller 11 may compare a predetermined reference value with a touch sensing value based on the touch sensing operation to obtain coordinate information about the touch input position, and may transmit the coordinate information to the host system. The host system may execute a touch application corresponding to the coordinate information.

[0049] The data driving circuit 12 may include one or more source driving ICs SDIC. Each of the source driving ICs SDIC may include a latch array, a plurality of digital-to-analog converters DAC respectively connected to the data lines 14A, a plurality of sensing circuits SU respectively connected to the sensing lines 14B, a plurality of multiplexing switches SS selectively connecting the sensing circuits SU to a plurality of analog-to-digital converters ADC, and a shift register SR sequentially turning on the multiplexing switches SS.

[0050] The latch array may latch the corrected image data DATA input from the timing controller 11 based on the data control signal DDC, and may supply the latched image data DATA to the digital-to-analog converter DAC. The digital-to-analog converter DAC may convert the latched image data DATA into a display data voltage, and may supply the display data voltage to the data lines 14A. In the external compensation driving, the digital-to-analog converter DAC may generate a predetermined external sensing data voltage, and may supply the external sensing data voltage to the data lines 14A. In the touch sensing driving, the digital-to-analog converter DAC may generate a predetermined touch driving data voltage, and may supply the touch driving data voltage to the data lines 14A.

[0051] The sensing circuit SU can be used commonly in external compensation driving and touch sensing driving, and thus, a separate touch sensing circuit for touch sensing can be removed. Since touch sensing is possible without a separate touch sensing circuit, the source driver IC can be simplified, and thus, power consumption and manufacturing costs can be reduced.

[0052] The sensing circuit SU can supply a reference voltage Vpre to the sensing line 14B based on a data control signal DDC, or can sample a touch sensing value or a device characteristic sensing value input through the sensing line 14B, and can supply the sampled touch sensing value or device characteristic sensing value to an analog-to-digital converter ADC.

[0053] The analog-to-digital converter ADC can convert the touch sensing value or device characteristic sensing value input from the sensing circuit SU into a digital sensing signal SLV, and can transmit the digital sensing signal SLV to the timing controller 11.

[0054] The gate driving circuit 13 can generate a scan signal ( Figure 3 SCAN) applicable to display driving, external compensation driving, and touch sensing driving based on a gate control signal GDC, and then can supply the scan signal SCAN to the gate line 15. The scan signal can include a display scan signal for display driving, an external sensing scan signal for external compensation driving, and a touch scan signal for touch sensing driving. The on-time period of the display scan signal can correspond to the supply timing of the display data voltage. The on-time period of the external sensing scan signal can correspond to the supply timing of the external sensing data voltage. The on-time period of the touch scan signal can correspond to the supply timing of the touch driving data voltage.

[0055] The gate control signal GDC can include a plurality of scan clocks and a plurality of carry clocks. The on-pulse width of the carry clock can be designed to be narrower in touch sensing driving than in display driving, and thus, the transmission time of the carry signal in the touch frame can be shortened. The time that can be allocated for the output of the touch scan signal in the touch frame can increase in proportion to the reduction in the transmission time of the carry signal, and thus, touch performance can be enhanced.

[0056] Figure 3 is a diagram showing the structure of the pixel P and the sensing circuit SU.

[0057] As Figure 3As shown, the pixel P can be implemented in a structure capable of performing an external compensation operation and a touch sensing operation. The pixel P may include a light-emitting device OLED, a driving transistor DT, a storage capacitor Cst, a first switching transistor ST1, and a second switching transistor ST2. The transistors DT, ST1, and ST2 may each be implemented as thin film transistors (TFTs). The TFTs may be implemented as P-type, N-type, or a hybrid type in which P-type and N-type are jointly provided. In addition, the semiconductor layer of the TFT may include amorphous silicon, polysilicon, or an oxide.

[0058] The light-emitting device OLED may include an anode electrode connected to the source node DTS, a cathode electrode connected to the input terminal of the low-level driving voltage EVSS, and an organic compound layer provided between the anode electrode and the cathode electrode. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), a light-emitting layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL).

[0059] The driving transistor DT may control the level of the drain-source current (hereinafter referred to as Ids) of the driving transistor DT input to the light-emitting device OLED based on its gate-source voltage (hereinafter referred to as Vgs). The driving transistor DT may include a gate electrode connected to the gate node DTG, a drain electrode connected to the input terminal of the high-level driving voltage EVDD, and a source electrode connected to the source node DTS.

[0060] The storage capacitor Cst may be connected between the gate node DTG and the source node DTS, and may hold the gate-source voltage of the driving transistor DT during a predetermined period.

[0061] The first switching transistor ST1 may electrically connect the data line 14A to the gate node DTG based on the scan signal SCAN from the gate line 15, and may allow the data voltage Vdata to be charged into the gate node DTG. The first switching transistor ST1 may include a gate electrode connected to the gate line 15, a drain electrode connected to the data line 14A, and a source electrode connected to the gate node DTG.

[0062] The second switching transistor ST2 may electrically connect the source node DTS to the sensing line 14B based on the scan signal SCAN, and thus may allow the reference voltage Vpre to be charged into the source node DTS. The second switching transistor ST2 may allow the source node voltage corresponding to the Ids of the driving transistor DT to be charged into the line capacitor LCa of the sensing line 14B. The second switching transistor ST2 may include a gate electrode connected to the gate line 15, a drain electrode connected to the sensing line 14B, and a source electrode connected to the source node DTS.

[0063] The sensing circuit SU can be implemented as a voltage sensing type. The sensing circuit SU can be used to sense the voltage stored in the line capacitor LCa of the sensing line 14B, and may include a reference voltage control switch SW1, a sampling switch SW2, and a sample and hold unit S / H.

[0064] Based on the reference control voltage signal SPRE, the reference voltage control switch SW1 can be turned on, and the input terminal of the reference voltage Vpre can be connected to the sensing line 14B. Based on the sampling control signal SAM, the sampling switch SW2 can be turned on, and the sensing line 14B can be connected to the sample and hold unit S / H.

[0065] When the driving transistor DT deteriorates or there is a touch input, the Vgs of the driving transistor DT may change, and thus, the Ids of the driving transistor DT may change. The voltage of the source node DTS of the driving transistor DT can change based on the level of the Ids of the driving transistor DT. When the second switching transistor ST2 is turned on, the voltage of the source node DTS of the driving transistor DT can be stored in the line capacitor LCa of the sensing line 14B. When the sampling switch SW2 is turned on, the sample and hold unit S / H can sample and hold the voltage of the source node DTS of the driving transistor DT stored in the line capacitor LCa of the sensing line 14B, and then, the sampled voltage can be transmitted to the analog-to-digital converter ADC.

[0066] Figure 4 and Figure 5 FIG. is a diagram showing the concept of sensing the change in the source node voltage of a pixel based on a touch input.

[0067] Hereinafter, reference will be made to Figure 4 and Figure 5 to describe the principle of sensing a touch input in a touch sensing display device according to the present embodiment. When a touch input object such as a finger touches the screen of the display panel in a state where the Vgs of the driving transistor is set to the difference voltage between the touch driving data voltage and the reference voltage, the Vgs of the driving transistor can be reduced by the touch capacitor Ctouch between the touch input object and the driving transistor.

[0068] The touch capacitor Ctouch can be a capacitive capacitor between the touch input object and the gate node DTG of the driving transistor. When the Vgs of the driving transistor is reduced, the Ids of the driving transistor can be reduced, and thus, based on the change in the source node voltage Vs of the driving transistor between the pixel touched by the touch input object and the non-touched pixel, it can be determined whether there is a touch input. According to the TFT current formula, the Ids can be proportional to the square of the Vgs.

[0069] Therefore, even when the change amount of Vgs based on touch input is small, Ids can be amplified, and thus, the source node voltage Vs can be quickly shifted, thereby enhancing touch sensing performance. In Figure 5 ,"Vg" can represent the gate node voltage of the driving transistor.

[0070] Figure 6 is a diagram showing a cross-sectional structure of a pixel P capable of performing touch sensing.

[0071] Since the area in contact with the touch input object is much larger than the area occupied by one pixel, the touch sensing device according to the present embodiment can sense touch input related to only some pixels (hereinafter referred to as representative pixels), and thus, the touch sensing period can be shortened, thereby improving the touch reporting rate.

[0072] As Figure 6 shown, the pixel P may include a light emitting portion EP for displaying an image and a circuit unit CP for not displaying an image. The light emitting portion EP of the pixel P may include Figure 3 a light emitting device OLED. The circuit unit CP of the representative pixel P may include Figure 3 a driving transistor DT, a storage capacitor Cst, a first switching transistor ST1, and a second switching transistor ST2.

[0073] The circuit unit CP of the pixel P may include an insulating layer BUF, GI, and OC and conductive patterns M1, M2, and PXL stacked on a substrate GLS. When a touch is input, as the Vgs of the driving transistor increases, the touch sensing performance can increase. For this purpose, it may be preferable that the gate node connected to the gate electrode of the driving transistor is set closer to the substrate GLS than the source node connected to the source electrode of the driving transistor. Therefore, the reactivity of the touch input can be improved.

[0074] In addition, since the source node of the driving transistor is connected to the internal capacitor of the light emitting device, when the source node is set closer to the substrate GLS than the gate node, the change in Vgs corresponding to the touch input (i.e., the reactivity of the touch input) may be very small, and thus may not be applicable to touch sensing. The internal capacitor of the light emitting device may be a capacitor between the anode electrode PXL and the cathode electrode.

[0075] The array structure of the pixel P will be described in detail below with reference to Figure 6

[0076] ​The voltage of the source node DTS of the pixel P can be a target for touch sensing. The pixel P can include a gate node DTG that is electrically disconnected from the source node DTS. The gate node DTG can include a first conductive pattern M1 and a second conductive pattern M2. The first conductive pattern M1 faces the source node DTS, and one or more insulating layers GI and BUF are located therebetween, and it is an electrode of the storage capacitor Cst. The second conductive pattern M2 is connected to the first conductive pattern M1 through a first contact hole CH1 that penetrates the insulating layers GI and BUF.

[0077] The source node DTS can be a third conductive pattern M3 disposed on the insulating layers GI and BUF, and it is the other electrode of the storage capacitor Cst. In this case, among the first conductive pattern M1, the second conductive pattern M2, and the third conductive pattern M3, the first conductive pattern M1 can be disposed closest to the substrate GLS. That is, the first conductive pattern M1 formed close to the substrate GLS can be used as a touch electrode, and in addition, can be used as a light-shielding pattern. The first conductive pattern M1 can block external light incident on the semiconductor layer ACT of the driving transistor, thereby preventing the characteristic values of the driving transistor from being deteriorated by the external light.

[0078] The first conductive pattern M1 can be covered by the buffer insulating layer BUF and the gate insulating layer GI, and can be electrically connected to the second conductive pattern M2 disposed on the gate insulating layer GI through the first contact hole CH1. The second conductive pattern M2 can construct the gate electrode of the driving transistor.

[0079] The third conductive pattern M3, which is the other electrode of the storage capacitor Cst, can be disposed on the first conductive pattern M1, and the buffer insulating layer BUF and the gate insulating layer GI are located therebetween. The third conductive pattern M3 can include the same material as that of the second conductive pattern M2, and can be formed in the same layer as the second conductive pattern M2. The source electrode of the driving transistor can be formed by providing conductivity to the semiconductor layer ACT or by stacking a conductive layer on the semiconductor layer ACT, and can be electrically connected to the third conductive pattern M3 through a contact hole.

[0080] The second conductive pattern M2 and the third conductive pattern M3 can be covered by a planarization layer OC, and the anode electrode PXL of the light-emitting device can be formed on the planarization layer OC. Although not shown, the source node DTS of the driving transistor and the anode electrode PXL of the light-emitting device can be electrically connected to each other through a contact hole that penetrates the planarization layer OC.

[0081] Figure 7 It is a diagram showing voltage changes in each of the gate node and the source node of the driving transistor when a touch input is applied.

[0082] As Figure 7As shown, a touch input corresponding to a pixel can be sensed during the conduction pulse period of the touch scan signal T-SCAN. In response to the touch scan signal T-SCAN, a touch driving data voltage can be applied to the gate node DTG of the driving transistor. A reference voltage Vpre can be applied to the source node DTS of the driving transistor. When the driving transistor is turned on, Ids can flow in the driving transistor.

[0083] When a touch input is received at the first time t1 during the conduction pulse period, Ids1 corresponding to Vgs1 can flow in the driving transistor. The Ids1 of the driving transistor can be less than Ids2 when there is no touch input. In other words, the Ids1 of the first representative pixel corresponding to the position where a touch input exists can be less than the Ids2 of the second representative pixel corresponding to the position where there is no touch input.

[0084] When touch sensing is performed at the second time t2 during the conduction pulse period, the voltage of the source node DTS of the driving transistor can be sensed as Vsen based on Ids1. The Vsen of the driving transistor can be less than Vsen' based on Ids2 when there is no touch input. In other words, the Vsen of the first representative pixel corresponding to the position where a touch input exists can be less than the Vsen' of the second representative pixel corresponding to the position where there is no touch input. Therefore, it can be determined whether there is a touch input corresponding to the pixel based on the difference between Vsen and Vsen', where Vsen is the voltage of the source node DTS of the driving transistor.

[0085] Figure 8 and Figure 9 are diagrams showing examples of implementing display driving and touch sensing driving based on time division.

[0086] As Figure 8 shown, a display frame D-Frame for display driving and a touch frame T-Frame for touch sensing driving can be alternated. The touch frame T-Frame can be arranged between two adjacent display frames D-Frame.

[0087] Display driving can be used to write image data to all pixels P of the display panel to update the image, and can be performed during the vertical active period of the display frame D-Frame. Touch sensing driving can be performed during the vertical active period of the touch frame T-Frame, and since the touch sensing driving is only performed on representative pixels P, a longer time can be ensured for touch sensing. Since a longer time is allocated for touch sensing, the touch sensing period can be shortened, and the touch reporting rate can be increased.

[0088] Furthermore, the external compensation driving may be performed in a vertical blank period of each of the display frame D-Frame and the touch frame T-Frame.

[0089] like Figure 9 As shown, the screen of the display panel can be divided into a plurality of touch screen blocks TBLK, and the touch screen block TBLK unit can sense a touch input. Each of the touch screen blocks TBLK can include a plurality of pixel set lines PL1 to PLn, and one of the pixel set lines PL1 to PLn in each touch screen block TBLK can be constructed with a representative pixel.

[0090] The gate driving circuit may apply the display scan signal D-SCAN to all pixels in the display frame D-Frame, and may apply the touch scan signal T-SCAN to a representative pixel in the touch frame T-Frame. The on-pulse width PW1 of the touch scan signal T-SCAN may be wider than the on-pulse width PW2 of the display scan signal D-SCAN. Since the on-pulse width PW1 of the touch scan signal T-SCAN is wider, the touch sensing performance of the touch screen block TBLK may be enhanced.

[0091] Figure 10 and Figure 11 Schematically shows the stage structure of the gate driving circuit.

[0092] like Figure 10 and Figure 11 As shown, the gate driving circuit 13 may include a first stage circuit STG(1) to a kth stage circuit STG(k), a gate driving voltage line 131 and a clock signal line 132. In addition, the gate driving circuit 13 may further include a dummy stage circuit DST1, which is arranged at the previous stage relative to the first stage circuit STG(1).

[0093] The gate drive voltage line 131 may transmit a high level voltage GVDD and a low level voltage GVSS supplied from a power supply circuit (not shown) to the first stage circuit STG(1) to the kth stage circuit STG(k) and the dummy stage circuit DST1. In the present embodiment, the gate drive voltage line 131 may include two high level voltage lines that transmit a first high level voltage GVDD1 and a second high level voltage GVDD2 having different voltage levels, respectively, and three low level voltage lines that transmit a first low level voltage GVSS1, a second low level voltage GVSS2, and a third low level voltage GVSS3 having different voltage levels, respectively. However, this may be merely an embodiment, and the number of voltage lines included in the gate drive voltage line 131 may vary.

[0094] The clock signal line 132 can transmit a plurality of clock signals (e.g., carry clock signal CRCLK and scan clock signal SCCLK) supplied from the timing controller 11 to the first-stage circuit STG(1) to the k-stage circuit STG(k) and the virtual stage circuit DST1.

[0095] The carry clock signal CRCLK can be implemented as a first carry clock to a third carry clock CRCLK1, CRCLK2, and CRCLK3 having different phases, but is not limited thereto. The first carry clock to the third carry clock CRCLK1, CRCLK2, and CRCLK3 can be phase-shifted while swinging between the gate-on voltage and the gate-off voltage. The first carry clock to the third carry clock CRCLK1, CRCLK2, and CRCLK3 can be respectively supplied to the first-stage circuit STG(1) to the k-stage circuit STG(k) through the first carry clock line to the third carry clock line 132-1, 132-2, and 132-3. Each of the first-stage circuit STG(1) to the k-stage circuit STG(k) can receive one of the first carry clock to the third carry clock CRCLK1, CRCLK2, and CRCLK3 based on a phase sequence scheme, and can output carry signals C(1) to C(K) corresponding to the received carry clock. Each of the first-stage circuit STG(1) to the k-stage circuit STG(k) can be activated in the stage operation based on the previous carry signal.

[0096] The scan clock signal SCCLK can be implemented as a first scan clock SCLK1 to a twelfth scan clock SCLK12 having different phases, but is not limited thereto. The first scan clock SCLK1 to the twelfth scan clock SCLK12 can be phase-shifted while swinging between the gate-on voltage and the gate-off voltage. The first scan clock SCLK1 to the twelfth scan clock SCLK12 can be respectively supplied to the first-stage circuit STG(1) to the k-stage circuit STG(k) through the first scan clock line 232-1 to the twelfth scan clock line 232-12. Each of the first-stage circuit STG(1) to the k-stage circuit STG(k) can receive one of the first scan clock SCLK1 to the twelfth scan clock SCLK12 based on a phase sequence scheme, and can output scan signals SCOUT(1) to SCOUT(n) corresponding to the received scan clock. Each of the first-stage circuit STG(1) to the k-stage circuit STG(k) can be activated in the stage operation based on the previous carry signal.

[0097] Each stage circuit can output four gate signals SCOUT and one carry signal C. For example, the first stage circuit STG(1) can output the first gate signal SCOUT(1) to the fourth gate signal SCOUT(4) and the first carry signal C(1), and the second stage circuit STG(2) can output the fifth gate signal SCOUT(5) to the eighth gate signal SCOUT(8) and the second carry signal C(2).

[0098] The number of gate signals output from the first stage circuit STG(1) to the k-th stage circuit STG(k) can match the number of gate lines provided in the display panel. The number “k” of stage circuits can be 1 / 4 of the number “n” of gate lines. That is to say, k can be n / 4 (i.e., k = n / 4).

[0099] As described above, when the number “k” of stage circuits is designed to be 1 / 4 of the number “n” of gate lines, the mounting area of the gate driving circuit 13 can be reduced, and thus, the bezel size of the display panel can be reduced.

[0100] Figure 12 FIG. is a diagram showing the configuration of the n-th stage circuit included in the gate driving circuit.

[0101] As Figure 12 shown, the n-th stage circuit may include a Q node Q_o, a QH node Qh_o, and a QB node Qb_o. The n-th stage circuit may include an M and Q node controller BK1, a QB node controller BK2, and a signal output unit BK3. The n-th stage circuit may represent any stage included in the gate driving circuit.

[0102] The M and Q node controller BK1 may start operating based on a line selection signal LSP applied through a line selection signal line. The M and Q node controller BK1 may charge the Q node Q_o to the first high-level voltage GVDD1 level in response to the input of the previous carry signal C(n - 2), and may discharge the Q node Q_o to the third high-level voltage GVSS3 level in response to the input of a start signal VST applied through a start signal line. In addition, the M and Q node controller BK1 may charge the Q node Q_o to the forward voltage GVDD_F level applied through a forward voltage line in response to the input of the previous carry signal C(n - 2), and may charge the Q node Q_o to the reverse voltage GVDD_R level applied through a reverse voltage line in response to the input of the next carry signal C(n + 2). To this end, the M and Q node controller BK1 may include a plurality of transistors, and this will be described below.

[0103] The A transistor Ta and the B transistor Tb can transfer the previous carry signal C(n - 2) to the M node M_o in response to the line selection signal LSP. The gate electrodes of each of the A transistor Ta and the B transistor Tb can be commonly connected to the line selection signal line through which the line selection signal LSP is applied. The first electrode of the A transistor Ta can be connected to the previous carry signal line through which the previous carry signal C(n - 2) is applied, the first electrode of the B transistor Tb can be connected to the second electrode of the A transistor Ta, and the second electrode of the B transistor Tb can be connected to the M node M_o. The C transistor can include a gate electrode connected to the M node M_o, a first electrode connected to the first high-level voltage line that transmits the first high-level voltage GVDD1, and a second electrode connected to the second electrode of the A transistor Ta and the first electrode of the B transistor Tb.

[0104] The 1A transistor T1a and the first transistor T1 can transfer the forward voltage GVDD_F to the Q node Q_o in response to the previous carry signal C(n - 2). The gate electrodes of each of the 1A transistor T1a and the first transistor T1 can be commonly connected to the previous carry signal line through which the previous carry signal C(n - 2) is applied. The first transistor T1 can include a first electrode connected to the forward voltage line that transmits the forward voltage GVDD_F and a second electrode connected to the QH node Qh_o. The 1A transistor T1a can include a first electrode connected to the QH node Qh_o and a second electrode connected to the Q node Q_o.

[0105] The 1B transistor T1b and the 1C transistor T1c can transfer the first high-level voltage GVDD1 to the Q node Q_o in response to the voltage of the M node M_o. The 1B transistor T1b can include a gate electrode connected to the M node M_o, a first electrode connected to the first high-level voltage line that transmits the first high-level voltage GVDD1, and a second electrode connected to the first electrode of the 1C transistor T1c. The 1C transistor T1c can include a gate electrode connected to the reset signal line through which the reset signal RESET is applied, a first electrode connected to the second electrode of the 1B transistor T1b, and a second electrode connected to the Q node Q_o.

[0106] The 3NB transistor T3nb and the 3NC transistor T3nc can transmit a third low-level voltage GVSS3 to the Q node Q_o in response to a start signal VST. The gate electrodes of each of the 3NB transistor T3nb and the 3NC transistor T3nc can be commonly connected to a start signal line. The 3NB transistor T3nb can include a first electrode connected to the Q node Q_o and a second electrode connected to the QH node Qh_o and the first electrode of the 3NC transistor T3nc. The 3NC transistor T3nc can include a first electrode connected to the QH node Qh_o and a second electrode connected to a third low-level voltage line that transmits the third low-level voltage GVSS3.

[0107] The 3N transistor T3n and the 3NA transistor T3na can transmit a reverse voltage GVDD_R to the QH node Qh_o and the Q node Q_o in response to a next carry signal C(n+2). The gate electrodes of each of the 3N transistor T3n and the 3NA transistor T3na can be commonly connected to a next carry signal line that transmits the next carry signal C(n+2). The 3N transistor T3n can include a first electrode connected to the Q node Q_o and a second electrode connected to the QH node Qh_o and the first electrode of the 3NA transistor T3na. The 3NA transistor T3na can include a first electrode connected to the second electrode of the 3N transistor T3n and a second electrode connected to a reverse voltage line that transmits the reverse voltage GVDD_R.

[0108] The 3Q transistor T3q can transmit a first high-level voltage GVDD1 to the QH node Qh_o in response to the voltage of the Q node Q_o. The 3Q transistor T3q can be formed in a dual-gate type to minimize the occurrence of leakage current. The 3Q transistor T3q can include a first electrode connected to a first high-level voltage line and a second electrode connected to the QH node Qh_o.

[0109] The third transistor T3 and the 3A transistor T3a can transmit a third low-level voltage GVSS3 to the QH node Qh_o and the Q node Q_o in response to the voltage of the QB node Qb_o. The gate electrodes of each of the third transistor T3 and the 3A transistor T3a can be commonly connected to the QB node Qb_o. The third transistor T3 can include a first electrode connected to the Q node Q_o and a second electrode connected to the first electrode of the 3A transistor T3a. The 3A transistor T3a can include a first electrode connected to the QH node Qh_o and the second electrode of the third transistor T3 and a second electrode connected to a third low-level voltage line that transmits the third low-level voltage GVSS3.

[0110] The QB node controller BK2 can charge the voltage of the QB node Qb_o based on the voltage of the Q node Q_o. To this end, the QB node controller BK2 can include a plurality of transistors, and this will be described below.

[0111] The 41st transistor T41 can include a gate electrode and a first electrode connected to a second high-level voltage line for transmitting a second high-level voltage GVDD2, and a second electrode connected to the gate electrode of the fourth transistor T4 and the first electrode of the 4Q transistor T4q. The 41st transistor T41 can be formed in a dual-gate (double-gate) type to minimize the occurrence of leakage current. The fourth transistor T4 can transmit the second high-level voltage GVDD2 to the QB node Qb_o in response to the second high-level voltage GVDD2. The fourth transistor T4 can include a first electrode connected to the second high-level voltage line and a second electrode connected to the QB node Qb_o. The 4Q transistor T4q can transmit the second low-level voltage GVSS2 to the gate electrode of the fourth transistor T4 in response to the voltage of the Q node Q_o. The 4Q transistor T4q can include a gate electrode connected to the Q node Q_o, a first electrode connected to the gate electrode of the fourth transistor T4, and a second electrode connected to the second low-level voltage line.

[0112] The 5Q transistor T5q can transmit the third low-level voltage GVSS3 to the QB node Qb_o in response to the voltage of the Q node Q_o. The 5Q transistor T5q can include a gate electrode connected to the Q node Q_o, a first electrode connected to the QB node Qb_o, and a second electrode connected to the third low-level voltage line.

[0113] In addition, the QB node controller BK2 can transfer the third low-level voltage GVSS3 to the QB node Qb_o by applying a forward voltage GVDD_F or a reverse voltage GVDD_R in response to the previous carry signal C(n - 2) or the next carry signal C(n + 2). The 5S transistor T5s can transfer the forward voltage GVDD_F to the gate electrode of the fifth transistor T5 in response to the previous carry signal C(n - 2). The 5S transistor T5s can include a gate electrode connected to the previous carry signal line, a first electrode connected to the gate electrode of the fifth transistor T5, and a second electrode connected to the forward voltage line. The 5N transistor T5n can transfer the reverse voltage GVDD_R to the gate electrode of the fifth transistor T5 in response to the next carry signal C(n + 2). The 5N transistor T5n can include a gate electrode connected to the next carry signal line, a first electrode connected to the gate electrode of the fifth transistor T5, and a second electrode connected to the reverse voltage line. The 5H transistor T5h can transfer the third low-level voltage GVSS3 to the gate electrode of the fifth transistor T5 in response to the voltage of the QB node Qb_o. The 5H transistor T5h can include a gate electrode connected to the QB node Qb_o, a first electrode connected to the gate electrode of the fifth transistor T5, and a second electrode connected to the third low-level voltage line.

[0114] In addition, the QB node controller BK2 can transfer the third low-level voltage GVSS3 to the QB node Qb_o in response to the reset signal RESET and the voltage of the M node M_o. The 5A transistor T5a can include a gate electrode connected to the reset signal line, a first electrode connected to the QB node Qb_o, and a second electrode connected to the first electrode of the 5B transistor T5b. The 5B transistor T5b can include a gate electrode connected to the M node M_o, a first electrode connected to the second electrode of the 5A transistor T5a, and a second electrode connected to the third low-level voltage line.

[0115] The signal output unit BK3 can output the carry clock CRCLK(n) as the carry signal C(n) of the on-voltage, and the first scan clock SCCLK(n) to the fourth scan clock SCCLK(n + 3) as the first scan signal SCOUT(n) to the fourth scan signal SCOUT(n + 3) of the on-voltage, while the Q node Q_o is charged at the on-voltage level. The signal output unit BK3 can output the third low-level voltage GVSS3 as the carry signal C(n) of the off-voltage and the second low-level voltage GVSS2 as the first scan signal SCOUT(n) to the fourth scan signal SCOUT(n + 3) of the off-voltage, while the QB node Qb_o is charged at the on-voltage level. For this purpose, the signal output unit BK3 can include a plurality of transistors and a plurality of capacitors, and this will be described below.

[0116] The sixth CR transistor T6cr and the seventh CR transistor T7cr can output a carry signal C(n). The sixth CR transistor T6cr can include a gate electrode connected to the Q node Q_o, a first electrode connected to a carry clock line for transmitting a carry clock CRCLK(n), and a second electrode connected to a carry signal output line. The carry capacitor Cap_CR can bootstrap the Q node Q_o based on the carry clock CRCLK(n). The carry capacitor Cap_CR can include a first electrode and a second electrode respectively connected to the gate electrode and the second electrode of the sixth CR transistor T6cr. The seventh CR transistor T7cr can include a gate electrode connected to the QB node Qb_o, a first electrode connected to the carry signal output line, and a second electrode connected to a third low-level voltage line.

[0117] Four sixth transistors T6 and four seventh transistors T7 can output a first scan signal SCOUT(n) to a fourth scan signal SCOUT(n + 3). The four sixth transistors T6 can respectively include a gate electrode connected to the Q node Q_o, first electrodes separately connected to a first scan clock line to a fourth scan clock line, and second electrodes separately connected to a first scan signal output line to a fourth scan signal output line. Four scan capacitors Cap_SC can bootstrap the Q node Q_o based on a first scan clock SCCLK(n) to a fourth scan clock SCCLK(n + 3). The four scan capacitors Cap_SC can each include a first electrode and a second electrode respectively connected to the gate electrode and the second electrode of each of the four sixth transistors T6. The four seventh transistors T7 can respectively include a gate electrode connected to the QB node Qb_o, first electrodes separately connected to a scan signal output line, and second electrodes commonly connected to a first low-level voltage line.

[0118] Figure 13 is a diagram for schematically describing a carry signal transmission method for ensuring a touch scan time according to an embodiment, and Figure 14 is a diagram for more detailedly describing a carry signal transmission method for ensuring a touch scan time according to an embodiment.

[0119] As Figure 13 shown, an embodiment can divide each of a first touch frame 1_T-Frame and a second touch frame 2_T-Frame into 1 / 2 to perform touch sensing, thereby ensuring a touch scan time. The first touch frame 1_T-Frame can be arranged after or before a first display frame 1_D-Frame, and the second touch frame 2_T-Frame can be arranged after or before a second display frame 2_D-Frame.

[0120] In an embodiment, the method of transmitting the carry signal of the gate driving circuit may be changed to divide each of the first touch frame 1_T-Frame and the second touch frame 2_T-Frame into 1 / 2. This will be described below with reference to Figure 14 as follows.

[0121] First, the gate driving circuit according to the embodiment may be operated such that during the first touch frame 1_T-Frame, touch sensing is performed on the upper 1 / 2 region of the display panel (see the sensing region). The gate driving circuit may be set to a forward condition such that a carry signal C is generated in the upper region of the display panel, and may be set such that a start signal VST is applied to the first-stage circuit provided with the first gate line (or a first virtual stage circuit arranged at the front end with respect to the first-stage circuit).

[0122] In this case, the gate driving circuit may start operating from the first-stage circuit to output the carry signal C, and although not shown, a scan signal may be output such that touch sensing is performed within the touch sensing time T. In addition, such an operation may be sequentially performed from the first-stage circuit provided with the first gate line of the display panel until the f-stage circuit where the gate line is provided in the central region of the display panel.

[0123] Subsequently, the gate driving circuit according to the embodiment may be operated such that during the second touch frame 2_T-Frame, touch sensing is performed on the lower 1 / 2 region of the display panel (see the sensing region). The gate driving circuit may be set to a reverse condition such that a carry signal C is generated in the lower region of the display panel, and may be set such that a start signal VST is applied to the k-stage circuit provided with the last gate line (or a k virtual stage circuit arranged at the lower end with respect to the k-stage circuit).

[0124] In this case, the gate driving circuit may start operating from the k-stage circuit to output the carry signal C, and although not shown, a scan signal may be output such that touch sensing is performed within the touch sensing time T. In addition, such an operation may be sequentially performed from the k-stage circuit provided with the last gate line of the display panel until the (f + 1)-stage circuit where the gate line is provided in the central region of the display panel.

[0125] Hereinafter, the gate driving circuit implemented based on the above Figures 9 to 12 stage and the operations and signals required for driving the gate driving circuit will be described in combination with each other. However, the gate driving circuit for implementing the embodiment may be implemented in various types, but the embodiment is not limited thereto.

[0126] Figure 15It is a block diagram for describing the signal relationships transmitted and received between stages when the driving conditions of the gate driving circuit are set to the forward direction. Figure 16 It shows during Figure 15 the conditions, the waveforms of the carry clock and the scan clock applied to the gate driving circuit during the first display frame, and Figure 17 It shows during Figure 15 the conditions, the waveforms of the carry clock and the scan clock applied to the gate driving circuit during the first touch frame.

[0127] As Figure 15 shown, when the driving conditions of the gate driving circuit are set to the forward direction, a forward voltage with a high voltage level can be applied to the forward voltage line FW connected to stages STG(a) to STG(c). On the other hand, a reverse voltage with a low voltage level (or ground voltage level) can be applied to the reverse voltage line BW connected to stages STG(a) to STG(c).

[0128] When the driving conditions of the gate driving circuit are set to the forward direction, the set signal SET can be transmitted (in the forward direction) from the A-stage STG(a) to the B-stage STG(b), and from the B-stage STG(b) to the C-stage STG(c). On the other hand, the reset signal RESET can be transmitted (in the reverse direction) from the C-stage STG(c) to the B-stage STG(b), and from the B-stage STG(b) to the A-stage STG(a).

[0129] As Figure 16 shown, when the driving conditions of the gate driving circuit are set to the forward direction, the carry clocks CRCLK1 to CRCLK3 and the scan clocks SCLK1 to SCLK12 can be sequentially generated in the forward direction. For example, the carry clocks CRCLK1 to CRCLK3 can be generated in the order of the first carry clock CRCLK1, the second carry clock CRCLK2, and the third carry clock CRCLK3. In addition, the scan clocks SCLK1 to SCLK12 can be generated in the order of the first scan clock SCLK1, the second scan clock SCLK2... and the twelfth scan clock SCLK12.

[0130] The carry clocks CRCLK1 to CRCLK3 can be generated so that each has a conduction pulse width of at least two horizontal periods 2H. In this case, the carry clocks CRCLK1 to CRCLK3 can be generated such that the conduction pulse width generation times do not overlap on each of the off-pulse widths of at least two horizontal periods 2H. For example, the off-pulse interval time of at least two horizontal periods 2H can be between the conduction pulses of the first carry clock CRCLK1 and the second carry clock CRCLK2.

[0131] It is possible to generate scan clocks SCLK1 to SCLK12 such that each has a conduction pulse width of at least two horizontal periods 2H. In this case, it is possible to generate scan clocks SCLK1 to SCLK12 such that the conduction pulse width generation times are sequentially overlapped on each horizontal period that is half of the two horizontal periods 2H. For example, the conduction pulse overlap time of at least one horizontal time can be between the conduction pulses of the first scan clock SCLK1 and the second scan clock SCLK2.

[0132] As Figure 14 and Figure 16 shown, the first display frame 1_D-Frame can be a period during which image data is written to all pixels and the image is displayed. The gate driver circuit can be set to a forward condition and can output display scan signals (e.g., Figure 9 D-SCAN) based on carry clocks CRCLK1 to CRCLK3 and scan clocks SCLK1 to SCLK12 during the first display frame 1_D-Frame such that the image data is written to all pixels P of the display panel.

[0133] As Figure 14 and Figure 17 shown, the first touch frame 1_T-Frame can be a period during which touch sensing driving is performed only on representative pixels of the display panel. The gate driver circuit can be set to a forward condition and can output touch scan signals (e.g., Figure 9 T-SCAN) based on carry clocks CRCLK1 to CRCLK3 and scan clocks SCLK1 to SCLK12 during the first touch frame 1_T-Frame such that touch input is sensed from the representative pixels of the display panel.

[0134] In addition, in Figure 17 , an example is shown in which the carry clocks CRCLK1 to CRCLK3 have a conduction pulse width of one horizontal period 1H to transmit a carry signal C and have a conduction pulse width of four horizontal periods 4H to perform touch sensing time T, but the embodiments are not limited thereto. In addition, in Figure 17 , an example is shown in which touch sensing is performed based on the first scan clock SCLK1, the fifth scan clock SCLK5, and the ninth scan clock SCLK9, but the embodiments are not limited thereto.

[0135] Figure 18 is a block diagram for describing the signal relationship transmitted and received between stages when the driving condition of the gate driver circuit is set to reverse, Figure 19 is a waveform diagram showing the carry clocks and scan clocks applied to the gate driver circuit during the second display frame under the conditions of Figure 18 , and Figure 20 is a waveform diagram showing the carry clocks and scan clocks applied to the gate driver circuit during the second display frame under the conditions ofFigure 18 Waveform diagrams of the carry clock and the scan clock applied to the gate drive circuit during the second touch frame under the following conditions.

[0136] As Figure 18 shown, when the driving condition of the gate drive circuit is set to reverse, a forward voltage having a low voltage level (or a ground voltage level) can be applied to the forward voltage line FW connected to stages STG(a) to STG(c). On the other hand, a reverse voltage having a high voltage level can be applied to the reverse voltage line BW connected to stages STG(a) to STG(c).

[0137] When the driving condition of the gate drive circuit is set to reverse, the set signal SET can be transmitted (in the reverse direction) from the C-th stage STG(c) to the B-th stage STG(b), and from the B-th stage STG(b) to the A-th stage STG(a). On the other hand, the reset signal RESET can be transmitted (in the forward direction) from the A-th stage STG(a) to the B-th stage STG(b), and from the B-th stage STG(b) to the C-th stage STG(c).

[0138] As Figure 19 shown, when the driving condition of the gate drive circuit is set to reverse, the carry clocks CRCLK1 to CRCLK3 and the scan clocks SCLK1 to SCLK12 can be sequentially generated in the reverse direction. For example, the carry clocks CRCLK1 to CRCLK3 can be generated in the order of the third carry clock CRCLK3, the second carry clock CRCLK2, and the first carry clock CRCLK1. In addition, the scan clocks SCLK1 to SCLK12 can be generated in the order of the twelfth scan clock SCLK12, the eleventh scan clock SCLK11... and the first scan clock SCLK1.

[0139] The generation conditions of the carry clocks CRCLK1 to CRCLK3 and the scan clocks SCLK1 to SCLK12 can be as described above with reference to Figure 16 and Figure 17 but only the generation order can be changed from the forward direction to the reverse direction.

[0140] As Figure 14 and Figure 19 shown, the second display frame 2_D-Frame can be a period during which image data is written in all pixels and the image is displayed. The gate drive circuit can be set to the reverse condition, and display scan signals (e.g., Figure 9 D-SCAN) can be output based on the carry clocks CRCLK1 to CRCLK3 and the scan clocks SCLK1 to SCLK12 during the second display frame 2_D-Frame, so that the image data is written into all pixels P of the display panel.

[0141] As Figure 14 and Figure 20 shown, the second touch frame 2_T-Frame may be a period during which touch sensing driving is performed only on representative pixels of the display panel. The gate driving circuit may be set to a reverse condition, and may output touch scan signals (e.g., Figure 9 T-SCAN) based on carry clocks CRCLK1 to CRCLK3 and scan clocks SCLK1 to SCLK12 during the second touch frame 2_T-Frame, such that a touch input is sensed from the representative pixels of the display panel.

[0142] In addition, in Figure 20 , an example is shown in which the carry clocks CRCLK1 to CRCLK3 have a conduction pulse width of one horizontal period 1H to transmit a carry signal C and have a conduction pulse width of four horizontal periods 4H to perform a touch sensing time T, but the embodiment is not limited thereto. In addition, in Figure 20 , an example is shown in which touch sensing is performed based on the fourth scan clock SCLK4, the eighth scan clock SCLK8, and the twelfth scan clock SCLK12, but the embodiment is not limited thereto.

[0143] In addition, in Figure 16 , Figure 17 , Figure 19 and Figure 20 , an example is shown in which the carry clocks CRCLK1 to CRCLK3 and the scan clocks SCLK1 to SCLK12 are generated at levels between the gate high voltage Vgh and the gate low voltage Vgl, but the embodiment is not limited thereto.

[0144] Figure 21 is a diagram for describing the difference between the touch scan method of the comparative example and the touch scan method of the embodiment.

[0145] Figure 21 The comparative example of

[0146] may be the following method, which, during the touch frame T-Frame, starts operating from the first-stage circuit provided with the first gate line of the display panel, outputs a carry signal, and sequentially transmits the carry signal until the k-th stage circuit provided with the last gate line.

[0146] Comparing the comparative example of Figure 21 with the embodiment, the embodiment may reduce the carry signal transmission time CT by approximately half (CT / 2) compared to the comparative example. The reason may be that the embodiment drives the gate driving circuit such that the touch frame is divided into a first touch frame 1_T-Frame and a second touch frame 2_T-Frame, and the carry signal is divided into 1 / 2 during the two divided frames and is transmitted from the upper region to the central region or from the lower region to the central region.

[0147] In an embodiment, although the touch frame is divided into two touch frames, since the carry signal transmission time CT is reduced by approximately half (CT / 2), the time can be more sufficient than in the comparative example, and thus, the sensitivity based on the touch sensing operation can be enhanced. Further, touch data can be obtained, and further, the time for analyzing the coordinates of the touch input position can be ensured.

[0148] As described above, the present disclosure can reduce the carry signal transmission time to ensure the touch sensing time, and based on this, the sensitivity based on the touch sensing operation can be enhanced. Further, the present disclosure can increase the target for obtaining touch data (touch screen blocks), and the time for analyzing the coordinates of the touch input position can be ensured.

[0149] The effects according to the present disclosure are not limited to the above examples, and various other effects can be included in the specification.

[0150] Although the present disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A touch-sensing display device, comprising: A display panel configured to alternately perform display driving and touch-sensing driving; And A gate driving circuit including stage circuits for driving gate lines of the display panel, wherein the gate driving circuit is configured to output a display scan signal generated based on a display carry clock to the display panel during a display frame defining a display driving period, and output a touch scan signal generated based on a touch carry clock to the display panel during a touch frame defining a touch-sensing driving period, and A position where the touch carry clock is generated during a first touch-sensing frame included in the touch-sensing driving period is different from a position where the touch carry clock is generated during a second touch-sensing frame included in the touch-sensing driving period.

2. The touch sensing display device according to claim 1, wherein, The touch carry clock is transmitted in a forward direction with respect to the display panel during the first touch-sensing frame and is transmitted in a reverse direction with respect to the display panel during the second touch-sensing frame.

3. The touch sensing display device according to claim 2, wherein, The gate driving circuit is configured to apply a forward voltage during the first touch-sensing frame to drive the stage circuits in the forward direction, and apply a reverse voltage during the second touch-sensing frame to drive the stage circuits in the reverse direction.

4. The touch sensing display device according to claim 1, wherein, During the first touch-sensing frame, the touch carry clock is generated from a first gate line of the display panel and is transmitted until a gate line provided in a central region of the display panel, and during the second touch-sensing frame, the touch carry clock is generated from a last gate line of the display panel and is transmitted until a gate line provided in a central region of the display panel.

5. The touch sensing display device according to claim 3, wherein, During the touch-sensing driving period, A first stage of the stage circuits is configured to supply a first touch scan signal to a first gate line included in a first touch screen block of the display panel, and A second stage of the stage circuits is configured to supply a second touch scan signal to a second gate line included in a second touch screen block of the display panel.

6. The touch-sensing display device according to claim 1, further comprising a sensing circuit configured to sense a voltage of a source node of a representative pixel formed in a substrate of the display panel according to the touch scan signal during the touch-sensing driving period, thereby sensing a touch input applied to the display panel.

7. The touch sensing display device according to claim 6, wherein, The representative pixel includes a driving transistor including a source electrode connected to the source node and a gate electrode connected to a gate node of the representative pixel, The gate node includes a first conductive pattern and a second conductive pattern, the first conductive pattern faces the source node and is an electrode of a storage capacitor, wherein there is at least one insulating layer between the first conductive pattern and the source node, and the second conductive pattern is connected to the first conductive pattern through a contact hole passing through the at least one insulating layer, The source node includes a third conductive pattern, which is disposed on the at least one insulating layer and is the other electrode of the storage capacitor, and The first conductive pattern is disposed closer to the substrate than the second conductive pattern and the third conductive pattern.

8. The touch sensing display device according to claim 1, wherein, The number of the stage circuits is 1 / 4 of the number of the gate lines.

9. A driving method of a touch sensing display device, the touch sensing display device including a display panel and a gate driving circuit, the display panel alternately performing display driving and touch sensing driving, the gate driving circuit including stage circuits for driving gate lines of the display panel, the driving method including: During a display frame defining a display driving period, outputting a display scan signal generated based on a display carry clock to the display panel; And During a touch frame defining a touch sensing driving period, outputting a touch scan signal generated based on a touch carry clock to the display panel, wherein a position where the touch carry clock is generated during a first touch sensing frame included in the touch sensing driving period is different from a position where the touch carry clock is generated during a second touch sensing frame included in the touch sensing driving period.

10. The driving method according to claim 9, wherein, The touch carry clock is transmitted in a forward direction with respect to the display panel during the first touch sensing frame and is transmitted in a reverse direction with respect to the display panel during the second touch sensing frame.

11. The driving method according to claim 9, wherein, During the first touch sensing frame, the touch carry clock is generated from a first gate line of the display panel and is transmitted until a gate line provided in a central region of the display panel, and during the second touch sensing frame, the touch carry clock is generated from a last gate line of the display panel and is transmitted until a gate line provided in the central region of the display panel.

12. The driving method according to claim 9, wherein, The method further includes, during the touch sensing driving period: Supplying a first touch scan signal from a first stage of the stage circuits to a first gate line included in a first touch screen block of the display panel, and Supplying a second touch scan signal from a second stage of the stage circuits to a second gate line included in a second touch screen block of the display panel.

13. The driving method according to claim 9, wherein, The method further includes, during the touch sensing driving period: Sensing a voltage of a source node of a representative pixel formed in a substrate of the display panel according to the touch scan signal, thereby sensing a touch input applied to the display panel.

14. The driving method according to claim 9, wherein, The number of the stage circuits is 1 / 4 of the number of the gate lines.

Images