Parallel arithmetic processor and electronic equipment

Abstract

The invention provides a parallel operation processor and electronic equipment. The parallel operation processor comprises a write-in control unit, a selector, N transmitting queues, N state machines and N pre-decoding units, the input end of the write-in control unit and the first input end of the selector are connected to the first register, the ith control end of the write-in control unit, the ith control end of the selector and the first input end of the ith pre-decoding unit are connected to the first end of the ith state machine, and the ith output end of the write-in control unit is connected to the input end of the ith transmitting queue; the output end of the ith transmitting queue is connected to the second input end of the selector, the output end of the selector is connected to the second register and the second input ends of the N pre-decoding units, and the output ends of the N pre-decoding units are connected to the second register; the N state machines and the N pre-decoding units are further connected with the decoding module, and the decoding module is further connected to the second register. N microcode instructions are executed in parallel, and the operation efficiency of the processor is improved.

Description

Technical Field

[0001] The present invention relates to the field of chips, and more particularly, to a parallel operation processor and an electronic device. Background Art

[0002] As an emerging computing architecture, RISC-V is gradually becoming an important driving force for the development of AI computing power. With its open and flexible characteristics, RISC-V provides great freedom for chip designers, allowing them to customize AI accelerators according to specific requirements. Its instruction set is concise and highly extensible, and designers can add custom instruction set extensions to improve the performance and efficiency of AI computing.

[0003] Due to its simplicity, openness, flexibility, low power consumption, modularity, and scalability, the RISC-V computing architecture can achieve a proprietary implementation for AI computing through instruction extension and customization. In this case, how to significantly improve the performance of the RISC-V processor without greatly increasing the hardware complexity has become a difficult problem that concerns those skilled in the art. Summary of the Invention

[0004] The purpose of the present invention is to provide a parallel operation processor and an electronic device to improve the above problems.

[0005] To achieve the above purpose, the technical solutions adopted in the embodiments of the present invention are as follows: In a first aspect, an embodiment of the present invention provides a parallel operation processor. The parallel operation processor includes a status monitoring module, a first register, a second register, and a decoding module. The status monitoring module includes: a write control unit, a selector, N emission queues, N state machines, and N pre-decoding units; The input end of the write control unit and the first input end of the selector are connected to the first register. The i-th control end of the write control unit, the i-th control end of the selector, and the first input end of the i-th pre-decoding unit are connected to the first end of the i-th state machine. The i-th output end of the write control unit is connected to the input end of the i-th emission queue. The output end of the i-th emission queue is connected to the second input end of the selector. The output end of the selector is connected to the second register and the second input ends of N pre-decoding units. The output ends of N pre-decoding units are connected to the second register, where 1 ≤ i ≤ N; The N state machines and N pre-decoding units are also connected to the decoding module, and the decoding module is also connected to the second register.

[0006] Optionally, the i-th state machine is configured to send the status identifier of the i-th microcode instruction in the i-th emission queue to the selector and the write control unit, and send the number of executed times and the status identifier of the i-th microcode instruction to the i-th pre-decoding unit; Among them, the status identifier indicates whether the i-th microcode instruction is in an effective state; When all microcode instructions are in an invalid state, the write control unit and the selector are used to read the most recently written and valid target instruction from the first register, and the target instruction includes N microcode instructions; The write control unit is used to write the i-th microcode instruction in the read target instruction into the i-th issue queue; When any one of the microcode instructions is in an effective state, the write control unit and the selector stop reading instructions from the first register, and the selector is used to read the i-th microcode instruction stored in the i-th issue queue; The selector is used to write the N read microcode instructions into the second register, write the i-th microcode instruction into the i-th pre-decoding unit, and update the N status identifier bits in the second register, where the i-th status identifier bit corresponds to the i-th microcode instruction. During the security period, all N status identifier bits are in an effective state. During the non-security period, the i-th status identifier bit is the same as the status identifier of the i-th microcode instruction sent by the i-th state machine in the current clock cycle; The i-th pre-decoding unit is used to receive the split requirement indication sent by the decoding module in the current clock cycle, and obtain the i-th pre-decoding information corresponding to the i-th microcode instruction received by it according to the split requirement indication, the number of executed times of the i-th microcode instruction, and the status identifier, where the i-th pre-decoding information includes the instruction type, the source register address, and the destination register address; The i-th pre-decoding unit is used to write the i-th pre-decoding information obtained by it into the second register.

[0007] Optionally, in the case where the split requirement indication indicates that splitting is required, if the i-th microcode instruction is in an effective state, the i-th pre-decoding unit is used to combine the number of executed times of the i-th microcode instruction to obtain the i-th pre-decoding information corresponding to the i-th microcode instruction received by it; In the case where the split requirement indication indicates that splitting is required, if the i-th microcode instruction is in an invalid state, the i-th pre-decoding unit stops pre-decoding the i-th microcode instruction; In the case where the split requirement indication indicates that splitting is not required, the i-th pre-decoding unit is used to directly obtain the i-th pre-decoding information corresponding to the i-th microcode instruction received by it when the i-th microcode instruction sent by the i-th state machine is in an effective state.

[0008] Optionally, the parallel operation processor further includes a third register, and the decoding module includes a microcode scoreboard, a register file unit, a hazard check unit, and N decoding units; The first end of the i-th decoding unit is connected to the first end of the i-th state machine. The second ends of the N decoding units are connected to the 2nd register, and the output ends of the N decoding units are all connected to the microcode scoreboard and the 3rd register; Both the register file unit and the hazard check unit are connected to the 2nd register. The register file unit is also connected to the 3rd register, and the hazard check unit is also connected to the microcode scoreboard and the N state machines; The i-th state machine is further configured to send the executed times of the i-th microcode instruction to the i-th decoding unit; If the i-th state flag bit in the 2nd register is in an active state in the current clock cycle, the i-th decoding unit is configured to read the i-th microcode instruction written in the previous clock cycle in the 2nd register, and perform decoding in combination with the executed times of the i-th microcode instruction to obtain the i-th decoding information, send the i-th decoding information to the microcode scoreboard and the 3rd register, and send the number of split instructions corresponding to the i-th microcode instruction to the i-th state machine; Wherein, the i-th decoding information includes the number of split instructions, instruction type, destination register address, operation action, execution cycle number, and immediate number corresponding to the i-th microcode instruction; The microcode scoreboard is used to store hazard-related information, wherein the hazard-related information includes the instruction type, destination register address, and execution cycle number corresponding to the microcode instruction; The hazard check unit is configured to read the i-th pre-decoding information written in the previous clock cycle in the 2nd register in the current clock cycle, and query in the microcode scoreboard based on the i-th pre-decoding information to determine whether there are data hazards and structural hazards, and send a hazard indication signal to the i-th state machine; If there is a data hazard or a structural hazard in the i-th pre-decoding information, the hazard indication signal is a hazard signal; if there is no data hazard and no structural hazard in the i-th pre-decoding information, the hazard indication signal is a non-hazard signal; The register file unit is configured to read the i-th pre-decoding information written in the previous clock cycle in the 2nd register in the current clock cycle, and send the corresponding source data to the 3rd register according to the source register address in the i-th pre-decoding information.

[0009] Optionally, the i-th state machine is configured to update the executed times of the i-th microcode instruction stored therein according to the hazard indication signal received in the previous clock cycle, and update the state threshold according to the number of split instructions received in the previous clock cycle; The i-th state machine is configured to determine the state flag of the i-th microcode instruction according to the updated executed times and state threshold.

[0010] Optionally, when the i-th decoding unit determines that the number of instruction splitting lines of the i-th microcode instruction is greater than 1, it sends a splitting requirement indication indicating the need for splitting to the i-th pre-decoding unit; when the i-th microcode instruction changes from the valid state to the invalid state, or when the number of executed times of the i-th microcode instruction is equal to its corresponding state threshold, it sends a splitting requirement indication indicating the need for no splitting to the i-th pre-decoding unit.

[0011] Optionally, the microcode scoreboard includes a fixed-point scoreboard, a floating-point scoreboard, and a vector scoreboard, and the register file unit includes a fixed-point register file, a floating-point register file, and a vector register file; The output ends of the N decoding units are all connected to the fixed-point scoreboard, the floating-point scoreboard, and the vector scoreboard; the fixed-point register file, the floating-point register file, and the vector register file are all connected to the second register, and the fixed-point register file, the floating-point register file, and the vector register file are also connected to the third register; the hazard check unit is also connected to the fixed-point scoreboard, the floating-point scoreboard, and the vector scoreboard; When the destination register in the i-th decoding information is a fixed-point register, the fixed-point scoreboard is used to store the hazard-related information in the i-th decoding information; When the destination register in the i-th decoding information is a floating-point register, the floating-point scoreboard is used to store the hazard-related information in the i-th decoding information; When the destination register in the i-th decoding information is a vector register, the vector scoreboard is used to store the hazard-related information in the i-th decoding information; When the relevant register in the i-th pre-decoding information is a fixed-point register, the hazard check unit is used to query in the fixed-point scoreboard to determine whether there are data hazards and structural hazards, and generate a hazard indication signal, where the relevant register is any one of the destination register and one or more source registers in the i-th pre-decoding information; When the relevant register in the i-th pre-decoding information is a floating-point register, the hazard check unit is used to query in the floating-point scoreboard to determine whether there are data hazards and structural hazards, and generate a hazard indication signal; When the relevant register in the i-th pre-decoding information is a vector register, the hazard check unit is used to query in the vector scoreboard to determine whether there are data hazards and structural hazards, and generate a hazard indication signal; When the source register in the i-th pre-decoding information includes a fixed-point register, the fixed-point register file is used to send the corresponding source data to the third register according to the source register address in the i-th pre-decoding information; When the source register in the i-th pre-decoded information includes a floating-point register, the floating-point register file is used to send the corresponding source data to the third register according to the source register address in the i-th pre-decoded information; When the source register in the i-th pre-decoded information includes a vector register, the vector register file is used to send the corresponding source data to the third register according to the source register address in the i-th pre-decoded information.

[0012] Optionally, the parallel operation processor further includes an operation module and a fourth register, and the operation module is respectively connected to the third register and the fourth register; The operation module is used to read the decoded information and source data written by the third register in the previous clock cycle, perform corresponding operations according to them, and send the obtained operation result and the corresponding destination register address to the fourth register for the backend module to call.

[0013] Optionally, the operation module includes N fixed-point arithmetic logic units, N floating-point arithmetic logic units, and N vector arithmetic logic units; When the instruction type in the i-th decoded information is a fixed-point instruction, the i-th fixed-point arithmetic logic unit is used to perform arithmetic processing in combination with the source data corresponding to the i-th decoded information to obtain the i-th operation result, and send the i-th operation result and the corresponding destination register address to the fourth register; When the instruction type in the i-th decoded information is a floating-point instruction, the i-th floating-point arithmetic logic unit is used to perform arithmetic processing in combination with the source data corresponding to the i-th decoded information to obtain the i-th operation result, and send the i-th operation result and the corresponding destination register address to the fourth register; When the instruction type in the i-th decoded information is a vector instruction, the i-th vector arithmetic logic unit is used to perform arithmetic processing in combination with the source data corresponding to the i-th decoded information to obtain the i-th operation result, and send the i-th operation result and the corresponding destination register address to the fourth register.

[0014] In a second aspect, an embodiment of the present invention provides an electronic device, including the above-mentioned parallel operation processor.

[0015] Compared with the prior art, a parallel operation processor and an electronic device provided by an embodiment of the present invention, the parallel operation processor includes a status monitoring module, a first register, a second register, and a decoding module. The status monitoring module includes: a write control unit, a selector, N emission queues, N state machines, and N pre-decoding units; the input end of the write control unit and the first input end of the selector are connected to the first register, the i-th control end of the write control unit, the i-th control end of the selector, and the first input end of the i-th pre-decoding unit are connected to the first end of the i-th state machine, the i-th output end of the write control unit is connected to the input end of the i-th emission queue, the output end of the i-th emission queue is connected to the second input end of the selector, the output end of the selector is connected to the second register and the second input ends of the N pre-decoding units, the output ends of the N pre-decoding units are connected to the second register, 1 ≤ i ≤ N; the N state machines and the N pre-decoding units are also connected to the decoding module, and the decoding module is also connected to the second register. N microcode instructions can be executed in parallel, improving the operating efficiency of the processor.

[0016] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, provides a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0018] Figure 1 It is a schematic structural diagram of the status monitoring module provided by an embodiment of the present invention.

[0019] Figure 2 It is one of the schematic structural diagrams of the decoding module provided by an embodiment of the present invention.

[0020] Figure 3 It is another schematic structural diagram of the decoding module provided by an embodiment of the present invention.

[0021] Figure 4 It is a schematic structural diagram of the operation module provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0022] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. The components of the embodiments of the present invention described and illustrated herein can be arranged and designed in various different configurations.

[0023] Therefore, the detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0024] It should be noted that like reference numerals and letters denote like items in the following drawings. Therefore, once an item is defined in one drawing, it does not require further definition and explanation in subsequent drawings. At the same time, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive distinction and cannot be construed as indicating or implying relative importance.

[0025] It should be noted that in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0026] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings or the orientation or positional relationship in which the inventive product is customarily placed during use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

[0027] In the description of the present invention, it should also be noted that unless otherwise clearly specified and defined, the terms "arrangement" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0028] The following will describe in detail some embodiments of the present invention with reference to the accompanying drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0029] An embodiment of the present invention provides a parallel operation processor, which includes a status monitoring module, a first register, a second register, and a decoding module. Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of the status monitoring module provided by the embodiment of the present invention.

[0030] The status monitoring module includes: a write control unit, a selector, N emission queues, N state machines, and N pre-decoding units. In the accompanying drawings of the embodiment of the present invention, N is taken as 4 as an example, but it is not limited thereto, and N≥2.

[0031] The input end of the write control unit and the first input end of the selector are connected to the first register. The i-th control end of the write control unit, the i-th control end of the selector, and the first input end of the i-th pre-decoding unit are connected to the first end of the i-th state machine. The i-th output end of the write control unit is connected to the input end of the i-th emission queue. The output end of the i-th emission queue is connected to the second input end of the selector. The output end of the selector is connected to the second register and the second input ends of the N pre-decoding units. The output ends of the N pre-decoding units are connected to the second register, where 1≤i≤N.

[0032] It should be noted that the first register can be used to store instructions sent by an upper module (such as an instruction fetching module).

[0033] The N state machines and the N pre-decoding units are also connected to the decoding module, and the decoding module is also connected to the second register.

[0034] Based on Figure 1 , regarding the working logic of the parallel operation processor, an embodiment of the present invention also provides an alternative embodiment. Please refer to the following text.

[0035] The i-th state machine is used to send the status identifier of the i-th microcode instruction in the i-th emission queue to the selector and the write control unit, and send the executed times and the status identifier of the i-th microcode instruction to the i-th pre-decoding unit.

[0036] Among them, the status flag indicates whether the i-th microcode instruction is in a valid state. If it is in a valid state, it means that the i-th microcode instruction in the i-th issue queue still needs to be executed continuously. If it is in an invalid state, it means that the i-th microcode instruction in the i-th issue queue has been executed completely.

[0037] In some scenarios, the i-th microcode instruction corresponds to multiple destination registers. For each destination register, the i-th microcode instruction needs to be executed once. The total number of executions of the i-th microcode instruction is the same as the number of its corresponding destination registers. The number of times the i-th microcode instruction has been executed can be counted by a counter. It should be noted that the execution result of the microcode instruction needs to be written into its corresponding destination register. When the i-th microcode instruction is in an invalid state, the corresponding number of executed times is reset to zero.

[0038] When all microcode instructions are in an invalid state, the write control unit and the selector recognize that the current clock cycle is a safe cycle. The write control unit and the selector are used to read the most recently written and valid target instruction from the first register. The target instruction includes N microcode instructions.

[0039] The write control unit is used to write the i-th microcode instruction in the read target instruction into the i-th issue queue.

[0040] When any microcode instruction is in a valid state, the write control unit and the selector recognize that the current clock cycle is a non-safe cycle, stop reading instructions from the first register, and the selector is used to read the i-th microcode instruction stored in the i-th issue queue.

[0041] The selector is used to write the N read microcode instructions into the second register, write the i-th microcode instruction into the i-th pre-decoder unit, and update the N status flag bits in the second register. Among them, the i-th status flag bit corresponds to the i-th microcode instruction. In the safe cycle (and there are valid instructions in the first register), all N status flag bits are in a valid state. In the non-safe cycle, the i-th status flag bit is the same as the status flag of the i-th microcode instruction issued by the i-th state machine in the current clock cycle.

[0042] Among them, the safe cycle is the clock cycle when all microcode instructions are in an invalid state, and the non-safe cycle is the clock cycle when any microcode instruction is in a valid state.

[0043] The i-th pre-decoding unit is used to receive the splitting requirement indication sent by the decoding module (specifically, the i-th decoding unit therein) in the current clock cycle. The splitting requirement indication is used to indicate whether the i-th microcode instruction needs to be split during pre-decoding in the current clock cycle. According to the splitting requirement indication, the executed times of the i-th microcode instruction, and the status flag, the i-th pre-decoding unit obtains the i-th pre-decoding information corresponding to the i-th microcode instruction it receives, where the i-th pre-decoding information includes the instruction type, the source register address, and the destination register address.

[0044] The i-th pre-decoding unit is used to write the i-th pre-decoding information it obtains into the second register.

[0045] The decoding module can read the data in the second register, thereby completing the decoding work.

[0046] In the parallel operation processor provided in the embodiment of the present invention, N microcode instructions can be executed in parallel, improving the operation efficiency of the processor.

[0047] On the basis of the foregoing, regarding how the i-th pre-decoding unit obtains the i-th pre-decoding information, the embodiment of the present invention further provides an optional implementation manner. Please refer to the following text.

[0048] In the case where the splitting requirement indication indicates that splitting is required, if the i-th microcode instruction is in an effective state, the i-th pre-decoding unit is used to combine the executed times of the i-th microcode instruction to obtain the i-th pre-decoding information corresponding to the i-th microcode instruction it receives.

[0049] It should be noted that the i-th pre-decoding unit can add 1 to the executed times of the i-th microcode instruction, and determine the source register address and the destination register address in the i-th microcode instruction according to the updated value after adding 1, so as to generate the i-th pre-decoding information.

[0050] It should be understood that after entering the current clock cycle, the i-th pre-decoding unit first receives the splitting requirement indication fed back by the decoding module, receives the executed times and the status flag of the i-th microcode instruction sent by the i-th state machine, and then performs pre-decoding.

[0051] In the case where the splitting requirement indication indicates that splitting is required, if the i-th microcode instruction is in an invalid state, the i-th pre-decoding unit stops pre-decoding the i-th microcode instruction.

[0052] In the case where the splitting requirement indication indicates that splitting is not required, ignoring the executed times of the i-th microcode instruction sent by the i-th state machine, the i-th pre-decoding unit is used to directly obtain the i-th pre-decoding information corresponding to the i-th microcode instruction it receives when the i-th microcode instruction sent by the i-th state machine is in an effective state.

[0053] By performing pre - decoding and obtaining the corresponding pre - decoding information, the operating efficiency of the processor can be improved and clock cycles can be saved.

[0054] Regarding the structure of the decoding module, an alternative implementation manner is also provided in the embodiments of the present invention. Please refer to Figure 2 , Figure 2 which is one of the schematic diagrams of the structure of the decoding module provided by the embodiments of the present invention.

[0055] The parallel operation processor further includes a third register. The decoding module includes a microcode scoreboard, a register file unit, a hazard check unit, and N decoding units.

[0056] The first end of the i - th decoding unit is connected to the first end of the i - th state machine. The second ends of the N decoding units are connected to the second register. The output ends of the N decoding units are all connected to the microcode scoreboard and the third register.

[0057] Both the register file unit and the hazard check unit are connected to the second register. The register file unit is further connected to the third register. The hazard check unit is further connected to the microcode scoreboard and N state machines.

[0058] The i - th state machine is further configured to send the number of executed times of the i - th microcode instruction to the i - th decoding unit.

[0059] If the i - th state flag bit in the second register is in an effective state in the current clock cycle, the i - th decoding unit is configured to read the i - th microcode instruction written in the previous clock cycle in the second register, and perform decoding in combination with the number of executed times of the i - th microcode instruction (sent in the current clock cycle) to obtain the i - th decoding information, send the i - th decoding information to the microcode scoreboard and the third register, and send the number of split instructions corresponding to the i - th microcode instruction to the i - th state machine.

[0060] Among them, the i - th decoding information includes the number of split instructions corresponding to the i - th microcode instruction, instruction type, destination register address, operation action (such as addition, subtraction, multiplication, division, etc.), number of execution cycles (the number of clock cycles required for the execution of this microcode instruction to complete), and immediate number. The i - th decoding unit is configured to determine the destination register address in the i - th microcode instruction according to the number of executed times of the i - th microcode instruction. It can be understood that only the destination register address in the i - th microcode instruction changes with the number of executed times of the i - th microcode instruction in the i - th decoding information.

[0061] The microcode scoreboard is used to store hazard - related information. Among them, the hazard - related information includes the instruction type, destination register address, and number of execution cycles corresponding to the microcode instruction.

[0062] Among them, the instruction type and the execution cycle count are used to determine the number of cycles during which the destination register address is occupied. After the corresponding number of cycles, the microcode scoreboard releases the occupancy status of the destination register address.

[0063] The hazard detection unit is used to read the i-th pre-decoded information written in the second register in the previous clock cycle in the current clock cycle, and query in the microcode scoreboard based on the i-th pre-decoded information to determine whether there are data hazards and structural hazards, and send a hazard indication signal to the i-th state machine.

[0064] If the source register address and / or destination register address in the i-th pre-decoded information is the same as any occupied destination register address in the microcode scoreboard, it is considered that the i-th pre-decoded information has a data hazard or a structural hazard; otherwise, it is considered that the i-th pre-decoded information has no data hazard and no structural hazard. If the i-th pre-decoded information has a data hazard or a structural hazard, the hazard indication signal is a hazard signal; if the i-th pre-decoded information has no data hazard and no structural hazard, the hazard indication signal is a non-hazard signal. If the i-th pre-decoded information was not written in the second register in the previous clock cycle, it is directly determined that the i-th pre-decoded information has no data hazard and no structural hazard, and a corresponding non-hazard signal is sent to the i-th state machine, but the i-th state machine will ignore this non-hazard signal.

[0065] The register file unit is used to read the i-th pre-decoded information written in the second register in the previous clock cycle in the current clock cycle, and send the corresponding source data to the third register according to the source register address in the i-th pre-decoded information.

[0066] Based on Figure 2 the above, the embodiments of the present invention also provide an optional implementation manner on how the i-th state machine updates the executed times and status flags of the stored i-th microcode instruction. Please refer to the following text.

[0067] The i-th state machine is used to update the executed times of the stored i-th microcode instruction according to the hazard indication signal received in the previous clock cycle. If the hazard indication signal received in the previous clock cycle is a non-hazard signal, increment the executed times of the i-th microcode instruction by 1; if the hazard indication signal received in the previous clock cycle is a hazard signal, keep the executed times of the i-th microcode instruction unchanged, and update the status threshold according to the number of instruction split pieces received in the previous clock cycle.

[0068] It should be noted that, assuming that the hazard indication signal received by the i-th state machine in the k-th clock cycle is a non-hazard signal, the i-th state machine needs to update the executed times of the i-th microcode instruction stored by it (increment it by 1) in the (k + 1)-th clock cycle; if the hazard indication signal received by the i-th state machine in the k-th clock cycle is a hazard signal, the i-th state machine needs to keep the executed times of the i-th microcode instruction unchanged in the (k + 1)-th clock cycle.

[0069] Assuming that the i-th state machine receives the number of instruction splits in the k-th clock cycle, the i-th state machine needs to use the number of instruction splits received in the k-th clock cycle as the updated state threshold in the (k + 1)-th clock cycle. It can be understood that after entering a non-safe period, the number of instruction splits corresponding to the i-th microcode instruction remains unchanged until entering a safe period, at which time the number of instruction splits is cleared.

[0070] The i-th state machine is used to determine the status flag of the i-th microcode instruction according to the updated executed times and the state threshold. If the executed times are less than the state threshold, the i-th microcode instruction is in a valid state; if the executed times are equal to the state threshold, the i-th microcode instruction is in an invalid state.

[0071] It should be noted that the i-th state machine updates the executed times and the status flag in the current clock cycle, and sends the updated executed times and status flag of the i-th microcode instruction to the write logic control unit, the selector, the i-th pre-decoder unit, the i-th decoder unit, and so on.

[0072] In an alternative embodiment, the i-th decoder unit is used to send a split requirement indication indicating that splitting is required to the i-th pre-decoder unit when it determines that the number of instruction splits of the i-th microcode instruction is greater than 1; when the i-th microcode instruction changes from a valid state to an invalid state, or when the executed times of the i-th microcode instruction are equal to its corresponding state threshold, it sends a split requirement indication indicating that splitting is not required to the i-th pre-decoder unit.

[0073] On the Figure 2 basis, regarding the structures of the microcode scoreboard and the register file unit, the embodiments of the present invention also provide an alternative embodiment. Please refer to Figure 3 , Figure 3 which is the second structural schematic diagram of the decoder module provided by the embodiments of the present invention.

[0074] The microcode scoreboard includes a fixed-point scoreboard, a floating-point scoreboard, and a vector scoreboard. The register file unit includes a fixed-point register file, a floating-point register file, and a vector register file.

[0075] The output terminals of N decoding units are all connected to the fixed-point scoreboard, the floating-point scoreboard, and the vector scoreboard; the fixed-point register file, the floating-point register file, and the vector register file are all connected to the second register, and the fixed-point register file, the floating-point register file, and the vector register file are also connected to the third register; the hazard check unit is also connected to the fixed-point scoreboard, the floating-point scoreboard, and the vector scoreboard.

[0076] When the destination register in the i-th decoding information is a fixed-point register, the fixed-point scoreboard is used to store the hazard-related information in the i-th decoding information.

[0077] When the destination register in the i-th decoding information is a floating-point register, the floating-point scoreboard is used to store the hazard-related information in the i-th decoding information.

[0078] When the destination register in the i-th decoding information is a vector register, the vector scoreboard is used to store the hazard-related information in the i-th decoding information.

[0079] When the relevant register in the i-th pre-decoding information is a fixed-point register, the hazard check unit is used to query in the fixed-point scoreboard to determine whether there are data hazards and structural hazards, and generate a hazard indication signal, where the relevant register is any one of the destination register and one or more source registers in the i-th pre-decoding information.

[0080] When the relevant register in the i-th pre-decoding information is a floating-point register, the hazard check unit is used to query in the floating-point scoreboard to determine whether there are data hazards and structural hazards, and generate a hazard indication signal.

[0081] When the relevant register in the i-th pre-decoding information is a vector register, the hazard check unit is used to query in the vector scoreboard to determine whether there are data hazards and structural hazards, and generate a hazard indication signal.

[0082] When the source registers in the i-th pre-decoding information include fixed-point registers, the fixed-point register file is used to send the corresponding source data to the third register according to the source register addresses in the i-th pre-decoding information.

[0083] When the source registers in the i-th pre-decoding information include floating-point registers, the floating-point register file is used to send the corresponding source data to the third register according to the source register addresses in the i-th pre-decoding information.

[0084] When the source registers in the i-th pre-decoding information include vector registers, the vector register file is used to send the corresponding source data to the third register according to the source register addresses in the i-th pre-decoding information.

[0085] In an alternative embodiment, the parallel operation processor further includes an operation module and a fourth register. The operation module is respectively connected to the third register and the fourth register. The operation module is configured to read the decoded information and source data written in the third register in the previous clock cycle, perform corresponding operations based thereon, and send the obtained operation result and the corresponding destination register address to the fourth register for the backend module to call.

[0086] Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of the operation module provided by an embodiment of the present invention.

[0087] The operation module includes N fixed-point arithmetic logic units, N floating-point arithmetic logic units, and N vector arithmetic logic units.

[0088] When the instruction type in the i-th decoded information is a fixed-point instruction, the i-th fixed-point arithmetic logic unit is configured to perform operation processing in combination with the source data corresponding to the i-th decoded information to obtain the i-th operation result, and send the i-th operation result and the corresponding destination register address to the fourth register.

[0089] When the instruction type in the i-th decoded information is a floating-point instruction, the i-th floating-point arithmetic logic unit is configured to perform operation processing in combination with the source data corresponding to the i-th decoded information to obtain the i-th operation result, and send the i-th operation result and the corresponding destination register address to the fourth register.

[0090] When the instruction type in the i-th decoded information is a vector instruction, the i-th vector arithmetic logic unit is configured to perform operation processing in combination with the source data corresponding to the i-th decoded information to obtain the i-th operation result, and send the i-th operation result and the corresponding destination register address to the fourth register.

[0091] In the parallel computing processor provided by the embodiment of the present invention, an improved VLIW (Very Long Instruction Word) architecture is used to implement the vector extension of the RISC-V processor. Vector instructions can perform the same operation on multiple data simultaneously, making more efficient use of the processor resources, reducing the necessary number of instructions and processor cycles, and thus improving the energy efficiency ratio when performing large-scale parallel data processing tasks. By improving the microcode slot issue queue, adding an issue queue state machine and an issue queue write control logic can achieve the microcode splitting of vector operators. Since each microcode in the VLIW structure can only write back one register after completing the operation, while vector operators need to support the write-back of multiple registers, it is necessary to improve the VLIW structure. Through the method of microcode splitting, it is made to support the write-back of multiple registers by a single instruction. According to the RISC-V Vector1.0 vector extension requirements, vector operators and source registers may come from fixed-point registers, floating-point registers, or vector registers. Therefore, corresponding floating-point and vector parts need to be added to the register file unit, microcode scoreboard, hazard check unit, and arithmetic unit to support the RISC-V vector extension.

[0092] The embodiment of the present invention provides an electronic device, including the above-mentioned parallel computing processor.

[0093] In summary, the embodiment of the present invention provides a parallel computing processor and an electronic device. The parallel computing processor includes a status monitoring module, a first register, a second register, and a decoding module. The status monitoring module includes: a write control unit, a selector, N issue queues, N state machines, and N pre-decoding units; the input end of the write control unit and the first input end of the selector are connected to the first register, the i-th control end of the write control unit, the i-th control end of the selector, and the first input end of the i-th pre-decoding unit are connected to the first end of the i-th state machine, the i-th output end of the write control unit is connected to the input end of the i-th issue queue, the output end of the i-th issue queue is connected to the second input end of the selector, the output end of the selector is connected to the second register and the second input ends of the N pre-decoding units, and the output ends of the N pre-decoding units are connected to the second register, where 1 ≤ i ≤ N; the N state machines and the N pre-decoding units are also connected to the decoding module, and the decoding module is also connected to the second register. N microcode instructions can be executed in parallel, improving the operating efficiency of the processor.

[0094] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0095] It is obvious to those skilled in the art that the present invention is not limited to the details of the above-described exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention. Therefore, in any aspect, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the appended claims rather than the above description. Accordingly, all changes that fall within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention. Any reference signs in the claims should not be construed as limiting the claims involved.

Claims

1. A parallel computing processor, characterized in that, The parallel operation processor includes a status monitoring module, a first register, a second register, and a decoding module. The status monitoring module includes: a write control unit, a selector, N emission queues, N state machines, and N pre-decoding units; The input end of the write control unit and the first input end of the selector are connected to the first register. The i-th control end of the write control unit, the i-th control end of the selector, and the first input end of the i-th pre-decoding unit are connected to the first end of the i-th state machine. The i-th output end of the write control unit is connected to the input end of the i-th emission queue. The output end of the i-th emission queue is connected to the second input end of the selector. The output end of the selector is connected to the second input ends of the second register and the N pre-decoding units. The output ends of the N pre-decoding units are connected to the second register, where 1 ≤ i ≤ N; The N state machines and the N pre-decoding units are also connected to the decoding module, and the decoding module is also connected to the second register.

2. The parallel operation processor according to claim 1, wherein The i-th state machine is used to send the status identifier of the i-th microcode instruction in the i-th emission queue to the selector and the write control unit, and send the executed times and status identifier of the i-th microcode instruction to the i-th pre-decoding unit; Wherein, the status identifier indicates whether the i-th microcode instruction is in an effective state; When all microcode instructions are in an invalid state, the write control unit and the selector are used to read the target instruction that was recently written and is valid from the first register. The target instruction includes N microcode instructions; The write control unit is used to write the i-th microcode instruction in the read target instruction into the i-th emission queue; When any one of the microcode instructions is in an effective state, the write control unit and the selector stop reading instructions from the first register, and the selector is used to read the i-th microcode instruction stored in the i-th emission queue; The selector is used to write the read N microcode instructions into the second register, write the i-th microcode instruction into the i-th pre-decoding unit, and update the N status identifier bits in the second register. Wherein, the i-th status identifier bit corresponds to the i-th microcode instruction. During the security period, the N status identifier bits are all in an effective state. During the non-security period, the i-th status identifier bit is the same as the status identifier of the i-th microcode instruction sent by the i-th state machine in the current clock cycle; The i-th pre-decoding unit is used to receive the splitting requirement indication sent by the decoding module in the current clock cycle, and obtain the i-th pre-decoding information corresponding to the i-th microcode instruction received by it according to the splitting requirement indication, the executed times and status identifier of the i-th microcode instruction. Wherein, the i-th pre-decoding information includes the instruction type, the source register address, and the destination register address; The i-th pre-decoding unit is used to write the obtained i-th pre-decoding information into the second register.

3. The parallel operation processor according to claim 2, wherein When the splitting requirement indication indicates that splitting is required, if the i-th microcode instruction is in an active state, the i-th pre-decoding unit is used to obtain the i-th pre-decoding information corresponding to the i-th microcode instruction it receives in combination with the number of executed times of the i-th microcode instruction; When the splitting requirement indication indicates that splitting is required, if the i-th microcode instruction is in an invalid state, the i-th pre-decoding unit stops pre-decoding the i-th microcode instruction; When the splitting requirement indication indicates that splitting is not required, the i-th pre-decoding unit is used to directly obtain the i-th pre-decoding information corresponding to the i-th microcode instruction it receives when the i-th microcode instruction sent by the i-th state machine is in an active state.

4. The parallel operation processor according to claim 2, wherein, The parallel operation processor further includes a third register, and the decoding module includes a microcode scoreboard, a register file unit, a hazard check unit, and N decoding units; The first end of the i-th decoding unit is connected to the first end of the i-th state machine, the second ends of the N decoding units are connected to the second register, and the output ends of the N decoding units are all connected to the microcode scoreboard and the third register; The register file unit and the hazard check unit are both connected to the second register, the register file unit is further connected to the third register, and the hazard check unit is further connected to the microcode scoreboard and N state machines; The i-th state machine is further used to send the number of executed times of the i-th microcode instruction to the i-th decoding unit; If the i-th status identification bit in the second register is in an active state in the current clock cycle, the i-th decoding unit is used to read the i-th microcode instruction written in the previous clock cycle in the second register, and perform decoding in combination with the number of executed times of the i-th microcode instruction to obtain the i-th decoding information, send the i-th decoding information to the microcode scoreboard and the third register, and send the number of instruction splitting lines corresponding to the i-th microcode instruction to the i-th state machine; Among them, the i-th decoding information includes the number of instruction splitting lines, instruction type, destination register address, operation action, execution cycle number, and immediate number corresponding to the i-th microcode instruction; The microcode scoreboard is used to store hazard-related information, where the hazard-related information includes the instruction type, destination register address, and execution cycle number corresponding to the microcode instruction; The hazard check unit is used to read the i-th pre-decoding information written in the previous clock cycle in the second register in the current clock cycle, and query in the microcode scoreboard based on the i-th pre-decoding information to determine whether there are data hazards and structural hazards, and send a hazard indication signal to the i-th state machine; If there is a data hazard or a structural hazard in the i-th pre-decoding information, the hazard indication signal is a hazard signal; if there is no data hazard and no structural hazard in the i-th pre-decoding information, the hazard indication signal is a non-hazard signal; The register file unit is used to read the i-th pre-decoding information written in the previous clock cycle in the second register in the current clock cycle, and send the corresponding source data to the third register according to the source register address in the i-th pre-decoding information.

5. The parallel operation processor according to claim 4, wherein The i-th state machine is used to update the executed times of the i-th microcode instruction stored therein according to the hazard indication signal received in the previous clock cycle, and update the state threshold according to the number of instruction splitting received in the previous clock cycle; The i-th state machine is used to determine the state identifier of the i-th microcode instruction according to the updated executed times and state threshold.

6. The parallel operation processor according to claim 4, wherein When the i-th decoding unit determines that the number of instruction splitting of the i-th microcode instruction is greater than 1, it sends a splitting requirement indication representing the need for splitting to the i-th pre-decoding unit; When the i-th microcode instruction changes from the valid state to the invalid state, or when the executed times of the i-th microcode instruction is equal to its corresponding state threshold, it sends a splitting requirement indication representing the need for no splitting to the i-th pre-decoding unit.

7. The parallel operation processor according to claim 4, wherein The microcode scoreboard includes a fixed-point scoreboard, a floating-point scoreboard, and a vector scoreboard, and the register file unit includes a fixed-point register file, a floating-point register file, and a vector register file; The output terminals of the N decoding units are all connected to the fixed-point scoreboard, the floating-point scoreboard, and the vector scoreboard; the fixed-point register file, the floating-point register file, and the vector register file are all connected to the second register, and the fixed-point register file, the floating-point register file, and the vector register file are also connected to the third register; the hazard checking unit is also connected to the fixed-point scoreboard, the floating-point scoreboard, and the vector scoreboard; When the destination register in the i-th decoding information is a fixed-point register, the fixed-point scoreboard is used to store the hazard-related information in the i-th decoding information; When the destination register in the i-th decoding information is a floating-point register, the floating-point scoreboard is used to store the hazard-related information in the i-th decoding information; When the destination register in the i-th decoding information is a vector register, the vector scoreboard is used to store the hazard-related information in the i-th decoding information; When the related register in the i-th pre-decoding information is a fixed-point register, the hazard checking unit is used to query in the fixed-point scoreboard to determine whether there are data hazards and structural hazards, and generate a hazard indication signal, where the related register is any one of the destination register and one or more source registers in the i-th pre-decoding information; When the related register in the i-th pre-decoding information is a floating-point register, the hazard checking unit is used to query in the floating-point scoreboard to determine whether there are data hazards and structural hazards, and generate a hazard indication signal; When the related register in the i-th pre-decoding information is a vector register, the hazard checking unit is used to query in the vector scoreboard to determine whether there are data hazards and structural hazards, and generate a hazard indication signal; When the source register in the i-th pre-decoding information includes a fixed-point register, the fixed-point register file is used to send the corresponding source data to the third register according to the source register address in the i-th pre-decoding information; When the source register in the i-th pre-decoded information includes a floating-point register, the floating-point register file is used to send the corresponding source data to the third register according to the source register address in the i-th pre-decoded information; When the source register in the i-th pre-decoded information includes a vector register, the vector register file is used to send the corresponding source data to the third register according to the source register address in the i-th pre-decoded information.

8. The parallel operation processor according to claim 7, wherein The parallel operation processor further includes an operation module and a fourth register, and the operation module is respectively connected to the third register and the fourth register; The operation module is used to read the decoded information and source data written in the third register in the previous clock cycle, perform corresponding operations according to them, and send the obtained operation results and the corresponding destination register addresses to the fourth register for the backend module to call.

9. The parallel operation processor according to claim 8, wherein, The operation module includes N fixed-point arithmetic logic units, N floating-point arithmetic logic units, and N vector arithmetic logic units; When the instruction type in the i-th decoded information is a fixed-point instruction, the i-th fixed-point arithmetic logic unit is used to perform arithmetic processing in combination with the source data corresponding to the i-th decoded information to obtain the i-th operation result, and send the i-th operation result and the corresponding destination register address to the fourth register; When the instruction type in the i-th decoded information is a floating-point instruction, the i-th floating-point arithmetic logic unit is used to perform arithmetic processing in combination with the source data corresponding to the i-th decoded information to obtain the i-th operation result, and send the i-th operation result and the corresponding destination register address to the fourth register; When the instruction type in the i-th decoded information is a vector instruction, the i-th vector arithmetic logic unit is used to perform arithmetic processing in combination with the source data corresponding to the i-th decoded information to obtain the i-th operation result, and send the i-th operation result and the corresponding destination register address to the fourth register.

10. An electronic device, characterized in that, Including the parallel operation processor according to any one of claims 1-9.

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