Data storage method, system and device, debugger, medium and product

Abstract

The invention relates to a data storage method, system and device, a debugger, a medium and a product. The method comprises the following steps: converting program operation data which is output by equipment to be tested in real time and conforms to a first communication protocol into program operation data which conforms to a second communication protocol; the first communication protocol is a protocol for testing the to-be-tested equipment, and the second communication protocol is a protocol matched with the computer equipment; the program running data is running data fed back by a pile program in a test program in the to-be-tested equipment, and a plurality of pile programs are set at key program positions in the test program of the to-be-tested equipment in advance through instrumentation; and storing the program operation data conforming to the second communication protocol in the storage module, so that the computer equipment obtains the program operation data conforming to the second communication protocol stored in the storage module. By adopting the method, the test reliability of the to-be-tested equipment can be improved.

Description

Technical Field

[0001] The present application relates to the field of hardware-in-the-loop testing technology, and in particular to a data storage method, system, device, debugger, medium and product. Background Art

[0002] Hardware-in-the-Loop (HiL) testing is a testing method that combines the device under test with a virtual simulation environment. It is mainly used to verify the function, performance and reliability of the device under test in a complex real environment.

[0003] Taking the hardware-in-the-loop test of automotive electronics as an example, in the hardware-in-the-loop test of automotive electronics, the program running data of the device under test (such as a whole vehicle or a device in a vehicle) can be monitored to determine the running status of the test program in the device under test. In the related art, a computer device is often connected to the device under test so that the device under test transmits the program running data of the test program in the device under test to the computer device in real time. The computer device monitors the program running status of the test program during the test process based on the received data to determine whether the hardware-in-the-loop test of the device under test has passed.

[0004] However, in the hardware-in-the-loop test of the related art, the computer equipment is often unable to monitor the complete program running status of the test program in the device under test during the test process, resulting in low reliability of the test of the device under test. Summary of the invention

[0005] Based on this, the present application provides a data storage method, system, device, debugger, medium and product, which can improve the completeness of the computer device obtaining the program running status of the test program in the device under test during the test process, thereby improving the reliability of the test of the device under test.

[0006] In the first aspect, the present application provides a data storage method, which is applied to a data processing chip in a debugger for hardware-in-the-loop testing. The debugger is also configured with a storage module connected to the data processing chip, and the method includes: converting program running data that conforms to a first communication protocol and is output in real time by a device under test into program running data that conforms to a second communication protocol; the first communication protocol is a protocol for testing the device under test, and the second communication protocol is a protocol adapted to a computer device; the program running data is running data fed back by a stub program in a test program in the device under test, and a plurality of stub programs are pre-set at key program positions in the test program of the device under test through stub insertion; the program running data that conforms to the second communication protocol is stored in the storage module, so that the computer device obtains the program running data that conforms to the second communication protocol stored in the storage module.

[0007] In the technical solution provided by the embodiment of the present application, after the debugger obtains the program running data, the program running data is stored in the storage module. In this way, even when the computer device is stuck or the computer device does not support real-time acquisition of program running data, the computer device can still obtain the program running data stored in the storage module, improving the integrity of the program running status of the test program in the device under test during the test process by the computer device, and further improving the reliability of the test of the device under test. In addition, the debugger is connected between the device under test and the computer device, and the data processing chip in the debugger can perform communication protocol conversion, solving the problem of protocol incompatibility between the device under test and the computer device, and there is no need to perform additional configuration on the computer device to make the computer device support the first communication protocol, expanding the application range of the debugger. And the program running data stored in the storage module conforms to the second communication protocol. Therefore, when the computer device needs to read the program running data, the stored program running data conforming to the second communication protocol is forwarded, and there is no need to perform the step of protocol conversion, reducing the delay of the computer device in reading the program running data conforming to the second communication protocol.

[0008] In some embodiments, the storage module includes multiple types of storage units; storing the program running data conforming to the second communication protocol in the storage module includes: receiving the transmission configuration information sent by the computer device; the transmission configuration information is used to represent the transmission path of the program running data conforming to the second communication protocol; determining the target type of the storage unit for storing the program running data conforming to the second communication protocol according to the transmission configuration information; storing the program running data conforming to the second communication protocol in the storage unit of the target type.

[0009] In the technical solution provided by the embodiment of the present application, by receiving the transmission path of the second communication protocol program running data represented by the transmission configuration information sent by the computer device, and accurately matching the target type of the storage unit accordingly for data storage, different storage units can be adapted to different transmission path characteristics to achieve classified data storage. This not only improves the utilization efficiency of storage resources, but also ensures data integrity and storage stability, avoiding problems such as data loss and transmission delay caused by improper selection of storage units, and significantly improving the flexibility and reliability of data storage for different transmission paths.

[0010] In some embodiments, determining the target type of the storage unit for storing the program running data conforming to the second communication protocol according to the transmission configuration information includes at least one of the following: when the transmission configuration information indicates that the program running data conforming to the second communication protocol is transmitted through the random access memory, determining that the target type of the storage unit is the random access memory type; when the transmission configuration information indicates that the program running data conforming to the second communication protocol is transmitted in real time, determining that the target type of the storage unit is the cache type; when the transmission configuration information indicates that the program running data conforming to the second communication protocol is transmitted through the read-only memory, determining that the target type of the storage unit is the read-only memory type.

[0011] In the technical solution provided by the embodiments of the present application, dynamically selecting an appropriate memory type according to the transmission configuration information can achieve the optimal allocation of storage resources, avoiding problems such as waste of storage resources and reduction of data transmission efficiency caused by using an inappropriate memory type. For example, storing data that needs to be transmitted in real time in a cache with a small capacity but high speed, storing data that needs to be stored without power in a read-only memory with a large capacity, and storing data that requires a certain storage capacity and needs to be quickly read in a random access memory with a moderate capacity. Thus, the corresponding memory type can be flexibly selected according to the reliability and speed of data transmission, improving the utilization efficiency of storage resources.

[0012] In some embodiments, storing the program running data conforming to the second communication protocol in the storage unit of the target type includes at least one of the following: when the transmission configuration information indicates that the program running data conforming to the second communication protocol is transmitted through the random access memory in the storage module, storing the program running data conforming to the second communication protocol in the cache in the storage module, and transferring the program running data conforming to the second communication protocol in the cache to the random access memory; when the transmission configuration information indicates that the program running data conforming to the second communication protocol is transmitted in real time, storing the program running data conforming to the second communication protocol in the cache in the storage module; when the transmission configuration information indicates that the program running data conforming to the second communication protocol is transmitted through the read-only memory in the storage module, storing the program running data conforming to the second communication protocol in the cache in the storage module, transferring the program running data conforming to the second communication protocol in the cache to the random access memory in the storage module, and transferring the program running data conforming to the second communication protocol in the random access memory to the read-only memory.

[0013] In the technical solution provided by the embodiment of the present application, in the technical solution provided by the embodiment of the present application, the data after the data processing chip converts the protocol is first written into the cache, and then read from the cache and written into the random access memory. The write latency of the cache is lower than that of the random access memory, and the write latency in the random access memory is lower than that of the read-only memory. Therefore, the cache can immediately respond to the data storage of the data processing chip. Compared with the solution of directly writing the data after the data processing chip converts the protocol into the random access memory, or compared with the solution of directly writing the data after the data processing chip converts the protocol into the read-only memory, the data processing chip does not need to wait for a high latency for the data writing to complete before it can perform the next operation, improving the processing efficiency of the data processing chip; and, by writing the random access memory into the read-only memory, and the read-only memory needs to be written by page. Therefore, multiple small data stored in the random access memory can be merged into a complete page and written into the read-only memory by page. Compared with the solution of directly writing the data in the cache into the read-only memory, the write times of the read-only memory are reduced, not only reducing the aging risk of the read-only memory caused by the write times limit of the read-only memory, improving the service life of the read-only memory, but also improving the write efficiency of the read-only memory.

[0014] In some embodiments, transferring the program running data conforming to the second communication protocol in the cache to the random access memory includes: receiving a clock signal sent by a computer device; the clock signal is a waveform signal with a preset frequency; according to the waveform signal with the preset frequency and the number of bytes written into the random access memory each time pre-configured, transferring the program running data conforming to the second communication protocol in the cache to the random access memory at the preset frequency; the method further includes: sending the program running data conforming to the second communication protocol in the random access memory to the computer device at the preset frequency according to the waveform signal with the preset frequency and the number of bytes read from the random access memory each time pre-configured.

[0015] In the technical solution provided by the embodiment of the present application, based on the waveform signal with a preset frequency, the rhythm of data transfer to the random access memory can be accurately controlled, avoiding problems such as data loss and misalignment caused by timing chaos, ensuring that the program running data is transferred to the random access memory completely and orderly, improving the accuracy of data transfer from the cache to the random access memory; transferring data to the random access memory according to the number of written bytes can make full use of the high-speed read and write characteristics of the random access memory, reduce the number of data transfer interactions, reduce the transfer delay, and improve the timeliness of data transfer; and sending data to the computer device according to the waveform signal with a preset frequency and the number of bytes read from the random access memory each time, thereby improving the correctness and synchronization of the data processing chip sending data to the computer device, and further improving the reliability of data transmission.

[0016] In some embodiments, transferring the program running data that conforms to the second communication protocol in the random access memory to the read-only memory includes: receiving a clock signal sent by the computer device; the clock signal is a waveform signal with a preset frequency; according to the waveform signal with a preset frequency and the number of bytes written to the read-only memory each time configured in advance, transferring the program running data that conforms to the second communication protocol in the random access memory to the read-only memory at a preset frequency; the method further includes: sending the program running data that conforms to the second communication protocol in the read-only memory to the computer device at a preset frequency according to the waveform signal with a preset frequency and the number of bytes read from the read-only memory each time configured in advance.

[0017] In the technical solution provided by the embodiment of the present application, based on the waveform signal with a preset frequency, the rhythm of data transfer to the read-only memory can be accurately controlled, avoiding problems such as data loss and misalignment caused by timing chaos, ensuring that the program running data is transferred to the read-only memory completely and orderly, improving the accuracy of data transfer from the random access memory to the read-only memory, and transferring data to the read-only memory according to the number of written bytes can make full use of the high-speed read and write characteristics of the read-only memory, reduce the number of data transfer interactions, reduce the transfer delay, and improve the timeliness of data transfer; and sending data to the computer device according to the waveform signal with a preset frequency and the number of bytes read from the read-only memory each time, thereby improving the correctness and synchronization of the data processing chip sending data to the computer device, and further improving the reliability of data transmission.

[0018] In some embodiments, the method further includes: when the program operation data conforming to the second communication protocol is configured to be transmitted through the target memory in the storage module, during the hardware-in-the-loop test, reading, according to each received target data reading request, the program operation data conforming to the second communication protocol in the target memory; the target memory includes a random access memory or a read-only memory; and sending the read program operation data conforming to the second communication protocol to the computer device.

[0019] In the technical solution provided by the embodiments of the present application, when the target memory is a random access memory, the capacity of the random access memory is appropriate, which not only avoids the problem that the data storage is insufficient due to too small storage capacity and cannot respond to the intermittent target data reading requests sent by the computer device, but also prevents resource waste caused by too large capacity; moreover, the fast reading performance of the random access memory enables the data processing chip to quickly read data from the random access memory and send it to the computer device after receiving the target data reading request sent by the computer device, greatly improving the timeliness of data interaction and ensuring the high efficiency of data transmission during the test; when the target memory is a read-only memory, the program operation data stored in the read-only memory can also be obtained during the hardware-in-the-loop test, avoiding the inability to read the program operation data in the read-only memory during the hardware-in-the-loop test and improving the timeliness of data transmission.

[0020] In some embodiments, reading, according to each received target data reading request, the program operation data conforming to the second communication protocol in the target memory includes: determining the target reading address of the program operation data conforming to the second communication protocol to be read in the target memory according to the latest running time in the program operation data already obtained by the computer device carried in each received target data reading request; and reading, according to the target reading address, the program operation data conforming to the second communication protocol from the target memory.

[0021] In the technical solution provided by the embodiments of the present application, by carrying the latest running time in the program operation data already obtained by the computer device in the target data reading request, not only does the data processing chip not need to record the latest time of each sent program operation data, reducing the internal resource occupation of the data processing chip and avoiding the operation overhead caused by frequent recording and updating of time, but also it can avoid the problem that the data processing chip sends the program operation data but the computer device does not obtain the program operation data, resulting in incomplete program operation data obtained by the computer device, and improving the reliability of data transmission.

[0022] In some embodiments, the method further includes: when receiving a data reception success instruction sent by a computer device, determining that the program operation data conforming to the second communication protocol sent each time is sent completely; when receiving a retransmission instruction for the program operation data at at least one running time sent by the computer device, determining the set read address for the program operation data at at least one running time; according to the set read address, reading the program operation data conforming to the second communication protocol at at least one running time from a target memory, and sending the program operation data conforming to the second communication protocol at at least one running time to the computer device.

[0023] In the technical solution provided by the embodiments of the present application, by means of the data reception success instruction, it is determined that the program operation data conforming to the second communication protocol sent each time is sent completely. By means of the retransmission instruction for the program operation data at at least one running time, the set read address can be accurately determined, and the program operation data at at least one running time is read from the target memory and resent, realizing reliable confirmation and efficient retransmission of program operation data transmission, effectively ensuring the integrity and accuracy of data transmission, and improving the reliability of program operation data transmission.

[0024] In some embodiments, the method further includes: when the program operation data conforming to the second communication protocol is configured for real-time transmission, sending the program operation data of the second communication protocol stored in the cache of the storage module to the computer device in real time; wherein, the storage module includes a random access memory, a cache and a read-only memory; the capacity in the random access memory is greater than the capacity of the cache and less than the capacity of the read-only memory.

[0025] In the technical solution provided by the embodiments of the present application, when the program operation data conforming to the second communication protocol is configured for real-time transmission, the program operation data in the cache of the storage module can be immediately sent to the computer device in real time, greatly shortening the delay time of data transmission, realizing instant interaction and processing of data, and improving data transmission efficiency; moreover, it can perform real-time transmission of program operation data only when the program operation data conforming to the second communication protocol is configured for real-time transmission, avoiding real-time transmission when it is not configured for real-time transmission, not only reducing the operation load of the data processing chip, but also avoiding the problem of data loss when the computer device does not support real-time acquisition of runtime, and improving the reliability of data transmission.

[0026] In some embodiments, the method further includes: when the program operation data conforming to the second communication protocol is configured to be transmitted through the read-only memory, detecting the connection state between the debugger and the computer device; when the connection state is that the debugger is disconnected from the computer device during the hardware-in-the-loop test and the debugger is successfully connected to the computer device after the hardware-in-the-loop test ends, reading all the stored program operation data conforming to the second communication protocol in the read-only memory according to the received predetermined data reading request sent by the computer device; and sending all the stored program operation data conforming to the second communication protocol to the computer device.

[0027] In the technical solution provided by the embodiments of the present application, when the program operation data is configured to be transmitted through the read-only memory, even if the debugger is disconnected from the computer device during the hardware-in-the-loop test, the stable storage performance of the read-only memory can be relied on to completely retain the program operation data conforming to the second communication protocol. After the test ends and the connection between the debugger and the computer device is restored, according to the predetermined data reading request of the computer device, all the stored program operation data is accurately transmitted back, effectively avoiding the risk of data loss and improving the comprehensiveness of the program operation data obtained by the computer device.

[0028] In a second aspect, the present application provides a hardware-in-the-loop test system. The hardware-in-the-loop test system includes: a device under test, a computer device, and a debugger; the debugger includes a data processing chip and a storage module; the device under test is configured to send program operation data conforming to the first communication protocol to the data processing chip; the first communication protocol is a protocol for testing the device under test; the program operation data is the operation data fed back by the stub programs in the test program of the device under test, and a plurality of stub programs are pre-set at key program positions in the test program of the device under test through instrumentation; the data processing chip is configured to convert the program operation data conforming to the first communication protocol into program operation data conforming to the second communication protocol and store the program operation data conforming to the second communication protocol in the storage device; the second communication protocol is a protocol adapted to the computer device; the data processing chip is further configured to read the program operation data conforming to the second communication protocol in the storage device for the computer device to obtain the program operation data conforming to the second communication protocol stored in the storage module.

[0029] In a third aspect, the present application provides a data storage device, which includes: a protocol conversion module for converting the program operation data conforming to the first communication protocol output by the device under test in real time into program operation data conforming to the second communication protocol; the first communication protocol is a protocol for testing the device under test, and the second communication protocol is a protocol adapted to the computer device; the program operation data is the operation data fed back by the stub programs in the test program of the device under test, and a plurality of stub programs are pre-set at the key program positions in the test program of the device under test through instrumentation; a storage control module for storing the program operation data conforming to the second communication protocol into the storage module for the computer device to obtain the program operation data conforming to the second communication protocol stored in the storage module.

[0030] In a fourth aspect, the present application provides a debugger, which includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, the steps of the method according to any one of the first aspect are implemented.

[0031] In a fifth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method according to any one of the first aspect are implemented.

[0032] In a sixth aspect, the present application provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of the method according to any one of the first aspect are implemented. Description of the Drawings

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments of the present application or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other related drawings can be obtained based on these drawings.

[0034] Figure 1 It is a schematic structural diagram of the hardware-in-the-loop test system provided in the first embodiment;

[0035] Figure 2 It is a schematic flowchart of the data storage method provided in the first embodiment;

[0036] Figure 3 It is a schematic flowchart of the data storage method provided in the second embodiment;

[0037] Figure 4 It is a schematic flowchart of the data storage method provided in the third embodiment;

[0038] Figure 5 It is a schematic flowchart of the data storage method provided in the fourth embodiment;

[0039] Figure 6 Flow schematic diagram of the data storage method provided for the fifth embodiment;

[0040] Figure 7 Structural schematic diagram of the hardware-in-the-loop test system provided for the second embodiment;

[0041] Figure 8 Structural schematic diagram of the hardware-in-the-loop test system provided for the third embodiment;

[0042] Figure 9 Structural schematic diagram of the data storage device provided for some embodiments;

[0043] Figure 10 Structural schematic diagram of a debugger provided for some embodiments. Detailed implementation manners

[0044] Next, embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application, so they are only examples and cannot be used to limit the protection scope of the present application.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above accompanying drawing descriptions are intended to cover non-exclusive inclusion.

[0046] In the description of the embodiments of this application, technical terms such as "first" and "second" are only used to distinguish different objects and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity, specific order or primary-secondary relationship of the indicated technical features. In the description of the embodiments of this application, "a plurality" means more than two unless otherwise specifically defined. In the description of the embodiments of this application, "each" means each or every one of a plurality unless otherwise specifically defined.

[0047] Referring to "embodiment" in this article means that specific features, structures or characteristics described in connection with the embodiment may be included in at least one embodiment of this application. The phrase appears in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0048] In the description of the embodiments of the present application, the term "and / or" is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, the character " / " in this text generally represents an "or" relationship between the associated objects before and after.

[0049] Figure 1 Schematic diagram of the hardware-in-the-loop test system provided for the first embodiment, as Figure 1 shown, the hardware-in-the-loop test system includes a computer device, a communication device, a debugger, a device under test, and a test bench. The computer device is connected to the device under test through the communication device, the computer device is connected to the test bench through the communication device, the computer device is also connected to the device under test through the debugger, and the device under test is also connected to the test bench. In some embodiments, the debugger may include a data parser.

[0050] Exemplarily, the computer device may include one of the following: a test host, a computer, an industrial control computer, or a server, etc. Exemplarily, the communication device may include a CAN communication device or a Tongxing communication device, etc. Exemplarily, the device under test may be a whole vehicle or a processing device in the whole vehicle. For example, the processing device may include a Battery Management System (BMS) or an Electronic Control Unit (ECU), etc.

[0051] The test bench is connected to the device under test. The computer device is further configured to, in response to a test start instruction to start testing the test program, send the condition parameters of each operating condition to the test bench connected to the device under test through the communication device; the test bench is configured to simulate an environment matching the condition parameters of each operating condition according to the condition parameters of each operating condition, so that the device under test operates in each operating condition.

[0052] The test bench is configured to simulate the real working environment of the device under test. For example, the test bench can provide high voltage and low voltage to the device under test to enable the device under test to operate. For another example, the test bench can provide signals of different engine speeds and different loads simulated by it to the device under test, so as to provide an operating environment with different speeds and different loads for the device under test.

[0053] The computer device can obtain the operation data of the device under test through the communication device, and determine whether the test of the device under test passes according to whether the operation data is abnormal. Exemplarily, a test software can be installed in the computer device to obtain the operation data of the device under test. Exemplarily, the device under test outputs a CAN message to the communication device, so that the communication device sends the CAN message to the computer device, and the CAN message includes the operation data of the device under test under various operating conditions.

[0054] Exemplarily, the device under test can output program operation data to the debugger. The program operation data includes the position and / or running time of the stub program. The debugger transmits the program operation data to the computer device. The device under test can send the status operation data of the device under test to the computer device through the communication device. Exemplarily, the status operation data can include the operation data of voltage, current, temperature, and power consumption.

[0055] In some solutions, a trace debugger can be used. The trace debugger exports data to an external trace buffer or storage device through a dedicated trace interface. However, the trace debugger is expensive and has low applicability for hardware-in-the-loop testing.

[0056] Moreover, during the use of the debugger, the debugger obtains the program operation data of the device under test in real time and transmits the program operation data to the computer device in real time. However, the computer device often freezes during the test, or the computer device does not support obtaining the program operation data in real time (that is, the debugger and the computer device cannot interact in real time. For example, the program operation data is received at a preset time point every preset time interval). The computer device cannot obtain the program operation data set sent by the debugger during the freeze, or the computer device cannot obtain the program operation data outside the preset time point, resulting in the computer device being unable to obtain the complete program operation status of the test program in the device under test, and the computer device often being unable to monitor the complete program operation status of the test program in the device under test during the test, resulting in low reliability of the test of the device under test.

[0057] To alleviate the above problems, a new debugger will be provided. The new debugger is not a trace debugger. Through research, it is found that when the debugger obtains the program operation data, it stores the program operation data. In this way, even when the computer device freezes, or when the computer device does not support obtaining the program operation data in real time, the debugger can still send the program operation data stored in its internal storage module to the computer device, improving the integrity of the computer device's acquisition of the program operation status of the test program in the device under test during the test, and thus improving the reliability of the test of the device under test.

[0058] Based on the above considerations, the present application provides a data storage method, which is applied to a data processing chip in a debugger for hardware-in-the-loop testing. A storage module connected to the data processing chip is also configured in the debugger. The method includes: converting the program operation data conforming to the first communication protocol output by the device under test in real time into program operation data conforming to the second communication protocol; the first communication protocol is a protocol for testing the device under test, and the second communication protocol is a protocol adapted to the computer device; the program operation data is the operation data fed back by the stub programs in the test program of the device under test, and multiple stub programs are pre-set at key program positions in the test program of the device under test through instrumentation; storing the program operation data conforming to the second communication protocol into the storage module for the computer device to obtain the program operation data conforming to the second communication protocol stored in the storage module.

[0059] In this way, after the debugger obtains the program operation data, the program operation data is stored in the storage module. Thus, even when the computer device is stuck or the computer device does not support real-time acquisition of program operation data, the computer device can still obtain the program operation data stored in the storage module, improving the integrity of the program operation status of the test program in the device under test obtained by the computer device during the test, and further improving the reliability of the test of the device under test; in addition, the debugger is connected between the device under test and the computer device, and the data processing chip in the debugger can perform communication protocol conversion, solving the problem of protocol incompatibility between the device under test and the computer device, and there is no need to configure the computer device additionally to support the first communication protocol, expanding the application scope of the debugger; and the program operation data stored in the storage module conforms to the second communication protocol. Therefore, when the computer device needs to read the program operation data, the stored program operation data of the second communication protocol is forwarded, and there is no need to perform the step of protocol conversion, reducing the delay of the computer device in reading the program operation data of the second communication protocol.

[0060] Figure 2 The flow chart of the data storage method provided for the first embodiment is as Figure 2 shown. This method is applied to a data processing chip in a debugger for hardware-in-the-loop testing. The method includes:

[0061] S201. Convert the program operation data conforming to the first communication protocol output by the device under test in real time into program operation data conforming to the second communication protocol.

[0062] Among them, the first communication protocol is a protocol for testing the device under test, and the second communication protocol is a protocol adapted to the computer device; the program operation data is the operation data fed back by the stub programs in the test program of the device under test, and multiple stub programs are pre-set at key program positions in the test program of the device under test through instrumentation.

[0063] Exemplarily, the device under test can be subjected to hardware-in-the-loop testing through a hardware-in-the-loop test system. In the hardware-in-the-loop testing of the device under test, the device under test can be tested under multiple operating conditions. Exemplarily, taking the device under test as a BMS, the multiple operating conditions can cover various scenarios from battery charging and discharging to fault handling. For example, the multiple operating conditions can include at least two of the following: slow charge condition, fast charge condition, discharge condition, high temperature condition, low temperature condition, high altitude condition, overvoltage fault condition, overcurrent fault condition, thermal runaway warning condition, battery balancing condition, sleep condition, wake-up condition, etc., and the embodiments of the present application are not limited thereto.

[0064] For example, the first communication protocol can include a protocol for in-chip testing. Exemplarily, the first communication protocol includes the Joint Test Action Group (JTAG) protocol.

[0065] For example, the second communication protocol can include one of the following: Universal Serial Bus (USB), Video Graphics Array (VGA), High Definition Multimedia Interface (HDMI), etc. For example, the target protocol data includes the USB communication protocol.

[0066] The device under test outputs program operation data conforming to the first communication protocol in real time. The data processing chip receives the program operation data conforming to the first communication protocol in real time, converts the program operation data conforming to the first communication protocol output by the device under test in real time into program operation data conforming to the second communication protocol, and stores the program operation data of the second communication protocol in the storage module in real time. Exemplarily, the data processing chip can include a protocol conversion module, and the protocol conversion module is used to convert the program operation data conforming to the first communication protocol received in real time into program operation data conforming to the second communication protocol, and store the program operation data conforming to the second communication protocol in the storage module.

[0067] In some embodiments, the operation data fed back by the stub program can include the running position of the stub program and the running time of the stub program.

[0068] In some embodiments, the running position of the stub program may be the identifier and / or position of the basic test block associated with the stub program. In some other embodiments, the running position of the stub program may be the program line where the stub program is located in the test program. In some embodiments, the stub program may be a program for feeding back the running position of the stub program. In some other embodiments, the stub program may be a program for feeding back the running position and running time of the stub program.

[0069] In some embodiments, the running time of the stub program may be the time recorded by a timer in the device under test. In some other embodiments, the running time of the stub program may be the standard time recorded after the device under test synchronizes time with the computer device.

[0070] Exemplarily, the test program may include several basic test blocks. A stub program is set at the input point (also referred to as the entry point or program start point) of each basic test block, and a stub program is set at the output point (also referred to as the exit point or program end point) of each basic test block. Additionally exemplarily, the test program may be divided according to the variables to be measured to obtain multiple basic test blocks, and a stub program is set before each basic test block, or after each basic test block, or before and after each basic test block.

[0071] Exemplarily, the key program positions in the test program generally refer to those code segments in the program that have a significant impact on the overall performance and function of the program. Exemplarily, the key program positions in the test program may include at least one of the following: the position of the core data processing function, the position of the program for outputting the running data of the variable to be measured, the position of the input / output interface, the position of the conditional statement, the front and back positions of the loop structure, the position of the function call, the position of the exception handling, etc. The embodiments of the present application are not limited thereto.

[0072] Instrumentation (also known as program instrumentation) is to insert some probes into the program on the basis of maintaining the original logical integrity of the program under test. The probes are essentially code segments for information collection (i.e., stub programs), which can be assignment statements or function calls for collecting coverage information. By executing the probes, characteristic data of the program running (such as the running data of the device under test) is thrown. By analyzing these data, the control flow and data flow information of the program can be obtained, and then dynamic information such as logical coverage can be obtained, so as to achieve the test purpose.

[0073] In any embodiment of the present application, inserting at least one stub program in a program segment or a position may include inserting the stub program at least one of the positions before, after, or several intermediate positions in the program segment or position.

[0074] In some embodiments, the computer device may send the type of variable to be measured to the device under test through a communication device, so that the device under test can determine the key program location according to the type of variable to be measured and enable the stub program at the key program location. Exemplarily, the type of variable to be measured may include: temperature, voltage, current, power, battery charge state, etc., and the embodiments of the present application are not limited thereto. In some embodiments, the operation data fed back by the stub program in the test program of the device under test may include the operation data fed back by the stub program enabled in the test program of the device under test. In some embodiments, the type of variable to be measured may be adjusted according to the different operating conditions of the device under test.

[0075] In some embodiments, by the stub program feeding back the location of the stub program, the computer device can obtain the execution order of the basic test blocks in the test program of the stub program. In some embodiments, by the stub program feeding back the running time when the stub program runs, the computer device can obtain the execution timing of the basic test blocks in the test program of the stub program.

[0076] S202. Store the program operation data conforming to the second communication protocol into the storage module for the computer device to obtain the program operation data conforming to the second communication protocol stored in the storage module.

[0077] In some embodiments, the program operation data conforming to the second communication protocol may be stored into the storage module according to the clock signal configured by the computer device. In other embodiments, the program operation data conforming to the second communication protocol may be stored into the storage module according to the clock signal pre-configured by the data processing chip. Wherein, the clock signal may be a waveform signal with a preset frequency, and by configuring the clock period, the storage speed of storing the program operation data of the second communication protocol into the storage module can be adjusted.

[0078] In some embodiments, the data processing chip may have a data interaction function. For example, the data processing chip may include a communication module (such as a communication module of the second communication protocol), and the communication module is used to read the program operation data of the second communication protocol from the storage module and send the program operation data conforming to the second communication protocol to the computer device. Hereinafter, the interaction operations between the data processing chip and the computer device, such as the data processing chip receiving the instruction sent by the computer device and the data processing chip sending the program operation data conforming to the second communication protocol to the computer device, may all include the interaction operations between the communication module and the computer device.

[0079] In some embodiments, the communication bandwidth of the first communication protocol may be less than that of the second communication protocol. Herein, the communication bandwidth refers to the number of bits that can be transmitted per unit time. The larger the communication bandwidth, the more data that can be transmitted per unit time, and the faster the supported transmission rate. In some other embodiments, the communication bandwidth of the first communication protocol may be equal to that of the second communication protocol.

[0080] In some embodiments, the data processing chip may actively read the program operation data conforming to the second communication protocol and send the program operation data conforming to the second communication protocol to the computer device. For example, the data processing chip may read in real time the program operation data conforming to the second communication protocol and send in real time the read program operation data conforming to the second communication protocol to the computer device. For another example, the data processing chip may read the program operation data of the second communication protocol stored within a preset duration every preset duration and send the program operation data of the second communication protocol stored within the preset duration to the computer device.

[0081] In some other embodiments, the data processing chip may read the program operation data conforming to the second communication protocol according to the data reading instruction of the computer device and send the program operation data conforming to the second communication protocol to the computer device. For example, during the hardware-in-the-loop test, each time the data processing chip receives the data reading instruction sent by the computer device, the data processing chip may read the unread program operation data in the storage module and send the read program operation data to the computer device. For another example, after the hardware-in-the-loop test is completed, the data processing chip may receive the data reading instruction sent by the computer device, the data processing chip reads all the program operation data stored in the storage module and sends the read program operation data to the computer device.

[0082] In the embodiments of the present application, data reading and data sending are carried out synchronously. For example, every time the data processing chip reads a preset number of bits of data, it sends the preset number of bits of data to the computer device, and then continues to read the next preset number of bits of data and sends the next preset number of bits of data to the computer device until the data reading and sending are completed.

[0083] Exemplarily, the number of bits occupied by the program operation data of different stub programs or the same stub program with different feedbacks is the same. For example, the number of bits occupied by the running positions of different stub programs or the same stub program with different feedbacks is the same, and the running times of different stub programs or the same stub program with different feedbacks are different, but the number of bits occupied is the same.

[0084] Exemplarily, the program running data of the second communication protocol can be stored in a row storage manner. For example, according to the bandwidth corresponding to the second communication protocol and the clock signal sent by the computer device (the clock signal is a waveform signal with a preset frequency), the maximum number of bits transmitted in each cycle of the waveform signal can be determined. According to the maximum number of bits transmitted in each cycle, the number of data packets of the second communication protocol transmitted each time can be determined, and the number of data packets of the second communication protocol transmitted each time is determined as a data block. Among them, the number of data packets transmitted each time can include at least one or multiple feedbacks of program running data. Exemplarily, the number of program running data included in different data packets is the same.

[0085] In the technical solution provided by the embodiments of the present application, after the debugger obtains the program running data, the program running data is stored in the storage module. In this way, even when the computer device is stuck or the computer device does not support real-time acquisition of program running data, the computer device can still obtain the program running data stored in the storage module, improving the integrity of the program running status of the test program in the device under test obtained by the computer device during the test process, and further improving the reliability of the test of the device under test; in addition, the debugger is connected between the device under test and the computer device, and the data processing chip in the debugger can perform communication protocol conversion, solving the problem of protocol incompatibility between the device under test and the computer device, and there is no need to perform additional configuration on the computer device to make the computer device support the first communication protocol, expanding the application range of the debugger; and the program running data stored in the storage module conforms to the second communication protocol. Therefore, when the computer device needs to read the program running data, the stored program running data of the second communication protocol is forwarded, and there is no need to perform the step of protocol conversion, reducing the delay of the computer device reading the program running data of the second communication protocol.

[0086] Figure 3 It is a schematic flowchart of the data storage method provided for the second embodiment. As Figure 3 shown, this method is applied to the data processing chip in the debugger for hardware-in-the-loop testing. Figure 3 The difference between this embodiment and Figure 2 the embodiment is that the storage module includes multiple types of storage units; S202 includes S2021 to S2023.

[0087] S2021: Receive the transmission configuration information sent by the computer device; the transmission configuration information is used to represent the transmission path of the program running data conforming to the second communication protocol.

[0088] In some embodiments, the transmission path may include at least one of the following: the path through the random access memory, the real-time transmission path, the path through the read-only memory, etc.

[0089] In some embodiments, the transmission configuration information may be sent by a computer device to a data processing chip before a hardware-in-the-loop test process. Exemplarily, the data processing chip may determine, according to the transmission configuration information, that during the hardware-in-the-loop test process, the program operation data is always stored and transmitted according to the transmission configuration information.

[0090] In other embodiments, the transmission configuration information may be sent to the data processing chip before and during the hardware-in-the-loop test process. Exemplarily, the computer device may dynamically send the transmission configuration information to the data processing chip according to its own current computing load and / or its own transmission requirements, so that the data processing chip stores and transmits the program operation data according to the latest configured transmission configuration information of the computer device. For example, in a case where the computer device needs to focus on processing other services, obtaining the program operation data may be postponed.

[0091] For example, when the computing load of the computer device is greater than or equal to a preset load, it indicates that the computer device is severely stuck, and the computer device may send the transmission configuration information transmitted through a read-only memory to the data processing chip; when the computing load of the computer device is less than the preset load and greater than or equal to a set load, it indicates that the computer device is moderately stuck, and the computer device may send the transmission configuration information transmitted through a random access memory to the data processing chip; when the computing load of the computer device is less than the set load, it indicates that the computer device is running smoothly, and the computer device may send the transmission configuration information for real-time transmission of the program operation data to the data processing chip.

[0092] S2022. Determine a target type of a storage unit for storing program operation data that complies with a second communication protocol according to the transmission configuration information.

[0093] Exemplarily, different transmission configuration information may correspond to different target types. Exemplarily, the target type of the storage unit may include a random access memory type (Random Access Memory, RAM), a cache type, and a read-only memory type (Read Only Memory, ROM).

[0094] The random access memory may be a volatile memory. Exemplarily, the random access memory may be in various forms, such as a static random access memory (Static Random Access Memory, SRAM) or a dynamic random access memory (Dynamic Random Access Memory, DRAM), etc.

[0095] The read-only memory can be a non-volatile memory. Exemplarily, the read-only memory can include one of the following: Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Ferromagnetic Random Access Memory (FRAM), Flash Memory, magnetic surface memory, optical disc, Compact Disc Read-Only Memory (CD-ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, Resistive Random Access Memory (ReRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Phase Change Memory (PCM), graphene memory, volatile memory, etc.

[0096] S2023. Store the program running data conforming to the second communication protocol in the storage unit of the target type.

[0097] In the technical solution provided by the embodiments of the present application, by receiving the transmission path of the program running data represented by the transmission configuration information sent by the computer device, and accurately matching the target type of the storage unit accordingly for data storage, it is possible to adapt to the corresponding storage unit according to the characteristics of different transmission paths, achieve classified data storage, not only improve the utilization efficiency of storage resources, but also ensure data integrity and storage stability, and avoid problems such as data loss and transmission delay caused by improper selection of storage units, significantly improving the flexibility and reliability of data storage for different transmission paths.

[0098] In some embodiments, determining the target type of the storage unit for storing the program running data conforming to the second communication protocol according to the transmission configuration information may include: when the transmission configuration information indicates that the program running data conforming to the second communication protocol is transmitted through a random access memory, determining that the target type of the storage unit is a random access memory type.

[0099] Exemplarily, the data writing rate of the read-only memory should be greater than or equal to the data writing rate of the random access memory. Exemplarily, the data writing rate in the read-only memory should be greater than or equal to the data reading rate of the random access memory.

[0100] Exemplarily, in the storage module of the debugger, the capacity of the random access memory is greater than the capacity of the cache, and the capacity of the random access memory is less than the capacity of the read-only memory.

[0101] In this way, because the capacity of the random access memory is moderate, it can meet the requirements of quickly storing and reading a certain amount of data. Also, due to its characteristics, the reading speed can also be maintained at a relatively high level. Thus, through the random access memory, it can not only meet the storage operation of program running data with a certain amount of data, satisfy the situation where the computer device cannot obtain program running data in real time, enable the computer device to intermittently obtain the program running data in the random access memory, improve the integrity of the program running data obtained by the computer device, thereby improving the reliability of the program running data transmission, but also quickly read the data, improving the transmission efficiency of the program running data.

[0102] In some embodiments, according to the transmission configuration information, determining the target type of the storage unit for storing program running data conforming to the second communication protocol may include: when the transmission configuration information indicates real-time transmission of program running data conforming to the second communication protocol, determining the target type of the storage unit as the cache type.

[0103] In this way, the cache has an extremely fast read and write speed. Although its capacity is relatively small, it is sufficient for the temporary storage and quick access of real-time data. By storing real-time data in the cache, it can ensure that the data can be processed and responded to in a timely manner, avoiding system lags or errors caused by data transmission delays, and providing stable and reliable support for applications with extremely high real-time requirements.

[0104] In some embodiments, according to the transmission configuration information, determining the target type of the storage unit for storing program running data conforming to the second communication protocol may include: when the transmission configuration information indicates that the program running data conforming to the second communication protocol is transmitted through the read-only memory, determining the target type of the storage unit as the read-only memory type.

[0105] In some embodiments, the capacity in the read-only memory may be greater than or equal to the program operation data of all the second communication protocols in one hardware-in-the-loop test. In this way, during the hardware-in-the-loop test, there is no need for the computer device to obtain the program operation data, and the computer device can be powered off. After the computer device is powered on, it can obtain the program operation data conforming to the second communication protocol in the read-only memory. In this solution, it is applicable to the following scenario: when the engineer is about to get off work, the engineer can send the transmission configuration information indicating that the program operation data conforming to the second communication protocol is transmitted through the read-only memory to the data processing chip in the debugger. Then the engineer can turn off the computer device, and the program operation data of the second communication protocol will also be stored in the read-only memory and will not be lost due to the power-off of the computer device. After the engineer turns on the computer device the next day, the engineer can send a data reading request to the data processing chip of the debugger, so that the data processing chip reads the program operation data of the second communication protocol from the read-only memory and sends the program operation data of the second communication protocol to the computer device.

[0106] In this way, the advantages of high data stability and non-loss of data during power-off of the read-only memory can be fully utilized, and the reliability of data storage of the program operation data of the second communication protocol is improved.

[0107] In the technical solution provided by the embodiments of the present application, dynamically selecting a suitable memory type according to the transmission configuration information can achieve the optimal allocation of storage resources, and avoid problems such as waste of storage resources and reduction of data transmission efficiency caused by using an inappropriate memory type. For example, storing data that needs to be transmitted in real time in a cache with a small capacity but high speed, storing data that needs to be stored when powered off in a large-capacity read-only memory, and storing data that requires a certain amount of storage and needs to be read quickly in a random access memory with a moderate capacity. Thus, the corresponding memory type can be flexibly selected according to the reliability and speed of data transmission, improving the utilization efficiency of storage resources.

[0108] In some embodiments, storing the program operation data conforming to the second communication protocol in the storage unit of the target type includes: when the transmission configuration information indicates that the program operation data conforming to the second communication protocol is transmitted through the random access memory in the storage module, storing the program operation data conforming to the second communication protocol in the cache in the storage module, and transferring the program operation data conforming to the second communication protocol in the cache to the random access memory.

[0109] In some embodiments, the data read from the cache can be verified to reduce the accuracy rate of data transmission.

[0110] In some embodiments, storing program operation data conforming to a second communication protocol in a storage unit of a target type includes: when the transmission configuration information indicates that the program operation data conforming to the second communication protocol is transmitted in real time, storing the program operation data conforming to the second communication protocol in a cache in a storage module.

[0111] In some embodiments, storing program operation data conforming to a second communication protocol in a storage unit of a target type includes: when the transmission configuration information indicates that the program operation data conforming to the second communication protocol is transmitted through a read-only memory in a storage module, storing the program operation data conforming to the second communication protocol in a cache in the storage module, transferring the program operation data conforming to the second communication protocol in the cache to a random access memory in the storage module, and transferring the program operation data conforming to the second communication protocol in the random access memory to the read-only memory.

[0112] In some embodiments, the read-only memory may include a ferroelectric memory, and the read / write speed of the ferroelectric memory is greater than or equal to the read / write speed of the random access memory.

[0113] In the technical solution provided by the embodiments of the present application, after the data of the data processing chip after protocol conversion is first written into the cache and then read from the cache and written into the random access memory, the write latency of the cache is lower than that of the random access memory, and the write latency in the random access memory is lower than that of the read-only memory. Therefore, the cache can immediately respond to the data storage of the data processing chip. Compared with the solution of directly writing the data of the data processing chip after protocol conversion into the random access memory, or compared with the solution of directly writing the data of the data processing chip after protocol conversion into the read-only memory, the data processing chip does not need to wait for a high latency for the data writing to be completed before it can perform the next operation, improving the processing efficiency of the data processing chip; and, by writing from the random access memory to the read-only memory, and the read-only memory needs to be written page by page. Therefore, multiple small data stored in the random access memory can be combined into a complete page and written into the read-only memory page by page. Compared with the solution of directly writing the data in the cache into the read-only memory, the write times of the read-only memory are reduced, not only reducing the aging risk of the read-only memory caused by the write times limit of the read-only memory, improving the lifespan of the read-only memory, but also improving the write efficiency of the read-only memory.

[0114] In some embodiments, transferring the program running data that conforms to the second communication protocol in the cache to the random access memory includes: receiving a clock signal sent by a computer device; the clock signal is a waveform signal with a preset frequency; according to the waveform signal with the preset frequency and the number of bytes written to the random access memory each time configured in advance, transferring the program running data that conforms to the second communication protocol in the cache to the random access memory at the preset frequency. The method further includes: according to the waveform signal with the preset frequency and the number of bytes read from the random access memory each time configured in advance, sending the program running data that conforms to the second communication protocol in the random access memory to the computer device at the preset frequency.

[0115] In some embodiments, the clock signal may include a Serial Peripheral Interface (SPI) clock signal. Exemplarily, both the computer device and the debugger may include an SPI interface, so that the computer device sends the SPI clock signal to the debugger. Exemplarily, the computer device may implement the SPI interface through an expansion card or a USB adapter.

[0116] The SPI clock signal is a periodic signal generated by the master device (i.e., the computer device) and is used to synchronize data transmission between the master device and the slave device (i.e., the debugger). The SPI clock signal controls the rhythm and timing of data transmission between the master and slave devices, ensuring that both parties can accurately send and receive data.

[0117] The waveform signal with the preset frequency may include a periodic waveform signal with the preset frequency. Exemplarily, the waveform signal may include a square wave signal.

[0118] In some embodiments, the data processing chip may include a random access transfer processing module. When the communication module of the data processing chip receives the transmission configuration information indicating that the program running data conforming to the second communication protocol is transmitted through the random access memory, it may send a data transfer instruction to the random access transfer processing module, so that the random access transfer processing module transfers the data in the cache to the random access memory. In some embodiments, the SPI interface may transmit the clock signal to the random access transfer processing module.

[0119] In some embodiments, data may be written to the random access memory according to the number of bytes written to the random access memory each time at each rising edge or falling edge of the waveform signal with the preset frequency.

[0120] In the technical solution provided by the embodiment of the present application, based on the waveform signal with a preset frequency, the rhythm of data transfer to the random access memory can be accurately controlled, avoiding problems such as data loss and misalignment caused by timing chaos, ensuring that the program running data is transferred to the random access memory completely and orderly, and improving the accuracy of data transfer from the cache to the random access memory; transferring data to the random access memory according to the number of written bytes can make full use of the high-speed reading and writing characteristics of the random access memory, reduce the number of data transfer interactions, reduce the transfer delay, and improve the timeliness of data transfer; and sending data to the computer device according to the waveform signal with a preset frequency and the number of bytes read from the random access memory each time, thereby improving the correctness and synchronization of the data processing chip sending data to the computer device, and further improving the reliability of data transmission.

[0121] In some embodiments, transferring the program running data conforming to the second communication protocol in the random access memory to the read-only memory includes: receiving the clock signal sent by the computer device; the clock signal is a waveform signal with a preset frequency; according to the waveform signal with a preset frequency and the number of bytes written to the read-only memory each time configured in advance, transferring the program running data conforming to the second communication protocol in the random access memory to the read-only memory at the preset frequency. The method further includes: sending the program running data conforming to the second communication protocol in the read-only memory to the computer device at the preset frequency according to the waveform signal with a preset frequency and the number of bytes read from the read-only memory each time configured in advance.

[0122] In some embodiments, the data processing chip may include a read-only transfer processing module. When the communication module of the data processing chip receives the transmission configuration information indicating that the program running data conforming to the second communication protocol is transmitted through the read-only memory, it may send data transfer instructions to both the random access transfer processing module and the read-only memory, so that the random access transfer processing module transfers the data in the cache to the random access memory, and the read-only transfer processing module transfers the data in the random access memory to the read-only memory. In some embodiments, the SPI interface may transmit the clock signal to the read-only transfer processing module.

[0123] In some embodiments, data may be written to the read-only memory at each rising edge or falling edge of the waveform signal with a preset frequency according to the number of bytes written to the read-only memory each time.

[0124] In some embodiments, the number of bytes written to the read-only memory each time can be the same as the number of bytes written to the random access memory each time. In this way, the waveform signal with a unified preset frequency constructs a stable and synchronous transmission rhythm for the transfer of data between different storage media, effectively avoiding problems such as timing chaos, loss, or misalignment during data transmission, greatly ensuring the integrity and accuracy of data. Through the design of the same number of written bytes, the control logic and configuration management of data transmission are simplified, and the complexity of system design and development cost are reduced.

[0125] In the technical solution provided by the embodiments of the present application, based on the waveform signal with a preset frequency, the rhythm of data transfer to the read-only memory can be accurately controlled, avoiding problems such as data loss and misalignment caused by timing chaos, ensuring that the program running data is transferred to the read-only memory completely and orderly, improving the accuracy of data transfer from the random access memory to the read-only memory, and transferring data to the read-only memory according to the number of written bytes can make full use of the high-speed read-write characteristics of the read-only memory, reduce the number of interactions for data transfer, reduce the transfer delay, and improve the timeliness of data transfer; and sending data to the computer device according to the waveform signal with a preset frequency and the number of bytes read from the read-only memory each time configured in advance, thereby improving the correctness and synchronization of data sent by the data processing chip to the computer device, and further improving the reliability of data transmission.

[0126] In some embodiments, after S202, the following steps may further be performed: reading the program running data conforming to the second communication protocol from the storage module, and sending the program running data conforming to the second communication protocol to the computer device. In some embodiments, when the transmission configuration information indicates that the program running data conforming to the second communication protocol is transmitted through the random access memory, data is read from the random access memory; when the transmission configuration information indicates that the program running data conforming to the second communication protocol is transmitted in real time, data is read from the cache; when the transmission configuration information indicates that the program running data conforming to the second communication protocol is transmitted through the read-only memory, data is read from the read-only memory.

[0127] In some embodiments, any two of the number of bytes written to the read-only memory each time, the number of bytes written to the random access memory each time, and the number of bytes transmitted to the computer device each time may be the same, or all three may be the same.

[0128] The following Figures 4 to 6 embodiment illustrates the process of transmitting the program running data conforming to the second communication protocol:

[0129] Figure 4 is a schematic flowchart of the data storage method provided for the third embodiment, as Figure 4As shown, the method is applied to the data processing chip in the debugger for hardware-in-the-loop testing. Figure 4 The difference between this embodiment and Figure 2 the embodiment is that after S202, S203 to S204 are included.

[0130] S203. When the program running data conforming to the second communication protocol is configured to be transmitted through the target memory in the storage module, during the hardware-in-the-loop testing process, according to each received target data reading request, read the program running data conforming to the second communication protocol in the target memory.

[0131] Among them, the target memory includes a random access memory or a read-only memory.

[0132] In some embodiments, the storage module includes a random access memory, a cache, and a read-only memory; the capacity in the random access memory is greater than the capacity of the cache and less than the capacity of the read-only memory.

[0133] In some embodiments, the computer can send the target data reading request periodically or aperiodically. Correspondingly, the data processing chip can receive the target data reading request periodically or aperiodically.

[0134] In some embodiments, each time the data processing chip sends the program running data conforming to the second communication protocol, it can record the latest running time in the sent program running data, and the recorded latest running time is updated as the number of sending times increases, so as to determine the program running data between the next running time of the recorded latest running time and the latest running time in the storage module as the program running data to be sent next time.

[0135] In some other embodiments, each time the data processing chip sends the program running data conforming to the second communication protocol, it can record the end reading address in the sent program running data, and the recorded end reading address is updated as the number of sending times increases, so as to determine the program running data between the next address of the recorded end reading address and the last written address in the storage module as the program running data to be sent next time.

[0136] S204. Send the read program running data conforming to the second communication protocol to the computer device.

[0137] In the technical solution provided by the embodiment of the present application, when the target memory is a random access memory, the capacity of the random access memory is moderate, which not only avoids the problem that the data storage is insufficient due to too small storage capacity and cannot respond to the intermittent target data reading request sent by the computer device, but also prevents resource waste caused by too large capacity. Moreover, the fast reading performance of the random access memory enables the data processing chip to quickly read the data from the random access memory and send it to the computer device after receiving the target data reading request sent by the computer device, greatly improving the timeliness of data interaction and ensuring the efficiency of data transmission during the test. When the target memory is a read-only memory, the program operation data stored in the read-only memory can also be obtained during the hardware-in-the-loop test, avoiding the inability to read the program operation data in the read-only memory during the hardware-in-the-loop test and improving the timeliness of data transmission.

[0138] In some embodiments, according to each received target data reading request, reading the program operation data that conforms to the second communication protocol in the target memory includes: determining the target reading address of the program operation data that conforms to the second communication protocol to be read in the target memory according to the latest running time in the program operation data obtained by the computer device carried in each received target data reading request; and reading the program operation data that conforms to the second communication protocol from the target memory according to the target reading address.

[0139] In some embodiments, the end address of the program operation data corresponding to the latest running time can be determined according to the latest running time in the program operation data obtained by the computer device, and the target reading address can be determined according to the end address of the program operation data corresponding to the latest running time and the end address of the latest stored program operation data. For example, all the addresses between these two end addresses can be determined as the target reading address, or these two end addresses can be determined as the target reading address.

[0140] In some embodiments, the program operation data between the end address of the program operation data corresponding to the latest running time and the end address of the latest stored program operation data can be determined as the program operation data that conforms to the second communication protocol read this time.

[0141] In the technical solution provided by the embodiment of the present application, by carrying the latest running time in the program running data obtained by the computer device in the target data reading request, not only does the data processing chip not need to record the latest time of each sent program running data, reducing the internal resource occupation of the data processing chip and avoiding the computing overhead caused by frequent recording and updating of time, but also it can avoid the problem that the data processing chip sends the program running data but the computer device fails to obtain the program running data, resulting in incomplete program running data obtained by the computer device, and improving the reliability of data transmission.

[0142] In some embodiments, after the data processing chip receives each target data reading request and sends the read program running data that conforms to the second communication protocol to the computer device, the following steps can be executed: in the case of receiving the data reception success instruction sent by the computer device, determine that the program running data that conforms to the second communication protocol sent each time is sent successfully; in the case of receiving the retransmission instruction of the program running data at at least one running time sent by the computer device, determine the set reading address of the program running data at at least one running time; according to the set reading address, read the program running data that conforms to the second communication protocol at at least one running time from the target memory, and send the program running data that conforms to the second communication protocol at at least one running time to the computer device.

[0143] Exemplarily, each running time in at least one running time can be the running time in each program running data. In the case where the computer device sends the retransmission instruction of the program running data at at least one running time, it indicates that the computer device fails to receive the program running data at at least one running time. At this time, the retransmission mechanism can be adopted to make the data processing chip re-send the program running data at at least one running time to the computer device.

[0144] In the technical solution provided by the embodiment of the present application, by the data reception success instruction, it is determined that the program running data that conforms to the second communication protocol sent each time is sent successfully. By the retransmission instruction of the program running data at at least one running time, the set reading address can be accurately determined, and the program running data at at least one running time is read from the target memory and re-sent, realizing the reliable confirmation and efficient retransmission of the program running data transmission, effectively ensuring the integrity and accuracy of data transmission, and improving the reliability of the program running data transmission.

[0145] Figure 5 For the flowchart of the data storage method provided in the fourth embodiment, as Figure 5 shown, this method is applied to the data processing chip in the debugger for hardware-in-the-loop testing, Figure 5 The embodiment compared with Figure 2The difference in the embodiment is that after S202, S205 is included.

[0146] S205. When the program running data conforming to the second communication protocol is configured for real-time transmission, the program running data of the second communication protocol stored in the cache of the storage module is sent to the computer device in real time.

[0147] In the technical solution provided by the embodiment of the present application, when the program running data conforming to the second communication protocol is configured for real-time transmission, the program running data in the cache of the storage module can be immediately sent to the computer device in real time, greatly shortening the delay time of data transmission, realizing the instant interaction and processing of data, and improving the data transmission efficiency; moreover, it can perform real-time transmission of program running data only when the program running data conforming to the second communication protocol is configured for real-time transmission, avoiding real-time transmission when it is not configured for real-time transmission, not only reducing the operating load of the data processing chip, but also avoiding the problem of data loss when the computer device does not support real-time acquisition during operation, and improving the reliability of data transmission.

[0148] Figure 6 It is a schematic flowchart of the data storage method provided for the fifth embodiment, as Figure 6 shown. This method is applied to the data processing chip in the debugger for hardware-in-the-loop testing. Figure 6 The difference between this embodiment and Figure 2 the embodiment is that after S202, S206 to S208 are included.

[0149] S206. When the program running data conforming to the second communication protocol is configured to be transmitted through the read-only memory, the connection status between the debugger and the computer device is detected.

[0150] In some embodiments, the connection status between the debugger and the computer device can be detected when the hardware-in-the-loop testing starts. In other embodiments, the connection status between the debugger and the computer device can be detected when the debugger is turned on.

[0151] S207. When the connection status is that the debugger and the computer device are disconnected during the hardware-in-the-loop testing and are successfully connected after the hardware-in-the-loop testing ends, all the program running data conforming to the second communication protocol stored in the read-only memory is read according to the received predetermined data read request sent by the computer device.

[0152] In some embodiments, an indicator light can be set in the debugger. When the data processing chip does not receive program operation data conforming to the first communication protocol within a set time period, it is determined that the hardware-in-the-loop test ends. Or, when there are preset times of loops in the positions of the stub programs in the program operation data received by the data processing chip, it is determined that the hardware-in-the-loop test ends. The data processing chip can control the indicator light to turn on when the hardware-in-the-loop test ends.

[0153] S208. Send all the stored program operation data conforming to the second communication protocol to the computer device.

[0154] In this embodiment, through a predetermined data reading request, the transmission of all the stored program operation data conforming to the second communication protocol in the read-only memory can be realized, which simplifies the data acquisition process and improves the data transmission efficiency.

[0155] In the technical solution provided by the embodiments of the present application, when the program operation data is configured to be transmitted through the read-only memory, even if the debugger is disconnected from the computer device during the hardware-in-the-loop test, the stable storage performance of the read-only memory can be relied on to completely retain the program operation data conforming to the second communication protocol. After the test ends and the connection between the debugger and the computer device is restored, according to the predetermined data reading request of the computer device, all the stored program operation data is accurately transmitted back, effectively avoiding the risk of data loss and improving the comprehensiveness of the program operation data obtained by the computer device.

[0156] Figure 7 FIG. is a schematic structural diagram of the hardware-in-the-loop test system provided for the second embodiment, as Figure 7 shown. The hardware-in-the-loop test system includes a device under test, a computer device, and a debugger. The debugger includes a data processing chip and a storage module. Exemplarily, the data processing chip is configured to execute the method in any of the above embodiments.

[0157] In some embodiments, the device under test sends program operation data conforming to the first communication protocol to the data processing chip; the first communication protocol is a protocol for testing the device under test; the program operation data is the operation data fed back by the stub programs in the test program of the device under test, and multiple stub programs are pre-set at the key program positions in the test program of the device under test through instrumentation; the data processing chip can convert the program operation data conforming to the first communication protocol into program operation data conforming to the second communication protocol and store the program operation data conforming to the second communication protocol in the storage device; the second communication protocol is a protocol adapted to the computer device; the data processing chip can also read the program operation data of the second communication protocol in the storage device and send the program operation data of the second communication protocol to the computer device.

[0158] Figure 8 The structural schematic diagram of the hardware-in-the-loop test system provided for the third embodiment is as follows Figure 8 shown Figure 8 The system shown in the embodiment is different from Figure 7 the system shown in the embodiment in that the storage module includes a cache, a random access memory, and a read-only memory.

[0159] Among them, the data processing chip receives the transmission configuration information sent by the computer device. When the transmission configuration information indicates that the program operation data conforming to the second communication protocol is transmitted through the random access memory, the program operation data conforming to the second communication protocol is stored in the cache, and the program operation data of the second communication protocol in the cache is transferred to the random access memory; when receiving the data reading instruction sent by the computer device, the program operation data of the second communication protocol in the random access memory is read, and the program operation data of the second communication protocol is sent to the computer device.

[0160] When the transmission configuration information indicates that the program operation data conforming to the second communication protocol is transmitted in real time, the program operation data conforming to the second communication protocol is stored in the cache; then the program operation data of the second communication protocol in the cache is read, and the program operation data of the second communication protocol is sent to the computer device.

[0161] When the transmission configuration information indicates that the program operation data conforming to the second communication protocol is transmitted through the read-only memory, the program operation data conforming to the second communication protocol is stored in the cache, and the program operation data of the second communication protocol in the cache is transferred to the random access memory, and the program operation data of the second communication protocol in the random access memory is transferred to the read-only memory; when receiving the data reading instruction sent by the computer device, the program operation data of the second communication protocol in the read-only memory is read, and the program operation data of the second communication protocol is sent to the computer device.

[0162] In the hardware test system provided by the embodiments of the present application, in the hardware part, through a data processing chip (including protocol conversion function), the JTAG program running data is connected to the data processing chip through a debug port (such as a JTAG interface), and is converted into USB data by the data processing chip. The data read / write instructions are sent from a computer device to the data processing chip, and the USB data can be forwarded through a buffer, or can be forwarded through a random access memory, or can be forwarded through a read-only memory. The computer device can send an SPI clock signal to the data processing chip to control the data processing chip to write to the random access memory and the read-only memory through the SPI clock signal. In the software part, the computer device controls the writing to the random access memory and the read-only memory through the SPI clock signal, and sends data to the computer device. After the data processing chip converts the received JTAG program running data into USB data, it forwards it to the computer device so that the computer device can parse the USB data to obtain the program running data. In the debugger, real-time forwarding, first-level forwarding, and second-level forwarding are configured. Under real-time forwarding, the data is forwarded through a buffer. Under first-level forwarding, the data is forwarded through a random access memory. Under second-level forwarding, the data is forwarded through a read-only memory. When the performance of the computer host is poor or the load is high, which may affect the timeliness of data reading and storing programs, first-level forwarding is selected for configuration. When the computer device shuts down during the hardware test process, second-level forwarding is configured.

[0163] Based on the same inventive concept, the embodiments of the present application further provide a data storage device for implementing the data storage method involved above. The implementation solutions provided by this device to solve problems are similar to the implementation solutions described in the above method. Therefore, the specific limitations in one or more of the following data storage device embodiments can refer to the limitations on the data storage method in the above text, and will not be repeated here.

[0164] In an exemplary embodiment, Figure 9 For the structural schematic diagram of the data storage device provided for some embodiments, as Figure 9 shown, the data storage device 900 includes:

[0165] A protocol conversion module 901, configured to convert the program running data that conforms to the first communication protocol and is output in real time by the device under test into program running data that conforms to the second communication protocol; the first communication protocol is the protocol for testing the device under test, and the second communication protocol is the protocol adapted to the computer device; the program running data is the running data fed back by the stub programs in the test program of the device under test, and multiple stub programs are pre-set at key program positions in the test program of the device under test through instrumentation;

[0166] A storage control module 902 is configured to store program operation data conforming to the second communication protocol into the storage module for the computer device to obtain the program operation data conforming to the second communication protocol stored in the storage module.

[0167] In some embodiments, the storage module includes multiple types of storage units; the protocol conversion module 901 includes a receiving unit, a storage type determination unit, and a storage control unit. The receiving unit is configured to receive transmission configuration information sent by the computer device; the transmission configuration information is used to represent the transmission path of the program operation data conforming to the second communication protocol. The storage type determination unit is configured to determine the target type of the storage unit for storing the program operation data conforming to the second communication protocol according to the transmission configuration information. The storage control unit stores the program operation data conforming to the second communication protocol in the storage unit of the target type.

[0168] In some embodiments, the storage type determination unit is further configured to determine that the target type of the storage unit is a random access memory type when the transmission configuration information indicates that the program operation data conforming to the second communication protocol is transmitted through a random access memory.

[0169] In some embodiments, the storage type determination unit is further configured to determine that the target type of the storage unit is a cache type when the transmission configuration information indicates that the program operation data conforming to the second communication protocol is transmitted in real time.

[0170] In some embodiments, the storage type determination unit is further configured to determine that the target type of the storage unit is a read-only memory type when the transmission configuration information indicates that the program operation data conforming to the second communication protocol is transmitted through a read-only memory.

[0171] In some embodiments, the storage control unit is further configured to store the program operation data conforming to the second communication protocol in the cache in the storage module and transfer the program operation data conforming to the second communication protocol in the cache to the random access memory when the transmission configuration information indicates that the program operation data conforming to the second communication protocol is transmitted through the random access memory in the storage module.

[0172] In some embodiments, the storage control unit is further configured to store the program operation data conforming to the second communication protocol in the cache in the storage module when the transmission configuration information indicates that the program operation data conforming to the second communication protocol is transmitted in real time.

[0173] In some embodiments, the storage control unit is further configured to, when the transmission configuration information indicates that the program running data conforming to the second communication protocol is transmitted through the read-only memory in the storage module, store the program running data conforming to the second communication protocol in the cache in the storage module, transfer the program running data conforming to the second communication protocol in the cache to the random access memory in the storage module, and transfer the program running data conforming to the second communication protocol in the random access memory to the read-only memory.

[0174] In some embodiments, the receiving unit is further configured to receive a clock signal sent by the computer device; the clock signal is a waveform signal with a preset frequency; the storage control unit is further configured to transfer the program running data conforming to the second communication protocol in the cache to the random access memory at the preset frequency according to the waveform signal with the preset frequency and the number of bytes written to the random access memory each time configured in advance; the data storage device 900 further includes a sending module, and the sending module is configured to send the program running data conforming to the second communication protocol in the random access memory to the computer device at the preset frequency according to the waveform signal with the preset frequency and the number of bytes read from the random access memory each time configured in advance.

[0175] In some embodiments, the receiving unit is further configured to receive a clock signal sent by the computer device; the clock signal is a waveform signal with a preset frequency; the storage control unit is further configured to transfer the program running data conforming to the second communication protocol in the random access memory to the read-only memory at the preset frequency according to the waveform signal with the preset frequency and the number of bytes written to the read-only memory each time configured in advance; the data storage device 900 further includes a sending module, and the sending module is configured to send the program running data conforming to the second communication protocol in the read-only memory to the computer device at the preset frequency according to the waveform signal with the preset frequency and the number of bytes read from the read-only memory each time configured in advance.

[0176] In some embodiments, the data storage device 900 further includes a reading module and a sending module; the reading module is configured to, when the program running data conforming to the second communication protocol is configured to be transmitted through the target memory in the storage module, read the program running data conforming to the second communication protocol in the target memory according to each received target data read request during the hardware-in-the-loop test process; the target memory includes a random access memory or a read-only memory; the sending module is configured to send the read program running data conforming to the second communication protocol to the computer device.

[0177] In some embodiments, the reading module includes an address determination unit and a reading unit; the address determination unit is configured to determine a target reading address of the program operation data that conforms to the second communication protocol to be read in the target memory according to the latest operation time in the program operation data acquired by the computer device carried in each received target data reading request; the reading unit is configured to read the program operation data that conforms to the second communication protocol from the target memory according to the target reading address.

[0178] In some embodiments, the data storage device 900 further includes a retransmission module, which is configured to determine that the transmission of the program operation data that conforms to the second communication protocol sent each time is completed when receiving a data reception success instruction sent by the computer device; determine a set reading address of the program operation data at at least one operation time when receiving a retransmission instruction of the program operation data at at least one operation time sent by the computer device; read the program operation data that conforms to the second communication protocol at the at least one operation time from the target memory according to the set reading address, and send the program operation data that conforms to the second communication protocol at the at least one operation time to the computer device.

[0179] In some embodiments, the data storage device 900 further includes a sending module; when the program operation data that conforms to the second communication protocol is configured for real-time transmission, the sending module is configured to send the program operation data of the second communication protocol stored in the cache of the storage module to the computer device in real time.

[0180] In some embodiments, the data storage device 900 further includes a connection state detection module, a reading module, and a sending module; the state detection module is configured to detect the connection state between the debugger and the computer device when the program operation data that conforms to the second communication protocol is configured to be transmitted through a read-only memory; the reading module is configured to read all the program operation data that conforms to the second communication protocol stored in the read-only memory according to the received target data reading request sent by the computer device when the connection state is that the debugger is disconnected from the computer device during the hardware-in-the-loop test and the debugger is successfully connected to the computer device after the hardware-in-the-loop test; the sending module is configured to send all the program operation data that conforms to the second communication protocol to the computer device.

[0181] The description of the above device embodiments is similar to the description of the above method embodiments and has similar beneficial effects to those of the method embodiments. For the technical details not disclosed in the device embodiments of the present application, please refer to the description of the method embodiments of the present application for understanding.

[0182] Each module in the above data storage device can be implemented in whole or in part by a program, hardware, or a combination thereof. Each of the above modules can be embedded in the processor in the debugger in hardware form or independent of the processor, or stored in the memory in the debugger in program form, so that the processor can call and execute the operations corresponding to each of the above modules.

[0183] In an exemplary embodiment, Figure 10 FIG. 5 is a schematic structural diagram of a debugger provided for some embodiments. The debugger includes a data processing chip and a storage module; the data processing chip includes a processor and a memory; the debugger may further include at least one of the following: an input / output interface, a communication interface, an indicator light, and an input device. Among them, the processor, the memory, and the input / output interface are connected through a system bus, and the communication interface, the indicator light, and the input device are connected to the system bus through the input / output interface. Among them, the processor of the debugger is used to provide computing and control capabilities. The memory of the debugger includes a non-volatile storage medium and / or an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the debugger is used to exchange data between the processor and external devices. The communication interface of the debugger is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through Wireless Fidelity (WIFI), a mobile cellular network, Near Field Communication (NFC), or other technologies. The computer program, when executed by the processor, implements a data storage method. The indicator light of the debugger is used to form a visually visible picture, which can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen. The input device of the debugger can be a touch layer covering the display screen, or a button, a trackball, or a touchpad provided on the debugger housing, or an external keyboard, touchpad, or mouse, etc.

[0184] Those skilled in the art can understand that Figure 10 the structure shown in FIG. 5 is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the debugger to which the solution of the present application is applied. The specific debugger may include more or fewer components than those shown in the figure, or combine some components, or have a different component layout.

[0185] For example, the debugger includes a memory and a processor. The memory stores a computer program. When the processor executes the computer program, the steps of the method in any of the above embodiments are implemented.

[0186] In one embodiment, a computer-readable storage medium is provided. When the computer program is executed by a processor, the steps of the method provided in any of the above embodiments are implemented.

[0187] In one embodiment, a computer program product is provided, including a computer program. When the computer program is executed by a processor, the steps of the method provided in any of the above embodiments are implemented.

[0188] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing related hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods.

[0189] The processor, each functional module or each functional unit in any embodiment of the present application may include any one or more of the following integrations: general-purpose processor, application specific integrated circuit (ASIC), digital signal processor (DSP), digital signal processing device (DSPD), programmable logic device (PLD), field programmable gate array (FPGA), central processing unit (CPU), graphics processing unit (GPU), embedded neural network processor (neural-network processing units, NPU), controller, microcontroller, microprocessor, programmable logic device, discrete gate or transistor logic device, discrete hardware component, quantum computing-based data processing logic, artificial intelligence (AI) processor, etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0190] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in the present application.

[0191] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A data storage method, characterized in that, A data processing chip in a debugger for hardware-in-the-loop testing, and a storage module connected to the data processing chip is also configured in the debugger. The method includes: Converting program operation data conforming to a first communication protocol output in real time by a device under test into program operation data conforming to a second communication protocol; the first communication protocol is a protocol for testing the device under test, and the second communication protocol is a protocol adapted to a computer device; the program operation data is operation data fed back by a stub program in a test program in the device under test, and multiple stub programs are pre-set at key program positions in the test program of the device under test through instrumentation; Storing the program operation data conforming to the second communication protocol in the storage module for the computer device to obtain the program operation data conforming to the second communication protocol stored in the storage module.

2. The method according to claim 1, wherein The storage module includes various types of storage units; the storing the program operation data conforming to the second communication protocol in the storage module includes: Receiving transmission configuration information sent by the computer device; the transmission configuration information is used to represent a transmission path of the program operation data conforming to the second communication protocol; Determining a target type of a storage unit for storing the program operation data conforming to the second communication protocol according to the transmission configuration information; Storing the program operation data conforming to the second communication protocol in the storage unit of the target type.

3. The method according to claim 2, characterized in that, The determining a target type of a storage unit for storing the program operation data conforming to the second communication protocol according to the transmission configuration information includes at least one of the following: When the transmission configuration information indicates that the program operation data conforming to the second communication protocol is transmitted through a random access memory, determining that the target type of the storage unit is a random access memory type; When the transmission configuration information indicates that the program operation data conforming to the second communication protocol is transmitted in real time, determining that the target type of the storage unit is a cache type; When the transmission configuration information indicates that the program operation data conforming to the second communication protocol is transmitted through a read-only memory, determining that the target type of the storage unit is a read-only memory type.

4. The method according to claim 2, wherein The storing the program operation data conforming to the second communication protocol in the storage unit of the target type includes at least one of the following: When the transmission configuration information indicates that the program operation data conforming to the second communication protocol is transmitted through the random access memory in the storage module, storing the program operation data conforming to the second communication protocol in a cache in the storage module, and transferring the program operation data conforming to the second communication protocol in the cache to the random access memory; When the transmission configuration information indicates that the program operation data conforming to the second communication protocol is transmitted in real time, storing the program operation data conforming to the second communication protocol in a cache in the storage module; When the transmission configuration information indicates that the program running data conforming to the second communication protocol is transmitted through the read-only memory in the storage module, store the program running data conforming to the second communication protocol in the cache in the storage module, transfer the program running data conforming to the second communication protocol in the cache to the random access memory in the storage module, and transfer the program running data conforming to the second communication protocol in the random access memory to the read-only memory.

5. The method according to claim 4, characterized in that, The transferring the program running data conforming to the second communication protocol in the cache to the random access memory includes: Receiving a clock signal sent by the computer device; the clock signal is a waveform signal with a preset frequency; According to the waveform signal with the preset frequency and the number of bytes written to the random access memory each time configured in advance, transfer the program running data conforming to the second communication protocol in the cache to the random access memory at the preset frequency; The method further includes: According to the waveform signal with the preset frequency and the number of bytes read from the random access memory each time configured in advance, send the program running data conforming to the second communication protocol in the random access memory to the computer device at the preset frequency.

6. The method according to claim 4, wherein The transferring the program running data conforming to the second communication protocol in the random access memory to the read-only memory includes: Receiving a clock signal sent by the computer device; the clock signal is a waveform signal with a preset frequency; According to the waveform signal with the preset frequency and the number of bytes written to the read-only memory each time configured in advance, transfer the program running data conforming to the second communication protocol in the random access memory to the read-only memory at the preset frequency; The method further includes: According to the waveform signal with the preset frequency and the number of bytes read from the read-only memory each time configured in advance, send the program running data conforming to the second communication protocol in the read-only memory to the computer device at the preset frequency.

7. The method according to any one of claims 1 to 6, characterized in that, The method further includes: When the program running data conforming to the second communication protocol is configured to be transmitted through the target memory in the storage module, during the hardware-in-the-loop test, according to each received target data read request, read the program running data conforming to the second communication protocol in the target memory; the target memory includes a random access memory or a read-only memory; Send the read program running data conforming to the second communication protocol to the computer device.

8. The method according to claim 7, characterized in that The reading the program running data conforming to the second communication protocol in the target memory according to each received target data read request includes: Determine the target read address of the program running data conforming to the second communication protocol to be read in the target memory according to the latest running time in the program running data obtained by the computer device carried in each received target data read request; Read the program running data conforming to the second communication protocol from the target memory according to the target reading address.

9. The method according to claim 7, characterized in that The method further includes: When receiving the data reception success instruction sent by the computer device, determine that the program running data conforming to the second communication protocol sent each time is sent completely; When receiving the retransmission instruction of the program running data at at least one running time sent by the computer device, determine the set reading address of the program running data at the at least one running time; According to the set reading address, read the program running data conforming to the second communication protocol at the at least one running time from the target memory, and send the program running data conforming to the second communication protocol at the at least one running time to the computer device.

10. The method according to any one of claims 1 to 6, characterized in that The method further includes: When the program running data conforming to the second communication protocol is configured for real-time transmission, send the program running data of the second communication protocol stored in the cache of the storage module to the computer device in real time.

11. The method according to any one of claims 1 to 6, characterized in that The method further includes: When the program running data conforming to the second communication protocol is configured to be transmitted through a read-only memory, detect the connection state between the debugger and the computer device; When the connection state is that the debugger is disconnected from the computer device during the hardware-in-the-loop test process and the debugger is successfully connected to the computer device after the hardware-in-the-loop test process ends, read all the program running data conforming to the second communication protocol stored in the read-only memory according to the predetermined data reading request received from the computer device; Send all the stored program running data conforming to the second communication protocol to the computer device.

12. A hardware-in-the-loop test system, characterized in that, The hardware-in-the-loop test system includes: a device under test, a computer device, and a debugger; the debugger includes a data processing chip and a storage module; The device under test is used to send the program running data conforming to the first communication protocol to the data processing chip; the first communication protocol is a protocol for testing the device under test; the program running data is the running data fed back by the stub program in the test program of the device under test, and multiple stub programs are pre-set at the key program positions in the test program of the device under test through instrumentation; The data processing chip is used to convert the program running data conforming to the first communication protocol into the program running data conforming to the second communication protocol, and store the program running data conforming to the second communication protocol in a storage device; the second communication protocol is a protocol adapted to the computer device; The data processing chip is further used to read the program running data conforming to the second communication protocol in the storage device, so that the computer device can obtain the program running data conforming to the second communication protocol stored in the storage module.

13. A data storage device, characterized in that, The data storage device includes: A protocol conversion module, configured to convert the program operation data conforming to the first communication protocol output in real time by a device under test into program operation data conforming to the second communication protocol; the first communication protocol is a protocol for testing the device under test, and the second communication protocol is a protocol adapted to a computer device; the program operation data is the operation data fed back by stub programs in a test program in the device under test, and a plurality of stub programs are pre-set at key program positions in the test program of the device under test through instrumentation. A storage control module, configured to store the program operation data conforming to the second communication protocol into a storage module, so that the computer device can obtain the program operation data conforming to the second communication protocol stored in the storage module.

14. A debugger, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, the steps of the method according to any one of claims 1 to 11 are implemented.

15. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 11 are implemented.

16. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 11 are implemented.

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