High-availability low-bandwidth data acquisition system

Abstract

The invention relates to a high-availability low-bandwidth data acquisition system, which comprises a processor, a data bus, a first-path data acquisition channel, a second-path data acquisition channel and a third-path data acquisition channel, and the first-path data acquisition channel, the second-path data acquisition channel and the third-path data acquisition channel are connected in parallel. And the first data acquisition channel, the second data acquisition channel and the third data acquisition channel are connected with the processor through a data bus. Compared with a traditional two-redundancy data acquisition scheme, the high-availability low-bandwidth data acquisition system has the advantages that the data bandwidth is almost not increased, the probability of misoperation is reduced on the basis of ensuring the data acquisition efficiency, and the availability and reliability of acquired data are improved. Compared with a traditional three-redundancy data acquisition scheme, the high-availability low-bandwidth data acquisition system effectively shortens data acquisition time and reduces data bandwidth on the basis of keeping data availability and reliability.

Description

Technical Field

[0001] The present invention relates to a high - availability and low - bandwidth data acquisition system. Background Art

[0002] When instruments, sensors and other products are working, to ensure the safety of the system, reduce misoperation, and avoid system anomalies caused by fault failures, it is necessary to improve the availability and reliability of data acquisition. Generally, it is achieved by doubling functional components, that is, redundant design of the acquisition circuit. Considering cost and system complexity, the redundancy should not be increased too much.

[0003] The first prior - art solution is to design an additional data acquisition channel as a backup, that is, dual - redundancy data acquisition. When one of the data acquisition channels fails, there can still be output of acquired data. However, when the acquisition results of the two data acquisition channels conflict, it is impossible to accurately judge the accuracy of the output data, and it is impossible to effectively avoid misoperation of the acquisition.

[0004] The second prior - art solution is to include three parallel data acquisition channels, that is, triple - redundancy data acquisition. A majority - voting mechanism is set at the end of the data acquisition channels, that is, the principle of the minority obeying the majority. When the output signal of one of the data acquisition channels is different from that of the other two data acquisition channels, the output signal of the other data acquisition channel is selected as the final output. This data acquisition method allows one data acquisition channel to fail without affecting data output. However, data processing, bus transmission, and output judgment will consume more processor resources, and the data acquisition time is longer each time, and the data bandwidth is higher.

[0005] Both of the above - mentioned two technical solutions have certain defects. The data availability and reliability of the dual - redundancy data acquisition solution are insufficient; the data acquisition efficiency of the triple - redundancy data acquisition solution is low. Summary of the Invention

[0006] In view of the above problems existing in the prior art, the main object of the present invention is to provide a high - availability and low - bandwidth data acquisition system.

[0007] The technical solution of the present invention is as follows:

[0008] A high - availability and low - bandwidth data acquisition system includes a processor MCU, a data bus, a first data acquisition channel, a second data acquisition channel, and a third data acquisition channel, wherein:

[0009] The first data acquisition channel, the second data acquisition channel, and the third data acquisition channel are connected in parallel.

[0010] The first data acquisition channel, the second data acquisition channel, and the third data acquisition channel are connected to the processor MCU through the data bus.

[0011] During each data acquisition, only the first data acquisition channel and the second data acquisition channel are activated. Among them: the first data acquisition channel transmits the first acquired data collected to the processor MCU through the data bus; the second data acquisition channel transmits the second acquired data collected to the processor MCU through the data bus.

[0012] The processor MCU receives the first acquired data sent by the first data acquisition channel and the second acquired data sent by the second data acquisition channel, and then judges the first acquired data and the second acquired data.

[0013] When the processor MCU judges that the first acquired data and the second acquired data are consistent, the first acquired data and the second acquired data are output as the final data acquisition result.

[0014] When the processor MCU judges that the first acquired data and the second acquired data are inconsistent, the third data acquisition channel is activated for data acquisition.

[0015] The third data acquisition channel transmits the third acquired data collected to the processor MCU through the data bus.

[0016] The processor MCU receives the third acquired data sent by the third data acquisition channel, and then outputs the third acquired data as the final data acquisition result, and the data acquisition ends.

[0017] The present invention has the following advantages and beneficial effects: The present invention proposes a high-availability and low-bandwidth data acquisition system, and designs three redundant data acquisition channels. During each data acquisition, only the first two data acquisition channels are activated. When the data is the same, the acquired data is directly output; when the data is different, the third data acquisition channel is activated, and the result of the third data acquisition channel is output as the acquired data. Compared with the traditional dual-redundancy data acquisition, on the basis of ensuring the data acquisition efficiency, the availability and reliability of the data are further improved. Compared with the traditional triple-redundancy data acquisition, on the basis of ensuring the data availability and reliability, the data acquisition time is effectively shortened, and the data bandwidth is reduced. Brief Description of the Drawings

[0018] Figure 1 It is a principle block diagram of the high-availability and low-bandwidth data acquisition system provided by the embodiment of the present invention.

[0019] Figure 2 It is a flow chart of the high-availability and low-bandwidth data acquisition system provided by the embodiment of the present invention. Detailed Embodiments

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. The components of the embodiments of the present invention usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0021] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0022] In the description of the present invention, it should also be noted that unless otherwise clearly specified and defined, the terms "set", "install", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0023] The following will further illustrate the present invention with reference to the accompanying drawings and specific embodiments.

[0024] As Figures 1 to 2 shown: The high-availability and low-bandwidth data acquisition system of the embodiments of the present invention includes a processor MCU, a data bus, a first data acquisition channel, a second data acquisition channel, and a third data acquisition channel, where:

[0025] The first data acquisition channel, the second data acquisition channel, and the third data acquisition channel are connected in parallel.

[0026] The first data acquisition channel, the second data acquisition channel, and the third data acquisition channel are connected to the processor MCU through the data bus.

[0027] Each time data is collected, only the first data collection channel and the second data collection channel are activated. Among them: the first data collection channel transmits the collected first-channel collected data to the processor MCU through the data bus; the second data collection channel transmits the collected second-channel collected data to the processor MCU through the data bus.

[0028] The processor MCU receives the first-channel collected data sent by the first data collection channel and the second-channel collected data sent by the second data collection channel, and then judges the first-channel collected data and the second-channel collected data.

[0029] When the processor MCU judges that the first-channel collected data and the second-channel collected data are consistent, the first-channel collected data and the second-channel collected data are output as the final data collection result.

[0030] When the processor MCU judges that the first-channel collected data and the second-channel collected data are inconsistent, the third data collection channel is activated to collect data.

[0031] The third data collection channel transmits the collected third-channel collected data to the processor MCU through the data bus.

[0032] The processor MCU receives the third-channel collected data sent by the third data collection channel, and then outputs the third-channel collected data as the final data collection result, and the data collection ends.

[0033] A highly available and low-bandwidth data collection system proposed in an embodiment of the present invention designs three redundant data collection channels. Each time data is collected, only the first two data collection channels are activated. When the data is the same, the collected data is directly output; when the data is different, the third data collection channel is activated, and the result of the third data collection channel is output as the collected data.

[0034] The highly available and low-bandwidth data collection system includes a processor MCU, a data bus, a first data collection channel, a second data collection channel, and a third data collection channel. The first data collection channel, the second data collection channel, and the third data collection channel are in parallel and are connected to the processor MCU through the data bus.

[0035] The first data acquisition channel, the second data acquisition channel, and the third data acquisition channel collect the same data and transmit it to the processor MCU through the data bus. The first data acquisition channel and the second data acquisition channel perform real-time data acquisition simultaneously; the third data acquisition channel is periodically started at a set time interval and only judges whether the working state is normal, without using the acquisition data of the third data acquisition channel.

[0036] In a high-availability and low-bandwidth data acquisition system proposed by an embodiment of the present invention, the processor MCU judges the data acquisition results of the first data acquisition channel and the second data acquisition channel. When the acquisition results are the same, the acquisition data is directly output as the final data acquisition result.

[0037] In a high-availability and low-bandwidth data acquisition system proposed by an embodiment of the present invention, the processor MCU judges the data acquisition results of the first data acquisition channel and the second data acquisition channel. When the acquisition results are different, the third data acquisition channel is started, and the data acquisition result of the third data acquisition channel is output as the final data acquisition result.

[0038] In a high-availability and low-bandwidth data acquisition system proposed by an embodiment of the present invention, the third data acquisition channel is periodically started for function self-detection to ensure the normal function of the third data acquisition channel, and conflict decision-making can be performed in the abnormal situation of data acquisition conflict between the first data acquisition channel and the second data acquisition channel.

[0039] In a high-availability and low-bandwidth data acquisition system proposed by an embodiment of the present invention, when important data is collected, the acquisition circuit is usually redundantly designed to improve the availability and reliability of data acquisition.

[0040] When two redundant data acquisition channels are used for data acquisition, data can still be output after one of the data acquisition channels fails. However, when the acquisition results of the two data acquisition channels conflict, it is impossible to accurately judge the accuracy of the output data, and it is impossible to effectively avoid the misoperation of the acquisition.

[0041] When three redundant data acquisition channels are used for data acquisition, three-way data is collected each time for majority voting, that is, the principle of the minority obeying the majority. The failure of one data acquisition channel does not affect the data output. However, data acquisition, bus transmission, and output judgment will consume more processor resources, and the data acquisition time is longer each time.

[0042] A high-availability and low-bandwidth data acquisition system provided by an embodiment of the present invention designs three redundant data acquisition channels. Only the first two data acquisition channels are started each time data is acquired. When the data is the same, the acquired data is directly output; when the data is different, the third data acquisition channel is started, and the result of the third data acquisition channel is used as the acquired data output. Compared with the traditional dual-redundancy data acquisition, while ensuring the data acquisition efficiency, the availability and reliability of the data are further improved. Compared with the traditional triple-redundancy data acquisition, while ensuring the data availability and reliability, the data acquisition time is effectively shortened and the data bandwidth is reduced.

[0043] A high-availability and low-bandwidth data acquisition system proposed by an embodiment of the present invention improves the availability and reliability of data acquisition and reduces misoperation by adding functional components and adopting redundant circuits.

[0044] In the existing technical solutions, for the dual-redundancy data acquisition solution, in the face of conflicts in the acquisition results, it is impossible to accurately judge the accuracy of the output data, the data availability and reliability are insufficient, and it is impossible to effectively avoid misoperation in the acquisition; for the triple-redundancy data acquisition solution, data processing, bus transmission, and output judgment will occupy more processor resources, the time for each data acquisition is relatively long, and the data acquisition efficiency is low.

[0045] A high-availability and low-bandwidth data acquisition system proposed by an embodiment of the present invention only starts the first data acquisition channel and the second data acquisition channel each time data is acquired. When the data is the same, the acquired data is directly output; in the face of the abnormal situation of data conflict in the first data acquisition channel and the second data acquisition channel, conflict decision-making is carried out by starting the third data acquisition channel, and the result of the third data acquisition channel is used as the acquired data output.

[0046] A high-availability and low-bandwidth data acquisition system proposed by an embodiment of the present invention hardly increases the data bandwidth compared with the traditional dual-redundancy data acquisition solution. While ensuring the data acquisition efficiency, the probability of misoperation is reduced, and the availability and reliability of the acquired data are improved.

[0047] A high-availability and low-bandwidth data acquisition system proposed by an embodiment of the present invention effectively shortens the data acquisition time and reduces the data bandwidth while maintaining the data availability and reliability compared with the traditional triple-redundancy data acquisition solution.

[0048] Finally, it should be noted that the above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-availability and low-bandwidth data acquisition system, characterized in that: It includes a processor MCU, a data bus, a first data acquisition channel, a second data acquisition channel, and a third data acquisition channel, where: The first data acquisition channel, the second data acquisition channel, and the third data acquisition channel are connected in parallel. The first data acquisition channel, the second data acquisition channel, and the third data acquisition channel are connected to the processor MCU through the data bus.

2. The high-availability low-bandwidth data acquisition system according to claim 1, wherein Each time data is acquired, only the first data acquisition channel and the second data acquisition channel are started, where: The first data acquisition channel transmits the first acquired data collected to the processor MCU through the data bus; The second data acquisition channel transmits the second acquired data collected to the processor MCU through the data bus.

3. The high-availability low-bandwidth data acquisition system according to claim 2, characterized in that, The processor MCU receives the first acquired data sent by the first data acquisition channel and the second acquired data sent by the second data acquisition channel, and then judges the first acquired data and the second acquired data.

4. The high-availability low-bandwidth data acquisition system according to claim 3, wherein When the processor MCU judges that the first acquired data and the second acquired data are consistent, the first acquired data and the second acquired data are output as the final data acquisition result.

5. The high-availability low-bandwidth data acquisition system according to claim 3, wherein When the processor MCU judges that the first acquired data and the second acquired data are inconsistent, the third data acquisition channel is started for data acquisition.

6. The high-availability low-bandwidth data acquisition system according to claim 5, wherein The third data acquisition channel transmits the third acquired data collected to the processor MCU through the data bus.

7. The high-availability low-bandwidth data acquisition system according to claim 6, wherein The processor MCU receives the third acquired data sent by the third data acquisition channel, and then outputs the third acquired data as the final data acquisition result, and the data acquisition ends.

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