Memory error simulation method and device based on satellite-borne intelligent computing system, medium and simulator

Abstract

The invention provides a memory error simulation method and device based on a satellite-borne intelligent computing system, a medium and a simulator, and relates to the technical field of satellites. The method comprises the following steps: inputting a deep learning neural network engine into a deep learning reasoning program of a satellite-borne intelligent computing system; executing a deep learning reasoning program to read a process page table; based on the DRAM standard file, the DRAM mapping file and the address mapping relation, determining a memory active area of the deep learning neural network engine in the virtual memory model; performing construction processing on the memory active area, constructing an error injection space represented in a bitmap tree form, and determining an error information injection position in the error injection space according to particle flipping error model information and a Monte Carlo random algorithm; and performing reverse translation processing on the physical address in the virtual memory model, and determining a target virtual address of the deep learning reasoning process. And a single-particle upset memory error and a multi-particle upset memory error caused by space radiation can be effectively simulated.

Description

Technical Field

[0001] The present invention relates to the field of satellite technology, and in particular, to a method, device, medium and simulator for simulating memory errors based on an on-board intelligent computing system. Background Art

[0002] With the development of space technology, on-orbit intelligent computing has become a new type of "edge computing" paradigm, directly performing data processing on satellites, effectively reducing the downlink bandwidth requirements, and can support latency-sensitive on-orbit tasks such as wildfire monitoring. In order to run complex intelligent computing tasks such as Deep Neural Network (DNN), deploying computing devices such as Commercial Off-the-Shelf (COTS) General-Purpose computing on Graphics Processing Units (GPGPU) into space has become a very promising development trend. In contrast, traditional radiation-hardened chips are costly, and their computing power is insufficient to support the inference of common DNN models. However, different from the ground edge computing scenario, unirradiated COTS GPUs are extremely vulnerable to radiation-induced errors in the space environment.

[0003] Satellites in space are surrounded by radiation particles, which mainly consist of trapped protons, secondary neutrons generated by nuclear interactions, and high-energy cosmic rays. Radiation can affect on-orbit electronic components, especially those low-cost COTS devices without radiation hardening, thus causing permanent damage (such as performance degradation and burning) or transient damage (such as logic state flipping) to the unprotected Dynamic Random Access Memory (DRAM) therein. Among them, transient damage is widespread and threatening because it can secretly inject flipped logic states into the computing process, resulting in incorrect control flow and data flow, thus affecting the computing results and being difficult to be detected in time.

[0004] In related technologies, the 10-year on-orbit experiment records of the European Space Agency (ESA) and multiple ground irradiation tests have all shown that space radiation particles will frequently cause transient damage such as bit flips in the DARM of COTS devices, mainly including two types: Single Event Upset (SEU) and Multiple Cell Upset (MCU), which are respectively manifested as single spatio-temporally independent bit flips and multiple spatially related bits flipping simultaneously, and their occurrence probabilities cannot be ignored (about ~ per bit per day, and the occurrence probability is proportional to the memory space and the running time).

[0005] Single event upset is caused by the impact of ionizing radiation, which generates and diffuses electron-hole pairs in the gate of the storage cell transistor, resulting in a change in the storage state, that is, a single-bit error. Multiple event upset is due to the reaction of neutron particles with impurities and the generation of a large number of secondary particles with sufficient energy, causing multiple storage cells to flip simultaneously. These storage cells have spatial correlations, such as row adjacent, column adjacent, and DQ (data I / O pins for parallel data transmission) adjacent.

[0006] In space, due to advanced nanotechnology and more compact chip sizes, MCUs occur more and more frequently in COTS. DNN inference during runtime is particularly sensitive to bit-flip errors. Just one bit error can cause serious errors, and its memory-intensive forward inference calculation process will cause the calculation error to increase layer by layer, resulting in serious decision-making errors. This may endanger the safety and accuracy of on-orbit critical applications such as disaster monitoring and ship detection.

[0007] Therefore, it is urgent to systematically evaluate the reliability of DNN inference before on-orbit operation.

[0008] However, in related technologies, it is difficult for the existing technology to simultaneously meet the accuracy, efficiency, and scalability of memory bit-flip error injection caused by space radiation, nor can it complete the systematic evaluation of the reliability of DNN inference before on-orbit operation. Summary of the Invention

[0009] The present invention provides a memory error simulation method, device, medium, and simulator based on an on-board intelligent computing system, which can effectively simulate space-time independent single event upset memory errors and space-related multiple event upset memory errors caused by space radiation to evaluate the impact of the space radiation memory errors on the on-board intelligent computing system during the deep learning inference process, and can also evaluate the impact of memory bit-flip errors caused by space radiation on the operation of the on-board intelligent computing system, realizing high processing efficiency and strong scalability on the basis of accurate simulation.

[0010] In a first aspect, the present invention provides a memory error simulation method based on an on-board intelligent computing system, including: Inputting an optimized deep learning neural network engine into the on-board intelligent computing system; wherein, the on-board intelligent computing system at least includes a deep learning inference program; Execute the deep learning inference program to create a deep learning inference process, load the deep learning neural network engine into the target DRAM memory device, and use the kernel interface of the operating system to read the process page table, where the process page table represents the address mapping relationship between the initial virtual address in the deep learning inference process and the physical address in the target DRAM memory device; Based on the configurable DRAM standard file, DRAM mapping file, and the address mapping relationship, determine the memory active area of the deep learning neural network engine in the virtual memory model; wherein, the virtual memory model is a model that simulates the target DRAM memory device; Perform a construction process on the memory active area to construct an error injection space represented in the form of a bitmap tree, and determine the error information injection position in the error injection space according to the particle flip error model information recorded in the real radiation test and the Monte Carlo random algorithm; wherein, the particle flip error model information at least includes single particle flip error information and multi-particle flip error information; the error information injection position is the position where the single particle flip error information and the multi-particle flip error information are randomly injected into the error injection space represented in the form of a bitmap tree; Based on the address mapping relationship and the error information injection position, perform reverse translation processing on the physical address in the virtual memory model to determine the target virtual address of the deep learning inference process.

[0011] Preferably, according to the memory error simulation method based on the on-board intelligent computing system provided by the present invention, after the step of performing reverse translation processing on the physical address in the virtual memory model based on the address mapping relationship and the error information injection position to determine the target virtual address of the deep learning inference process, the method includes: Perform bit flipping of random bits on the single-byte data of the target virtual address through an exclusive OR operation to obtain the bit flipping result of the target virtual address; Based on the bit flipping result of the target virtual address, use the deep learning inference program to execute an inference task to obtain an inference result corresponding to the on-board intelligent computing system.

[0012] Preferably, according to the memory error simulation method based on the on-board intelligent computing system provided by the present invention, the step of constructing the virtual memory model includes: Use a memory simulator to read the standard parameters in the DRAM standard file; Determine the connection relationship and address mapping rules of each component of the deep learning neural network engine in the target DRAM memory device according to the standard parameters in the DRAM standard file, the mapping information of the DRAM mapping file, and the memory device information of the target DRAM memory device; wherein, the address mapping rule represents the rule for mapping the addresses of each component in the target DRAM memory device to the virtual memory model; each component at least includes: a row part, a column part, a bank part, and a channel part. Construct a virtual memory model for simulating the target DRAM memory device according to the connection relationship and the address mapping rule of each component of the deep learning neural network engine in the target DRAM memory device.

[0013] Preferably, according to the memory error simulation method based on the spaceborne intelligent computing system provided by the present invention, determining the memory active area of the deep learning neural network engine in the virtual memory model according to the configurable DRAM standard file, the DRAM mapping file, and the address mapping relationship includes: The step of initializing an instance of the virtual memory model by using the memory simulator, and determining the memory active area of the deep learning neural network engine in the virtual memory model based on the connection relationship, the address mapping rule, and the address mapping relationship; wherein, the memory active area represents the effective error injection range at the DRAM level composed of row information, column information, bank information, and channel information.

[0014] Preferably, according to the memory error simulation method based on the spaceborne intelligent computing system provided by the present invention, the error injection space represented in the form of a bitmap tree is established by traversing all physical blocks in the memory active area and performing DRAM addressing addresses corresponding to all physical blocks. Each layer in the tree structure of the bitmap tree represents a DRAM level, each DRAM level includes multiple nodes, and each node includes at least one bitmap for indexing the next level.

[0015] Preferably, according to the memory error simulation method based on the spaceborne intelligent computing system provided by the present invention, the steps of determining effective error search in the error injection space represented in the form of a bitmap tree include: Randomly select a parent node from the parent nodes of the bitmap tree as a high-level node, and select a low-level node from the leaf nodes corresponding to the high-level node based on the error type corresponding to the particle flip error model information to determine the effective error information injection position; and By calculating the subtree memory size of each high-level node, starting from the root node, the number of errors corresponding to the particle flip error model information is allocated layer by layer to determine the effective error information injection location.

[0016] In a second aspect, the present invention further provides a memory error simulation device based on a spaceborne intelligent computing system, including: An input module, configured to input an optimized deep learning neural network engine into the spaceborne intelligent computing system; wherein, the spaceborne intelligent computing system at least includes a deep learning inference program. An address mapping relationship determination module, configured to execute the deep learning inference program to create a deep learning inference process and to load the deep learning neural network engine into a target DRAM memory device, and use the kernel interface of the operating system to read the process page table, where the process page table represents the address mapping relationship between the initial virtual address in the deep learning inference process and the physical address in the target DRAM memory device. A memory active area determination module, configured to determine the memory active area of the deep learning neural network engine in the virtual memory model based on a configurable DRAM standard file, a DRAM mapping file, and the address mapping relationship; wherein, the virtual memory model is a model that simulates the target DRAM memory device. An error information injection location determination module, configured to perform a construction process on the memory active area to construct an error injection space represented in the form of a bitmap tree, and determine an error information injection location in the error injection space according to the particle flip error model information recorded in the real radiation test and the Monte Carlo random algorithm; wherein, the particle flip error model information at least includes single particle flip error information and multi-particle flip error information; the error information injection location is the location where the single particle flip error information and the multi-particle flip error information are randomly injected into the error injection space represented in the form of a bitmap tree. A target virtual address determination module, configured to perform reverse translation processing on the physical address in the virtual memory model based on the address mapping relationship and the error information injection location to determine the target virtual address of the deep learning inference process.

[0017] In a third aspect, the present invention further provides a simulator, including a memory, a processor, and a computer program stored on the memory and executable on the processor, where when the processor executes the program, it implements the memory error simulation method based on a spaceborne intelligent computing system as described in any one of the above.

[0018] In a fourth aspect, the present invention further provides a non-transitory computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the memory error simulation method based on a spaceborne intelligent computing system as described in any one of the above.

[0019] In a fifth aspect, the present invention also provides a computer program product, including a computer program which, when executed by a processor, implements the memory error simulation method based on the on-board intelligent computing system as described in any one of the above.

[0020] A memory error simulation method, device, medium and simulator based on the on-board intelligent computing system provided by the present invention input an optimized deep learning neural network engine into the on-board intelligent computing system; wherein, the on-board intelligent computing system at least includes a deep learning inference program; execute the deep learning inference program to create a deep learning inference process and to load the deep learning neural network engine into the target DRAM memory device, and use the kernel interface of the operating system to read the process page table, and the process page table represents the address mapping relationship between the initial virtual address in the deep learning inference process and the physical address in the target DRAM memory device; based on the configurable DRAM standard file, DRAM mapping file and the address mapping relationship, determine the memory active area of the deep learning neural network engine in the virtual memory model; wherein, the virtual memory model is a model simulating the target DRAM memory device; perform construction processing on the memory active area, construct a mis-injection space represented in the form of a bitmap tree, and determine the error information injection position in the mis-injection space according to the particle flip error model information recorded in the real radiation test and the Monte Carlo random algorithm; wherein, the particle flip error model information at least includes single particle flip error information and multi-particle flip error information; the error information injection position is the position where the single particle flip error information and the multi-particle flip error information are randomly injected into the mis-injection space represented in the form of a bitmap tree; perform reverse translation processing on the physical address in the virtual memory model based on the address mapping relationship and the error information injection position to determine the target virtual address of the deep learning inference process. It can effectively simulate the space-time independent single particle flip memory error and the space-related multi-particle flip memory error caused by space radiation, so as to evaluate the impact of the space radiation memory error on the on-board intelligent computing system during the deep learning inference process, and can also evaluate the impact of the memory bit flip error caused by space radiation on the operation of the on-board intelligent computing system, and achieve high processing efficiency and strong scalability on the basis of accurate simulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0022] Figure 1 It is one of the flow schematic diagrams of a memory error simulation method based on a spaceborne intelligent computing system provided by the present invention.

[0023] Figure 2 It is the second of the flow schematic diagrams of the memory error simulation method based on the spaceborne intelligent computing system provided by the present invention.

[0024] Figure 3 It is a schematic diagram of the data structure of the bitmap tree provided by the present invention.

[0025] Figure 4 It is a schematic diagram of the structure of a memory error simulation device based on a spaceborne intelligent computing system provided by the present invention.

[0026] Figure 5 It is a schematic diagram of the structure of an electronic device provided by the present invention. Detailed implementation manners

[0027] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative efforts shall fall within the protection scope of the present invention.

[0028] First, several terms involved in the present invention are analyzed: Single Event Upset (SEU): A single bit flip that is independent in space and time, caused by an ionizing radiation strike, which generates and diffuses electron-hole pairs in the gate of the storage cell transistor, resulting in a change in the storage state, i.e., a single-bit error.

[0029] Multiple Cell Upset (MCU): Multiple bits related in space are flipped simultaneously. It is due to the reaction of neutron particles with impurities and the generation of a large number of secondary particles with sufficient energy, resulting in the simultaneous flipping of multiple storage cells, and these storage cells are spatially correlated, such as row adjacent, column adjacent, and DQ (data I / O pins for parallel data transmission) adjacent.

[0030] Dynamic random-access memory (DRAM): It is a common semiconductor storage device. The storage unit of DRAM consists of a transistor and a capacitor. The capacitor is used to store information. Its charged state represents that the data bit is 1, and its discharged state represents that the data bit is 0. Read and write principle: When writing, the row where the storage unit is located is selected through the word line, and data is written into the capacitor of the selected unit through the bit line. When reading, first select the row through the word line, then read the data through the bit line, and output it after amplification processing.

[0031] In the related art, there are at least the following technical problems: In order to simulate single / multi-bit particle flip errors caused by space radiation, the existing related technologies at home and abroad are mainly divided into two categories: error verification technology based on the real irradiation environment and error injection technology based on software simulation.

[0032] The first type of technology induces the state flip of the storage unit of the DRAM memory chip under controllable conditions through an artificial radiation source to obtain the real error situation of the memory storage unit. It is an important method to explore the physical characteristics of bit flips, especially to accurately analyze the spatial correlation characteristics of the MCU. To ensure the repeatability of the experimental results, modern irradiation experiments generally follow the JEDEC JESD89A standard specification. This standard clearly defines the multi-bit particle flip of the memory unit as the multi-bit flip adjacent in the physical space under the influence of a single particle, and standardizes the experimental process, data collection and analysis methods. Although the ground irradiation experiment provides a reliable method for studying device radiation errors, its deficiencies are reflected in: the high cost and long cycle of a single experiment, and the collection of complete verification and model calibration data may require months of continuous testing. Due to the time-consuming, costly and huge overhead of this type of method, and there is still a lack of direct correlation between the underlying memory hardware errors and the upper-layer DNN inference behavior, more efficient error injection technologies based on software simulation have gradually attracted attention at home and abroad.

[0033] The second type of technology is mainly divided into system simulation based on underlying hardware and model fault injection based on deep learning frameworks. System simulation can inject errors at the gate-level circuit, assembly code, or microarchitecture layer, mainly targeting registers and computing pipelines while ignoring DRAM memory chips. Although such methods are close to the hardware layer and generally applicable to most applications, their deficiencies are as follows: Due to the need for complex hardware simulation and instruction instrumentation processes, and the fact that errors may be masked by multi-layer software and hardware structures and unable to reach the DNN program, it is difficult to effectively evaluate the vulnerability of DNN inference. Therefore, to achieve more specialized goals, many error injection tools for specific deep learning frameworks have been proposed, such as TensoFI, PyTorchFI, and Ares, etc. These methods directly inject random bit-flip errors into the weights and feature maps of deep neural network models and are applicable to different deep learning frameworks, such as TensorFlow and PyTorch, etc. Although these methods are highly efficient due to targeted injection in small-scale numerical values, their deficiencies are as follows: Offline model-level error injection lacks key insights into the runtime process space, such as optimized data flow and actual memory allocation. Therefore, it is not only difficult to scale to other applications but may also overlook some sensitive points in deep neural network inference. In addition, the deficiencies of these existing technologies are also reflected in: Ignoring the accurate modeling of multi-particle flips with spatial position correlation in DRAM, resulting in insufficient accuracy of space radiation memory error injection.

[0034] To more accurately, efficiently, and scalably inject single / multi-particle flip errors caused by space radiation into the DNN inference process space, it is urgent to solve the propagation of hardware errors, especially multi-bit flip errors with spatial position correlation, from the underlying memory cells to the upper-layer DNN inference program process space. Therefore, accurate memory system modeling, efficient runtime error mapping, and adaptation to different memory devices are crucial.

[0035] The following combines Figures 1 - 5 Describes a memory error simulation method, device, medium, and simulator based on an on-board intelligent computing system of the present invention, which can effectively simulate space-time independent single-particle flip memory errors and space-related multi-particle flip memory errors caused by space radiation to evaluate the impact of such space radiation memory errors on the on-board intelligent computing system during the deep learning inference process, and can also evaluate the impact of memory bit flip errors caused by space radiation on the operation of the on-board intelligent computing system, achieving high processing efficiency and strong scalability on the basis of accurate simulation.

[0036] Figure 1 Is one of the schematic flowcharts of a memory error simulation method based on an on-board intelligent computing system provided by the present invention, as Figure 1As shown, the method may include but is not limited to steps S100 to S500: S100, input the optimized deep learning neural network engine into the on-board intelligent computing system; wherein, the on-board intelligent computing system at least includes a deep learning inference program; S200, execute the deep learning inference program to create a deep learning inference process and to load the deep learning neural network engine into the target DRAM memory device, and use the kernel interface of the operating system to read the process page table, where the process page table represents the address mapping relationship between the initial virtual address in the deep learning inference process and the physical address in the target DRAM memory device; S300, based on the configurable DRAM standard file, DRAM mapping file, and the address mapping relationship, determine the memory active area of the deep learning neural network engine in the virtual memory model; wherein, the virtual memory model is a model that simulates the target DRAM memory device; S400, perform a construction process on the memory active area to construct a misannotation space represented in the form of a bitmap tree, and determine the error information injection position in the misannotation space according to the particle flip error model information recorded in the real radiation test and the Monte Carlo random algorithm; wherein, the particle flip error model information at least includes single event upset error information and multiple event upset error information; the error information injection position is the position where the single event upset error information and the multiple event upset error information are randomly injected into the misannotation space represented in the form of a bitmap tree; S500, perform reverse translation processing on the physical address in the virtual memory model based on the address mapping relationship and the error information injection position to determine the target virtual address of the deep learning inference process.

[0037] It should be noted that for the convenience of description, in the following embodiments, some special technical terms can be represented by abbreviations.

[0038] REMU is the abbreviation of Memory-Aware Efficient Radiation Error Simulator, which is used to characterize the impact of memory bit flip errors caused by radiation on the operation of the on-board intelligent computing system (DNN inference program), and takes into account efficiency and scalability on the basis of accurate simulation.

[0039] SEU is the abbreviation of single event upset, MCU is the abbreviation of multiple event upset, DNN is the abbreviation of deep learning neural network, DRAM is the abbreviation of dynamic random access memory, DNN engine (DNN key data) is the deep learning neural network engine, and DNN inference process is the deep learning inference process.

[0040] In step S100 of some embodiments, the optimized deep learning neural network engine is input into the on-board intelligent computing system; wherein, the on-board intelligent computing system at least includes a deep learning inference program.

[0041] It should be noted that the on-board intelligent computing system contains a deep learning inference program, which means that the intelligent computing system has the ability to perform inference calculations using deep learning algorithms. It can analyze and process the input data, such as the data provided by the optimized deep learning neural network engine, and then obtain the corresponding inference results to complete specific tasks or functions.

[0042] In step S200 of some embodiments, the deep learning inference program is executed to create a deep learning inference process and to load the deep learning neural network engine into the target DRAM memory device, and the process page table is read using the kernel interface of the operating system. The process page table represents the address mapping relationship between the initial virtual address in the deep learning inference process and the physical address in the target DRAM memory device.

[0043] It can be understood that the deep learning inference program is executed to create a deep learning inference process and to load the deep learning neural network engine (i.e., the DNN key data) into the target DRAM memory device.

[0044] Subsequently, the process page table is read through the kernel interface of the operating system. The process page table can represent the address mapping relationship existing between the initial virtual address in the deep learning inference process and the physical address in the target DRAM memory device.

[0045] In some embodiments, that is, the on-board intelligent computing system takes the DNN key data as input and starts the execution of the DNN inference program. At this time, the DNN inference process is created, and the DNN key data (deep learning neural network engine file) is loaded into the target DRAM memory device. REMU reads the size and address of the DNN key data in the runtime environment process space and uses the kernel interface of the operating system to read the process page table to complete the preliminary mapping between the virtual address and the physical address.

[0046] The target DRAM memory device is the actual memory device for loading the DNN key data, which can be determined according to actual needs.

[0047] The runtime environment represents the operating state of the deep learning inference program, as well as the runtime environment in which the DNN inference process is created and the DNN key data (deep learning neural network engine file) is loaded into the target DRAM memory device.

[0048] In step S300 of some embodiments, based on the configurable DRAM standard file, the DRAM mapping file, and the address mapping relationship, determine the memory active region of the deep learning neural network engine in the virtual memory model; wherein, the virtual memory model is a model that simulates the target DRAM memory device.

[0049] It should be noted that for the DRAM standard file configuration: REMU will understand the characteristics and parameters of different types of DRAMs according to the configurable DRAM standard file. These files contain key information such as the number of rows, columns, number of banks, number of channels of the memory, as well as various operation timings and constraint conditions. By parsing these files, REMU can clarify the standard architecture and behavior specifications of the target DRAM memory.

[0050] For the DRAM mapping file configuration: The DRAM mapping file further defines the specific layout rules of the DNN key data in the DRAM memory. For example, it specifies which data is stored in which rows, columns, banks, and channels, as well as the access order and association relationship of the data. Based on these mapping files, REMU corresponds the abstract data to the actual physical locations of the DRAM, thus establishing a mapping relationship from the data to the memory regions.

[0051] In some embodiments, the steps of constructing the virtual memory model include: Use a memory simulator to read the standard parameters in the DRAM standard file; According to the standard parameters in the DRAM standard file, the mapping information in the DRAM mapping file, and the memory device information of the target DRAM memory device, determine the connection relationship and address mapping rules of each component of the deep learning neural network engine in the target DRAM memory device.

[0052] According to the connection relationship and the address mapping rules of each component of the deep learning neural network engine in the target DRAM memory device, construct a virtual memory model that simulates the target DRAM memory device.

[0053] Wherein, the address mapping rule represents the rule for mapping the addresses of each component in the target DRAM memory device to the virtual memory model; each component at least includes: row part, column part, bank part, channel part.

[0054] It should be noted that a memory simulator is a tool or software used to simulate the behavior and characteristics of a computer memory subsystem. The virtual memory model is a model file that configures the memory simulator based on the target DRAM memory device.

[0055] Memory simulators can be used for error diagnosis and debugging: simulating memory errors and abnormal situations to help developers diagnose and solve memory-related problems such as memory leaks, data corruption, compatibility issues, etc., and improve the stability and reliability of the system.

[0056] Memory simulators can include but are not limited to: DRAMsim3: A powerful, multi-protocol dynamic random access memory (DRAM) simulation tool that covers various memory protocols such as DDR3, DDR4, LPDDR3, LPDDR4, GDDR5, GDDR6, HBM, and STT-MRAM.

[0057] Ramulator 2.0: A newly upgraded dynamic random access memory (DRAM) simulation tool that supports the latest DRAM standards such as DDR5, LPDDR5, HBM3, and GDDR6, and has compatibility with a wide range of commercial and technical academic standards. It adopts three modes: memory trace-driven, CPU trace-driven, and gem5-driven to meet the simulation needs from single memory operations to the full system level. It can also be integrated with VAMPIRE or DRAMPower to provide detailed power consumption information.

[0058] In some embodiments, initialize the memory model: Using the memory simulator, according to the information in the above DRAM standard file and the mapping information in the DRAM mapping file, REMU initializes an instance of the virtual memory model. In this process, a model highly similar to the real target DRAM memory device will be constructed in the virtual environment of the computer, that is, the virtual memory model, including its physical structure and logical organization. This virtual memory model will be set according to the parameters defined in the DRAM standard file, such as the number of memory cells, the capacity of each bank, etc.

[0059] When DNN critical data (deep learning neural network engine) needs to be loaded into the virtual memory model, REMU will calculate the memory address where each data should be stored through a specific algorithm according to the layout rules in the DRAM mapping file. This address calculation process involves multi-dimensional considerations of rows, columns, banks, and channels to ensure that the data can be accurately placed in the corresponding memory locations. For example, for a given data block, REMU will determine its row number, column number, bank number, and channel number according to its semantics in the DNN critical data (deep learning neural network engine) and the definition in the mapping file, and then calculate the specific physical address.

[0060] In some embodiments of the present invention, the step of initializing an instance of the virtual memory model using the memory simulator, and determining the memory active region of the deep learning neural network engine in the virtual memory model based on the connection relationship, the address mapping rule, and the address mapping relationship; wherein, the memory active region represents the effective error injection range at the DRAM level composed of row information, column information, bank information, and channel information, specifically: Based on the connection relationship (i.e., the physical or logical connection method between different components), the address mapping rule (how to convert a virtual address to a physical address), and the address mapping relationship (which virtual addresses correspond to which physical addresses), to determine the specific memory active region of the deep learning neural network engine in the virtual memory model. The memory active region reflects the effective error injection range at the DRAM level composed of row information, column information, bank information, and channel information. In other words, it defines the memory region where data can be effectively written or read under given conditions.

[0061] During the operation of DNN critical data (deep learning neural network engine), REMU will monitor the data access situation in real time. When DNN critical data (deep learning neural network engine) performs a read or write operation on a certain data, REMU can capture this access request and quickly locate the position of the data in the virtual memory model according to the current mapping relationship.

[0062] Mapping relationship adjustment: If, during the operation, due to certain reasons (such as the structural adjustment of DNN, the change of optimization strategy, etc.) it is necessary to adjust the layout of DNN critical data, REMU can dynamically update the DRAM mapping file and the corresponding memory model. It will recalculate the mapping relationship of the data and feedback the new mapping information to the memory simulator to ensure the accurate storage and access of data under the new layout.

[0063] In summary, REMU realizes the calculation of the mapping relationship from DNN critical data (deep learning neural network engine) to its actual corresponding memory active region in various ways. The establishment of this mapping relationship is of great significance for optimizing the performance of DNN, reducing memory access latency, and improving memory utilization.

[0064] In step S400 of some embodiments, the memory active area is processed to construct an error injection space represented in the form of a bitmap tree, and according to the particle flip error model information recorded in the real radiation test and the Monte Carlo random algorithm, an error information injection position is determined in the error injection space; wherein, the particle flip error model information at least includes single particle flip error information and multi-particle flip error information; the error information injection position is the position where the single particle flip error information and the multi-particle flip error information are randomly injected into the error injection space represented in the form of a bitmap tree.

[0065] It should be noted that after determining the memory active area, various relevant information in this area is collected, including the physical address distribution of the memory, the organization form of the storage units (such as row-column structure, memory banks, channels, etc.), and the characteristics of different types of storage units (such as ordinary storage units, cache storage units, etc.), as well as parameters such as the refresh mechanism and access timing. This information will be used to subsequently construct an accurate bitmap tree to represent the error injection space.

[0066] According to the range of the memory active area and the collected information, the structure of the bitmap tree is designed. Each node of the bitmap tree represents a certain range or type of memory unit. The root node represents the entire memory active area, and the child nodes are gradually subdivided until the leaf nodes represent specific storage units or the smallest injectable error units.

[0067] Determine the number of layers of the bitmap tree and the specific content of each node. For example, the nodes can be set according to the division methods such as rows, columns, and memory banks of the memory, so that the bitmap tree can clearly reflect the spatial hierarchical relationship of the memory.

[0068] Furthermore, obtain the particle flip error model information recorded in the real radiation test, including single particle flip error information and multi-particle flip error information. This information can be obtained by conducting radiation experiments on the memory chip, simulating particle bombardment in different radiation environments, and recording the flipping situation of memory units caused by each radiation.

[0069] Even further, analyze the experimental data, summarize the occurrence probabilities of single particle flips and multi-particle flips under different conditions (such as radiation intensity, energy, angle, etc.), the distribution law of affected memory units, etc., to form a complete particle flip error model.

[0070] Using the Monte Carlo random algorithm, according to the particle flip error model information, randomly select an error information injection position in the error injection space represented by the bitmap tree. Specifically, based on the probability distribution given in the model, a random number is generated by a random number generator, and according to the random number, it is determined which node of the bitmap tree (i.e., which specific position in the memory) to inject the single particle flip error information or the multi-particle flip error information.

[0071] Repeat the above random selection process until a predetermined number of error injections is reached or other stop conditions are met. After each selection, update the state of the selected node to the state of the injected error to simulate the impact of particle flips on memory.

[0072] Furthermore, the error injection space represented in the form of a bitmap tree is established by traversing all physical blocks in the memory active area and performing DRAM addressing addresses corresponding to all physical blocks. Each layer in the tree structure of the bitmap tree represents a DRAM hierarchy. Each DRAM hierarchy includes multiple nodes, and each node includes at least one bitmap for indexing the next hierarchy.

[0073] It should be noted that the determined memory active area is divided into multiple physical blocks. The size of the physical block can be determined according to the characteristics of the memory and the accuracy requirements of the system. For example, it can be in units of memory pages (Page), or divided according to the storage array structure inside the DRAM chip.

[0074] Traverse each physical block in a certain order (such as from low address to high address). During the traversal process, record relevant information of each physical block, such as the starting address and size of the physical block.

[0075] In some embodiments, for each physical block, a corresponding DRAM addressing address is established. DRAM addressing is achieved through row addresses and column addresses. According to the specification of the DRAM chip and the design of the memory controller, determine how to map the physical block to specific row and column addresses.

[0076] For example, for a DRAM chip with a row-column structure, it may be necessary to first calculate the position of the physical block in the entire storage array, and then generate corresponding row strobe signals and column strobe signals according to the pin definition and timing requirements of the chip, so as to determine the unique DRAM addressing address.

[0077] Furthermore, the correspondence between the bitmap tree and the DRAM hierarchy: Each layer in the tree structure of the bitmap tree represents a DRAM hierarchy. The DRAM hierarchy can include different levels from macroscopic to microscopic, such as the memory active area, Rank, DRAM chip, Bank, storage array, storage unit, etc. For example, the root node can represent the entire memory active area, the first-level child nodes represent different Ranks, and the second-level child nodes represent DRAM chips in each Rank, etc.

[0078] Each DRAM hierarchy contains multiple nodes, and these nodes reflect different elements or states of this hierarchy. For example, at the storage array level, each node may represent a specific row or column.

[0079] Each node includes at least one bitmap for indexing the next level. A bitmap is a binary representation that can be used to record the connection relationship or status information between this node and the nodes of the next level.

[0080] For example, in a node representing a storage array, the bitmap can be used to indicate which rows or columns in the storage array are valid (i.e., contain data) and which are invalid (idle or unused). If a certain bit in the bitmap is 1, it means that the corresponding node of the next level is valid and further operations can be performed; if it is 0, it means that this path is unavailable.

[0081] The levels of the bit tree map are determined by the DRAM levels. For example, the levels of DRAM include: channel, bank, row, and column, etc. Therefore, the constructed bit tree map should have at least 4 levels.

[0082] The size of the bitmap for each level is determined by the number of valid ones in the next level. For example, if the channel level of DRAM is dual-channel, the size of the bitmap of the root node of the tree is 2, and there are three cases: 11, 10, 01, which respectively indicate whether channel 0 and channel 1 exist in the valid error space; If the bank level of DRAM has 8 banks, the size of the bitmap of the channel level is 8, which respectively index to 8 banks. For example, the bitmap 10000111 of channel 0 indicates that the next level of four banks: 0, 5, 6, 7 are indexed, meaning that banks 0, 5, 6, 7 exist in the valid error space, while banks 1, 2, 3, 4 do not exist in the valid error space. Such a design is to quickly locate the MCUs of adjacent rows or adjacent columns in the valid error space.

[0083] In some embodiments of the present invention, the steps of determining valid error search in the error space represented in the form of a bitmap tree include: Randomly select a parent node from the parent nodes of the bitmap tree as the high-level node, and select low-level nodes in the leaf nodes corresponding to the high-level node based on the error type corresponding to the particle flip error model information to determine the position of valid error information injection; and By calculating the memory size of the subtree of each high-level node, allocate the number of errors corresponding to the particle flip error model information layer by layer starting from the root node to determine the position of valid error information injection.

[0084] It should be noted that all the parent nodes of the bitmap tree are determined. A parent node is relative to a child node. In the structure of the bitmap tree, a node with child nodes is the parent node.

[0085] Then, a random index or number is generated by a random number generator, and this random index corresponds to a parent node in the bitmap tree. This random selection process can adopt a random algorithm with a uniform distribution to ensure that each parent node has an equal probability of being selected.

[0086] For example, if the bitmap tree has 5 parent nodes, the random number generator may generate an integer between 0 - 4, and the corresponding parent node is selected.

[0087] This random selection method can simulate the randomness of particle radiation. In the actual environment, the radiation of particles to different positions in the memory is random. By randomly selecting parent nodes, it can more realistically reflect the situation that particle flip errors may occur in any area of the memory.

[0088] It can avoid the bias introduced by selecting specific nodes, make the position of error injection more representative, and help to comprehensively evaluate the reliability of the system when facing particle flip errors.

[0089] In some embodiments, for single - particle flip errors, in the leaf nodes corresponding to the selected high - level nodes, a low - level node is selected according to a certain probability distribution. This probability distribution can be determined according to the vulnerability degree of different storage units in the memory or historical error data. For example, if some storage units are more vulnerable to single - particle flips due to physical location or circuit design reasons, then when selecting low - level nodes, the nodes corresponding to these storage units will have a higher probability of being selected. For multi - particle flip errors, multiple low - level nodes may be selected. The number and method of selection can be determined according to the specific model of multi - particle flip errors, such as selecting multiple adjacent or logically related nodes.

[0090] Selecting low - level nodes for different error types can more accurately simulate the actual particle flip error scenarios. Single - particle flip errors usually only affect one storage unit, while multi - particle flip errors may affect multiple related storage units. Through this targeted selection, it is possible to better study the impact of different types of errors on the system.

[0091] If it is found that some low - level nodes (i.e., storage units) often have problems under single - particle flip errors, then key optimizations can be carried out on the areas where these nodes are located, such as strengthening shielding measures or adopting error - correcting coding and other technologies.

[0092] It should be noted that calculate the memory size of the subtree of each high - level node, and start from the root node to allocate the number of errors layer by layer. The specific allocation rule: allocate the number of errors according to the proportion of the subtree memory size.

[0093] In the bitmap tree, each node can represent a part of the hierarchical memory address, such asFigure 3 Shown: "Channel 0 Bank 0". The leaf nodes of the bitmap tree (the bottommost nodes of the tree) can represent a complete memory address (including all DRAM levels).

[0094] The subtree memory size refers to the total number of all leaf nodes under a node (i.e., the number of addresses managed by that node). For example, the root node manages all addresses (such as 30MB), the child node "Channel 0" of the root node manages 10M addresses, and "Channel 1" manages 20M addresses.

[0095] This means that there are 10M memory addresses with "channel index" being 0 and 20M memory addresses with "channel index" being 1.

[0096] Proportional allocation: The number of errors allocated to each high-level node is proportional to its subtree memory size.

[0097] For example, if a total of 100 errors need to be injected, and channels 0 (10M) and 1 (20M) are allocated in a ratio of 1:2. Then approximately 33 errors are allocated to channel 0 and approximately 67 errors are allocated to channel 1.

[0098] Furthermore, the implementation steps for calculating the subtree memory size of each high-level node: Starting from the root node, traverse each high-level node of the bitmap tree.

[0099] For each high-level node, calculate the sum of the memory sizes represented by all its child nodes (including leaf nodes and the roots of other subtrees). This can be achieved by accumulating the memory block sizes marked by each child node. For example, if a child node represents a physical block and the size of this physical block is known to be 4KB, then when calculating the subtree memory size, this 4KB is added to the sum of the subtree memory sizes of its parent node.

[0100] Algorithms such as depth-first search (DFS) or breadth-first search (BFS) can be used to traverse the bitmap tree, and record the memory size information of each node during the traversal.

[0101] Calculating the subtree memory size is to reasonably allocate the number of errors according to the importance or scale of the memory area represented by the node. Generally speaking, the larger the memory area, the more opportunities it may be affected by particle radiation, so more weight should be given when allocating the number of errors.

[0102] In some embodiments, the implementation steps for allocating the number of errors layer by layer starting from the root node: Determine the total number of errors to be allocated according to the particle flip error model information. This total number can be obtained based on historical data, experimental tests, or theoretical calculations to simulate the number of errors that may occur within a certain time period or under a certain radiation intensity.

[0103] Starting from the root node, the error quantity is allocated to the child nodes in the next layer according to certain rules. The basis for allocation can be the proportion of the memory size of the subtree of each child node. For example, if the memory size of the subtree of a child node accounts for 20% of the memory size of the entire subtree, then it should be allocated approximately 20% of the error quantity.

[0104] For each layer, repeat the above allocation process until all the error quantities are allocated to the leaf nodes. During the allocation process, it is necessary to ensure that the allocation of the error quantity is an integer and the total allocated quantity is equal to the pre-determined total number of errors.

[0105] Allocating the error quantity layer by layer can achieve a non-uniform distribution of errors in memory, which is more in line with the actual situation. Because in an actual memory system, different regions are affected by particle radiation to different degrees due to factors such as their functions, usage frequencies, and physical locations. Through layer-by-layer allocation, errors can be injected more reasonably according to the hierarchical structure and characteristics of the memory.

[0106] In step S500 of some embodiments, based on the address mapping relationship and the error information injection location, reverse translation processing is performed on the physical address in the virtual memory model to determine the target virtual address of the deep learning inference process.

[0107] It should be noted that starting from the determined physical address, the reverse translation of the address mapping relationship is used to find the corresponding virtual address.

[0108] According to the address mapping relationship between the initial virtual address in the deep learning inference process represented by the process page table and the physical address in the target DRAM memory device, after reverse translation processing, the target virtual address corresponding to the physical address of the error injection location is obtained. This target virtual address is the address in the deep learning inference process that may be affected.

[0109] This target virtual address needs to be analyzed to determine which part of the deep learning inference process it belongs to, such as the code segment, data segment, or stack segment, in order to further evaluate the impact of the error on the process. Through reverse translation processing, the error injection location of the physical address can be accurately mapped to the virtual address space. This enables precise knowledge of which part of the deep learning inference process will be affected by the error, such as the model parameter storage area, program code area, or intermediate data storage area, etc.

[0110] It helps developers or researchers to specifically back up, verify, or take other error correction measures for the data within the virtual address range where errors may occur, improving the reliability of the system.

[0111] In some embodiments of the present invention, after the step of performing reverse translation processing on the physical address in the virtual memory model based on the address mapping relationship and the error information injection position to determine the target virtual address of the deep learning inference process, the method includes: Performing bit flipping of random bits on the single-byte data of the target virtual address through an exclusive OR operation to obtain a bit flipping result of the target virtual address; Based on the bit flipping result of the target virtual address, using the deep learning inference program to execute an inference task to obtain an inference result corresponding to the on-board intelligent computing system.

[0112] It should be noted that single-byte data is extracted from the target virtual address. For example, if the target virtual address is a 32-bit address, it can be divided into 4 bytes, and then one byte is selected as the object to be bit-flipped.

[0113] To perform bit flipping of random bits, a random bit pattern of the same length as the selected single-byte data needs to be generated. This random bit pattern can be created through a random number generator.

[0114] For example, for an 8-bit single-byte data, an 8-bit random bit pattern is generated, such as 10101010.

[0115] In some embodiments, the single-byte data of the target virtual address is subjected to an exclusive OR operation with the generated random bit pattern. The rule of the exclusive OR operation is: the result of the same bit is 0, and the result of different bits is 1.

[0116] For example, if the single-byte data is 11001100 and the random bit pattern is 10101010, then the result after the exclusive OR operation is 01100110. In this way, bit flipping of random bits in the single-byte data is achieved.

[0117] In some embodiments, after obtaining the bit flipping result of the target virtual address, this result is applied to the on-board intelligent computing system. This may involve integrating the flipped bits into the memory or data processing pipeline of the system.

[0118] Then, use the deep learning inference program to execute the inference task. This includes steps such as preprocessing of input data and inference calculation of the model. For example, the data collected by the on-board intelligent computing system is input into the trained deep learning model, and the model calculates according to the input data and its own parameters to obtain an inference result.

[0119] In some embodiments, after determining the target virtual address, the importance of this address in the deep learning inference process can be analyzed. If the error injection affects critical model weight data or the instruction code that controls the program, the reliability of the on-board intelligent computing system may be severely threatened. Through this analysis, the vulnerability of the system under error injection of different types and locations can be evaluated. The system can be optimized according to the evaluation results, such as adjusting the memory layout, adopting a more reliable coding method, or adding error detection and correction mechanisms, to improve the resilience of the on-board intelligent computing system when facing errors such as single-event upsets.

[0120] The embodiments provided by the present invention help to evaluate the performance of the on-board intelligent computing system when facing such errors, such as whether it can detect errors, whether it will cause the system to crash or produce incorrect outputs, etc.

[0121] By testing and analyzing in this way, it can help developers discover the reliability problems existing in the on-board intelligent computing system and take corresponding measures for optimization. For example, if it is found that bit flips in a certain area often lead to serious errors, special protection can be considered for the memory in this area, or the parameters of the deep learning model can be adjusted to improve its robustness to noise.

[0122] At the same time, this also helps to improve the reliability and performance of the system without significantly increasing the system overhead. For example, by reasonably selecting the type and length of the error correction code, the impact on the system performance can be reduced while ensuring a certain error correction ability.

[0123] In some embodiments of the present invention, Figure 2 is the second schematic flowchart of the memory error simulation method based on the on-board intelligent computing system provided by the present invention. The present invention mainly consists of four core stages: DNN engine loading, memory address translation, error injection point search, and error injection. Thus, a complete mapping link from the bit flip error of the DRAM memory cell to the running state of the application layer DNN is established, realizing the accurate simulation and injection of radiation errors.

[0124] The first stage: The on-board intelligent computing system takes the DNN engine file as the input and starts the execution of the DNN program. At this time, the DNN inference process is created, and the DNN key data (i.e., its engine file) is loaded into the memory. REMU reads the size and address of the DNN key data in the running process space and uses the kernel interface of the operating system to read the process page table to complete the preliminary mapping between the virtual address and the physical address.

[0125] In an embodiment of the present invention, REMU uses a "DRAM standard file" as input to construct a DRAM hierarchy. This file provides the number of effective channels, ranks, banks, rows, and columns to establish the DRAM hierarchy.

[0126] The design of the DRAM hierarchy uses a standard-independent state machine. That is to say, this state machine does not depend on specific memory standards (such as LPDDR4, DDR4, etc.). It is an abstract DRAM design that can adapt to multiple memory standards. Then, any specific standard (such as LPDDR4) is paired with this state machine and integrated into a single class. Secondly, REMU uses a "DRAM mapping file" to define the mapping from the DRAM hierarchy to the physical address, that is, which bits in the physical address are the row index and which bits are the column index.

[0127] To accurately inject SEU / MCU errors during DNN inference runtime, the primary task is to map the DNN to the DRAM. It is observed that the process space of DNN inference is huge, and the SEU / MCU errors caused by radiation are unpredictable. Therefore, the present invention simplifies the mapping process and focuses on the inference-critical and computationally intensive DNN engine (i.e., the optimized runtime DNN model for performing inference). This mapping is achieved through two steps.

[0128] First, the system uses the kernel interface to translate the user-space virtual address into a physical address. In a modern memory management system, due to the fragmentation and finiteness of the physical memory space during the process runtime, memory allocation is scattered. Therefore, the continuous virtual memory space of the DNN engine is usually allocated to discrete physical frames, and the order of these physical frames is different from that of the virtual pages. The present invention constructs a one-to-one mapping chain between the virtual block and the physical block through the process context page table.

[0129] Secondly, the present invention uses the correctness-verified scalable DRAM simulator Ramulator to process the translated physical blocks. This benefits from the general modeling of the DRAM memory system, as well as the configurable DRAM standards (such as LPDDR4 used in the embodiment of the present invention) and DRAM addressing methods.

[0130] The rule for determining the number of address bits for memory addressing: The default scenario is byte addressing, and the number of address bits needs to cover the number of bytes in the target memory space and round up to the nearest power of 2. For example, in a 10Kb space, 2KB > 10Kb > 1KB, and the lowest 11 bits of the physical address are required for addressing.

[0131] The present invention improves it to further support error injection simulation in DRAM. Specifically, the present invention determines the range of each DRAM level (including rows, columns, banks, channels, etc.) according to the target physical memory space. For example, in a 4KB space, only the lowest 12 bits of the physical address are used for addressing, and in LPDDR4, it usually contains rows and columns. In this way, SEU errors and MCU errors adjacent to rows, columns, and DQ can be simulated within this range, and the corresponding bit positions in the virtual memory space can be flipped.

[0132] The second stage: REMU focuses on memory address translation. According to the configurable DRAM standard file and DRAM mapping file, it initializes an instance of the target memory standard using a memory simulator, perceives the actual layout of DNN key data on the target DRAM memory device (including rows, columns, banks, channels, etc.), and constructs a special data structure to organize and record relevant information. So far, REMU has completed the calculation of the mapping relationship from DNN key data to its actual corresponding memory active area from top to bottom.

[0133] In some embodiments of the present invention, the multiplicity of MCU refers to the spatial correlation of multiple particle flips, that is, the number of adjacent bits that flip simultaneously, usually ranging from 2 bits to 8 bits, that is, 1 MCU may cause 2 to 8 adjacent bits to flip simultaneously.

[0134] The third stage: Construct the memory active area into an error injection space based on a bitmap tree. REMU quickly searches for error injection positions that conform to the SEU distribution model and MCU shape in the error injection space based on the SEU / MCU error model recorded in the actual radiation test and the Monte Carlo random algorithm.

[0135] The fourth stage: REMU returns to the process runtime environment of the DNN inference program, translates the searched error injection position from the memory cell address, through the physical address, and finally back to the process virtual address, performs an exclusive OR operation on the target virtual address to simulate bit flipping, and allows the program to continue with subsequent inference calculations.

[0136] Figure 3It is a schematic diagram of the data structure of the bitmap tree provided by the present invention. When performing DNN inference, memory access follows a top-down manner, starting from the virtual memory space, converting to the physical memory space, and finally locating to the DRAM memory cell (DRAM level). However, when an error caused by radiation occurs in the DRAM, its impact on DNN inference is mapped in the opposite direction. Due to the fragmentation of physical blocks, these random errors may get lost in the vast physical memory space (i.e., the huge physical memory space unrelated to DNN inference). Therefore, REMU introduces a dual addressing mechanism based on the bitmap tree to optimize the addressing process and narrow the search space for relevant errors, so as to efficiently inject SEU / MCU errors into DNN inference in the huge physical memory space.

[0137] The bitmap-based tree structure is established by traversing all physical blocks and performing DRAM addressing of these addresses. Each layer of the tree represents a DRAM level, and each node contains a bitmap for indexing the next level. For example, Figure 3 As shown, the bitmap 10000111 of channel "0" indicates indexing the next level of four banks - "0", "5", "6", "7", indicating that the banks in these channels are associated with the physical blocks allocated by the DNN inference engine, and the errors in them are valid. As mentioned above, the proximity of the MCU is manifested in three dimensions: row, column, and DQ. To achieve fast search, the present invention places the static bank and channel levels near the root, while placing the dynamic row, column, and DQ levels near the leaf nodes. In this way, in the depth-first traversal, the proximity check of the lower-level nodes (i.e., rows and columns) will not affect the initial fast selection of the higher-level nodes (i.e., channels and banks).

[0138] The search for valid errors mainly includes two steps: First, randomly select a higher-level node based on the bitmap of the parent node. For example, Figure 3 As shown, bank "0" is selected according to the bitmap 10000111 of channel "0". Second, select the lower-level nodes based on the error type. For SEU, the selection of rows and columns is the same as that of the higher-level node.

[0139] For column-adjacent and row-adjacent MCU, the selection of columns and rows is based on the proximity index in the bitmap of their parent node.

[0140] If the proximity is not found in the bitmap, continue to perform the proximity check on the sibling nodes of the parent node, following the depth-first principle. Once the adjacent columns are determined, the rows of the next layer can be selected by performing a bitwise AND operation based on the bitmaps of these columns.

[0141] However, if only one error is searched each time through traversal, injecting multiple errors is still costly.

[0142] Therefore, the present invention calculates the subtree memory size of each high-level node and allocates the number of errors layer by layer starting from the root node. For example, if channel "0" has a 10M address space and channel "1" has a 20M address space, approximately 1 / 3 of the SEUs / MCUs will be allocated to channel "0" and 2 / 3 to channel "1". In this way, all errors can be searched in a single depth-first traversal.

[0143] After the error search is completed in the physical memory space, a series of valid physical addresses storing the key data of DNN inference are obtained, and these addresses need to be further converted into valid virtual addresses using the one-to-one mapping chain between the aforementioned virtual and physical blocks. In addition, the present invention optimizes the mapping by merging multiple consecutive physical blocks into a larger block, thereby further improving the search efficiency.

[0144] In some embodiments of the present invention, the steps of the flexible extension framework (scalable) based on the unified error model include: current on-orbit and upcoming on-orbit intelligent computing COTS devices cover a variety of mainstream computing platforms such as the NVIDIA Jetson series (Xavier NX, AGX Orin, TX2, AGX Xavier, Nano), Intel processors (Loihi Gen-1, Movidius Myriad 2), and Qualcomm processors. Based on this, the present invention adopts a scalable design solution based on configuration, and comprehensively characterizes the target DRAM chip and the error model through a user-friendly configuration file. The present invention uses the external configuration file of the target DRAM chip as input to establish the REMU simulator, including the DRAM standard file and the DRAM addressing file. This external configuration file method provides good scalability for the system, enabling it to adapt to different types of DRAM chips and addressing schemes. In addition, the present invention uses a default error model. This error model is based on extensive on-orbit and ground radiation test statistical data. Among them, due to the space-independent characteristic of SEU, it is modeled as a random bit flip. While MCU shows spatial proximity in three dimensions (row, column, and DQ), with different multiplicities (usually ranging from 2 bits to 8 bits), ratios, and patterns.

[0145] This statistical modeling based on actual test data ensures a high degree of consistency between the error model and the actual radiation environment.

[0146] The present invention provides a configuration interface for the error model, allowing users to customize according to their own radiation test results, which provides the possibility for further exploring the performance of DNN inference in different radiation environments. Further, to improve the usability of the present invention, REMU links the libREMUmem.so library through source code instrumentation, realizing the automation of memory addressing and the automatic injection of SEU / MCU errors in runtime DNN inference. This design not only simplifies the usage process of the present invention but also provides a unified interface for error injection in different application scenarios.

[0147] The relevant configurations for implementing the memory error simulation method based on the on-orbit intelligent computing system in the present invention are as follows: Memory configuration: In edge computing on orbit, the low-power LPDDR memory standard is widely used in various COTS devices. The present invention can be implemented on a COTS GPU device with a physically unified memory architecture - NVIDIA Jetson Xavier NX, where the memory chip is 16GB 128-bit LPDDR4 (JESD209-4). Specifically as follows: (1) The DRAM devices on which the present invention can be implemented generally include six levels: die, channel, rank, bank, array, and cell. LPDDR4 defines dual-channel chips, each channel having 16 DQs (data I / O pins for parallel data transmission), supporting different storage densities (such as 16 Gb). To improve data parallelism, multiple dual-channel chips can be used (for example, 128-bit LPDDR4 uses 8 dual-channel chips). Each DRAM channel contains multiple banks, and each bank contains a three-dimensional array in the row, column, and DQ dimensions. The array is composed of DRAM cells arranged row by row and column by column. The DRAM cell is the most basic storage unit of the DRAM. A DRAM cell consists of a CMOS transistor responsible for switching and a capacitor responsible for storage. The DRAM cells in a row share a byte line. When the byte line is activated, the CMOS transistor is turned on, and the capacitor is connected to the bit line. The DRAM cells in a column share a bit line, and bits are read and written through the bit line. The capacitor is charged to store logic "1" or discharged to store logic "0". Therefore, the bit position adjacency of multiple-bit flips (MCU) is manifested in three dimensions: consecutive rows sharing the same bit line, consecutive columns sharing the same word line, and consecutive DQ bits in the same logical word.

[0148] (2) The COTS GPU devices applicable to the present invention generally have a physical unified memory architecture: the host memory and the GPU memory are physically the same. This architecture is common in spaceborne COTS GPUs, such as the NVIDIA Jetson series. The physically unified architecture simplifies the error injection in the GPU memory for REMU and eliminates the need to manage separate memory spaces for the CPU and the GPU respectively. The present invention can accurately generate radiation-induced low-level SEU / MCU errors in a unified DRAM device and inject these errors into the high-level process space through the CPU memory system. Then, the error-injected process space (i.e., the DNN engine) serves as the global memory of the GPU, and all GPU threads can access it during DNN inference.

[0149] System configuration: When the present invention performs the mapping from the process space for DNN inference to the DRAM memory cells, the memory management unit translates the virtual page to the physical frame through the memory paging mechanism, and this translation is implemented through the Linux kernel interface / proc / pid / pagemap, thereby converting the virtual address in the process space to the physical address; then, the memory controller converts the physical address to the DRAM address and accesses the data. The DRAM addressing adopts the default non-interleaved addressing strategy to ensure that the MCU errors are located in continuous physical address blocks. Specifically, the lowest 4 bits are for DQ addressing, followed by 10 bits for column addressing, followed by 1 bit for channel addressing, followed by 3 bits for bank addressing, and followed by 16 bits for row addressing.

[0150] The present invention can also support a custom DRAM address mapping scheme.

[0151] Error model configuration: Based on the statistical data of existing radiation tests, the present invention sets the bit error rate to to between. The default error model includes two modes, single event upset (SEU) and multiple event upset (MCU), and the concurrent mode. For different BER settings and memory space sizes, in the concurrent error model, the proportion of SEU usually exceeds 90%, and the occurrence probability of MCU with 3 bits and above is significantly lower than that of SEU and 2-bit MCU. The multiplicity of MCU ranges from 2 bits to 8 bits.

[0152] The error model of this implementation follows the results of existing radiation tests: the probability of flipping two DRAM cells along the same wordline reaches 80%, which is significantly higher than the probability of 20% of flipping along the same bitline. This statistical modeling based on actual test data ensures a high degree of consistency between the error model and the actual radiation environment.

[0153] The present invention is a configurable, software-only error emulation tool. The present invention injects memory errors at the hardware level into the runtime DNN inference process, which can not only be customized according to different memory devices (providing configurable memory standards and memory mapping interfaces), but also be migrated to different CPU instruction architectures (such as AArch64, x86-64) and FPGA architectures. In addition, the present invention provides a configurable error model interface, which enables users to further explore the inference performance of DNN models based on real-world radiation test results, including the frequency of single / multiple particle flips, the multiplicity and shape of multiple particle flips, etc.

[0154] The present invention combines an accurate error mapping mechanism and an efficient error search algorithm, enabling REMU to provide comprehensive technical support for evaluating and improving the reliability of deep neural network systems in space environments. Through a unified error model and a flexible configuration interface, the system can simulate error conditions in various radiation environments, providing an important experimental platform for the reliability research of space intelligent computing systems. The beneficial effects of the present invention at least include the following technical effects: (1) The error injection simulated by the present invention provides key insights into the reliability of on-board intelligent computing systems: different DNN model structures exhibit different inherent fault tolerance capabilities to radiation-induced errors.

[0155] During the DNN runtime inference process, there are some undiscovered sensitive points, which may trigger an accuracy collapse more serious than model parameter errors, ultimately leading to the degradation of decision results to random guessing.

[0156] Space-related multiple particle flip errors in memory cannot be simplified to multiple single particle flip errors. Multiple particle flips often have a more serious impact because sensitive points in DNN inference usually have a clustering property.

[0157] (2) Through the optimization of the bitmap tree, the efficiency of error injection is greatly improved.

[0158] After testing: the DNN inference completion time before / after error injection, and the DNN inference completion time with / without bitmap tree optimization. The test results show that unoptimized error injection will increase the completion time by 67.1 to 99.8 times, while the time overhead after optimization is reduced to 3.1 to 3.5 times.

[0159] A method, device, medium and simulator for memory error simulation based on a spaceborne intelligent computing system provided by the present invention. The optimized deep learning neural network engine is input into the spaceborne intelligent computing system, where the spaceborne intelligent computing system at least includes a deep learning inference program. The deep learning inference program is executed to create a deep learning inference process and load the deep learning neural network engine into the target DRAM memory device, and the kernel interface of the operating system is used to read the process page table, where the process page table represents the address mapping relationship between the initial virtual address in the deep learning inference process and the physical address in the target DRAM memory device. Based on the configurable DRAM standard file, DRAM mapping file and the address mapping relationship, the memory active area of the deep learning neural network engine in the virtual memory model is determined, where the virtual memory model is a model simulating the target DRAM memory device. The memory active area is processed to construct a miserror space represented in the form of a bitmap tree, and according to the particle flip error model information recorded in the real radiation test and the Monte Carlo random algorithm, the error information injection position is determined in the miserror space, where the particle flip error model information at least includes single particle flip error information and multi-particle flip error information, and the error information injection position is the position where the single particle flip error information and the multi-particle flip error information are randomly injected into the miserror space represented in the form of a bitmap tree. Based on the address mapping relationship and the error information injection position, reverse translation processing is performed on the physical address in the virtual memory model to determine the target virtual address of the deep learning inference process. It can effectively simulate the space-time independent single particle flip memory error and the space-related multi-particle flip memory error caused by space radiation, so as to evaluate the impact of the space radiation memory error on the spaceborne intelligent computing system during the deep learning inference process, and can also evaluate the impact of the memory bit flip error caused by space radiation on the operation of the spaceborne intelligent computing system, realizing high processing efficiency and strong scalability on the basis of accurate simulation.

[0160] The memory error simulation device based on the spaceborne intelligent computing system provided by the present invention is described below. The memory error simulation device based on the spaceborne intelligent computing system described below can be referred to correspondingly with the memory error simulation method based on the spaceborne intelligent computing system described above.

[0161] As Figure 4 shown is the structural schematic diagram of the memory error simulation device based on the spaceborne intelligent computing system provided by the present invention. A memory error simulation device based on the spaceborne intelligent computing system includes: An input module 410, configured to input the optimized deep learning neural network engine into the spaceborne intelligent computing system, where the spaceborne intelligent computing system at least includes a deep learning inference program; The address mapping relationship determination module 420 is configured to execute the deep learning inference program to create a deep learning inference process and load the deep learning neural network engine into the target DRAM memory device, and read the process page table by using the kernel interface of the operating system, where the process page table represents the address mapping relationship between the initial virtual address in the deep learning inference process and the physical address in the target DRAM memory device; The memory active area determination module 430 is configured to determine the memory active area of the deep learning neural network engine in the virtual memory model based on a configurable DRAM standard file, a DRAM mapping file, and the address mapping relationship; where the virtual memory model is a model that simulates the target DRAM memory device; The error information injection position determination module 440 is configured to perform a construction process on the memory active area, construct an error injection space represented in the form of a bitmap tree, and determine an error information injection position in the error injection space according to the particle flip error model information recorded in the real radiation test and the Monte Carlo random algorithm; where the particle flip error model information at least includes single particle flip error information and multi-particle flip error information; the error information injection position is the position where the single particle flip error information and the multi-particle flip error information are randomly injected into the error injection space represented in the form of a bitmap tree; The target virtual address determination module 450 is configured to perform reverse translation processing on the physical address in the virtual memory model based on the address mapping relationship and the error information injection position to determine the target virtual address of the deep learning inference process.

[0162] Preferably, the memory error simulation device based on the on-board intelligent computing system provided by the present invention is further specifically configured to input the optimized deep learning neural network engine into the on-board intelligent computing system; where the on-board intelligent computing system at least includes a deep learning inference program; Execute the deep learning inference program to create a deep learning inference process and load the deep learning neural network engine into the target DRAM memory device, and read the process page table by using the kernel interface of the operating system, where the process page table represents the address mapping relationship between the initial virtual address in the deep learning inference process and the physical address in the target DRAM memory device; Based on a configurable DRAM standard file, a DRAM mapping file, and the address mapping relationship, determine the memory active area of the deep learning neural network engine in the virtual memory model; where the virtual memory model is a model that simulates the target DRAM memory device; Perform construction processing on the memory active area to construct an error injection space represented in the form of a bitmap tree, and determine the error information injection position in the error injection space according to the particle flip error model information recorded in the real radiation test and the Monte Carlo random algorithm; wherein, the particle flip error model information at least includes single-event upset error information and multiple-event upset error information; the error information injection position is the position where the single-event upset error information and the multiple-event upset error information are randomly injected into the error injection space represented in the form of a bitmap tree. Based on the address mapping relationship and the error information injection position, perform reverse translation processing on the physical address in the virtual memory model to determine the target virtual address of the deep learning inference process.

[0163] Preferably, the memory error simulation device based on the spaceborne intelligent computing system provided by the present invention is specifically further configured to perform bit flipping on a single-byte data of the target virtual address through an exclusive OR operation to obtain a bit flipping result of the target virtual address. Based on the bit flipping result of the target virtual address, use the deep learning inference program to execute an inference task to obtain an inference result corresponding to the spaceborne intelligent computing system.

[0164] Preferably, the memory error simulation device based on the spaceborne intelligent computing system provided by the present invention is specifically further configured to use a memory simulator to read standard parameters in a DRAM standard file. According to the standard parameters in the DRAM standard file, the mapping information of the DRAM mapping file, and the memory device information of the target DRAM memory device, determine the connection relationship and address mapping rules of each component in the target DRAM memory device for the deep learning neural network engine; wherein, the address mapping rule represents the rule for mapping the addresses of each component in the target DRAM memory device to the virtual memory model; each component at least includes: a row part, a column part, a bank part, and a channel part. According to the connection relationship and the address mapping rules of each component in the target DRAM memory device for the deep learning neural network engine, construct a virtual memory model for simulating the target DRAM memory device.

[0165] Preferably, the memory error simulation device based on the spaceborne intelligent computing system provided by the present invention is specifically further used for the steps of initializing an instance of the virtual memory model by using the memory simulator, and determining an active memory area of the deep learning neural network engine in the virtual memory model based on the connection relationship, the address mapping rule, and the address mapping relationship; wherein, the active memory area represents a valid error injection range at the DRAM level composed of row information, column information, bank information, and channel information.

[0166] Preferably, the memory error simulation device based on the spaceborne intelligent computing system provided by the present invention is specifically further used for the error injection space represented in the form of a bitmap tree to traverse all physical blocks in the active memory area and establish DRAM addressing addresses corresponding to all physical blocks; Each layer in the tree structure of the bitmap tree represents a DRAM level, each DRAM level includes multiple nodes, and each node includes at least one bitmap for indexing the next level.

[0167] Preferably, the memory error simulation device based on the spaceborne intelligent computing system provided by the present invention is specifically further used for randomly selecting a parent node from the parent nodes of the bitmap tree as a high-level node, and selecting a low-level node from the leaf nodes corresponding to the high-level node based on the error type corresponding to the particle flip error model information to determine a valid error information injection position; and By calculating the memory size of the subtree of each high-level node, the number of errors corresponding to the particle flip error model information is allocated layer by layer starting from the root node to determine a valid error information injection position.

[0168] A method, device, medium and simulator for memory error simulation based on a spaceborne intelligent computing system provided by the present invention, wherein an optimized deep learning neural network engine is input into the spaceborne intelligent computing system; the spaceborne intelligent computing system at least includes a deep learning inference program; the deep learning inference program is executed to create a deep learning inference process and to load the deep learning neural network engine into a target DRAM memory device, and the kernel interface of the operating system is used to read the process page table, and the process page table represents the address mapping relationship between the initial virtual address in the deep learning inference process and the physical address in the target DRAM memory device; based on a configurable DRAM standard file, a DRAM mapping file and the address mapping relationship, determine the memory active area of the deep learning neural network engine in the virtual memory model; the virtual memory model is a model that simulates the target DRAM memory device; the memory active area is subjected to construction processing to construct a miserror space represented in the form of a bitmap tree, and according to the particle flip error model information recorded in the real radiation test and the Monte Carlo random algorithm, determine the error information injection position in the miserror space; the particle flip error model information at least includes single particle flip error information and multi-particle flip error information; the error information injection position is the position where the single particle flip error information and the multi-particle flip error information are randomly injected into the miserror space represented in the form of a bitmap tree; based on the address mapping relationship and the error information injection position, perform reverse translation processing on the physical address in the virtual memory model to determine the target virtual address of the deep learning inference process. It can effectively simulate the space-time independent single particle flip memory error and the space-related multi-particle flip memory error caused by space radiation, so as to evaluate the impact of the space radiation memory error on the spaceborne intelligent computing system during the deep learning inference process, and can also evaluate the impact of the memory bit flip error caused by space radiation on the operation of the spaceborne intelligent computing system, and achieve high processing efficiency and strong scalability on the basis of accurate simulation.

[0169] In an embodiment of the present invention, the present invention also provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, and when the processor executes the program, it implements the memory error simulation method based on a spaceborne intelligent computing system as described in any one of the above.

[0170] Figure 5 An entity structure diagram of an electronic device is exemplified, as Figure 5As shown in the figure, the electronic device may include: a processor 510, a communications interface 520, a memory 530, and a communication bus 540. Among them, the processor 510, the communications interface 520, and the memory 530 complete mutual communication through the communication bus 540. The processor 510 can call the logical instructions in the memory 530 to execute a memory error simulation method based on an on-board intelligent computing system. The method includes: inputting an optimized deep learning neural network engine into the on-board intelligent computing system; where the on-board intelligent computing system at least includes a deep learning inference program; executing the deep learning inference program to create a deep learning inference process and to load the deep learning neural network engine into a target DRAM memory device, and using the kernel interface of the operating system to read the process page table, where the process page table represents the address mapping relationship between the initial virtual address in the deep learning inference process and the physical address in the target DRAM memory device; based on a configurable DRAM standard file, a DRAM mapping file, and the address mapping relationship, determining the memory active area of the deep learning neural network engine in the virtual memory model; where the virtual memory model is a model that simulates the target DRAM memory device; performing a construction process on the memory active area to construct an error injection space represented in the form of a bitmap tree, and determining an error information injection position in the error injection space according to the particle flip error model information recorded in the real radiation test and the Monte Carlo random algorithm; where the particle flip error model information at least includes single particle flip error information and multi-particle flip error information; the error information injection position is the position where the single particle flip error information and the multi-particle flip error information are randomly injected into the error injection space represented in the form of a bitmap tree; based on the address mapping relationship and the error information injection position, performing reverse translation processing on the physical address in the virtual memory model to determine the target virtual address of the deep learning inference process.

[0171] In addition, when the logical instructions in the aforementioned memory 530 can be implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0172] On the other hand, the present invention also provides a computer program product. The computer program product includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute a memory error simulation method based on an on-board intelligent computing system provided by the above-mentioned various methods. The method includes: inputting an optimized deep learning neural network engine into the on-board intelligent computing system; wherein, the on-board intelligent computing system at least includes a deep learning inference program; executing the deep learning inference program to create a deep learning inference process and to load the deep learning neural network engine into a target DRAM memory device, and using the kernel interface of the operating system to read the process page table, where the process page table represents the address mapping relationship between the initial virtual address in the deep learning inference process and the physical address in the target DRAM memory device; based on a configurable DRAM standard file, a DRAM mapping file, and the address mapping relationship, determining the memory active area of the deep learning neural network engine in the virtual memory model; wherein, the virtual memory model is a model that simulates the target DRAM memory device; performing a construction process on the memory active area to construct a misannotation space represented in the form of a bitmap tree, and according to the particle flip error model information recorded in the real radiation test and the Monte Carlo random algorithm, determining the error information injection position in the misannotation space; wherein, the particle flip error model information at least includes single particle flip error information and multi-particle flip error information; the error information injection position is the position where the single particle flip error information and the multi-particle flip error information are randomly injected into the misannotation space represented in the form of a bitmap tree; based on the address mapping relationship and the error information injection position, performing reverse translation processing on the physical address in the virtual memory model to determine the target virtual address of the deep learning inference process.

[0173] In another aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements a memory error simulation method based on an on-board intelligent computing system provided by the above-mentioned various methods. The method includes: inputting the optimized deep learning neural network engine into the on-board intelligent computing system; wherein, the on-board intelligent computing system at least includes a deep learning inference program; executing the deep learning inference program to create a deep learning inference process and to load the deep learning neural network engine into the target DRAM memory device, and using the kernel interface of the operating system to read the process page table, where the process page table represents the address mapping relationship between the initial virtual address in the deep learning inference process and the physical address in the target DRAM memory device; based on the configurable DRAM standard file, the DRAM mapping file and the address mapping relationship, determining the memory active area of the deep learning neural network engine in the virtual memory model; wherein, the virtual memory model is a model simulating the target DRAM memory device; performing a construction process on the memory active area to construct an error injection space represented in the form of a bitmap tree, and determining an error information injection position in the error injection space according to the particle flip error model information recorded in the real radiation test and the Monte Carlo random algorithm; wherein, the particle flip error model information at least includes single particle flip error information and multi-particle flip error information; the error information injection position is the position where the single particle flip error information and the multi-particle flip error information are randomly injected into the error injection space represented in the form of a bitmap tree; based on the address mapping relationship and the error information injection position, performing reverse translation processing on the physical address in the virtual memory model to determine the target virtual address of the deep learning inference process.

[0174] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative labor.

[0175] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0176] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for simulating memory errors based on a spaceborne intelligent computing system, characterized in that, Including: Input the optimized deep learning neural network engine into the on-board intelligent computing system; wherein, the on-board intelligent computing system at least includes a deep learning inference program; Execute the deep learning inference program to create a deep learning inference process, and load the deep learning neural network engine into the target DRAM memory device, and use the kernel interface of the operating system to read the process page table, and the process page table represents the address mapping relationship between the initial virtual address in the deep learning inference process and the physical address in the target DRAM memory device; Based on the configurable DRAM standard file, DRAM mapping file, and the address mapping relationship, determine the memory active area of the deep learning neural network engine in the virtual memory model; wherein, the virtual memory model is a model that simulates the target DRAM memory device; Perform a construction process on the memory active area to construct an error injection space represented in the form of a bitmap tree, and determine the error information injection position in the error injection space according to the particle flip error model information recorded in the real radiation test and the Monte Carlo random algorithm; wherein, the particle flip error model information at least includes single particle flip error information and multi-particle flip error information; the error information injection position is the position where the single particle flip error information and the multi-particle flip error information are randomly injected into the error injection space represented in the form of a bitmap tree; Based on the address mapping relationship and the error information injection position, perform reverse translation processing on the physical address in the virtual memory model to determine the target virtual address of the deep learning inference process.

2. The method for simulating memory errors based on the on-board intelligent computing system according to claim 1, characterized in that, After the step of performing reverse translation processing on the physical address in the virtual memory model based on the address mapping relationship and the error information injection position to determine the target virtual address of the deep learning inference process, the method includes: Perform bit flipping of random bits on the single-byte data of the target virtual address through an exclusive OR operation to obtain the bit flipping result of the target virtual address; Based on the bit flipping result of the target virtual address, use the deep learning inference program to execute an inference task to obtain an inference result corresponding to the on-board intelligent computing system.

3. The memory error simulation method based on the on-board intelligent computing system according to claim 1, characterized in that, The step of constructing the virtual memory model includes: Use a memory simulator to read the standard parameters in the DRAM standard file; According to the standard parameters in the DRAM standard file, the mapping information of the DRAM mapping file, and the memory device information of the target DRAM memory device, determine the connection relationship and address mapping rules of each component of the deep learning neural network engine in the target DRAM memory device; wherein, the address mapping rules represent the rules for mapping the addresses of each component in the target DRAM memory device to the virtual memory model; each component at least includes: row part, column part, bank part, channel part; Construct a virtual memory model that simulates the target DRAM memory device according to the connection relationships and address mapping rules of the various components of the deep learning neural network engine in the target DRAM memory device.

4. The memory error simulation method based on the on-board intelligent computing system according to claim 3, wherein Determine the memory active region of the deep learning neural network engine in the virtual memory model based on the configurable DRAM standard file, DRAM mapping file, and the address mapping relationship, including: The step of initializing an instance of the virtual memory model using the memory simulator, and determining the memory active region of the deep learning neural network engine in the virtual memory model based on the connection relationship, the address mapping rule, and the address mapping relationship; wherein, the memory active region represents the effective error injection range of the DRAM hierarchy composed of row information, column information, bank information, and channel information.

5. The memory error simulation method based on the on-board intelligent computing system according to claim 1, characterized in that The method further includes: Traversing all physical blocks in the memory active region with the error injection space represented in the form of a bitmap tree, and performing DRAM addressing address establishment corresponding to all physical blocks; Wherein, each layer in the tree structure of the bitmap tree represents a DRAM hierarchy, each DRAM hierarchy includes multiple nodes, and each node includes at least one bitmap for indexing the next hierarchy.

6. The memory error simulation method based on the on-board intelligent computing system according to claim 5, wherein The step of determining effective error search in the error injection space represented in the form of a bitmap tree includes: Randomly selecting a parent node from the parent nodes of the bitmap tree as a high-level node, and selecting a low-level node in the leaf nodes corresponding to the high-level node based on the error type corresponding to the particle flip error model information to determine the effective error information injection position; and Determining the effective error information injection position by calculating the memory size of the subtree of each high-level node and allocating the number of errors corresponding to the particle flip error model information layer by layer starting from the root node.

7. A memory error simulation device based on a spaceborne intelligent computing system, characterized in that Includes: An input module for inputting the optimized deep learning neural network engine into the on-board intelligent computing system; wherein, the on-board intelligent computing system at least includes a deep learning inference program; An address mapping relationship determination module for executing the deep learning inference program to create a deep learning inference process, loading the deep learning neural network engine into the target DRAM memory device, and using the kernel interface of the operating system to read the process page table, where the process page table represents the address mapping relationship between the initial virtual address in the deep learning inference process and the physical address in the target DRAM memory device; A memory active region determination module for determining the memory active region of the deep learning neural network engine in the virtual memory model based on the configurable DRAM standard file, DRAM mapping file, and the address mapping relationship; wherein, the virtual memory model is a model that simulates the target DRAM memory device; An error message injection position determination module, which is used to perform construction processing on the memory active area, construct an error injection space represented in the form of a bitmap tree, and determine an error message injection position in the error injection space according to the particle flip error model information recorded in the real radiation test and the Monte Carlo random algorithm; wherein, the particle flip error model information at least includes single particle flip error information and multi-particle flip error information; the error message injection position is the position where the single particle flip error information and the multi-particle flip error information are randomly injected into the error injection space represented in the form of a bitmap tree. A target virtual address determination module, which is used to perform reverse translation processing on the physical address in the virtual memory model based on the address mapping relationship and the error message injection position, and determine the target virtual address of the deep learning inference process.

8. An emulator, comprising a memory, a processor, and a computer program stored on the memory and running on the processor, characterized in that, When the processor executes the program, it implements the memory error simulation method based on the on-board intelligent computing system according to any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the memory error simulation method based on the on-board intelligent computing system according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the memory error simulation method based on the on-board intelligent computing system according to any one of claims 1 to 6.

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