Hardware schematic diagram generation method, electronic equipment and storage medium

Abstract

The invention provides a hardware schematic diagram generation method, electronic equipment and a storage medium, and the method comprises the steps: firstly obtaining a hardware scheme block diagram, extracting block diagram elements in the hardware scheme block diagram through a pre-trained hardware scheme block diagram processing model, and obtaining target block diagram elements corresponding to the hardware scheme block diagram, generating a hardware schematic diagram code file corresponding to the hardware scheme block diagram according to the target block diagram element, and displaying a hardware schematic diagram corresponding to the hardware schematic diagram code file through a hardware schematic diagram drawing tool. According to the method, the hardware schematic diagram can be automatically generated and displayed, so that a hardware designer does not need to manually draw in a hardware schematic diagram drawing tool according to a hardware scheme block diagram, the time cost and the labor cost for drawing the hardware schematic diagram can be saved, and the drawing efficiency of the hardware schematic diagram can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to, but are not limited to, the field of computer technology, and in particular to a method for generating a hardware schematic diagram, an electronic device, and a storage medium. Background Art

[0002] Schematic drawing technology in the hardware design stage is an important part of the field of electronics and electrical engineering. With the continuous development of science and technology, hardware schematic drawing technology has developed rapidly from the initial paper drawings to digital design. At present, due to the complexity and professionalism of hardware schematics, hardware designers are generally required to refer to the hardware solution block diagram and draw it manually on the Electronic Design Automation (EDA) tool. However, this design method requires a lot of time and manpower, resulting in low drawing efficiency. Therefore, how to improve the drawing efficiency of hardware schematics is a technical problem that needs to be solved urgently. Summary of the invention

[0003] The embodiments of the present application provide a hardware schematic diagram generation method, an electronic device, and a storage medium, which are intended to save the time and labor costs of drawing a hardware schematic diagram, thereby improving the drawing efficiency of the hardware schematic diagram.

[0004] On the one hand, an embodiment of the present application provides a method for generating a hardware schematic diagram, including: obtaining a hardware solution block diagram, extracting block diagram elements in the hardware solution block diagram through a pre-trained hardware solution block diagram processing model, and obtaining a target block diagram element corresponding to the hardware solution block diagram; generating a hardware schematic code file corresponding to the hardware solution block diagram according to the target block diagram element; and displaying the hardware schematic corresponding to the hardware schematic code file through a hardware schematic drawing tool.

[0005] On the other hand, an embodiment of the present application also provides an electronic device, comprising: at least one processor; at least one memory for storing at least one program; at least one of the programs is run by at least one of the processors to execute the hardware schematic generation method as described above.

[0006] On the other hand, an embodiment of the present application further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are used to execute the hardware schematic diagram generating method as described above.

[0007] On the other hand, an embodiment of the present application further provides a computer program product, including a computer program or computer instructions, where the computer program or the computer instructions are stored in a computer-readable storage medium, and a processor of an electronic device reads the computer program or the computer instructions from the computer-readable storage medium and executes the computer program or the computer instructions, so that the electronic device executes the hardware schematic diagram generation method as described above.

[0008] In an embodiment of the present application, first, a hardware solution block diagram is obtained, then block diagram elements in the hardware solution block diagram are extracted through a pre-trained hardware solution block diagram processing model to obtain target block diagram elements corresponding to the hardware solution block diagram, and then a hardware schematic diagram code file corresponding to the hardware solution block diagram is generated according to the target block diagram elements, and a hardware schematic diagram corresponding to the hardware schematic diagram code file is displayed through a hardware schematic diagram drawing tool. In this way, the generation of the hardware schematic diagram can be automatically executed, and it is not necessary for hardware designers to manually draw in the hardware schematic diagram drawing tool according to the hardware solution block diagram, thereby saving the time cost and labor cost for drawing the hardware schematic diagram, and further improving the drawing efficiency of the hardware schematic diagram. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a flowchart of a hardware schematic diagram generation method provided by an embodiment of the present application;

[0010] Figure 2 is a flowchart of block diagram element extraction for a hardware solution block diagram provided by an embodiment of the present application;

[0011] Figure 3 is a flowchart of the training process of a hardware solution block diagram processing model provided by an embodiment of the present application;

[0012] Figure 4 is a schematic diagram of a hardware solution block diagram provided by an embodiment of the present application;

[0013] Figure 5 is a schematic diagram of a hardware solution block diagram sample provided by an embodiment of the present application;

[0014] Figure 6 is a schematic diagram of a hardware schematic diagram provided by an embodiment of the present application;

[0015] Figure 7 is a schematic diagram of the method flow of a hardware schematic diagram generation method provided by an embodiment of the present application;

[0016] Figure 8 is a schematic diagram of the method flow for training a hardware solution block diagram processing model provided by an embodiment of the present application;

[0017] Figure 9 It is a schematic flowchart of a method for generating a sample of a hardware solution block diagram provided by an embodiment of the present application;

[0018] Figure 10 It is a schematic flowchart of a method for generating a model training sample provided by an embodiment of the present application;

[0019] Figure 11 It is a schematic flowchart of a method for a hardware solution block diagram processing model to extract block diagram elements multiple times provided by an embodiment of the present application;

[0020] Figure 12 It is a schematic diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0021] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0022] It should be noted that although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order from that in the flowchart. In the description of the specification, claims and the above accompanying drawings, the meaning of multiple (or plural) is more than two, and understandings such as greater than, less than, exceeding, etc. do not include the present number, and understandings such as above, below, within, etc. include the present number. If there is a description of "first", "second", etc., it is only for the purpose of distinguishing technical features and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0023] Due to the complexity and professionalism of the hardware schematic diagram, currently when drawing the hardware schematic diagram, generally hardware designers need to manually draw on the EDA tool with reference to the hardware solution block diagram. When the hardware designers perform manual drawing, they not only need to compare the hardware schematic diagram with the hardware solution block diagram to ensure that the drawn hardware schematic diagram is correct, but also need to ensure that the drawn hardware schematic diagram complies with the hardware design rules. Therefore, this design method requires a lot of time and manpower, resulting in low drawing efficiency.

[0024] In order to improve the drawing efficiency of the hardware schematic diagram, an embodiment of the present application provides a method for generating a hardware schematic diagram, an electronic device, a computer-readable storage medium, and a computer program product. The method first obtains a hardware solution block diagram, and then extracts the block diagram elements in the hardware solution block diagram through a pre-trained hardware solution block diagram processing model to obtain the target block diagram elements corresponding to the hardware solution block diagram. Then, a hardware schematic diagram code file corresponding to the hardware solution block diagram is generated according to the target block diagram elements, and the hardware schematic diagram corresponding to the hardware schematic diagram code file is displayed through a hardware schematic diagram drawing tool. In this way, the generation of the hardware schematic diagram can be automatically executed, and there is no need for hardware designers to manually draw in the hardware schematic diagram drawing tool, thereby saving the time cost and labor cost for drawing the hardware schematic diagram, and further improving the drawing efficiency of the hardware schematic diagram.

[0025] Based on the above analysis, the embodiments of the present application will be further described below with reference to the accompanying drawings.

[0026] Refer to Figure 1 as shown Figure 1 is a flowchart of a method for generating a hardware schematic diagram provided by an embodiment of the present application. The method can be executed by a user terminal, or can be executed in cooperation with a server by the user terminal, and no specific limitation is made here. The method may include, but is not limited to, the following steps S110 to step S130.

[0027] Step S110: Obtain a hardware solution block diagram, extract the block diagram elements in the hardware solution block diagram through a pre-trained hardware solution block diagram processing model, and obtain the target block diagram elements corresponding to the hardware solution block diagram;

[0028] Step S120: Generate a hardware schematic diagram code file corresponding to the hardware solution block diagram according to the target block diagram elements;

[0029] Step S130: Display the hardware schematic diagram corresponding to the hardware schematic diagram code file through a hardware schematic diagram drawing tool.

[0030] In some embodiments, the user terminal may be installed with a hardware schematic diagram drawing tool, and the hardware schematic diagram can be drawn through the hardware schematic diagram drawing tool. The hardware solution block diagram processing model may be a function plug-in of the hardware schematic diagram drawing tool, and the hardware solution block diagram processing model can be run by running this function plug-in to extract the block diagram elements in the hardware solution block diagram. In addition, the hardware solution block diagram processing model may also be an external plug-in model, and the hardware solution block diagram processing model can be run by calling this external plug-in model to extract the block diagram elements in the hardware solution block diagram.

[0031] It should be noted that the hardware schematic diagram drawing tool in the embodiments of the present application is an EDA tool, such as Cadence Concept HDL, etc., and the embodiments of the present application do not make specific limitations thereto. When the user imports the hardware schematic block diagram into the hardware schematic diagram drawing tool, the user terminal can respond to the import operation, extract the block diagram elements in the hardware schematic block diagram through a pre-trained hardware schematic block diagram processing model (running the corresponding function plug-in or calling the corresponding external model) to obtain the target block diagram elements corresponding to the hardware schematic block diagram, and then generate a hardware schematic code file corresponding to the hardware schematic block diagram according to the extracted target block diagram elements. Then, the hardware schematic code file can be opened through the hardware schematic diagram drawing tool to display the hardware schematic diagram corresponding to the hardware schematic code file. In this way, the automatic drawing of the hardware schematic diagram is realized, saving the time cost and labor cost for drawing the hardware schematic diagram, thereby improving the drawing efficiency of the hardware schematic diagram. Among them, when displaying the hardware schematic diagram corresponding to the hardware schematic code file through the hardware schematic diagram drawing tool, after generating the hardware schematic code file corresponding to the hardware schematic block diagram, the corresponding hardware schematic diagram can be automatically generated according to the hardware schematic code file, and the hardware schematic diagram can be displayed in the hardware schematic diagram drawing tool; or, after generating the hardware schematic code file corresponding to the hardware schematic block diagram, it can be detected whether the user has triggered the schematic diagram opening control in the hardware schematic diagram drawing tool. When it is detected that the user has triggered the schematic diagram opening control in the hardware schematic diagram drawing tool, the user terminal will display the hardware schematic diagram corresponding to the hardware schematic code file in the hardware schematic diagram drawing tool.

[0032] In some embodiments, the user terminal may include but is not limited to intelligent devices such as smart phones, tablets, desktop computers, laptops, in-vehicle terminals, etc., and the present embodiment does not make specific limitations thereto.

[0033] It should be noted that the hardware schematic block diagram is a graphical tool in hardware design, used to show the structure of the entire hardware system and the relationships between various modules. Through the hardware schematic block diagram, the overall architecture of the hardware system, the connection methods between various modules, and the path of the data flow can be intuitively understood. Based on the hardware schematic block diagram, an accurate hardware schematic diagram that meets the design requirements can be drawn, which is beneficial to the subsequent correct production of printed circuit boards.

[0034] In some embodiments, the hardware schematic drawing tool installed on the user terminal may itself have a hardware schematic generation function capable of implementing the hardware schematic generation method of this embodiment, or may support the hardware schematic generation function by installing a function plug-in capable of implementing the hardware schematic generation method of this embodiment, or may support the hardware schematic generation function by mounting an external model capable of implementing the hardware schematic generation method of this embodiment. In this way, after the user imports the hardware solution block diagram into the hardware schematic drawing tool, the hardware schematic drawing tool can call its own capabilities, or call the function plug-in, or call the external model to implement the hardware schematic generation method of this embodiment.

[0035] In some embodiments, the hardware schematic drawing tool may itself be deployed with a pre-trained hardware solution block diagram processing model, or the function plug-in installed in it may be deployed with a pre-trained hardware solution block diagram processing model, or the external model it mounts is a pre-trained hardware solution block diagram processing model. In this way, after the user imports the hardware solution block diagram into the hardware schematic drawing tool, the hardware schematic drawing tool can call the hardware solution block diagram processing model deployed in itself, or call the hardware solution block diagram processing model in the function plug-in, or call the mounted hardware solution block diagram processing model to extract the block elements in the hardware solution block diagram. It should be noted that the hardware solution block diagram processing model can be a large multi-modal model (LMM). A large multi-modal model is a model based on the Transformer structure with a parameter quantity exceeding hundreds of millions, which can not only support two or more modalities as input or output, but also have a generation ability.

[0036] In some embodiments, the hardware schematic drawing tool itself may not be deployed with a hardware solution block diagram processing model, and the function plug-in installed in the hardware schematic drawing tool may also not be deployed with a hardware solution block diagram processing model. In this case, after the user imports the hardware solution block diagram into the hardware schematic drawing tool, the user terminal can respond to the import operation and call the hardware solution block diagram processing model deployed on the server through the hardware schematic drawing tool to extract the block elements in the hardware solution block diagram, or call the hardware solution block diagram processing model deployed on the server through the function plug-in to extract the block elements in the hardware solution block diagram.

[0037] In some embodiments, the block diagram elements of the hardware schematic diagram block can include various key information for drawing the hardware schematic diagram, such as standard module device types, standard module device names, connection line function names, frequency values, etc. After the target block diagram elements corresponding to the hardware schematic diagram block are obtained by extracting the block diagram elements in the hardware schematic diagram block through a pre-trained hardware schematic diagram block processing model, these target block diagram elements can be converted into a specific data format (such as a JSON array, etc.) and saved in the database of the hardware schematic diagram drawing tool. Then, the hardware schematic diagram drawing tool can map these target block diagram elements converted into a specific data format into the underlying code of the hardware schematic diagram, obtain the corresponding hardware schematic diagram code file, and generate the hardware schematic diagram corresponding to the hardware schematic diagram block based on this hardware schematic diagram code file. Through this method, the generation of the hardware schematic diagram can be automatically executed, saving the time cost and labor cost for drawing the hardware schematic diagram, thereby improving the drawing efficiency of the hardware schematic diagram.

[0038] In some embodiments, after the hardware schematic diagram drawing tool generates the hardware schematic diagram corresponding to the hardware schematic diagram block based on this hardware schematic diagram code file, it can remind the hardware designer that the automatic drawing of the hardware schematic diagram has been completed by means of a floating window or a pop-up window, etc., or it can also not remind the hardware designer. When the hardware designer triggers the schematic diagram opening control in the hardware schematic diagram drawing tool, the hardware schematic diagram drawing tool will display the hardware schematic diagram corresponding to the generated hardware schematic diagram block. In this way, the hardware designer can directly see the hardware schematic diagram corresponding to the hardware schematic diagram block in the hardware schematic diagram drawing tool. Since the entire process does not require the hardware designer to manually draw the hardware schematic diagram, it can effectively save the time cost and labor cost for drawing the hardware schematic diagram, thereby improving the drawing efficiency of the hardware schematic diagram.

[0039] Through the hardware schematic diagram generation method of the above steps S110 to S130, first obtain the hardware schematic diagram block, then extract the block diagram elements in the hardware schematic diagram block through a pre-trained hardware schematic diagram block processing model to obtain the target block diagram elements corresponding to the hardware schematic diagram block, then generate the hardware schematic diagram code file corresponding to the hardware schematic diagram block according to the target block diagram elements, and display the hardware schematic diagram corresponding to the hardware schematic diagram code file through the hardware schematic diagram drawing tool. In this way, the generation of the hardware schematic diagram can be automatically executed, without the hardware designer manually drawing in the hardware schematic diagram drawing tool according to the hardware schematic diagram block, thereby saving the time cost and labor cost for drawing the hardware schematic diagram, and further improving the drawing efficiency of the hardware schematic diagram.

[0040] In some embodiments, referring to Figure 2As shown, the process of extracting block diagram elements from a hardware solution block diagram through a pre-trained hardware solution block diagram processing model to obtain target block diagram elements corresponding to the hardware solution block diagram may include, but is not limited to, the following steps S210 to S220.

[0041] Step S210: Generate a block diagram element extraction thought chain for the hardware solution block diagram through a pre-trained hardware solution block diagram processing model to obtain the block diagram element extraction thought chain information of the hardware solution block diagram;

[0042] Step S220: Extract block diagram elements from the hardware solution block diagram according to the block diagram element extraction thought chain information to obtain target block diagram elements.

[0043] In some embodiments, after inputting the hardware solution block diagram into the hardware solution block diagram processing model, the hardware solution block diagram processing model may generate a block diagram element extraction thought chain for the hardware solution block diagram to obtain the block diagram element extraction thought chain information of the hardware solution block diagram. Among them, the block diagram element extraction thought chain information refers to the content of the intermediate step-by-step reasoning steps explicitly output by the hardware solution block diagram processing model before outputting the final answer (i.e., the target block diagram elements of the hardware solution block diagram). This block diagram element extraction thought chain information can enhance the arithmetic, common sense, and reasoning abilities of the hardware solution block diagram processing model. After the hardware solution block diagram processing model obtains the block diagram element extraction thought chain information of the hardware solution block diagram, it can extract the block diagram elements in the hardware solution block diagram according to the block diagram element extraction thought chain information to obtain the target block diagram elements of the hardware solution block diagram. Since the block diagram element extraction thought chain information can improve the reasoning ability and problem-solving ability of the hardware solution block diagram processing model, more accurate target block diagram elements of the hardware solution block diagram can be obtained, which is beneficial to generating a more accurate hardware schematic diagram in subsequent steps.

[0044] In some embodiments, when the hardware solution block diagram processing model extracts the block diagram elements in the hardware solution block diagram according to the block diagram element extraction thought chain information, it may output the corresponding standard module device information and the association relationships between different standard module devices in the form of device grouping in sequence. Grouping by device essentially simulates the process of a hardware design expert's understanding of diagrams. Compared with randomly outputting the complex connection relationships between various standard module devices, outputting in the form of device grouping can effectively reduce the hallucinations generated by the hardware solution block diagram processing model during the recognition process, thereby reducing the false alarm rate and missed alarm rate of the hardware solution block diagram processing model.

[0045] In some embodiments, after obtaining the target block diagram elements of the hardware block diagram, the hardware block diagram processing model can convert the target block diagram elements of the hardware block diagram into structured data for output. Converting the target block diagram elements of the hardware block diagram into structured data for output can provide a unified processing specification for the subsequent generation of hardware schematic code files.

[0046] In some embodiments, referring to Figure 3 As shown, before extracting the block diagram elements in the hardware block diagram through a pre-trained hardware block diagram processing model, the hardware schematic generation method may further include, but is not limited to, the following steps S310 to S330.

[0047] Step S310: Obtain model training samples, where the model training samples include hardware block diagram samples, block diagram element samples of the hardware block diagram samples, auxiliary description information samples of the hardware block diagram samples, and block diagram element extraction thought chain samples for the hardware block diagram samples;

[0048] Step S320: Use the initial hardware block diagram processing model to extract information from the hardware block diagram samples according to the auxiliary description information samples, and obtain the block diagram element extraction results of the hardware block diagram samples and the corresponding extraction thought chains of the block diagram element extraction results;

[0049] Step S330: According to the block diagram element extraction results, the extraction thought chains, the block diagram element samples, and the block diagram element extraction thought chain samples, correct the model parameters of the initial hardware block diagram processing model to obtain the hardware block diagram processing model.

[0050] In some embodiments, the auxiliary description information sample of the hardware block diagram sample refers to the abstract summary of the hardware block diagram sample.

[0051] In some embodiments, before extracting block diagram elements in the hardware block diagram through the hardware block diagram processing model, it is necessary to first train the hardware block diagram processing model through steps S310 to S330. Before training the hardware block diagram processing model, the required model training samples can be obtained first. The model training samples can include hardware block diagram samples, block diagram element samples of the hardware block diagram samples, auxiliary description information samples of the hardware block diagram samples, and block diagram element extraction thought chain samples for the hardware block diagram samples. After obtaining the required model training samples, first obtain the initial hardware block diagram processing model, and then use the initial hardware block diagram processing model to extract information from the hardware block diagram samples according to the auxiliary description information samples to obtain the block diagram element extraction results of the hardware block diagram samples and the extraction thought chains corresponding to the block diagram element extraction results. Then, according to the extracted block diagram element extraction results and the extraction thought chains corresponding to the block diagram element extraction results, combined with the block diagram element samples and the block diagram element extraction thought chain samples in the model training samples, the model parameters of the initial hardware block diagram processing model are corrected to obtain the hardware block diagram processing model. In this way, the finally obtained hardware block diagram processing model can have the ability to extract block diagram elements from the hardware block diagram and the ability to output the corresponding thought chain.

[0052] In some embodiments, when correcting the model parameters of the initial hardware block diagram processing model according to the block diagram element extraction results, extraction thought chains, block diagram element samples, and block diagram element extraction thought chain samples, the block diagram element loss value can be calculated first according to the block diagram element extraction results and the block diagram element samples, and the thought chain loss value can be calculated according to the extraction thought chains and the block diagram element extraction thought chain samples. Then, the total loss value is determined according to the block diagram element loss value and the thought chain loss value. Next, the model parameters of the initial hardware block diagram processing model are corrected according to the total loss value until both the block diagram element loss value and the thought chain loss value are less than the preset loss value threshold, or until the number of training times of the initial hardware block diagram processing model reaches the preset number threshold. At this time, the trained hardware block diagram processing model can be obtained. It should be noted that the preset loss value threshold and the preset number threshold can be appropriately selected according to the actual application situation and are not specifically limited here.

[0053] High-quality multi-modal training samples are the key to effectively injecting knowledge into the hardware schematic diagram processing model. However, due to the professionalism and confidentiality of hardware schematic diagrams, neither the industry open-source community nor within enterprises has accumulated a scale of hardware schematic diagram samples that remotely meets the quantity requirements for training the hardware schematic diagram processing model. It has been verified that the accuracy of a general multi-modal large model (such as the InternVL2-8B model) without fine-tuning training is less than 5% in the task of generating hardware schematic diagrams. Therefore, obtaining high-quality training samples has become an important stage for effectively training the hardware schematic diagram processing model. To achieve this goal, in one embodiment of this application, a method for obtaining hardware schematic diagram samples for training the hardware schematic diagram processing model is proposed. In some embodiments, the hardware schematic diagram samples can be obtained through the following steps: First, obtain multiple block diagram element instances, and then generate each block diagram sample in the hardware schematic diagram samples respectively according to at least some of the block diagram element instances among the multiple block diagram element instances, and determine at least some of the block diagram element instances that generate each block diagram sample as the block diagram element samples corresponding to the respective block diagram samples. Among them, the block diagram element samples of the hardware schematic diagram samples include block diagram element samples that correspond one-to-one to each block diagram sample in the hardware schematic diagram samples. In a feasible implementation manner, the block diagram element instances can be obtained according to historical hardware schematic diagrams, or can be obtained according to existing hardware schematic diagrams publicly available on the network. This embodiment does not make specific limitations in this regard. For example, when obtaining block diagram element instances according to historical hardware schematic diagrams, the metadata of the historical hardware schematic diagrams can be obtained first, and then multiple block diagram element instances can be obtained from a preset block diagram element resource pool according to this metadata. Among them, the metadata of the historical hardware schematic diagrams refers to the overall description information of the block diagram elements in the historical hardware schematic diagrams. This overall description information includes, for example, how many block diagram elements are in the historical hardware schematic diagrams, how many connection lines are there between two block diagram elements, and other contents. After obtaining the metadata of the historical hardware schematic diagrams, the specific style, element layout, and other information of the hardware schematic diagram samples can be determined. Then, according to the specific style, element layout, and other information of the hardware schematic diagram samples, the corresponding multiple block diagram element instances can be obtained from the preset block diagram element resource pool, so that in subsequent steps, the corresponding hardware schematic diagram samples can be generated according to these block diagram element instances. By obtaining block diagram element instances according to historical hardware schematic diagrams or existing hardware schematic diagrams publicly available on the network, the authenticity of the block diagram element instances can be guaranteed, thereby ensuring the accuracy of the hardware schematic diagram samples generated according to the block diagram element instances, which is beneficial to the effective training of the subsequent hardware schematic diagram processing model.

[0054] In some embodiments, to increase the diversity of hardware block diagram samples, metadata of historical hardware block diagrams or existing hardware block diagrams publicly available on the network may be obtained first, and then multiple first element instances may be obtained from a preset block diagram element resource pool according to the metadata. Then, data augmentation is performed on the multiple first element instances to obtain multiple second element instances. Next, multiple block diagram element instances are obtained based on the multiple first element instances and the multiple second element instances. Among them, when performing data augmentation on the multiple first element instances to obtain multiple second element instances, the standard module device names, frequency values, etc. of the multiple first element instances may be adjusted according to preset standard naming rules, numerical rules, etc., so as to expand and obtain multiple second element instances. For example, assuming that the frequency value of a certain first element instance is 10 MHz, then this frequency value can be adjusted to 100 MHz to obtain a second element instance with a frequency value of 100 MHz.

[0055] In some embodiments, when generating each block diagram sample in the hardware block diagram samples respectively according to at least some of the multiple block diagram element instances, each block diagram sample in the hardware block diagram samples may be generated by a target drawing script according to at least some of the multiple block diagram element instances, which can improve the generation efficiency of the hardware block diagram samples.

[0056] In some embodiments, when generating each block diagram sample in the hardware block diagram samples respectively according to at least some of the multiple block diagram element instances, N first block diagram samples may be generated according to the multiple block diagram element instances by an initial block diagram drawing script first; in response to the number of first block diagram samples that meet the preset sample requirements among the N first block diagram samples being less than a first threshold, the initial block diagram drawing script is adjusted, and the adjusted block diagram drawing script is determined as the initial block diagram drawing script, and then it is transferred to the step of generating N first block diagram samples according to the multiple block diagram element instances by the initial block diagram drawing script; in response to the number of first block diagram samples that meet the preset sample requirements among the N first block diagram samples being greater than or equal to the first threshold, the initial block diagram drawing script corresponding to when the number of first block diagram samples that meet the preset sample requirements is greater than or equal to the first threshold is determined as the target drawing script, and each block diagram sample in the hardware block diagram samples is generated by the target drawing script according to at least some of the multiple block diagram element instances. In this way, the correctness of the generated hardware block diagram samples can be ensured. Among them, the number of block diagram samples is M, and M is greater than N.

[0057] It should be noted that the first threshold is the minimum required number of the first block diagram samples that meet the preset sample requirements. The specific value of the first threshold can be appropriately selected according to actual application requirements. For example, the value of the first threshold can be N * 90%. In this case, if the number of the first block diagram samples that meet the preset sample requirements is less than N * 90%, it indicates that none of the N generated first block diagram samples meet the preset sample requirements. At this time, the initial block diagram drawing script needs to be adjusted. If the number of the first block diagram samples that meet the preset sample requirements is greater than or equal to N * 90%, it indicates that all N generated first block diagram samples meet the preset sample requirements. At this time, the initial block diagram drawing script corresponding to when the number of the first block diagram samples that meet the preset sample requirements is greater than or equal to the first threshold can be determined as the target drawing script.

[0058] As shown in the Figure 4 reference, the hardware solution block diagram is essentially a directed graph. Therefore, the hardware solution block diagram samples are also in the format of directed graphs. So, according to the format requirements of the preset directed graph, N first block diagram samples can be generated based on multiple block diagram element instances. For example Figure 4 as shown, according to the format requirements of the preset directed graph, the first block diagram samples shown in Figure 4 can be generated based on these block diagram element instances such as "temp l ate1", "temp late2", "temp l ate3", "5M+ / -", and "10M+ / -".

[0059] In some embodiments, a script for simulating manual drawing of the hardware solution block diagram (i.e., the initial block diagram drawing script) can be developed based on tools such as Graphviz or Mermaid, and N first block diagram samples can be generated by this script according to multiple block diagram element instances. Among them, Graphviz is an open-source graph visualization tool suitable for drawing structured icons and networks. Mermaid is a chart drawing tool based on Javascr ipt and can be used to create flowcharts, sequence diagrams, Gantt charts, class diagrams, state diagrams, pie charts, etc.

[0060] In some embodiments, meeting the preset sample requirements may include at least one of the following situations:

[0061] (1) The block diagram styles between the first block diagram sample and the preset reference block diagram match;

[0062] (2) The element types between the first block diagram sample and the preset reference block diagram match.

[0063] Among them, the preset reference block diagram refers to a pre-set hardware solution block diagram used as a reference. The block diagram style refers to the layout shape of the overall block diagram elements of the hardware solution block diagram. The element types include the element types, element names, element quantities, etc. in the hardware solution block diagram. When the block diagram style between the first block diagram sample and the preset reference block diagram matches, or the element types between the first block diagram sample and the preset reference block diagram match, or both the block diagram style and the element types between the first block diagram sample and the preset reference block diagram match, then it can be determined that this first block diagram sample meets the preset sample requirements. When the number of first block diagram samples that meet the preset sample requirements among the determined first block diagram samples is greater than or equal to the first threshold, it can be considered that the first block diagram samples generated according to the current initial block diagram drawing script are all qualified hardware solution block diagram samples. At this time, the current initial block diagram drawing script can be determined as the target drawing script, and further, hardware solution block diagram samples can be generated according to multiple block diagram element instances through this target drawing script, so as to effectively expand the number of hardware solution block diagram samples, facilitating obtaining sufficient hardware solution block diagram samples to train the hardware solution block diagram processing model.

[0064] In some embodiments, after generating N first block diagram samples, if the number of first block diagram samples that meet the preset sample requirements among these N first block diagram samples is less than the first threshold, it indicates that the first block diagram samples generated according to the current initial block diagram drawing script do not meet the requirements. At this time, the current initial block diagram drawing script can be adjusted, and the adjusted block diagram drawing script can be determined as the initial block diagram drawing script, and then the step of generating N first block diagram samples according to multiple block diagram element instances through the initial block diagram drawing script is continued until the number of first block diagram samples that meet the preset sample requirements among the N first block diagram samples is greater than or equal to the first threshold. In this way, it can be ensured that the finally obtained hardware solution block diagram samples can all be used to train the hardware solution block diagram processing model.

[0065] In some embodiments, after generating hardware solution block diagram samples according to multiple block diagram element instances through the target drawing script, these hardware solution block diagram samples may include, for example, block diagram samples with abnormal resolutions such as too large aspect ratios. These block diagram samples with abnormal resolutions will affect the training effect of the hardware solution block diagram processing model. Therefore, when generating hardware solution block diagram samples according to multiple block diagram element instances through the target drawing script, multiple candidate block diagram samples can be generated according to multiple block diagram element instances through the target drawing script first, and then sample cleaning is performed on the multiple candidate block diagram samples to eliminate block diagram samples with abnormal resolutions such as too large aspect ratios, so as to obtain qualified hardware solution block diagram samples. For example Figure 5 as shown Figure 5An exemplary block diagram sample of a hardware solution that meets the requirements is given. Using this block diagram sample of the hardware solution that meets the requirements, the hardware block diagram processing model can be effectively trained, so that the trained hardware block diagram processing model can have good block element extraction ability.

[0066] In some embodiments, after obtaining the hardware block diagram sample, a block element extraction thought chain sample in the model training sample of the hardware block diagram processing model can be further obtained based on the hardware block diagram sample. Specifically, the auxiliary description information sample of the hardware block diagram sample can be obtained first, and then the thought chain generation model is called. According to the hardware block diagram sample, the block element sample, and the auxiliary description information sample, a block element extraction thought chain sample of the hardware block diagram sample for extracting the block element sample of the hardware block diagram sample from the hardware block diagram sample is generated. Then, according to the hardware block diagram sample, the auxiliary description information sample of the hardware block diagram sample, the block element sample of the hardware block diagram sample, and the block element extraction thought chain sample of the hardware block diagram sample, the model training sample is obtained. In an alternative implementation, the auxiliary description information sample of the hardware block diagram sample can be formed by summarizing the composition structure of the hardware block diagram sample and the process of a hardware design expert identifying the diagram. The auxiliary description information sample of the hardware block diagram sample can make the implicit expert knowledge in the hardware R & D field explicit, which helps the thought chain generation model understand and generate the corresponding block element extraction thought chain sample. In addition, the generated block element extraction thought chain sample can focus on the multi-modal reasoning details in each different scenario, with richer diversity, and the generated model training sample is more consistent with the output probability distribution of the hardware block diagram processing model, which helps to improve the multi-modal knowledge injection effect during the subsequent fine-tuning training of the hardware block diagram processing model.

[0067] It should be noted that the thought chain generation model can adopt a conventional general multi-modal large model or other types of general large models. This embodiment does not make specific limitations on this, as long as these general large models have the ability to generate a block element extraction thought chain for extracting block elements from the hardware block diagram sample according to the hardware block diagram sample, the block element sample, and the auxiliary description information sample. After obtaining the model training sample through the above method, using this model training sample to train the hardware block diagram processing model can enable the hardware block diagram processing model to have the ability to recognize the meaning represented by each graphic and connection line in the hardware block diagram, the hardware parameters referred to by the text in the graphic and the text on the connection line, and the ability to recognize the strategy of the source end, sink end, and corresponding connection lines from the hardware block diagram.

[0068] In some embodiments, after generating the block diagram element extraction thought chain sample of the hardware solution block diagram sample, in the process of obtaining the model training sample based on the hardware solution block diagram sample, the auxiliary description information sample of the hardware solution block diagram sample, the block diagram element sample of the hardware solution block diagram sample, and the block diagram element extraction thought chain sample of the hardware solution block diagram sample, the hardware solution block diagram sample and the auxiliary description information sample of the hardware solution block diagram sample can be used as query information, and the block diagram element sample of the hardware solution block diagram sample and the block diagram element extraction thought chain sample of the hardware solution block diagram sample can be used as answer information, so as to obtain the model training sample of the hardware solution block diagram processing model.

[0069] In some embodiments, when extracting the block diagram elements in the hardware solution block diagram through the pre-trained hardware solution block diagram processing model to obtain the target block diagram elements corresponding to the hardware solution block diagram, due to the inevitable hallucination problem in the reasoning of the hardware solution block diagram processing model, the result output by the hardware solution block diagram processing model may have a low adoption rate. To solve this problem, in the process of extracting the block diagram elements in the hardware solution block diagram through the pre-trained hardware solution block diagram processing model to obtain the target block diagram elements corresponding to the hardware solution block diagram, the block diagram elements in the hardware solution block diagram can be extracted multiple times through the pre-trained hardware solution block diagram processing model to obtain multiple groups of candidate block diagram elements, and then the multiple groups of candidate block diagram elements are integrated to obtain the target block diagram elements corresponding to the hardware solution block diagram. In this way, the recall rate of the hardware solution block diagram processing model for block diagram element recognition can be effectively improved. Among them, in the process of extracting the block diagram elements in the hardware solution block diagram multiple times through the pre-trained hardware solution block diagram processing model, the block diagram elements in the hardware solution block diagram can be extracted multiple times through the hardware solution block diagram processing model according to the auxiliary description information of the same hardware solution block diagram, or the block diagram elements in the hardware solution block diagram can be extracted multiple times through the hardware solution block diagram processing model according to the auxiliary description information of different hardware solution block diagrams. This embodiment does not make specific limitations on this.

[0070] In some embodiments, when integrating multiple groups of candidate block diagram elements to obtain the target block diagram elements corresponding to the hardware solution block diagram, the intersection of these multiple groups of candidate block diagram elements can be taken to obtain the target block diagram elements corresponding to the hardware solution block diagram, or the union of these multiple groups of candidate block diagram elements can be taken to obtain the target block diagram elements corresponding to the hardware solution block diagram. This embodiment does not make specific limitations on this. For example, when taking the union of these multiple groups of candidate block diagram elements to obtain the target block diagram elements corresponding to the hardware solution block diagram, assuming that the connection line is the smallest unit, if the number of occurrences of a certain connection line extracted in the two output results of the hardware solution block diagram processing model is m and n respectively (where m≥n≥0), then m corresponding connection lines are retained in the output result after data integration.

[0071] In some embodiments, after the hardware solution block diagram processing model integrates data of multiple groups of candidate block diagram elements to obtain the target block diagram elements corresponding to the hardware solution block diagram, a preset mapping script can be called to convert the target block diagram elements after data integration into the final underlying hardware schematic code (i.e., the hardware schematic code file), so as to facilitate the subsequent generation of the hardware schematic of the hardware solution block diagram through the underlying hardware schematic code. It should be noted that the underlying schematic code is a paradigm code with clear syntax, so it can be directly and losslessly converted in a deterministic manner. For some detailed standard module devices, pin normalization information, etc., they can be automatically obtained by looking up tables.

[0072] In some embodiments, after generating the hardware schematic code file corresponding to the hardware solution block diagram according to the target block diagram elements, when a hardware designer triggers the schematic opening control in the hardware schematic drawing tool, the hardware schematic corresponding to the hardware schematic code file as shown in Figure 6 can be displayed in the hardware schematic drawing tool. If the hardware designer believes that the currently automatically generated hardware schematic does not meet the expectations, the hardware designer can perform corresponding operations in the hardware schematic drawing tool to update the hardware schematic. For example, the hardware designer can directly manually adjust the displayed hardware schematic in the hardware schematic drawing tool. At this time, the hardware schematic drawing tool can adjust the hardware schematic according to the drawing adjustment instructions input by the hardware designer. Or, the hardware designer can trigger the schematic correction control in the hardware schematic drawing tool, so that the hardware schematic drawing tool can correct the target block diagram elements through the hardware solution block diagram processing model to obtain the corrected block diagram elements, and then regenerate the hardware schematic code file corresponding to the hardware solution block diagram according to the corrected block diagram elements, and display the hardware schematic corresponding to the regenerated hardware schematic code file. Or, the hardware designer can trigger the schematic regeneration control in the hardware schematic drawing tool, so that the hardware schematic drawing tool can re-extract the block diagram elements in the hardware solution block diagram through the hardware solution block diagram processing model to obtain new target block diagram elements, and then regenerate the hardware schematic code file corresponding to the hardware solution block diagram according to the new target block diagram elements, and display the hardware schematic corresponding to the regenerated hardware schematic code file.

[0073] In some embodiments, after extracting the block diagram elements in the hardware solution block diagram through the hardware solution block diagram processing model to obtain the target block diagram elements corresponding to the hardware solution block diagram, the hardware solution block diagram processing model can also generate corresponding keyboard and mouse control instructions based on the extracted target block diagram elements. Then, the user terminal automatically executes the keyboard and mouse control instructions to simulate the operation of a hardware designer on a hardware schematic drawing tool, and draws the final hardware schematic diagram by means of dragging and the like.

[0074] The following is a detailed description of the hardware schematic diagram generation method provided by the present application in specific implementation manners.

[0075] Reference Figure 7 shown in Figure 7 is a schematic flowchart of a hardware schematic diagram generation method provided by an embodiment of the present application.

[0076] In Figure 7 , the method flow includes the following steps:

[0077] Step 701: A hardware designer imports a hardware solution block diagram into a hardware schematic drawing tool;

[0078] Step 702: The hardware schematic drawing tool in the user terminal extracts the block diagram elements in the hardware solution block diagram through a pre-trained hardware solution block diagram processing model to obtain the target block diagram elements corresponding to the hardware solution block diagram;

[0079] Step 703: The hardware schematic drawing tool in the user terminal maps the extracted target block diagram elements to the underlying code of the hardware schematic diagram;

[0080] Step 704: In response to the hardware designer triggering a schematic diagram opening control in the hardware schematic drawing tool, generate a hardware schematic diagram corresponding to the hardware solution block diagram according to the underlying code of the hardware schematic diagram, and display the hardware schematic diagram in the hardware schematic drawing tool;

[0081] Step 705: Detect whether the hardware designer has further operations. If not, execute Step 708; if so, execute Step 706;

[0082] Step 706: Determine whether the hardware designer triggered a schematic diagram correction control or a schematic diagram regeneration control. If the schematic diagram correction control is triggered, execute Step 707; if the schematic diagram regeneration control is triggered, execute Step 702;

[0083] Step 707: The hardware schematic drawing tool in the user terminal corrects the target block diagram elements through the hardware solution block diagram processing model to obtain the corrected block diagram elements, and then execute Step 703;

[0084] Step 708: End the process.

[0085] Reference Figure 8 as shown Figure 8 is a schematic flow chart of a method for training a hardware solution block diagram processing model provided by an embodiment of the present application. In Figure 8 it, the method flow includes the following steps:

[0086] Step 801: Batch generate high-quality hardware solution block diagram samples;

[0087] Step 802: Invoke the chain of thought generation model, and generate a block diagram element extraction chain of thought sample for obtaining the block diagram element sample from the hardware solution block diagram sample according to the hardware solution block diagram sample, its block diagram element sample, and auxiliary description information sample;

[0088] Step 803: Generate a model training sample for the hardware solution block diagram processing model according to the hardware solution block diagram sample, auxiliary description information sample, block diagram element sample, and block diagram element extraction chain of thought sample, and use the model training sample to train the hardware solution block diagram processing model;

[0089] Step 804: Evaluate the trained hardware solution block diagram processing model to obtain an evaluation result;

[0090] Step 805: Determine whether the evaluation result meets the requirements. If it meets the requirements, execute Step 807; if it does not meet the requirements, execute Step 806;

[0091] Step 806: Analyze and adjust the model training sample, and use the adjusted model training sample to retrain the hardware solution block diagram processing model, and then execute Step 804;

[0092] Step 807: End the process.

[0093] Reference Figure 9 as shown Figure 9 is a schematic flow chart of a method for generating a hardware solution block diagram sample provided by an embodiment of the present application. In Figure 9 it, the method flow includes the following steps:

[0094] Step 901: Obtain multiple block diagram element instances;

[0095] Step 902: Develop an initial block diagram drawing script based on block diagram element filling;

[0096] Step 903: Generate a small batch of hardware solution block diagram samples (i.e., N first block diagram samples) through the initial block diagram drawing script, and judge the matching of the small batch of hardware solution block diagram samples with a preset reference block diagram through a general multi-modal large model to obtain a matching judgment result;

[0097] Step 904: Determine whether the small batch hardware solution block diagram sample matches the preset reference block diagram according to the matching judgment result. If so, execute step 906; if not, execute step 905;

[0098] Step 905: adjust the initial block diagram drawing script to obtain a new initial block diagram drawing script, and then execute step 903;

[0099] Step 906: determine the current initial block diagram drawing script as the target drawing script, and generate a large number of hardware solution block diagram samples through the target drawing script;

[0100] Step 907: performing sample cleaning on all hardware solution block diagram samples to obtain final hardware solution block diagram samples;

[0101] Step 908: End the process.

[0102] refer to Figure 10 As shown, Figure 10 It is a flowchart of a method for generating model training samples provided by an embodiment of the present application.

[0103] exist Figure 10 The method flow includes the following steps:

[0104] Step 1001: Summarize the composition structure of the hardware solution block diagram sample and the drawing recognition process of the hardware designer, and generate an auxiliary description information sample of the hardware solution block diagram sample;

[0105] Step 1002: extracting block diagram elements from the hardware solution block diagram sample to obtain a block diagram element sample of the hardware solution block diagram sample;

[0106] Step 1003: calling the thinking chain generation model, and generating a block diagram element extraction thinking chain sample for extracting block diagram element samples from the hardware solution block diagram sample according to the hardware solution block diagram sample, the block diagram element sample and the auxiliary description information sample;

[0107] Step 1004: taking the hardware solution block diagram sample and the auxiliary description information sample as query information, and taking the block diagram element sample and the block diagram element extraction thinking chain sample as answer information, to obtain a model training sample;

[0108] Step 1005: End the process.

[0109] refer to Figure 11 As shown, Figure 11 This is a flowchart of a method for extracting block diagram elements multiple times using a hardware solution block diagram processing model provided by an embodiment of the present application. Figure 11 The method flow includes the following steps:

[0110] Step 1101: The hardware solution block diagram processing model generates a thinking chain for block diagram element extraction of the imported hardware solution block diagram to obtain the thinking chain information of block diagram element extraction of the hardware solution block diagram;

[0111] Step 1102: According to the thinking chain information of block diagram element extraction, extract the block diagram elements of the hardware solution block diagram to obtain the first block diagram elements of the hardware solution block diagram;

[0112] Step 1103: Convert the first block diagram elements of the hardware solution block diagram into the first structured data;

[0113] Step 1104: The hardware solution block diagram processing model uses another thinking method (corresponding to another block diagram element extraction thinking chain) to re-extract the block diagram elements of the hardware solution block diagram to obtain the second block diagram elements, and convert the second block diagram elements into the second structured data, and then perform data integration on the first structured data and the second structured data to obtain the target block diagram elements of the hardware solution block diagram;

[0114] Step 1105: End the process.

[0115] Through the above embodiments, when the hardware solution block diagram is imported into the hardware schematic drawing tool, first, the block diagram elements in the hardware solution block diagram are extracted by the pre-trained hardware solution block diagram processing model to obtain the target block diagram elements of the hardware solution block diagram, and then the hardware schematic code file corresponding to the hardware solution block diagram is generated according to the target block diagram elements, and then the corresponding hardware schematic is drawn according to the hardware schematic code file. In this way, the generation of the hardware schematic can be automatically executed. At this time, when the schematic opening control in the hardware schematic drawing tool is triggered, the hardware schematic can be displayed. Therefore, when it is necessary to draw the hardware schematic, through the method provided by the embodiments of the present application, it can enable hardware designers to avoid manually drawing in the hardware schematic drawing tool according to the hardware solution block diagram, thereby saving the time cost and labor cost of drawing the hardware schematic, and further improving the drawing efficiency of the hardware schematic.

[0116] In addition, as shown in Figure 12 An embodiment of the present application also discloses an electronic device. The electronic device 1200 includes at least one processor 1210; at least one memory 1220 for storing at least one program; when the at least one program is executed by the at least one processor 1210, it implements the hardware schematic generation method in any of the previous embodiments.

[0117] In addition, an embodiment of the present application also discloses a computer-readable storage medium storing computer-executable instructions for executing the hardware schematic generation method in any of the previous embodiments.

[0118] In addition, an embodiment of the present application also discloses a computer program product, including a computer program or computer instructions. The computer program or computer instructions are stored in a computer-readable storage medium. The processor of the electronic device reads the computer program or computer instructions from the computer-readable storage medium, and the processor executes the computer program or computer instructions, so that the electronic device executes the hardware schematic diagram generation method in any of the previous embodiments.

[0119] Those of ordinary skill in the art can understand that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and their appropriate combinations. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or can be implemented as hardware, or can be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include a computer storage medium (or non-transitory medium) and a communication medium (or transitory medium). As is well known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassette, tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, a communication medium typically contains computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and can include any information delivery medium.

[0120] The above is a specific description of the preferred embodiments of the present application, but the present application is not limited to the above embodiments. Those skilled in the art can make various equivalent deformations or substitutions without departing from the spirit of the present application, and these equivalent deformations or substitutions are all included within the scope defined by the claims of the present application.

Claims

1. A method for generating a hardware schematic diagram, comprising: Obtain a hardware solution block diagram, and extract block diagram elements in the hardware solution block diagram through a pre-trained hardware solution block diagram processing model to obtain target block diagram elements corresponding to the hardware solution block diagram; Generate a hardware schematic diagram code file corresponding to the hardware solution block diagram according to the target block diagram elements; Display a hardware schematic diagram corresponding to the hardware schematic diagram code file through a hardware schematic diagram drawing tool.

2. The method according to claim 1, wherein The step of extracting block diagram elements in the hardware solution block diagram through a pre-trained hardware solution block diagram processing model to obtain target block diagram elements corresponding to the hardware solution block diagram includes: Generate a block diagram element extraction thought chain of the hardware solution block diagram through a pre-trained hardware solution block diagram processing model to obtain block diagram element extraction thought chain information of the hardware solution block diagram; Extract block diagram elements from the hardware solution block diagram according to the block diagram element extraction thought chain information to obtain the target block diagram elements.

3. The method according to claim 1, wherein Before the step of extracting block diagram elements in the hardware solution block diagram through a pre-trained hardware solution block diagram processing model, the method further includes: Obtain model training samples, where the model training samples include hardware solution block diagram samples, block diagram element samples of the hardware solution block diagram samples, auxiliary description information samples of the hardware solution block diagram samples, and block diagram element extraction thought chain samples for the hardware solution block diagram samples. Among them, the auxiliary description information sample is a summary of the hardware solution block diagram sample; Extract information from the hardware solution block diagram samples through an initial hardware solution block diagram processing model according to the auxiliary description information samples to obtain block diagram element extraction results of the hardware solution block diagram samples and extraction thought chains corresponding to the block diagram element extraction results; Correct the model parameters of the initial hardware solution block diagram processing model according to the block diagram element extraction results, the extraction thought chains, the block diagram element samples, and the block diagram element extraction thought chain samples to obtain the hardware solution block diagram processing model.

4. The method according to claim 3, wherein The step of obtaining model training samples includes: Obtain multiple block diagram element instances; Generate each block diagram sample in the hardware solution block diagram samples respectively according to at least some of the multiple block diagram element instances, and determine the at least some block diagram element instances that generate each block diagram sample as block diagram element samples corresponding to the respective block diagram samples.

5. The method according to claim 4, characterized in that The step of generating each block diagram sample in the hardware solution block diagram samples respectively according to at least some of the multiple block diagram element instances includes: Generate each block diagram sample in the hardware solution block diagram samples respectively according to at least some of the multiple block diagram element instances through a target drawing script.

6. The method according to claim 4, wherein The step of generating each block diagram sample in the hardware solution block diagram samples respectively according to at least some of the multiple block diagram element instances includes: Generate N first block diagram samples according to the multiple block diagram element instances through an initial block diagram drawing script; In response to the number of the first block diagram samples that meet the preset sample requirements among the N first block diagram samples being less than the first threshold, adjust the initial block diagram drawing script, determine the adjusted block diagram drawing script as the initial block diagram drawing script, and go to the step of generating N first block diagram samples according to the multiple block diagram element instances by the initial block diagram drawing script; In response to the number of the first block diagram samples that meet the preset sample requirements among the N first block diagram samples being greater than or equal to the first threshold, determine the initial block diagram drawing script corresponding to when the number of the first block diagram samples that meet the preset sample requirements is greater than or equal to the first threshold as the target drawing script, and generate each block diagram sample in the hardware solution block diagram samples respectively according to at least some of the multiple block diagram element instances by the target drawing script, where the number of the block diagram samples is M, and M is greater than N.

7. The method according to claim 5 or 6, characterized in that The generating each block diagram sample in the hardware solution block diagram samples respectively according to at least some of the multiple block diagram element instances by the target drawing script includes: generating a plurality of candidate block diagram samples according to at least some of the multiple block diagram element instances by the target drawing script; performing sample cleaning on the plurality of candidate block diagram samples to obtain each block diagram sample in the hardware solution block diagram samples.

8. The method according to claim 6, characterized in that The meeting the preset sample requirements includes at least one of the following: the block diagram style between the first block diagram sample and the preset reference block diagram matches; the element types between the first block diagram sample and the preset reference block diagram match.

9. The method according to claim 4, wherein The obtaining a plurality of block diagram element instances includes at least one of the following: obtaining the metadata of the historical hardware solution block diagram, and obtaining a plurality of block diagram element instances in a preset block diagram element resource pool according to the metadata; obtaining the metadata of the historical hardware solution block diagram, obtaining a plurality of first element instances in a preset block diagram element resource pool according to the metadata, performing data augmentation on the plurality of first element instances to obtain a plurality of second element instances, and obtaining a plurality of block diagram element instances according to the plurality of first element instances and the plurality of second element instances.

10. The method according to claim 4, wherein The obtaining the model training samples further includes: obtaining the auxiliary description information samples of the hardware solution block diagram samples; invoking a thought chain generation model, and generating a thought chain sample for extracting the block diagram element samples of the hardware solution block diagram samples from the hardware solution block diagram samples according to the hardware solution block diagram samples, the block diagram element samples, and the auxiliary description information samples; obtaining the model training samples according to the hardware solution block diagram samples, the auxiliary description information samples of the hardware solution block diagram samples, the block diagram element samples of the hardware solution block diagram samples, and the thought chain sample for extracting the block diagram element samples of the hardware solution block diagram samples.

11. The method according to claim 1, wherein The extracting the target block diagram elements corresponding to the hardware solution block diagram by the pre-trained hardware solution block diagram processing model for the block diagram elements in the hardware solution block diagram includes: Extract the block diagram elements in the hardware block diagram multiple times through a pre-trained hardware block diagram processing model to obtain multiple groups of candidate block diagram elements; Integrate the data of multiple groups of the candidate block diagram elements to obtain the target block diagram elements corresponding to the hardware block diagram.

12. The method according to claim 11, wherein The extracting the block diagram elements in the hardware block diagram multiple times through a pre-trained hardware block diagram processing model includes one of the following: Extract the block diagram elements in the hardware block diagram multiple times through the hardware block diagram processing model according to the auxiliary description information of the same hardware block diagram; Extract the block diagram elements in the hardware block diagram multiple times through the hardware block diagram processing model according to the auxiliary description information of different hardware block diagrams.

13. The method according to claim 1, wherein The method further includes: In response to the displayed hardware schematic diagram not meeting the expectation, perform one of the following: Adjust the hardware schematic diagram according to the drawing adjustment instruction; Correct the target block diagram elements through the hardware block diagram processing model to obtain the corrected block diagram elements, and regenerate the hardware schematic diagram code file corresponding to the hardware block diagram according to the corrected block diagram elements, and display the hardware schematic diagram corresponding to the regenerated hardware schematic diagram code file; Extract the block diagram elements in the hardware block diagram again through the hardware block diagram processing model to obtain new target block diagram elements, regenerate the hardware schematic diagram code file corresponding to the hardware block diagram according to the new target block diagram elements, and display the hardware schematic diagram corresponding to the regenerated hardware schematic diagram code file.

14. An electronic device, comprising: At least one processor; At least one memory for storing at least one program; At least one of the programs is run by at least one of the processors to execute the hardware schematic diagram generation method according to any one of claims 1 to 13.

15. A computer-readable storage medium stores computer-executable instructions, characterized in that, The computer-executable instructions are used to execute the hardware schematic diagram generation method according to any one of claims 1 to 13.

16. A computer program product, comprising a computer program or computer instructions, characterized in that, The computer program or the computer instructions are stored in a computer-readable storage medium, and the processor of the electronic device reads the computer program or the computer instructions from the computer-readable storage medium and executes the computer program or the computer instructions, so that the electronic device executes the hardware schematic diagram generation method according to any one of claims 1 to 13.

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