Display panel driving method and display panel

Abstract

The embodiment of the invention provides a display panel driving method and a display panel, and the method comprises the steps: generating a first clock signal comprising a plurality of first stepped pulses for each first display subarea, and scanning a clock signal input end of a first gate driving circuit corresponding to the first display subarea through employing the first clock signal; the output end of the first gate driving circuit is used for providing a gate scanning signal for the pixel circuit of the first display partition; for each second display partition, generating a second clock signal comprising a plurality of second stepped pulses, and scanning a clock signal input end of a second gate drive circuit corresponding to the second display partition by using the second clock signal; the output end of the second gate driving circuit is used for providing a gate scanning signal for the pixel circuit of the second display partition; the step voltage duration of the first step-shaped pulse is smaller than that of the second step-shaped pulse, and the step voltage of the first step-shaped pulse is consistent with that of the second step-shaped pulse.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display panel driving method and a display panel. Background Art

[0002] In current displays, the clock signal at the clock signal input terminal of the GOA (Gate on array) will consume power when the high and low levels of the clock signal flip. In order to reduce the power consumption during the high and low level flips, on the basis of normal circuit function completion, in related technologies, a stepped voltage is set during the high and low level flips, that is, the low level of the clock signal reaches the high level after being buffered by an intermediate voltage (stepped voltage). As Figure 1 shown, the addition of the stepped voltage can reduce the voltage difference between the high and low level flips, can save the DC signal current connected to the GOA circuit, thereby achieving the purpose of saving power, and the duration of the stepped voltage also affects the power reduction effect. The shorter the duration of the stepped voltage, the worse the power reduction effect.

[0003] However, in practical applications, due to the influence of the RC loading (resistance-capacitance load) of the display panel, the gate scan signal of the pixel row farther from the driving integrated circuit (remote pixel row) has a delay (delay t1). As Figure 2 shown, the gate scan signal delay will shorten the effective charging time of the pixel capacitor, resulting in the pixel capacitor being unable to reach the target voltage value, thereby affecting the display quality. In order to prevent further deterioration of the display quality, only a shorter stepped voltage duration can be set (the longer the stepped voltage duration of the clock signal, the shorter the effective level time of the gate scan signal, the shorter the effective charging time of the pixel capacitor, and the worse the display quality). Therefore, the power reduction effect is very poor. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a display panel driving method and a display panel to improve the power reduction effect. The specific technical solutions are as follows:

[0005] In a first aspect, the embodiments of the present application provide a display panel driving method. The display panel includes N first display partitions and M second display partitions. Each of the first display partitions includes a plurality of pixel rows, and there is no overlapping area between any two adjacent first display partitions. Each of the second display partitions includes a plurality of pixel rows, and there is no overlapping area between any two adjacent second display partitions. The distance between the first display partition and the driving integrated circuit of the display panel is greater than a preset threshold, and the distance between the second display partition and the driving integrated circuit is not greater than the preset threshold. There is no overlapping area between the first display partition and the second display partition. N and M are integers not less than 1. The method includes:

[0006] For each first display partition, generate a first clock signal including a plurality of first stepped pulses, and use the first clock signal to scan the clock signal input terminal of the first gate driving circuit corresponding to the first display partition; wherein, the output terminal of the first gate driving circuit is used to provide a gate scanning signal to the pixel circuit of the first display partition;

[0007] For each second display partition, generate a second clock signal including a plurality of second stepped pulses, and use the second clock signal to scan the clock signal input terminal of the second gate driving circuit corresponding to the second display partition; wherein, the output terminal of the second gate driving circuit is used to provide a gate scanning signal to the pixel circuit of the second display partition;

[0008] Wherein, the step voltage duration of the first stepped pulse is less than the step voltage duration of the second stepped pulse, and the step voltage of the first stepped pulse is the same as the step voltage of the second stepped pulse.

[0009] In a possible implementation manner, the generating, for each first display partition, a first clock signal including a plurality of first stepped pulses and using the first clock signal to scan the clock signal input terminal of the first gate driving circuit corresponding to the first display partition includes:

[0010] For each first display partition, obtain the minimum clock unit and the first target number and the second target number of the minimum clock unit corresponding to the first display partition;

[0011] Based on the minimum clock unit and the first target number, determine the step voltage duration corresponding to the first display partition;

[0012] Based on the minimum clock unit and the second target number, determine the peak voltage duration corresponding to the first display partition;

[0013] Based on the step voltage duration and the peak voltage duration corresponding to the first display partition, generate a first clock signal including a plurality of first stepped pulses;

[0014] Use the first clock signal to scan the clock signal input terminal of the first gate driving circuit corresponding to the first display partition;

[0015] And / or,

[0016] The generating, for each second display partition, a second clock signal including a plurality of second stepped pulses and using the second clock signal to scan the clock signal input terminal of the second gate driving circuit corresponding to the second display partition includes:

[0017] For each second display partition, obtain the minimum clock unit, the third target number, and the fourth target number of the minimum clock unit corresponding to the second display partition;

[0018] Based on the minimum clock unit and the third target number, determine the step voltage duration corresponding to the second display partition;

[0019] Based on the minimum clock unit and the fourth target number, determine the peak voltage duration corresponding to the second display partition;

[0020] Based on the step voltage duration and the peak voltage duration corresponding to the second display partition, generate a second clock signal including a plurality of second stepped pulses;

[0021] Use the second clock signal to scan the clock signal input terminal of the second gate driving circuit corresponding to the second display partition.

[0022] In a possible implementation manner, in the same first stepped pulse / second stepped pulse, the step voltage includes an S-level first step voltage and an S-level second step voltage, and the step of the first step voltage is symmetric to the step of the second step voltage of the same level with respect to the peak of the peak voltage;

[0023] Wherein, S is an integer not less than 1.

[0024] In a possible implementation manner, among any two adjacent first display partitions, the first time is less than the second time; wherein, the first time is the step voltage duration corresponding to the first display partition far from the driving integrated circuit, and the second time is the step voltage duration corresponding to the first display partition close to the driving integrated circuit;

[0025] Among any two adjacent second display partitions, the third time is less than the fourth time; wherein, the third time is the step voltage duration corresponding to the second display partition far from the driving integrated circuit, and the fourth time is the step voltage duration corresponding to the second display partition close to the driving integrated circuit.

[0026] In a possible implementation manner, the step voltage durations corresponding to the first display partitions are the same, and the step voltage durations corresponding to the second display partitions are the same.

[0027] In a possible implementation manner, the step voltage durations corresponding to the first display partitions are different, and the step voltage durations corresponding to the second display partitions are different.

[0028] In a possible implementation manner, the step voltage durations corresponding to each of the first display partitions are the same, and the step voltage durations corresponding to each of the second display partitions are different.

[0029] In a possible implementation manner, the step voltage durations corresponding to each of the first display partitions are different, and the step voltage durations corresponding to each of the second display partitions are the same.

[0030] In a second aspect, an embodiment of the present application provides a display panel, where the display panel includes N first display partitions and M second display partitions. Each of the first display partitions includes a plurality of pixel rows, and there is no overlapping area between any two adjacent first display partitions. Each of the second display partitions includes a plurality of pixel rows, and there is no overlapping area between any two adjacent second display partitions. The distance between the first display partition and the driving integrated circuit of the display panel is greater than a preset threshold, and the distance between the second display partition and the driving integrated circuit is not greater than the preset threshold. There is no overlapping area between the first display partition and the second display partition, and N and M are integers not less than 1. The display panel further includes N first control modules and M second control modules. Each of the first control modules corresponds to one of the first display partitions, and each of the second control modules corresponds to one of the second display partitions.

[0031] The first control module is configured to generate a first clock signal including a plurality of first stepped pulses for each first display partition, and use the first clock signal to scan the clock signal input terminal of the first gate driving circuit corresponding to the first display partition. Wherein, the output terminal of the first gate driving circuit is configured to provide a gate scanning signal to the pixel circuit of the first display partition.

[0032] The second control module is configured to generate a second clock signal including a plurality of second stepped pulses for each second display partition, and use the second clock signal to scan the clock signal input terminal of the second gate driving circuit corresponding to the second display partition. Wherein, the output terminal of the second gate driving circuit is configured to provide a gate scanning signal to the pixel circuit of the second display partition.

[0033] Wherein, the step voltage duration of the first stepped pulse is less than the step voltage duration of the second stepped pulse, and the step voltage of the first stepped pulse is the same as the step voltage of the second stepped pulse.

[0034] In a possible implementation manner, the first control module is specifically configured to, for each first display partition, obtain the minimum clock unit and the first target number and the second target number of the minimum clock units corresponding to the first display partition; determine the step voltage duration corresponding to the first display partition based on the minimum clock unit and the first target number; determine the peak voltage duration corresponding to the first display partition based on the minimum clock unit and the second target number; generate a first clock signal including a plurality of first stepped pulses based on the step voltage duration and the peak voltage duration corresponding to the first display partition; and scan the clock signal input end of the first gate driving circuit corresponding to the first display partition by using the first clock signal.

[0035] and / or,

[0036] The second control module is specifically configured to, for each second display partition, obtain the minimum clock unit and the third target number and the fourth target number of the minimum clock units corresponding to the second display partition; determine the step voltage duration corresponding to the second display partition based on the minimum clock unit and the third target number; determine the peak voltage duration corresponding to the second display partition based on the minimum clock unit and the fourth target number; generate a second clock signal including a plurality of second stepped pulses based on the step voltage duration and the peak voltage duration corresponding to the second display partition; and scan the clock signal input end of the second gate driving circuit corresponding to the second display partition by using the second clock signal.

[0037] Advantageous effects of the embodiments of the present application:

[0038] A display panel driving method and a display panel provided by an embodiment of the present application. The display panel includes N first display partitions and M second display partitions. Each first display partition includes a plurality of pixel rows, and there is no overlapping area between any two adjacent first display partitions. Each second display partition includes a plurality of pixel rows, and there is no overlapping area between any two adjacent second display partitions. The distance between the first display partition and the driving integrated circuit of the display panel is greater than a preset threshold, and the distance between the second display partition and the driving integrated circuit is not greater than the preset threshold. There is no overlapping area between the first display partition and the second display partition. N and M are integers not less than 1. The display panel driving method includes: for each first display partition, generating a first clock signal including a plurality of first stepped pulses, and using the first clock signal to scan the clock signal input end of the first gate driving circuit corresponding to the first display partition; wherein, the output end of the first gate driving circuit is used to provide a gate scanning signal to the pixel circuit of the first display partition; for each second display partition, generating a second clock signal including a plurality of second stepped pulses, and using the second clock signal to scan the clock signal input end of the second gate driving circuit corresponding to the second display partition; wherein, the output end of the second gate driving circuit is used to provide a gate scanning signal to the pixel circuit of the second display partition; wherein, the step voltage duration of the first stepped pulse is less than the step voltage duration of the second stepped pulse, and the step voltage of the first stepped pulse is the same as the step voltage of the second stepped pulse. By dividing the display panel into N first display partitions and M second display partitions, and setting the step voltage duration of the first stepped pulse to be less than the step voltage duration of the second stepped pulse, that is, setting the step voltage duration corresponding to each first display partition farther from the driving integrated circuit to be shorter, and the step voltage duration corresponding to each second display partition closer to the driving integrated circuit to be longer, the effect of reducing power consumption is improved on the premise of ensuring display quality.

[0039] Of course, it is not necessary for any product or method implementing the present application to achieve all the above-mentioned advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application, and those of ordinary skill in the art can also obtain other embodiments based on these drawings.

[0041] Figure 1 A schematic diagram of setting the step voltage of the clock signal in the related art;

[0042] Figure 2A schematic diagram of the delay of the gate scan signal in the related art;

[0043] Figure 3a The first structural schematic diagram of the display panel provided by the embodiment of the present application;

[0044] Figure 3b A schematic diagram of the first clock signal and the second clock signal;

[0045] Figure 4a The first flow schematic diagram of the display panel driving method provided by the embodiment of the present application;

[0046] Figure 4b The second flow schematic diagram of the display panel driving method provided by the embodiment of the present application;

[0047] Figure 5 The second structural schematic diagram of the display panel provided by the embodiment of the present application. Detailed implementation manners

[0048] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art based on the present application belong to the scope of protection of the present application.

[0049] In current displays, the clock signal at the clock signal input terminal of the GOA (Gate on array, gate driving circuit) will cause power consumption when the high and low levels flip. In order to reduce the power consumption caused by the high and low level flips, on the basis that the circuit function is normally completed, in the related art, a step voltage is set during the high and low level flips, that is, the low level of the clock signal reaches the high level after being buffered by an intermediate voltage (step voltage), as Figure 1 shown. The addition of the step voltage can reduce the voltage difference between the high and low level flips, can save the direct current signal current connected to the GOA circuit, thereby achieving the purpose of saving power, and the duration of the step voltage will also affect the power reduction effect. The shorter the duration of the step voltage, the worse the power reduction effect.

[0050] However, in actual applications, due to the influence of the RC loading (resistance-capacitance load) of the display panel, the gate scan signal of the pixel row farther from the driving integrated circuit (remote pixel row) has a delay (delay t1), as Figure 2As shown, the delay of the gate scan signal shortens the effective charging time of the pixel capacitor, resulting in the pixel capacitor being unable to reach the target voltage value, thereby affecting the display quality. To prevent further deterioration of the display quality, only a short step voltage duration can be set (the longer the step voltage duration of the clock signal, the shorter the effective level time of the gate scan signal, the shorter the effective charging time of the pixel capacitor, and the worse the display quality). Therefore, the effect of power consumption reduction is very poor.

[0051] The charging time is defined as the time when the gate scan signal selects a row of pixels, the data writing transistor corresponding to the row is turned on, and the data voltage charges the pixel capacitor to the target voltage value through the data writing transistor.

[0052] To improve at least one of the above problems, an embodiment of the present application provides a display panel driving method and a display panel.

[0053] Next, the display panel driving method provided by the embodiment of the present application will be described in detail. Refer to Figure 3a , the display panel 1 includes N first display partitions 11 and M second display partitions 12. Each of the first display partitions 11 includes a plurality of pixel rows, and there is no overlapping area between any two adjacent first display partitions 11. Each of the second display partitions 12 includes a plurality of pixel rows, and there is no overlapping area between any two adjacent second display partitions 12. The distance between the first display partition 11 and the driving integrated circuit 13 of the display panel 1 is greater than a preset threshold, and the distance between the second display partition 12 and the driving integrated circuit 13 is not greater than the preset threshold. There is no overlapping area between the first display partition 11 and the second display partition 12. N and M are integers not less than 1. The method includes:

[0054] Step S301, for each first display partition 11, generate a first clock signal including a plurality of first stepped pulses, and use the first clock signal to scan the clock signal input terminal of the first gate driving circuit 14 corresponding to the first display partition 11; wherein, the output terminal of the first gate driving circuit 14 is used to provide a gate scan signal to the pixel circuit of the first display partition 11.

[0055] Step S302, for each second display partition 12, generate a second clock signal including a plurality of second stepped pulses, and use the second clock signal to scan the clock signal input terminal of the second gate driving circuit 15 corresponding to the second display partition 12; wherein, the output terminal of the second gate driving circuit 15 is used to provide a gate scan signal to the pixel circuit of the second display partition 12.

[0056] Among them, the step voltage duration of the first stepped pulse is less than that of the second stepped pulse, and the step voltage of the first stepped pulse is the same as that of the second stepped pulse.

[0057] A schematic diagram of the first clock signal including multiple first stepped pulses can be seen in Figure 3b , and a schematic diagram of the second clock signal including multiple second stepped pulses can be seen in Figure 3b .

[0058] The first stepped pulse and the second stepped pulse may include one-level step voltage or multiple-level step voltages, and the present application does not specifically limit this. In one example, the first stepped pulse and the second stepped pulse may include two-level step voltages, the first-level step voltage is 4V, the second-level step voltage is 6V, and the peak voltage is 8V.

[0059] It can be understood that Figure 3b the first stepped pulse and the second stepped pulse are schematically shown with one-level step voltage in

[0060] The preset threshold can be set according to the display situation of the display panel, the specific division of the display area, etc. In one example, the display panel 1 includes two first display areas 11 and two second display areas 12. The step voltage duration corresponding to the first first display area 11 can be 2 ms, the step voltage duration corresponding to the second first display area 11 can be 3 ms, the step voltage duration corresponding to the first second display area 12 can be 5 ms, and the step voltage duration corresponding to the second second display area 12 can be 7 ms.

[0061] In the same first clock signal, the step voltage durations of the first stepped pulses are the same. In the same second clock signal, the step voltage durations of the second stepped pulses are the same.

[0062] In the embodiment of the present application, by dividing the display panel 1 into N first display areas 11 and M second display areas 12, and setting the step voltage duration of the first stepped pulse to be less than that of the second stepped pulse, that is, setting the step voltage duration corresponding to each first display area 11 farther from the driving integrated circuit 13 to be shorter, and the step voltage duration corresponding to each second display area 12 closer to the driving integrated circuit 13 to be longer, the effect of reducing power consumption is improved on the premise of ensuring the display quality.

[0063] In a possible implementation manner, referring to Figure 4a , step S301 in the above embodiment is refined and includes the following steps:

[0064] Step S401: For each first display partition 11, obtain the minimum clock unit and the first target number Na and the second target number Nb of the minimum clock units corresponding to this first display partition 11.

[0065] Step S402: Based on the minimum clock unit and the first target number Na, determine the step voltage duration corresponding to this first display partition 11.

[0066] Step S403: Based on the minimum clock unit and the second target number Nb, determine the peak voltage duration corresponding to this first display partition 11.

[0067] Step S404: Based on the step voltage duration and the peak voltage duration corresponding to this first display partition 11, generate a first clock signal including a plurality of first stepped pulses.

[0068] Step S405: Use the first clock signal to scan the clock signal input terminal of the first gate driving circuit 14 corresponding to this first display partition 11.

[0069] And / or, refer to Figure 4b , the step S302 in the above embodiment is refined, including the following steps:

[0070] Step S501: For each second display partition 12, obtain the minimum clock unit and the third target number Nc and the fourth target number Nd of the minimum clock units corresponding to this second display partition 12.

[0071] Step S502: Based on the minimum clock unit and the third target number Nc, determine the step voltage duration corresponding to this second display partition 12.

[0072] Step S503: Based on the minimum clock unit and the fourth target number Nd, determine the peak voltage duration corresponding to this second display partition 12.

[0073] Step S504: Based on the step voltage duration and the peak voltage duration corresponding to this second display partition 12, generate a second clock signal including a plurality of second stepped pulses.

[0074] Step S505: Use the second clock signal to scan the clock signal input terminal of the second gate driving circuit 15 corresponding to this second display partition 12.

[0075] The minimum dot clock is the reciprocal of the crystal oscillator frequency of the timing control circuit, i.e., dot clock = 1 / Frequency, where Frequency is the crystal oscillator frequency. The duration of the step voltage and the peak voltage are set by setting the number of minimum clock signals (in microseconds).

[0076] Specifically, refer to Figure 3b , the first stepped pulse includes three stages: A1, B1, and C1. In the A1 stage (the duration of the step voltage of the first stepped pulse), set Na minimum clock signals to complete the signal output in the A1 stage; from the A1 stage to the B1 stage, the signal changes from the step voltage to the peak voltage; in the B1 stage (the duration of the peak voltage of the first stepped pulse), set Nb minimum clock signals to complete the signal output in the B stage; from the B1 stage to the C1 stage, the signal changes from the peak voltage to the step voltage; in the C1 stage (the duration of the step voltage of the first stepped pulse), set Na minimum clock signals to complete the signal output in the C1 stage.

[0077] The duration of the step voltage of the first stepped pulse = dot clock × Na, and the duration of the peak voltage of the first stepped pulse = dot clock × Nb.

[0078] For each first display partition 11, the adjustment parameters of the minimum clock unit are independently set by the control module corresponding to the first display partition 11, and the duration of the step voltage corresponding to the first display partition 11 is independently controlled.

[0079] Refer to Figure 3b , the second stepped pulse includes three stages: A2, B2, and C2. In the A2 stage (the duration of the step voltage of the second stepped pulse), set Nc minimum clock signals to complete the signal output in the A2 stage; from the A2 stage to the B2 stage, the signal changes from the step voltage to the peak voltage; in the B2 stage (the duration of the peak voltage of the second stepped pulse), set Nd minimum clock signals to complete the signal output in the B2 stage; from the B2 stage to the C2 stage, the signal changes from the peak voltage to the step voltage; in the C2 stage (the duration of the step voltage of the second stepped pulse), set Nc minimum clock signals to complete the signal output in the C2 stage.

[0080] The duration of the step voltage of the second stepped pulse = dot clock × Nc, and the duration of the peak voltage of the second stepped pulse = dot clock × Nd.

[0081] For each second display partition 12, the adjustment parameters of the minimum clock unit are independently set by the control module corresponding to the second display partition 12, and the step voltage duration corresponding to the second display partition 12 is independently controlled.

[0082] It can be understood that Na < Nc and Nb < Nd, and the pulse durations of the respective stepped pulses are the same.

[0083] In the embodiment of the present application, the step voltage duration and the peak voltage duration are set by setting the number of minimum clock signals. For each first display partition 11, the adjustment parameters of the minimum clock unit are independently set by the control module corresponding to the first display partition 11, and the step voltage duration corresponding to the first display partition 11 is independently controlled. For each second display partition 12, the adjustment parameters of the minimum clock unit are independently set by the control module corresponding to the second display partition 12, and the step voltage duration corresponding to the second display partition 12 is independently controlled.

[0084] In a possible implementation manner, in the same first stepped pulse / second stepped pulse, the step voltage includes an S-level first step voltage and an S-level second step voltage, and the step of the first step voltage is symmetric with respect to the peak of the peak voltage with the step of the second step voltage of the same level;

[0085] wherein S is an integer not less than 1.

[0086] See Figure 3b , in the same first stepped pulse / second stepped pulse, the step voltage includes a first step voltage of level 1 and a second step voltage of level 1, and the step of the first step voltage is symmetric with respect to the peak of the peak voltage with the step of the second step voltage.

[0087] In a possible implementation manner, in any two adjacent first display partitions 11, a first time is less than a second time; wherein, the first time is the step voltage duration corresponding to the first display partition 11 far from the driving integrated circuit 13, and the second time is the step voltage duration corresponding to the first display partition 11 close to the driving integrated circuit 13;

[0088] In any two adjacent second display partitions 12, a third time is less than a fourth time; wherein, the third time is the step voltage duration corresponding to the second display partition 12 far from the driving integrated circuit 13, and the fourth time is the step voltage duration corresponding to the second display partition 12 close to the driving integrated circuit 13.

[0089] In an embodiment of the present application, in the display panel 1, in the direction from the second display partition 12 to the first display partition 11, the step voltage duration corresponding to each display partition decreases in sequence.

[0090] In a possible implementation manner, the step voltage durations corresponding to each of the first display partitions 11 are the same, and the step voltage durations corresponding to each of the second display partitions 12 are the same.

[0091] In a possible implementation manner, the step voltage durations corresponding to each of the first display partitions 11 are different, and the step voltage durations corresponding to each of the second display partitions 12 are different.

[0092] In a possible implementation manner, the step voltage durations corresponding to each of the first display partitions 11 are the same, and the step voltage durations corresponding to each of the second display partitions 12 are different.

[0093] In a possible implementation manner, the step voltage durations corresponding to each of the first display partitions 11 are different, and the step voltage durations corresponding to each of the second display partitions 12 are the same.

[0094] In a possible implementation manner, among a part of the first display partitions 11, the step voltage durations corresponding to each of the first display partitions 11 are the same, and among another part of the first display partitions 11, the step voltage durations corresponding to each of the first display partitions 11 are different; among a part of the second display partitions 12, the step voltage durations corresponding to each of the second display partitions 12 are the same, and among another part of the second display partitions 12, the step voltage durations corresponding to each of the second display partitions 12 are different.

[0095] It can be understood that there are other setting methods, which will not be elaborated herein in the present application.

[0096] In an embodiment of the present application, the step voltage durations corresponding to each of the first display partitions 11 can be the same, can be different, or can be partially the same; the step voltage durations corresponding to each of the second display partitions 12 can be the same, can be different, or can be partially the same.

[0097] In a possible implementation manner, the number of pixel rows included in each of the first display partitions 11 can be the same, can be different, or can be partially the same; the number of pixel rows included in each of the second display partitions 12 can be the same, can be different, or can be partially the same.

[0098] The embodiment of the present application also provides a display panel 1, see Figure 5, the display panel 1 includes N first display partitions 11 and M second display partitions 12. Each of the first display partitions 11 includes a plurality of pixel rows, and there is no overlapping area between any two adjacent first display partitions 11. Each of the second display partitions 12 includes a plurality of pixel rows, and there is no overlapping area between any two adjacent second display partitions 12. The distance between the first display partition 11 and the driving integrated circuit 13 of the display panel 1 is greater than a preset threshold, and the distance between the second display partition 12 and the driving integrated circuit 13 is not greater than the preset threshold. There is no overlapping area between the first display partition 11 and the second display partition 12. N and M are integers not less than 1. The display panel 1 further includes N first control modules 16 and M second control modules 17. Each of the first control modules 16 corresponds to one of the first display partitions 11 one by one, and each of the second control modules 17 corresponds to one of the second display partitions 12 one by one;

[0099] The first control module 16 is configured to generate, for each first display partition 11, a first clock signal including a plurality of first stepped pulses, and use the first clock signal to scan the clock signal input terminal of the first gate driving circuit 14 corresponding to the first display partition 11. Wherein, the output terminal of the first gate driving circuit 14 is configured to provide a gate scanning signal to the pixel circuit of the first display partition 11;

[0100] The second control module 17 is configured to generate, for each second display partition 12, a second clock signal including a plurality of second stepped pulses, and use the second clock signal to scan the clock signal input terminal of the second gate driving circuit 15 corresponding to the second display partition 12. Wherein, the output terminal of the second gate driving circuit 15 is configured to provide a gate scanning signal to the pixel circuit of the second display partition 12;

[0101] Wherein, the step voltage duration of the first stepped pulse is less than the step voltage duration of the second stepped pulse, and the step voltage of the first stepped pulse is the same as the step voltage of the second stepped pulse.

[0102] Each of the first control modules 16 may include a register and a timing control circuit. Each of the second control modules 17 may include a register and a timing control circuit. The register is used to set parameters such as the minimum clock unit, the number of minimum clock units, the voltage value of the step voltage, and the voltage value of the peak voltage. The timing control circuit is used to generate a clock signal according to the parameters set by its corresponding register.

[0103] In a possible implementation manner, considering the number of control modules, the value range of M + N may be 2 ≤ M + N ≤ 64.

[0104] The remaining analysis is the same as above and will not be elaborated here.

[0105] In the embodiment of the present application, by dividing the display panel 1 into N first display partitions 11 and M second display partitions 12, and setting the step voltage duration of the first stepped pulse to be less than the step voltage duration of the second stepped pulse, that is, setting the step voltage duration corresponding to each first display partition 11 farther away from the driving integrated circuit 13 to be shorter, and the step voltage duration corresponding to each second display partition 12 closer to the driving integrated circuit 13 to be longer, the effect of reducing power consumption is improved on the premise of ensuring the display quality.

[0106] In a possible implementation manner, the first control module 16 is specifically configured to, for each first display partition 11, obtain the minimum clock unit and the first target number and the second target number of the minimum clock unit corresponding to the first display partition 11; determine the step voltage duration corresponding to the first display partition 11 based on the minimum clock unit and the first target number; determine the peak voltage duration corresponding to the first display partition 11 based on the minimum clock unit and the second target number; generate a first clock signal including a plurality of first stepped pulses based on the step voltage duration and the peak voltage duration corresponding to the first display partition 11; and scan the clock signal input end of the first gate driving circuit 14 corresponding to the first display partition 11 by using the first clock signal.

[0107] and / or

[0108] The second control module 17 is specifically configured to, for each second display partition 12, obtain the minimum clock unit and the third target number and the fourth target number of the minimum clock unit corresponding to the second display partition 12; determine the step voltage duration corresponding to the second display partition 12 based on the minimum clock unit and the third target number; determine the peak voltage duration corresponding to the second display partition 12 based on the minimum clock unit and the fourth target number; generate a second clock signal including a plurality of second stepped pulses based on the step voltage duration and the peak voltage duration corresponding to the second display partition 12; and scan the clock signal input end of the second gate driving circuit 15 corresponding to the second display partition 12 by using the second clock signal.

[0109] The specific analysis is the same as above and will not be elaborated here.

[0110] In the embodiments of the present application, the duration of the step voltage and the duration of the peak voltage are set by setting the number of minimum clock signals. For each first display partition 11, the adjustment parameters of the minimum clock unit are independently set by the first control module 16 corresponding to the first display partition 11, and the duration of the step voltage corresponding to the first display partition 11 is independently controlled. For each second display partition 12, the adjustment parameters of the minimum clock unit are independently set by the second control module 17 corresponding to the second display partition 12, and the duration of the step voltage corresponding to the second display partition 12 is independently controlled.

[0111] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0112] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiment.

[0113] The above description is only the preferred embodiment of the present application and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A display panel driving method, characterized in that, The display panel includes N first display partitions and M second display partitions. Each of the first display partitions includes a plurality of pixel rows, and there is no overlapping area between any two adjacent first display partitions. Each of the second display partitions includes a plurality of pixel rows, and there is no overlapping area between any two adjacent second display partitions. The distance between the first display partition and the driving integrated circuit of the display panel is greater than a preset threshold, and the distance between the second display partition and the driving integrated circuit is not greater than the preset threshold. There is no overlapping area between the first display partition and the second display partition. N and M are integers not less than 1. The method includes: For each first display partition, generate a first clock signal including a plurality of first stepped pulses, and use the first clock signal to scan the clock signal input end of the first gate driving circuit corresponding to the first display partition; wherein, the output end of the first gate driving circuit is used to provide a gate scanning signal to the pixel circuit of the first display partition; For each second display partition, generate a second clock signal including a plurality of second stepped pulses, and use the second clock signal to scan the clock signal input end of the second gate driving circuit corresponding to the second display partition; wherein, the output end of the second gate driving circuit is used to provide a gate scanning signal to the pixel circuit of the second display partition; Wherein, the step voltage duration of the first stepped pulse is less than the step voltage duration of the second stepped pulse, and the step voltage of the first stepped pulse is the same as the step voltage of the second stepped pulse.

2. The method according to claim 1, characterized in that, The step of, for each first display partition, generating a first clock signal including a plurality of first stepped pulses and using the first clock signal to scan the clock signal input end of the first gate driving circuit corresponding to the first display partition includes: For each first display partition, obtain the minimum clock unit and the first target number and the second target number of the minimum clock unit corresponding to the first display partition; Based on the minimum clock unit and the first target number, determine the step voltage duration corresponding to the first display partition; Based on the minimum clock unit and the second target number, determine the peak voltage duration corresponding to the first display partition; Based on the step voltage duration and the peak voltage duration corresponding to the first display partition, generate a first clock signal including a plurality of first stepped pulses; Use the first clock signal to scan the clock signal input end of the first gate driving circuit corresponding to the first display partition; And / or, The step of, for each second display partition, generating a second clock signal including a plurality of second stepped pulses and using the second clock signal to scan the clock signal input end of the second gate driving circuit corresponding to the second display partition includes: For each second display partition, obtain the minimum clock unit and the third target number and the fourth target number of the minimum clock unit corresponding to the second display partition; Based on the minimum clock unit and the third target number, determine the step voltage duration corresponding to the second display partition; Determine the peak voltage duration corresponding to the second display partition based on the minimum clock unit and the fourth target number; Generate a second clock signal including a plurality of second stepped pulses based on the stepped voltage duration and the peak voltage duration corresponding to the second display partition; Use the second clock signal to scan the clock signal input terminal of the second gate driving circuit corresponding to the second display partition.

3. The method according to claim 1, characterized in that, In the same first stepped pulse / second stepped pulse, the stepped voltage includes an S-level first stepped voltage and an S-level second stepped voltage, and the step of the first stepped voltage is symmetric to the step of the second stepped voltage of the same level with respect to the peak of the peak voltage; Wherein, S is an integer not less than 1.

4. The method according to claim 1, characterized in that, Among any two adjacent first display partitions, the first time is less than the second time; wherein, the first time is the stepped voltage duration corresponding to the first display partition far from the driving integrated circuit, and the second time is the stepped voltage duration corresponding to the first display partition close to the driving integrated circuit; Among any two adjacent second display partitions, the third time is less than the fourth time; wherein, the third time is the stepped voltage duration corresponding to the second display partition far from the driving integrated circuit, and the fourth time is the stepped voltage duration corresponding to the second display partition close to the driving integrated circuit.

5. The method according to claim 1, wherein The stepped voltage durations corresponding to each of the first display partitions are the same, and the stepped voltage durations corresponding to each of the second display partitions are the same.

6. The method according to claim 1, wherein The stepped voltage durations corresponding to each of the first display partitions are different, and the stepped voltage durations corresponding to each of the second display partitions are different.

7. The method according to claim 1, wherein The stepped voltage durations corresponding to each of the first display partitions are the same, and the stepped voltage durations corresponding to each of the second display partitions are different.

8. The method according to claim 1, characterized in that The stepped voltage durations corresponding to each of the first display partitions are different, and the stepped voltage durations corresponding to each of the second display partitions are the same.

9. A display panel, characterized in that, The display panel includes N first display partitions and M second display partitions. Each of the first display partitions includes a plurality of pixel rows, and there is no overlapping area between any two adjacent first display partitions. Each of the second display partitions includes a plurality of pixel rows, and there is no overlapping area between any two adjacent second display partitions. The distance between the first display partition and the driving integrated circuit of the display panel is greater than a preset threshold, and the distance between the second display partition and the driving integrated circuit is not greater than the preset threshold. There is no overlapping area between the first display partition and the second display partition. N and M are integers not less than 1; the display panel further includes N first control modules and M second control modules. Each of the first control modules corresponds to each of the first display partitions one by one, and each of the second control modules corresponds to each of the second display partitions one by one; The first control module is configured to generate, for each first display partition, a first clock signal including a plurality of first stepped pulses, and scan a clock signal input terminal of a first gate driving circuit corresponding to the first display partition by using the first clock signal; wherein, an output terminal of the first gate driving circuit is configured to provide a gate scanning signal to a pixel circuit of the first display partition; The second control module is configured to generate, for each second display partition, a second clock signal including a plurality of second stepped pulses, and scan a clock signal input terminal of a second gate driving circuit corresponding to the second display partition by using the second clock signal; wherein, an output terminal of the second gate driving circuit is configured to provide a gate scanning signal to a pixel circuit of the second display partition; Wherein, a step voltage duration of the first stepped pulse is less than a step voltage duration of the second stepped pulse, and a step voltage of the first stepped pulse is the same as a step voltage of the second stepped pulse.

10. The display panel according to claim 9, wherein The first control module is specifically configured to, for each first display partition, obtain a minimum clock unit and a first target number and a second target number of the minimum clock units corresponding to the first display partition; determine a step voltage duration corresponding to the first display partition based on the minimum clock unit and the first target number; Determine a peak voltage duration corresponding to the first display partition based on the minimum clock unit and the second target number; Generate a first clock signal including a plurality of first stepped pulses based on the step voltage duration and the peak voltage duration corresponding to the first display partition; scan a clock signal input terminal of a first gate driving circuit corresponding to the first display partition by using the first clock signal; And / or The second control module is specifically configured to, for each second display partition, obtain a minimum clock unit and a third target number and a fourth target number of the minimum clock units corresponding to the second display partition; determine a step voltage duration corresponding to the second display partition based on the minimum clock unit and the third target number; Determine a peak voltage duration corresponding to the second display partition based on the minimum clock unit and the fourth target number; Generate a second clock signal including a plurality of second stepped pulses based on the step voltage duration and the peak voltage duration corresponding to the second display partition; scan a clock signal input terminal of a second gate driving circuit corresponding to the second display partition by using the second clock signal.

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