Display panel and display device

Abstract

The invention discloses a display panel and a display device, in the display panel, the colors of light-emitting elements driven by pixel driving circuits in the same column are the same, and every four columns of pixel driving circuits serve as a driving group. The four columns of pixel driving circuits in the same driving group comprise one column of first pixel driving circuits, one column of second pixel driving circuits and two columns of third pixel driving circuits which are sequentially arranged in the row direction; each driving group is correspondingly connected with two first-type power supply signal lines, and the two first-type power supply signal lines connected with the same driving group comprise a first power supply signal line for providing first power supply voltage and a second power supply signal line for providing second power supply voltage; the first power supply signal lines are connected with the first pixel driving circuits and the second pixel driving circuits in the corresponding driving groups, the second power supply signal lines are connected with the third pixel driving circuits in the corresponding driving groups, and the first power supply voltage and the second power supply voltage are different, so that the power consumption of the display panel is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] With the development of display technologies, more and more display devices are applied to people's daily life and work.

[0003] For current display devices such as mobile phones or tablets, with the development of display requirements, people's demand for higher brightness is becoming increasingly apparent, resulting in an increase in the power consumption of the screen body. Summary of the Invention

[0004] The present invention provides a display panel and a display device to solve the problem of large power consumption of the screen body.

[0005] According to one aspect of the present invention, a display panel is provided, including:

[0006] A substrate;

[0007] A driving array layer located on one side of the substrate. The driving array layer includes a plurality of pixel driving circuits arranged in an array. The light-emitting elements driven by the pixel driving circuits in the same column have the same light-emitting color. Along the row direction, every four columns of pixel driving circuits form a driving group, and the arrangement modes of the respective pixel driving circuits in each driving group are the same. The four columns of pixel driving circuits in the same driving group include a column of first pixel driving circuits, a column of second pixel driving circuits, and two columns of third pixel driving circuits arranged in sequence along the row direction. Among them, the light-emitting elements driven by the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit have different colors;

[0008] The driving array layer further includes a plurality of first type power signal lines extending along the column direction and arranged along the row direction. Each driving group is correspondingly connected to two first type power signal lines. The two first type power signal lines connected to the same driving group include a first power signal line and a second power signal line. The first power signal line is connected to each of the first pixel driving circuits and each of the second pixel driving circuits in the corresponding driving group to provide a first power voltage. The second power signal line is connected to each of the third pixel driving circuits in the corresponding driving group to provide a second power voltage. The first power voltage and the second power voltage are different.

[0009] Optionally, the light-emitting element driven by the first pixel driving circuit has a blue light-emitting color, the light-emitting element driven by the second pixel driving circuit has a red light-emitting color, and the light-emitting element driven by the third pixel driving circuit has a green light-emitting color.

[0010] Optionally, the first power supply signal line is mirror-symmetrical about the first center line, and the first pixel driving circuit and the second pixel driving circuit in any row of pixel driving circuits in the same driving group are mirror-symmetrical about the first center line, and the first center line extends along the column direction;

[0011] The second power supply signal line is mirror-symmetrical about the second center line, the second center line extends along the column direction, and two third pixel driving circuits in any row of pixel driving circuits in the same driving group are mirror-symmetrical about the second center line;

[0012] Optionally, the vertical projection of the first pixel driving circuit on the substrate overlaps at least partially with the vertical projection of the first power supply signal line connected to the first pixel driving circuit on the substrate;

[0013] The vertical projection of the second pixel driving circuit on the substrate overlaps at least partially with the vertical projection of the first power supply signal line connected to the second pixel driving circuit on the substrate;

[0014] The vertical projection of the third pixel driving circuit on the substrate overlaps at least partially with the vertical projection of the second power supply signal line connected to the third pixel driving circuit on the substrate.

[0015] Optionally, the driving array layer further includes: a plurality of second type power supply signal lines extending along the row direction and arranged along the column direction, and the plurality of second type power supply signal lines include: a plurality of third power supply signal lines and a plurality of fourth power supply signal lines;

[0016] Each of the first power supply signal lines is connected to each of the third power supply signal lines;

[0017] Each of the second power supply signal lines is connected to each of the fourth power supply signal lines;

[0018] Optionally, one row of pixel driving circuits corresponds to one of the second type power supply signal lines, and along the column direction, the third power supply signal lines and the fourth power supply signal lines are alternately arranged;

[0019] Optionally, the first type power supply signal lines and the second type power supply signal lines are located in different conductive layers in the driving array layer;

[0020] Optionally, the pixel driving circuit includes a plurality of transistors and at least one capacitor, and the driving array layer includes a first active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially stacked from one side of the substrate, the gate of at least one of the transistors is located in the first conductive layer, one plate of at least one capacitor is located in the second conductive layer, and the source and drain of at least one of the transistors are both located in the third conductive layer;

[0021] Among them, the first type of power supply signal line is located in the third conductive layer or the fourth conductive layer. Alternatively, the driving array layer further includes a fifth conductive layer located on a side of the fourth conductive layer away from the substrate, and the first type of power supply signal line is located in any one of the third conductive layer, the fourth conductive layer, and the fifth conductive layer;

[0022] The second type of power supply signal line is located in any one of the first conductive layer, the second conductive layer, and the third conductive layer. Alternatively, the driving array layer further includes a second active layer and a sixth conductive layer located between the second conductive layer and the third conductive layer, the second active layer is located on a side of the sixth conductive layer close to the substrate, the plurality of transistors include low-temperature polysilicon transistors and oxide transistors, the gate of the oxide transistor is located in the sixth conductive layer, the gate of the low-temperature polysilicon transistor is located in the first conductive layer, and the second type of power supply signal line is located in any one of the first conductive layer, the second conductive layer, the third conductive layer, and the sixth conductive layer.

[0023] Optionally, the driving array layer further includes:

[0024] A plurality of first type of initialization signal lines extending along the row direction and arranged along the column direction, and any one of the first type of initialization signal lines is configured to provide a first initialization voltage to the light-emitting element and / or provide a second initialization voltage to the gate of the driving transistor of the pixel driving circuit;

[0025] A plurality of second type of initialization signal lines extending along the column direction and arranged along the row direction, and any one of the second type of initialization signal lines is configured to provide a first initialization voltage to the light-emitting element and / or provide a second initialization voltage to the gate of the driving transistor of the pixel driving circuit;

[0026] The first type of initialization signal lines and the second type of initialization signal lines that provide the same voltage are connected;

[0027] Optionally, the first initialization voltage and the second initialization voltage are the same, and each of the first type of initialization signal lines and each of the second type of initialization signal lines are connected. Alternatively, the first initialization voltage and the second initialization voltage are different, some of the first type of initialization signal lines are configured to provide the first initialization voltage, some of the first type of initialization signal lines are configured to provide the second initialization voltage, some of the second type of initialization signal lines are configured to provide the first initialization voltage, and some of the second type of initialization signal lines are configured to provide the second initialization voltage;

[0028] Optionally, the first type of initialization signal lines and the second type of initialization signal lines are located in different conductive layers of the driving array layer;

[0029] Optionally, the pixel driving circuit includes multiple transistors and at least one capacitor. The driving array layer includes a first active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer that are sequentially stacked from one side of the substrate. The gate of at least one of the transistors is located in the first conductive layer, one plate of at least one capacitor is located in the second conductive layer, and the source and drain of at least one of the transistors are both located in the third conductive layer;

[0030] The second type of initialization signal lines are located in the third conductive layer or the fourth conductive layer. Alternatively, the driving array layer further includes a fifth conductive layer located on the side of the fourth conductive layer away from the substrate, and the second type of initialization signal lines are located in any one of the third conductive layer, the fourth conductive layer, and the fifth conductive layer; the first type of initialization signal lines are located in any one of the first conductive layer, the second conductive layer, and the third conductive layer. Alternatively, the driving array layer further includes a second active layer and a sixth conductive layer both located between the second conductive layer and the third conductive layer. The second active layer is located on the side of the sixth conductive layer close to the substrate. The multiple transistors include low-temperature polysilicon transistors and oxide transistors. The gate of the oxide transistor is located in the sixth conductive layer, the gate of the low-temperature polysilicon transistor is located in the first conductive layer, and the first type of initialization signal lines are located in any one of the first conductive layer, the second conductive layer, the third conductive layer, and the sixth conductive layer.

[0031] Optionally, the driving array layer further includes multiple fifth power signal lines extending along the row direction and arranged along the column direction, and multiple sixth power signal lines extending along the column direction and arranged along the row direction. Each of the fifth power signal lines is connected to each of the sixth power signal lines, and the fifth power signal line and / or the sixth power signal line is connected to the second electrode of the light-emitting element;

[0032] Optionally, the sixth power signal lines are located in the third conductive layer or the fourth conductive layer. Alternatively, the driving array layer further includes a fifth conductive layer, and the sixth power signal lines are located in any one of the third conductive layer, the fourth conductive layer, and the fifth conductive layer; the fifth power signal lines are located in any one of the first conductive layer, the second conductive layer, and the third conductive layer. Alternatively, the driving array layer further includes a second active layer and a sixth conductive layer located between the second conductive layer and the third conductive layer, and the fifth power signal lines are located in any one of the first conductive layer, the second conductive layer, the third conductive layer, and the sixth conductive layer;

[0033] Optionally, the display panel further includes:

[0034] A light-emitting element layer, located on a side of the driving array layer away from the substrate, the light-emitting element layer includes a plurality of light-emitting elements arranged in an array, each of the light-emitting elements includes a first electrode, a light-emitting functional layer, and a second electrode that are sequentially stacked, and the first electrodes of the light-emitting elements are insulated from each other;

[0035] Optionally, the second electrode is a whole-layer structure.

[0036] Optionally, the driving array layer includes a plurality of first connection lines, the plurality of first connection lines include each of the first type of initialization signal lines and each of the fifth power supply signal lines, and one first connection line is provided corresponding to one row of the pixel driving circuits;

[0037] Along the column direction, the first type of initialization signal lines and the fifth power supply signal lines are alternately arranged;

[0038] Optionally, the plurality of first type of initialization signal lines include a plurality of first initialization signal lines and a plurality of second initialization signal lines, the first initialization signal lines are used to provide the first initialization voltage, and the second initialization signal lines are used to provide the second initialization voltage;

[0039] Along the column direction, the first initialization signal lines and the second initialization signal lines are alternately arranged;

[0040] Optionally, the driving array layer includes a plurality of second connection lines, the plurality of second connection lines include each of the second type of initialization signal lines and each of the sixth power supply signal lines;

[0041] One second connection line is provided between every two adjacent first type of power supply signal lines;

[0042] Along the row direction, the second type of initialization signal lines and the sixth power supply signal lines are alternately arranged;

[0043] Optionally, the plurality of second type of initialization signal lines include a plurality of third initialization signal lines and a plurality of fourth initialization signal lines, the third initialization signal lines are used to provide the first initialization voltage, and the fourth initialization signal lines are used to provide the second initialization voltage;

[0044] Along the row direction, the third initialization signal lines and the fourth initialization signal lines are alternately arranged.

[0045] Optionally, the driving array layer further includes:

[0046] Multiple data lines extending along the column direction, and one of the data lines is connected to a column of pixel driving circuits;

[0047] Optionally, the four data lines connected to the same driving group include a first data line, a second data line, a third data line, and a fourth data line. The first data line is connected to the pixel driving circuit of the first column, the second data line is connected to the pixel driving circuit of the second column, the third data line is connected to the pixel driving circuit of the third column, and the fourth data line is connected to the pixel driving circuit of the fourth column. The first data line and the second data line are respectively arranged on both sides of the first power signal line, and the third data line and the fourth data line are respectively arranged on both sides of the second power signal line;

[0048] Optionally, a second connection line is arranged between two adjacent data lines.

[0049] Optionally, the display panel further includes:

[0050] A light-emitting element layer, located on the side of the driving array layer away from the substrate. The light-emitting element layer includes a plurality of light-emitting elements arranged in an array. Along the row direction, every four columns of light-emitting elements are divided into a light-emitting element group, and the light-emitting elements in each light-emitting element group are arranged in the same way;

[0051] Among the first-column light-emitting elements in the same light-emitting element group, the light-emitting elements located in the even rows are the first light-emitting elements, and the light-emitting elements located in the odd rows are the second light-emitting elements. The second-column light-emitting elements and the fourth-column light-emitting elements in the same light-emitting element group are both the third light-emitting elements. Among the third-column light-emitting elements in the same light-emitting element group, the light-emitting elements located in the even rows are the second light-emitting elements, and the light-emitting elements located in the odd rows are the first light-emitting elements.

[0052] Wherein, the light-emitting colors of the first light-emitting element, the second light-emitting element, and the third light-emitting element are all different;

[0053] Each of the driving groups is connected to each of the light-emitting element groups in a one-to-one correspondence. For the corresponding driving group and the light-emitting element group, the pixel driving circuits in the odd rows of the first column of pixel driving circuits are respectively connected to the second light-emitting elements in the first column of light-emitting elements, and the pixel driving circuits in the even rows of the first column of pixel driving circuits are respectively connected to the second light-emitting elements in the third column of light-emitting elements; the pixel driving circuits in the odd rows of the second column of pixel driving circuits are respectively connected to the first light-emitting elements in the third column of light-emitting elements, and the pixel driving circuits in the even rows of the second column of pixel driving circuits are respectively connected to the first light-emitting elements in the first column of light-emitting elements; the pixel driving circuits in the odd rows of the third column of pixel driving circuits are connected to the third light-emitting elements in the odd rows of the second column of light-emitting elements, and the pixel driving circuits in the even rows of the third column of pixel driving circuits are connected to the third light-emitting elements in the even rows of the second column of light-emitting elements; the pixel driving circuits in the odd rows of the fourth column of pixel driving circuits are connected to the third light-emitting elements in the odd rows of the fourth column of light-emitting elements, and the pixel driving circuits in the even rows of the fourth column of pixel driving circuits are connected to the third light-emitting elements in the even rows of the fourth column of light-emitting elements

[0054] According to another aspect of the present invention, a display device is provided, including the display panel described in the above aspect.

[0055] In the display panel provided by the embodiment of the present invention, the four columns of pixel driving circuits in the same driving group include a column of first pixel driving circuits, a column of second pixel driving circuits, and two columns of third pixel driving circuits arranged in sequence along the row direction, and the light-emitting colors of the light-emitting elements driven by each column of pixel driving circuits are the same. This allows a second power signal line to be arranged between two adjacent columns of third pixel driving circuits, and a first power signal line to be arranged between two adjacent columns of first pixel driving circuits and second pixel driving circuits, facilitating the connection between the pixel driving circuits and the corresponding power signal lines and simplifying the layout structure. At the same time, different numerical values of power supply voltages are set for the pixel driving circuits driving different light-emitting elements so that the power supply voltage matches different types of light-emitting elements, thereby reducing the power consumption of the screen body.

[0056] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. Description of the Drawings

[0057] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0058] Figure 1 Schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0059] Figure 2 Schematic diagram of the structure of the first type of power signal line in a display panel provided by an embodiment of the present invention;

[0060] Figure 3 Schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0061] Figure 4 Schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0062] Figure 5 Cross-sectional view of another display panel provided by an embodiment of the present invention;

[0063] Figure 6 Schematic diagram of the structure of a pixel driving circuit provided by an embodiment of the present invention;

[0064] Figure 7 Schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0065] Figure 8 Schematic diagram of the layout structure of a display panel provided by an embodiment of the present invention;

[0066] Figure 9 Schematic diagram of the arrangement of light-emitting elements in a display panel provided by an embodiment of the present invention;

[0067] Figure 10 Schematic diagram of the connection relationship between a pixel driving circuit and a light-emitting element in a display panel provided by an embodiment of the present invention;

[0068] Figure 11 Schematic diagram of the layout of the connection relationship between a driving array layer and a light-emitting element in a display panel provided by an embodiment of the present invention;

[0069] Figure 12 Schematic diagram of the structure of a display device provided by an embodiment of the present invention. Detailed implementation manners

[0070] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0071] It should be noted that the terms "first", "second", etc. in the specification, claims and above-mentioned drawings of the present invention are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0072] As described in the background art, the existing screen has a relatively large power consumption. After research by the inventor, it is found that the reason is that the light-emitting elements of different light-emitting colors in the display panel are usually driven by the same positive power supply signal to achieve the display effect, thereby resulting in a relatively large power consumption. Specifically, at the same display brightness value DBV and the same gray scale, the magnitudes of the operating voltages (the voltage differences across the light-emitting elements) required by the light-emitting elements of different light-emitting colors are different. If the positive power supply voltages corresponding to the light-emitting elements of different light-emitting colors are the same, in order to meet the requirements of the light-emitting elements with a larger operating voltage, all the light-emitting elements need to be provided with a power supply voltage with a larger absolute value, resulting in a relatively large power consumption loss of the screen.

[0073] In view of the above technical problems, the embodiments of the present invention provide a display panel to provide different power supply voltages for light-emitting elements of different colors, thereby reducing the power consumption of the display panel.

[0074] Figure 1 The following is a schematic structural diagram of a display panel provided by an embodiment of the present invention. Refer to Figure 1 , the display panel includes:

[0075] A substrate;

[0076] A driving array layer located on one side of the substrate. The driving array layer includes a plurality of pixel driving circuits arranged in an array. The light-emitting elements driven by the pixel driving circuits in the same column have the same light-emitting color. Along the row direction X, every four columns of pixel driving circuits form a driving group 10, and the arrangement modes of the pixel driving circuits in each driving group 10 are the same. The four columns of pixel driving circuits in the same driving group 10 include a column of first pixel driving circuits, a column of second pixel driving circuits, and two columns of third pixel driving circuits arranged in sequence along the row direction X. Among them, the colors of the light-emitting elements driven by the first pixel driving circuits, the second pixel driving circuits, and the third pixel driving circuits are all different;

[0077] The driving array layer further includes a plurality of first - type power signal lines extending along the column direction Y and arranged along the row direction X. Each driving group 10 is correspondingly connected to two first - type power signal lines 11. The two first - type power signal lines 11 connected to the same driving group 10 include a first power signal line 111 and a second power signal line 112. The first power signal line 111 is connected to each first pixel driving circuit and each second pixel driving circuit in the corresponding driving group 10, and is used to provide a first power voltage. The second power signal line 112 is connected to each third pixel driving circuit in the corresponding driving group 10, and is used to provide a second power voltage. The first power voltage and the second power voltage are different.

[0078] The display panel further includes a plurality of light - emitting elements with different light - emitting colors. Exemplarily, it includes a first light - emitting element, a second light - emitting element, and a third light - emitting element. The first pixel driving circuit is used to drive the first light - emitting element to emit light, the second pixel driving circuit is used to drive the second light - emitting element to emit light, and the third pixel driving circuit is used to drive the third light - emitting element to emit light. Among them, the light - emitting elements with different colors may include at least three of red light - emitting elements, green light - emitting elements, blue light - emitting elements, yellow light - emitting elements, etc. The power voltages required by the light - emitting elements with different colors are different. The driving array layer is used to form an array of pixel driving circuits for driving the light - emitting elements to emit light. The light - emitting elements are formed on the side of the driving array layer away from the substrate. The pixel driving circuits are connected to the corresponding light - emitting elements and are used to drive the light - emitting elements to emit light. The pixel driving circuit can be a conventional 7T1C circuit or other pixel driving circuits, not limited to the 7T1C circuit, and can be other circuits with changes or additions and subtractions of transistors based on the 7T1C circuit. The arrangement patterns of the pixel driving circuits in each driving group 10 are the same. Each driving group 10 includes four columns of pixel driving circuits arranged in sequence along the row direction X, namely a first - column pixel driving circuit 101, a second - column pixel driving circuit 102, a third - column pixel driving circuit 103, and a fourth - column pixel driving circuit 104. The light - emitting colors of the light - emitting elements driven by each pixel driving circuit in each column of pixel driving circuits are the same. In this embodiment, it is exemplarily shown that the first light - emitting element is a blue light - emitting element, then the first pixel driving circuit is denoted as a red pixel driving circuit R, the light - emitting color of the second light - emitting element is red, the second pixel driving circuit is denoted as a red pixel driving circuit B, the light - emitting color of the third light - emitting element is green, and the third pixel driving circuit is denoted as a green pixel driving circuit G. In other words, the light - emitting color of the light - emitting element driven by the first pixel driving circuit is blue, the light - emitting color of the light - emitting element driven by the second pixel driving circuit is red, and the light - emitting color of the light - emitting element driven by the third pixel driving circuit is green. For any row in any driving group 10, the red pixel driving circuit R, the blue pixel driving circuit B, the green pixel driving circuit G, and the green pixel driving circuit G are arranged in sequence.

[0079] For each driving group 10, the first column pixel driving circuit 101 and the second column pixel driving circuit 102 are adjacent, and a first power signal line 111 can be set between the two columns of pixel driving circuits, and the power supply voltages required by the first column pixel driving circuit 101 and the second column pixel driving circuit 102 are both provided by the first power signal line 111. The third column pixel driving circuit 103 and the fourth column pixel driving circuit 104 are adjacent, and a second power signal line 112 can be set between the two columns of pixel driving circuits, and the power supply voltages required by the third column pixel driving circuit 103 and the fourth column pixel driving circuit 104 are both provided by the second power signal line 112. In this embodiment, the power supply voltage required by the light-emitting element driven by the third pixel driving circuit is separated, and the voltage difference between the two ends of the green light-emitting element when emitting light is smaller than that of the red light-emitting element and the blue light-emitting element. Therefore, the power supply voltage of the green light-emitting element is separated, so that the value of the power supply voltage matches the light-emitting element driven by the pixel driving circuit, thereby reducing the power consumption of the screen. In conventional technology, the power supply voltage of the pixel driving circuit corresponding to the light-emitting elements of different light-emitting colors is the same, so that the voltage difference across the light-emitting elements of different light-emitting colors is the same, such as 20V. In this embodiment, different power supply voltages are provided for the pixel driving circuits corresponding to the light-emitting elements of different colors, so that the voltage difference across the red light-emitting element is 20V, the voltage difference across the blue light-emitting element is 20V, and the voltage across the green light-emitting element is 18V. Compared with the voltage difference across all light-emitting elements being 20V, the power consumption of the screen can be reduced. In this embodiment, the first pixel driving circuit and the second pixel driving circuit are exemplarily shown to correspond to the same power supply voltage. In other embodiments, the power supply voltages corresponding to the blue pixel driving circuit and the red pixel driving circuit can be separated, just like the green pixel driving circuit, that is, the red pixel driving circuit R corresponds to one power supply voltage, the blue pixel driving circuit B corresponds to another power supply voltage, and the green pixel driving circuit G corresponds to another power supply voltage.

[0080] In the display panel provided by the embodiment of the present invention, the four columns of pixel driving circuits in the same driving group include a column of first pixel driving circuits, a column of second pixel driving circuits and two columns of third pixel driving circuits arranged in sequence along the row direction, and the luminous colors of the light-emitting elements driven by each column of pixel driving circuits are the same, so that a second power signal line can be set between two adjacent columns of third pixel driving circuits, and a first power signal line can be set between two adjacent columns of first pixel driving circuits and second pixel driving circuits, which facilitates the connection between the pixel driving circuit and the corresponding power signal line and simplifies the layout structure. At the same time, different power supply voltage values ​​are set for pixel driving circuits driving different light-emitting elements, so that the power supply voltage matches different types of light-emitting elements, thereby reducing the power consumption of the screen.

[0081] Figure 2Schematic diagram of the structure of a first type of power signal line in a display panel provided by an embodiment of the present invention. Refer to Figure 2 Optionally, the first power signal line 111 is mirror-symmetrical about the first median line 1. The first pixel driving circuit and the second pixel driving circuit in any row of pixel driving circuits in the same driving group are mirror-symmetrical about the first median line 1. The first median line 1 extends along the column direction Y.

[0082] The second power signal line 112 is mirror-symmetrical about the second median line 2. The second median line 2 extends along the column direction Y. The two third pixel driving circuits in any row of pixel driving circuits in the same driving group are mirror-symmetrical about the second median line 2.

[0083] For any row of pixel driving circuits in the same driving group, the first pixel driving circuit and the second pixel driving circuit are adjacent and mirror-designed, that is, the first column pixel driving circuit and the second column pixel driving circuit are mirror-designed about the first median line 1. The two third pixel driving circuits are adjacent and mirror-designed, that is, the third column pixel driving circuit and the fourth column pixel driving circuit are mirror-designed about the second median line 2, which is convenient for vertically separating the power signal lines providing different power supply voltages in the driving array layer.

[0084] Optionally, the vertical projection of the first pixel driving circuit on the substrate overlaps at least partially with the vertical projection of the first power signal line 111 connected to the first pixel driving circuit on the substrate.

[0085] The vertical projection of the second pixel driving circuit on the substrate overlaps at least partially with the vertical projection of the first power signal line 111 connected to the second pixel driving circuit on the substrate.

[0086] The vertical projection of the third pixel driving circuit on the substrate overlaps at least partially with the vertical projection of the second power signal line 112 connected to the third pixel driving circuit on the substrate.

[0087] The vertical projection of each pixel driving circuit on the substrate overlaps at least partially with the projection of the power signal line corresponding to the pixel driving circuit on the substrate, which can save layout space, is beneficial to reducing the size of the display panel. At the same time, it is convenient for the pixel driving circuit and the power signal line to be directly connected through vias and other means, reducing the number of connection traces and simplifying the layout structure.

[0088] Figure 3 Schematic diagram of another structure of a display panel provided by an embodiment of the present invention. Refer to Figure 3 The driving array layer further includes: a plurality of second type power signal lines 12 extending along the row direction X and arranged along the column direction Y. The plurality of second type power signal lines 12 include: a plurality of third power signal lines 121 and a plurality of fourth power signal lines 122.

[0089] Each first power supply signal line 111 is connected to each third power supply signal line 121;

[0090] Each second power supply signal line 112 is connected to each fourth power supply signal line 122.

[0091] The first type of power supply signal lines 11 extend along the column direction, and the second type of power supply signal lines 12 extend along the row direction X. Each first power supply signal line 111 is connected to each third power supply signal line 121, so that the signal lines for transmitting the first power supply voltage form a mesh structure, reducing the transmission resistance when transmitting the first power supply voltage, and thus reducing the voltage drop (IR Drop). After the IR Drop of the first power supply voltage is reduced, the difference between the first power supply voltage output at the driving chip end and the first power supply voltage received at the pixel driving circuit end is reduced, thereby reducing the first power supply voltage output at the driving chip end, and further reducing the power consumption of the display panel. Similarly, each second power supply signal line 112 is connected to each fourth power supply signal line 122, so that the signal lines for transmitting the second power supply voltage form a mesh structure, reducing the transmission resistance when transmitting the second power supply voltage, and thus reducing the second power supply voltage output at the driving chip end, and reducing the power consumption of the display panel. The number of the third power supply signal lines 121 and the number of the fourth power supply signal lines 122 in the display panel can be set according to requirements. In an optional implementation manner, one third power supply signal line 121 and one fourth power supply signal line 122 can be correspondingly set for each row of pixel driving circuits, or at least one third power supply signal line 121 and one fourth power supply signal line 122 can be correspondingly set for at least two adjacent rows of pixel driving circuits. The more the number of the second type of power supply signal lines 12, the smaller the transmission resistance, which is more conducive to reducing the power consumption of the display panel, but it will also result in more traces in the display panel and a more complex layout. The fewer the number of the second type of power supply signal lines 12, the greater the transmission resistance, and the weaker the ability to reduce the power consumption of the display panel, but it will make the traces in the display panel fewer and the layout simpler. Therefore, the second type of power supply signal lines 12 can be laid out according to actual requirements. Each first power supply signal line 111 is connected to each third power supply signal line 121. In an optional implementation manner, each third power supply signal line 121 is connected to the corresponding first power supply signal line 111 at each first intersection point, and the first intersection point is the overlapping part of the vertical projection of the first power supply signal line 111 on the substrate and the vertical projection of the third power supply signal line 121 on the substrate. Similarly, each second power supply signal line 112 is connected to each fourth power supply signal line 122. In an optional implementation manner, each fourth power supply signal line 122 is connected to the corresponding second power supply signal line 112 at each second intersection point, and the second intersection point is the overlapping part of the vertical projection of the second power supply signal line 112 on the substrate and the vertical projection of the fourth power supply signal line 122 on the substrate. Each third power supply signal line 121 is connected to the corresponding first power supply signal line 111 at each first intersection point, and each fourth power supply signal line 122 is connected to the corresponding second power supply signal line 112 at each second intersection point, so that the number of connection points between the first type of power supply signal lines 11 and the second type of power supply signal lines 12 is large, ensuring the connection stability and further reducing the transmission impedance of the first power supply voltage.

[0092] Figure 4 This is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Refer to Figure 4 , optionally, one row of pixel driving circuits corresponds to one second type of power supply signal line 12. Along the column direction Y, the third power supply signal line 121 and the fourth power supply signal line 122 are arranged alternately.

[0093] In the display panel, when performing layout design, the reserved space for signal lines extending along the row direction X is limited. If the number of the second type of power supply signal lines 12 is large, the distance between adjacent signal lines in the display panel is small, and it may affect the magnitude of the voltage transmitted on the signal line due to signal coupling and the like. Therefore, in this embodiment, one second type of power supply signal line 12 is provided corresponding to the position where one row of pixel driving circuits is located, that is, the number of rows of pixel driving circuits in the display panel is equal to the number of the second type of power supply signal lines 12. The odd-numbered rows of pixel driving circuits correspond to the third power supply signal line 121, and the even-numbered rows of pixel driving circuits correspond to the fourth power supply signal line 122, or the even-numbered rows of pixel driving circuits correspond to the third power supply signal line 121, and the odd-numbered rows of pixel driving circuits correspond to the fourth power supply signal line 122.

[0094] Optionally, the first type of power supply signal line 11 and the second type of power supply signal line 12 are located in different conductive layers in the driving array layer.

[0095] The first type of power supply signal line 11 and the second type of power supply signal line 12 are located in different conductive layers, so that the number of signal traces in each conductive layer is small, which is convenient for wiring and avoids the small distance between signal lines caused by all signal lines being arranged in the same layer. Among them, the first type of power supply signal line 11 and the second type of power supply signal line 12 are located in different conductive layers. When the two types of power supply signal lines need to be connected, they can be connected through vias and matching traces.

[0096] Figure 5 This is a cross-sectional view of another display panel provided by an embodiment of the present invention. Refer to Figure 4 and Figure 5 , optionally, the pixel driving circuit includes a plurality of transistors and at least one capacitor. The driving array layer 14 includes a first active layer 141, a first conductive layer 142, a second conductive layer 143, a third conductive layer 144, and a fourth conductive layer 145 that are sequentially stacked on one side of the substrate 13. The gate of at least one transistor is located in the first conductive layer 142, one electrode plate of at least one capacitor is located in the second conductive layer 143, and the source and drain of at least one transistor are both located in the third conductive layer 144.

[0097] The first active layer 141 may be a PSI layer, and the corresponding formed transistor is a low-temperature polysilicon transistor. Each conductive layer may be a metal conductive layer. The gates of the low-temperature polysilicon transistors included in the pixel driving circuit are all formed on the first conductive layer 142, and one electrode plate of the capacitor included in the display panel may also be located on the first conductive layer 142, and the other electrode plate is located on the second conductive layer 143. The sources and drains of all the transistors included in the pixel driving circuit are all formed on the third conductive layer 144, and the sources and drains are both connected to the first active layer 141 through vias. The first type of power signal lines 11, that is, the first power signal line 111 and the second power signal line 112, may both be located on the third conductive layer 144, or the first power signal line 111 and the second power signal line 112 may both be located on the fourth conductive layer 145, and the first power signal line 111 and the second power signal line 112 are located on the same layer. Figure 5 At least one insulating layer is provided between each of the conductive layers, and at least one insulating layer is also provided between the first active layer 141 and the first conductive layer 142.

[0098] Figure 5 It is exemplarily shown that the driving array layer 14 includes four conductive layers. In other embodiments, the driving array layer may include five conductive layers, that is, on the basis of Figure 5 the driving array layer 14 further includes a fifth conductive layer. The fifth conductive layer is located on the side of the fourth conductive layer 145 away from the substrate 13, and at least one insulating layer is also provided between the fourth conductive layer and the fifth conductive layer. The first type of power signal line 11 is located on any one of the third conductive layer 144, the fourth conductive layer 145, and the fifth conductive layer, that is, the first power signal line 111 is located on any one of the third conductive layer 144, the fourth conductive layer 145, and the fifth conductive layer. The second power signal line 112 is located on any one of the third conductive layer 144, the fourth conductive layer 145, and the fifth conductive layer, and the first power signal line 111 and the second power signal line 112 are arranged on the same layer.

[0099] Whether it is for Figure 5 the driving array layer including four conductive layers in, or in other embodiments the driving array layer includes five conductive layers, the second type of power signal line 12 is located on any one of the first conductive layer 142, the second conductive layer 143, and the third conductive layer 144. Specifically, both the third power signal line 121 and the fourth power signal line 122 are located on any one of the first conductive layer 142, the second conductive layer 143, and the third conductive layer 144, and the third power signal line 121 and the fourth power signal line 122 are arranged on the same layer.

[0100] Or, referring to Figure 4 and Figure 5, the driving array layer 14 further includes a second active layer 146 and a sixth conductive layer 147 located between the second conductive layer 143 and the third conductive layer 144. The second active layer 146 is located on the side of the sixth conductive layer 147 closer to the substrate 13. Among them, at least one insulating layer is provided between the second conductive layer 143 and the second active layer 146, and at least one insulating layer is provided between the sixth conductive layer 147 and the third conductive layer 144. The plurality of transistors include low-temperature polysilicon transistors and oxide transistors. The gate of the oxide transistor is located on the sixth conductive layer 147, the gate of the low-temperature polysilicon transistor is located on the first conductive layer 142, and the second type of power signal line 12 is located on any one of the first conductive layer 142, the second conductive layer 143, the third conductive layer 144, and the sixth conductive layer 147. Both the third power signal line 121 and the fourth power signal line 122 are located on any one of the first conductive layer 142, the second conductive layer 143, the third conductive layer 144, and the sixth conductive layer 147. The fourth power signal line 122 is located on any one of the first conductive layer 142, the second conductive layer 143, the third conductive layer 144, and the sixth conductive layer 147. The third power signal line 121 and the fourth power signal line 122 are arranged on the same layer.

[0101] Figure 6 It is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present invention. Figure 6Among them, the pixel driving circuit includes a driving transistor T0, a data writing transistor T1, a compensating transistor T2, a first initialization transistor T3, a second initialization transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a storage capacitor Cst. The first light-emitting control transistor T5, the driving transistor T0, and the second light-emitting control transistor T6 are sequentially connected in series between the first type of power supply signal line and the third type of power supply signal line. In this embodiment, the pixel driving circuit exemplarily shown is the second pixel driving circuit. If it is a pixel driving circuit for driving a red light-emitting element to emit light, the first type of power supply signal line provides a first power supply voltage VDDRB, the third type of power supply signal line provides a third power supply voltage VSS, and the corresponding data line provides a data voltage VdataR corresponding to the red light-emitting element. The first pole of the data writing transistor T1 is connected to the data line Data for providing the data voltage, the second pole is connected to the first pole of the driving transistor T0, the compensating transistor T2 is connected between the gate and the second pole of the driving transistor T0, the first pole of the first initialization transistor T3 is connected to the first initialization signal line for transmitting the second initialization voltage Vref2, the second pole is connected to the gate of the driving transistor T0, and the first pole of the second initialization transistor T4 is connected to the second initialization signal line for transmitting the first initialization voltage Vref1, and the second pole is connected to the first pole of the light-emitting element. The gate of the data writing transistor T1 is connected to the first scan signal S1, the gate of the compensating transistor T2 is connected to the second scan signal S2, the gate of the first initialization transistor T3 is connected to the third scan signal S3, the gate of the second initialization transistor T4 is connected to the fourth scan signal S4, and the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are connected to the light-emitting control signal EM. Figure 6 Among them, the driving transistor M0, the data writing transistor T1, the second initialization transistor T4, the first light-emitting control transistor T5, and the second light-emitting control transistor T6 are all low-temperature polysilicon transistors, and further are PMOS transistors. The first initialization transistor T3 and the compensating transistor T2 are both oxide transistors, and further are NMOS transistors to reduce leakage current. Figure 5 The low-temperature polysilicon transistor shown among them can be the second light-emitting control transistor T6 or the second initialization transistor T4, and the oxide transistor can be the compensating transistor T2 or the first initialization transistor T3. Figure 5 Taking the low-temperature polysilicon transistor as the second light-emitting control transistor T6 and the oxide transistor as the compensating transistor T2 as an example. The pixel driving circuit included in the display panel in this embodiment can also be other types of pixel driving circuits in addition to 7T1C, and no specific limitation is made here.

[0102] Figure 7 This is a schematic structural diagram of another display panel provided by an embodiment of the present invention. Refer to Figure 6 and Figure 7, optionally, the driving array layer further includes:

[0103] Multiple first - type initialization signal lines 15 extending along the row direction X and arranged along the column direction Y. Any one of the first - type initialization signal lines 15 is used to provide a first initialization voltage Vref1 to the light - emitting element and / or a second initialization voltage Vref2 to the gate of the driving transistor T0 of the pixel driving circuit;

[0104] Multiple second - type initialization signal lines 16 extending along the column direction Y and arranged along the row direction X. Any one of the second - type initialization signal lines 16 is used to provide a first initialization voltage Vref1 to the light - emitting element and / or a second initialization voltage Vref2 to the gate of the driving transistor T0 of the pixel driving circuit;

[0105] The first - type initialization signal lines 15 and the second - type initialization signal lines 16 that provide the same voltage are connected.

[0106] In an optional implementation manner, the first - type initialization signal lines 15 can only provide the first initialization voltage, and the second - type initialization signal lines 16 can only provide the second initialization voltage, or the first - type initialization signal lines only provide the second initialization voltage, and the second - type initialization signal lines only provide the first initialization voltage. When the first initialization voltage and the second initialization voltage are different, at this time, any one of the first - type initialization signal lines 15 and any one of the second - type initialization signal lines 6 are not connected. In other optional implementation manners, the first - type initialization signal lines 15 include a first initialization signal line 151 and a second initialization signal line 152, the second - type initialization signal lines 16 include a third initialization signal line 161 and a fourth initialization signal line 162, the first initialization voltage Vref1 and the second initialization voltage Vref2 are different. Some of the first - type initialization signal lines, such as the first initialization signal line 151, are used to provide the first initialization voltage Vref1, some of the first - type initialization signal lines, such as the second initialization signal line 152, are used to provide the second initialization voltage Vref2, some of the second - type initialization signal lines 16, such as the third initialization signal line 161, are used to provide the first initialization voltage Vref1, and some of the second - type initialization signal lines 16, such as the fourth initialization signal line 162, are used to provide the second initialization voltage Vref1. At this time, the first - type initialization signal lines 15 and the second - type initialization signal lines 16 that provide the first initialization voltage Vref1 are connected to form a mesh structure of signal lines for transmitting the first initialization voltage Vref1, and the first - type initialization signal lines 15 and the second - type initialization signal lines 16 that provide the same second initialization voltage Vref2 are connected to form a mesh structure of signal lines for transmitting the second initialization voltage Vref2, reducing the transmission resistance, and further reducing the power consumption of the display panel.

[0107] Alternatively, the first initialization voltage Vref1 is the same as the second initialization voltage Vref1, and each first type of initialization signal line 15 and each second type of initialization signal line 16 are connected. Specifically, each first type of initialization signal line 15 is connected to each second type of initialization signal line 16 at each third intersection point, so that there are more connection points between the first type of initialization signal line 15 and the second type of initialization signal line 16, ensuring connection stability and further reducing the transmission resistance. The third intersection point is the overlapping part of the vertical projection of the first type of initialization signal line 15 on the substrate and the vertical projection of the second type of initialization signal line 16 on the substrate.

[0108] Optionally, the first type of initialization signal line 15 and the second type of initialization signal line 16 are located in different conductive layers in the driving array layer, so that the number of traces arranged in each conductive layer is small, facilitating layout.

[0109] Reference Figure 5 and Figure 7 For example, the second type of initialization signal line 16 is located in the third conductive layer 144 or the fourth conductive layer 145. Alternatively, the driving array layer further includes a fifth conductive layer, and the second type of initialization signal line 16 is located in any one of the third conductive layer 144, the fourth conductive layer 145, and the fifth conductive layer 146. The first type of initialization signal line 15 is located in any one of the first conductive layer 142, the second conductive layer 143, and the third conductive layer 144. Alternatively, the driving array layer further includes a second active layer 146 and a sixth conductive layer 147, and the first type of initialization signal line 15 is located in any one of the first conductive layer 142, the second conductive layer 143, the third conductive layer 144, and the sixth conductive layer 147.

[0110] Figure 8 FIG. [X] is a schematic layout structure diagram of a display panel provided by an embodiment of the present invention. Referring to Figure 8 FIG. [X], the driving array layer further includes a plurality of fifth power signal lines 171 extending along the row direction X and arranged along the column direction Y, and a plurality of sixth power signal lines 181 extending along the column direction Y and arranged along the row direction X. Each fifth power signal line 171 is connected to each sixth power signal line 181, and the fifth power signal line 171 and / or the sixth power signal line 181 is connected to the second electrode of the light-emitting element.

[0111] Exemplarily, a fifth power supply signal line 171 may be correspondingly provided for the area where a row of pixel driving circuits is located, and a sixth power supply signal line 181 may be correspondingly provided for the area where a column of pixel driving circuits is located. Alternatively, a fifth power supply signal line 171 may be correspondingly provided for the area where at least two rows of pixel driving circuits are located, and a sixth power supply signal line 181 may be correspondingly provided for the area where at least two columns of pixel driving circuits are located. Each fifth power supply signal line 171 is connected to the corresponding sixth power supply signal line 181 at each fourth intersection point to form a mesh structure of signal lines for transmitting the third power supply voltage, reducing the transmission resistance, so as to reduce the power consumption of the screen body. Among them, the overlapping part of the vertical projection of the fifth power supply signal line 171 on the substrate and the vertical projection of the sixth power supply signal line 181 on the substrate is the fourth intersection point.

[0112] As Figure 5 shown, the display panel further includes:

[0113] A light-emitting element layer, located on the side of the driving array layer 14 away from the substrate 13, the light-emitting element layer includes a plurality of light-emitting elements arranged in an array, and each light-emitting element includes a first electrode 191, a light-emitting functional layer, and a second electrode stacked in sequence. The first electrodes 191 of each light-emitting element are insulated from each other; the first electrode 191 may be the anode of the light-emitting element, the second electrode is the cathode of the light-emitting element, and the second electrode is a whole-layer structure. In this embodiment, in addition to the second electrode, additionally providing the fifth power supply signal line 171 and the sixth power supply signal line 181 can further reduce the transmission resistance of the third power supply voltage VSS, and further reduce the power consumption of the screen body.

[0114] Optionally, the sixth power supply signal line 181 is located in the third conductive layer 144 or the fourth conductive layer 145,

[0115] Or, the driving array layer further includes a fifth conductive layer 146, and the sixth power supply signal line 181 is located in any one of the third conductive layer 144, the fourth conductive layer 145, and the fifth conductive layer 146; the fifth power supply signal line 171 is located in any one of the first conductive layer 142, the second conductive layer 143, and the third conductive layer 144, or the driving array layer further includes a second active layer 146 and a sixth conductive layer 147 located between the second conductive layer 143 and the third conductive layer 144, and the fifth power supply signal line 171 is located in any one of the first conductive layer 142, the second conductive layer 143, the third conductive layer 144, and the sixth conductive layer 147.

[0116] Optionally, as Figure 8As shown, the first power supply signal line 111, the second power supply signal line 112, the second type of initialization signal line 16, and the sixth power supply signal line 181 are all located in the fourth conductive layer 145. The second power supply signal line 121 and the third power supply signal line 122 are both located in the third conductive layer 144. The light emission control signal line 148 that provides the light emission control signal EM is also located in the third conductive layer 144. The scan signal lines that provide each scan signal are also all located in the third conductive layer 144. Figure 8 Only the first scan signal line 149 that provides the first scan signal S1 is exemplarily shown in Figure 8 . The first type of initialization signal line 16 and the fifth power supply signal line 171 are both located in the second conductive layer 143. When signal lines located in different layers need to be connected, they are connected through vias 3.

[0117] Reference Figure 7 and Figure 8 , the driving array layer includes a plurality of first connection lines. The plurality of first connection lines include each first type of initialization signal line 15 and each fifth power supply signal line 171. One first connection line is provided corresponding to each row of pixel driving circuits, that is, the first connection lines are provided in one-to-one correspondence with the rows of pixel driving circuits, and the number of first connection lines is equal to the number of rows of pixel driving circuits.

[0118] Along the column direction Y, the first type of initialization signal line 15 and the fifth power supply signal line 171 are alternately arranged.

[0119] Since the layout space reserved for signal lines in each layer of the display panel is limited, considering the layout space of signal lines and the size of the transmission resistance comprehensively, the first connection lines are provided in one-to-one correspondence with the rows of pixel driving circuits, so that when laying signal lines in the limited layout space, the transmission resistance for transmitting a certain voltage will not be too large. Along the column direction Y, the first type of initialization signal line 15 and the fifth power supply signal line 171 are alternately arranged, that is, if the first type of initialization signal line 15 is provided corresponding to the pixel driving circuit in the upper row, then the fifth power supply signal line 171 is provided corresponding to the pixel driving circuit in the lower row, and the first connection lines are arranged in this order in turn.

[0120] Exemplarily, when the first type of initialization signal line 15 only includes the first initialization signal line 151 that provides the first initialization voltage Vref1, the first connection line correspondingly set for the pixel driving circuit of the odd rows is the first initialization signal line 151, and the first connection line correspondingly set for the row driving circuit of the even rows is the fifth power supply signal line 171. Or, the first connection line correspondingly set for the pixel driving circuit of the even rows is the first initialization signal line 151, and the first connection line correspondingly set for the pixel driving circuit of the odd rows is the fifth power supply signal line 171. When the first type of initialization signal line 15 only includes the second initialization signal line 152 that provides the second initialization voltage Vref2, the first connection line correspondingly set for the pixel driving circuit of the odd rows is the second initialization signal line 152, and the first connection line correspondingly set for the row driving circuit of the even rows is the fifth power supply signal line 171. Or, the first connection line correspondingly set for the pixel driving circuit of the even rows is the second initialization signal line 152, and the first connection line correspondingly set for the pixel driving circuit of the odd rows is the fifth power supply signal line 171.

[0121] Optionally, the multiple first type of initialization signal lines 15 include multiple first initialization signal lines 151 and multiple second initialization signal lines 152. The first initialization signal line 151 is used to provide the first initialization voltage Vref1, and the second initialization signal line 152 is used to provide the second initialization voltage Vref2;

[0122] Along the column direction Y, the first initialization signal line 151 and the second initialization signal line 152 are alternately arranged.

[0123] Since the first type of initialization signal line 15 and the fifth power supply signal line 171 are alternately arranged, and the first initialization signal line 151 and the second initialization signal line 152 are also alternately arranged, therefore, every four first connection lines along the column direction form a first repeated routing unit, and the sorting of each routing in each first repeated routing unit is the same. Exemplarily, for any first repeated routing unit, along the column direction, the four first connection lines are successively the first initialization signal line 151, the fifth power supply signal line 171, the second initialization signal line 152, and the fifth power supply signal line 171, or the four first connection lines are successively the second initialization signal line 152, the fifth power supply signal line 171, the first initialization signal line 151, and the fifth power supply signal line 171, or successively the fifth power supply signal line 171, the first initialization signal line 151, the fifth power supply signal line 171, the second initialization signal line 152, or successively the fifth power supply signal line 171, the second initialization signal line 152, the fifth power supply signal line 171, the first initialization signal line 151.

[0124] Optionally, the driving array layer includes multiple second connection lines, and the multiple second connection lines include each second type of initialization signal line 16 and each sixth power supply signal line 181;

[0125] A second connection line is arranged between every two adjacent first-type power signal lines;

[0126] Along the row direction X, the second-type initialization signal lines 16 and the sixth power signal lines 181 are alternately arranged.

[0127] Since the layout space reserved for the signal lines extending along the column direction Y in the display panel is limited, arranging a second connection line between every two adjacent first-type power signal lines can save the number of signal lines extending along the column direction Y and simplify the layout. When the second-type initialization signal lines 16 only include the third initialization signal lines 161 for providing the first initialization voltage Vref1 or only include the fourth initialization signal lines 162 for providing the second initialization voltage Vref2, along the row direction X, every two second connection lines form a second repeated routing unit, and the routing order of each routing line in each second repeated routing unit is the same. Exemplarily, for any second repeated routing unit, along the row direction X, the two first connection lines are the third initialization signal line 161 and the sixth power signal line 181 in sequence, or the sixth power signal line 181 and the third initialization signal line 161. When the second-type initialization signal lines 16 only include the fourth initialization signal lines 162 for providing the second initialization voltage Vref2, for any second repeated routing unit, along the row direction X, the two first connection lines are the fourth initialization signal line 162 and the sixth power signal line 181 in sequence, or the sixth power signal line 181 and the fourth initialization signal line 162.

[0128] Optionally, the multiple second-type initialization signal lines 16 include multiple third initialization signal lines 161 and multiple fourth initialization signal lines 162, the third initialization signal lines 161 are used to provide the first initialization voltage Vref1, and the fourth initialization signal lines 162 are used to provide the second initialization voltage Vref2;

[0129] Along the row direction X, the third initialization signal lines 161 and the fourth initialization signal lines 162 are alternately arranged.

[0130] Since the second type of initialization signal lines 16 and the sixth power supply signal lines 181 are arranged alternately, and the third initialization signal lines 161 and the fourth initialization signal lines 162 are arranged alternately, therefore, every four second connection lines along the row direction X form a second repeated routing unit, and the routing order of each routing line in each second repeated routing unit is the same. Exemplarily, for any second repeated routing unit, along the row direction X, the four second connection lines are the third initialization signal line 161, the sixth power supply signal line 181, the fourth initialization signal line 162, and the sixth power supply signal line 181 in sequence, or the four second connection lines are the fourth initialization signal line 162, the sixth power supply signal line 181, the third initialization signal line 161, and the sixth power supply signal line 181 in sequence, or are the sixth power supply signal line 181, the third initialization signal line 161, the sixth power supply signal line 181, the fourth initialization signal line 162, or are the sixth power supply signal line 181, the fourth initialization signal line 162, the sixth power supply signal line 181, the third initialization signal line 161.

[0131] Continue to refer to Figure 8 , optionally, the driving array layer further includes:

[0132] A plurality of data lines extending along the column direction Y, and one data line is connected to one column of pixel driving circuits.

[0133] The four data lines connected by the same driving group include the first data line 191, the second data line 192, the third data line 193, and the fourth data line 194. The first data line 191 is connected to the first column of pixel driving circuits, the second data line 192 is connected to the second column of pixel driving circuits, the third data line 193 is connected to the third column of pixel driving circuits, and the fourth data line 194 is connected to the fourth column of pixel driving circuits. The first data line 191 and the second data line 192 are respectively arranged on both sides of the first power supply signal line 111, and the third data line 193 and the fourth data line 194 are respectively arranged on both sides of the second power supply signal line 112.

[0134] A second connection line is arranged between two adjacent data lines.

[0135] The data lines are located in the third conductive layer 144 or the fourth conductive layer 145, or the driving array layer further includes a fifth conductive layer 146, and the data lines are located in any one of the third conductive layer 144, the fourth conductive layer 145, and the fifth conductive layer 146. In this embodiment, it is exemplarily shown that the data lines and the first type of power supply signal lines are located in the same layer.

[0136] The light-emitting elements driven by the pixel driving circuits corresponding to one data line all have the same light-emitting color. When the display panel displays a pure color picture such as a red picture, a blue picture, a green picture, or a white picture, the data voltage transmitted on the data line does not need to jump row by row, reducing the power consumption of the driving chip.Figure 8 Exemplarily shown for a group of driving groups, along the row direction, the sixth power supply signal line 181, the first data line 191, the first power supply signal line 111, the second data line 192, the third initialization signal line 161, the third data line 193, the second power supply signal line 112, and the fourth data line 194 are arranged in sequence.

[0137] Figure 8 Only the first scan line 149 is exemplarily shown. Along the column direction, the first initialization signal line 151, the fourth power supply signal line 122, the first scan line 149, the light emission control signal line 148, the fifth power supply signal line 171, and the third power supply signal line 121 are arranged in sequence.

[0138] Figure 9 It is a schematic diagram of the arrangement of light-emitting elements in a display panel provided by an embodiment of the present invention. Refer to Figure 9 , optionally, the display panel further includes:

[0139] A light-emitting element layer, located on the side of the driving array layer away from the substrate. The light-emitting element layer includes a plurality of light-emitting elements arranged in an array. Along the row X direction, every four columns of light-emitting elements are divided into a light-emitting element group, and the light-emitting elements in each light-emitting element group are arranged in the same way;

[0140] Among the first column of light-emitting elements in the same light-emitting element group, the light-emitting elements located in even rows are the first light-emitting elements, and the light-emitting elements located in odd rows are the second light-emitting elements. The second column of light-emitting elements and the fourth column of light-emitting elements in the same light-emitting element group are both the third light-emitting elements. Among the third column of light-emitting elements in the same light-emitting element group, the light-emitting elements located in even rows are the second light-emitting elements, and the light-emitting elements located in odd rows are the first light-emitting elements.

[0141] Among them, the light-emitting colors of the first light-emitting element, the second light-emitting element, and the third light-emitting element are all different.

[0142] For the light-emitting elements located in odd rows, along the row direction X, the light-emitting colors of adjacent light-emitting elements are different. In this embodiment, it is exemplarily shown that the light-emitting color of the first light-emitting element is blue, the light-emitting color of the second light-emitting element is red, and the light-emitting color of the third light-emitting element is green. The light-emitting elements are arranged in a tripod shape, improving the display effect of the display panel.

[0143] Figure 10 It is a schematic diagram of the connection relationship between the pixel driving circuit and the light-emitting elements in a display panel provided by an embodiment of the present invention. Figure 11 It is a layout schematic diagram of the connection relationship between the driving array layer and the light-emitting elements in a display panel provided by an embodiment of the present invention. Refer to Figure 10 and Figure 11, each driving group is connected to each light-emitting element group in a one-to-one correspondence. For the corresponding driving group and light-emitting element group, the pixel driving circuits in the odd rows of the first column pixel driving circuit 101 are respectively connected to the second light-emitting elements in the first column of light-emitting elements, and the pixel driving circuits in the even rows of the first column pixel driving circuit 101 are respectively connected to the second light-emitting elements in the third column of light-emitting elements; the pixel driving circuits in the odd rows of the second column pixel driving circuit 102 are respectively connected to the first light-emitting elements in the third column of light-emitting elements, and the pixel driving circuits in the even rows of the second column pixel driving circuit 102 are respectively connected to the first light-emitting elements in the first column of light-emitting elements; the pixel driving circuits in the odd rows of the third column pixel driving circuit 103 are connected to the third light-emitting elements in the odd rows of the second column of light-emitting elements, and the pixel driving circuits in the even rows of the third column pixel driving circuit 103 are connected to the third light-emitting elements in the even rows of the second column of light-emitting elements; the pixel driving circuits in the odd rows of the fourth column pixel driving circuit 104 are connected to the third light-emitting elements in the odd rows of the fourth column of light-emitting elements, and the pixel driving circuits in the even rows of the fourth column pixel driving circuit 104 are connected to the third light-emitting elements in the even rows of the fourth column of light-emitting elements.

[0144] In this embodiment, it is exemplarily shown that in a light-emitting element group, the odd rows in the first column light-emitting element group are red light-emitting elements, and the even rows are blue light-emitting elements. The odd rows in the third column light-emitting element group are blue light-emitting elements, and the even rows are red light-emitting elements. For any driving group and any light-emitting element group, the pixel driving circuit in the first row of the first column pixel driving circuit is connected to the light-emitting element in the first row of the first column of light-emitting elements, the pixel driving circuit in the second row of the first column pixel driving circuit 101 is connected to the light-emitting element in the second row of the third column of light-emitting elements, the pixel driving circuit in the first row of the second column pixel driving circuit 102 is connected to the light-emitting element in the first row of the third column of light-emitting elements, the pixel driving circuit in the second row of the second column pixel driving circuit 102 is connected to the light-emitting element in the second row of the first column of light-emitting elements, the pixel driving circuit in the first row of the third column pixel driving circuit 103 is connected to the light-emitting element in the first row of the second column of light-emitting elements, the pixel driving circuit in the second row of the third column pixel driving circuit 103 is connected to the light-emitting element in the second row of the second column of light-emitting elements, the pixel driving circuit in the first row of the fourth column pixel driving circuit 104 is connected to the light-emitting element in the first row of the fourth column of light-emitting elements, and the pixel driving circuit in the second row of the fourth column pixel driving circuit 104 is connected to the light-emitting element in the second row of the fourth column of light-emitting elements.

[0145] If the arrangement of the light-emitting elements in the light-emitting element layer is the same as that of the pixel driving circuit that drives the light-emitting elements of the underlying layer, when forming the light-emitting elements using a mask plate, the mask plate needs to form strip-shaped gaps extending in the column direction, which requires strict preparation processes for the mask plate, and the performance of the light-emitting elements formed using the mask plate of the above shape is poor. Therefore, the light-emitting elements on the upper layer of the driving array layer adopt a tripod layout, so that the process requirements for the mask plate are lower when the mask plate forms the light-emitting elements, and the performance of the formed light-emitting elements is excellent.

[0146] An embodiment of the present invention further provides a display device. Figure 12 It is a schematic structural diagram of a display device provided by an embodiment of the present invention. Refer to Figure 12 , this display device includes the display panel in any of the above embodiments. The display device 4 can be Figure 12 the mobile phone shown in the figure, or a computer, a television, a smart wearable display device, etc. The embodiments of the present invention do not make special limitations on this.

[0147] It should be understood that various forms of the processes shown above can be used, steps can be reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in different orders, as long as the desired results of the technical solutions of the present invention can be achieved. There is no limitation herein.

[0148] The above specific implementation manners do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A display panel, characterized in that, Comprising: A substrate; A driving array layer located on one side of the substrate. The driving array layer includes a plurality of pixel driving circuits arranged in an array. The light-emitting colors of the light-emitting elements driven by the pixel driving circuits in the same column are the same. Along the row direction, every four columns of pixel driving circuits form a driving group, and the arrangement manners of the respective pixel driving circuits in each driving group are the same. The four columns of pixel driving circuits in the same driving group include a column of first pixel driving circuits, a column of second pixel driving circuits, and two columns of third pixel driving circuits arranged in sequence along the row direction. Among them, the light-emitting colors of the light-emitting elements driven by the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit are all different; The driving array layer further includes a plurality of first-type power signal lines extending along the column direction and arranged along the row direction. Each driving group is correspondingly connected to two first-type power signal lines. The two first-type power signal lines connected to the same driving group include a first power signal line and a second power signal line. The first power signal line is connected to each of the first pixel driving circuits and each of the second pixel driving circuits in the corresponding driving group, and is used to provide a first power voltage. The second power signal line is connected to each of the third pixel driving circuits in the corresponding driving group, and is used to provide a second power voltage. The first power voltage and the second power voltage are different.

2. The display panel according to claim 1, wherein The light-emitting color of the light-emitting element driven by the first pixel driving circuit is blue, the light-emitting color of the light-emitting element driven by the second pixel driving circuit is red, and the light-emitting color of the light-emitting element driven by the third pixel driving circuit is green.

3. The display panel according to claim 1, wherein, The first power signal line is mirror-symmetrical about a first center line. The first pixel driving circuit and the second pixel driving circuit in any row of pixel driving circuits in the same driving group are mirror-symmetrical about the first center line. The first center line extends along the column direction; The second power signal line is mirror-symmetrical about a second center line. The second center line extends along the column direction. The two third pixel driving circuits in any row of pixel driving circuits in the same driving group are mirror-symmetrical about the second center line; Preferably, the vertical projection of the first pixel driving circuit on the substrate and the vertical projection of the first power signal line connected to the first pixel driving circuit on the substrate at least partially overlap; The vertical projection of the second pixel driving circuit on the substrate and the vertical projection of the first power signal line connected to the second pixel driving circuit on the substrate at least partially overlap; The vertical projection of the third pixel driving circuit on the substrate and the vertical projection of the second power signal line connected to the third pixel driving circuit on the substrate at least partially overlap.

4. The display panel according to claim 1, wherein The driving array layer further includes: a plurality of second-type power signal lines extending along the row direction and arranged along the column direction. Among the plurality of second-type power signal lines, there are included: a plurality of third power signal lines and a plurality of fourth power signal lines; Each of the first power signal lines is connected to each of the third power signal lines; Each of the second power signal lines is connected to each of the fourth power signal lines; Preferably, one row of pixel driving circuits corresponds to one of the second type of power signal lines. Along the column direction, the third power signal line and the fourth power signal line are arranged alternately; Preferably, the first type of power signal line and the second type of power signal line are located in different conductive layers in the driving array layer; Preferably, the pixel driving circuit includes a plurality of transistors and at least one capacitor. The driving array layer includes a first active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially stacked from one side of the substrate. The gate of at least one of the transistors is located in the first conductive layer, one plate of at least one capacitor is located in the second conductive layer, and the source and drain of at least one of the transistors are both located in the third conductive layer; Among them, the first type of power signal line is located in the third conductive layer or the fourth conductive layer. Alternatively, the driving array layer further includes a fifth conductive layer. The fifth conductive layer is located on the side of the fourth conductive layer away from the substrate, and the first type of power signal line is located in any one of the third conductive layer, the fourth conductive layer, and the fifth conductive layer; The second type of power signal line is located in any one of the first conductive layer, the second conductive layer, and the third conductive layer. Alternatively, the driving array layer further includes a second active layer and a sixth conductive layer located between the second conductive layer and the third conductive layer. The second active layer is located on the side of the sixth conductive layer close to the substrate. The plurality of transistors include low-temperature polysilicon transistors and oxide transistors. The gate of the oxide transistor is located in the sixth conductive layer, the gate of the low-temperature polysilicon transistor is located in the first conductive layer, and the second type of power signal line is located in any one of the first conductive layer, the second conductive layer, the third conductive layer, and the sixth conductive layer.

5. The display panel according to claim 1, wherein The driving array layer further includes: A plurality of first type of initialization signal lines extending along the row direction and arranged along the column direction. Any one of the first type of initialization signal lines is used to provide a first initialization voltage to the light-emitting element and / or provide a second initialization voltage to the gate of the driving transistor of the pixel driving circuit; A plurality of second type of initialization signal lines extending along the column direction and arranged along the row direction. Any one of the second type of initialization signal lines is used to provide a first initialization voltage to the light-emitting element and / or provide a second initialization voltage to the gate of the driving transistor of the pixel driving circuit; The first type of initialization signal line and the second type of initialization signal line that provide the same voltage are connected; Preferably, the first initialization voltage and the second initialization voltage are the same, and each of the first type of initialization signal lines and each of the second type of initialization signal lines are connected. Alternatively, the first initialization voltage and the second initialization voltage are different, some of the first type of initialization signal lines are used to provide the first initialization voltage, some of the first type of initialization signal lines are used to provide the second initialization voltage, some of the second type of initialization signal lines are used to provide the first initialization voltage, and some of the second type of initialization signal lines are used to provide the second initialization voltage; Preferably, the first type of initialization signal lines and the second type of initialization signal lines are located in different conductive layers of the driving array layer; Preferably, the pixel driving circuit includes a plurality of transistors and at least one capacitor. The driving array layer includes a first active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer that are sequentially stacked from one side of the substrate. The gate of at least one of the transistors is located in the first conductive layer, one electrode plate of at least one capacitor is located in the second conductive layer, and the source and drain of at least one of the transistors are both located in the third conductive layer; The second type of initialization signal lines are located in the third conductive layer or the fourth conductive layer. Alternatively, the driving array layer further includes a fifth conductive layer located on the side of the fourth conductive layer away from the substrate, and the second type of initialization signal lines are located in any one of the third conductive layer, the fourth conductive layer, and the fifth conductive layer; The first type of initialization signal lines are located in any one of the first conductive layer, the second conductive layer, and the third conductive layer. Alternatively, the driving array layer further includes a second active layer and a sixth conductive layer both located between the second conductive layer and the third conductive layer. The second active layer is located on the side of the sixth conductive layer close to the substrate. The plurality of transistors include low-temperature polysilicon transistors and oxide transistors. The gate of the oxide transistor is located in the sixth conductive layer, the gate of the low-temperature polysilicon transistor is located in the first conductive layer, and the first type of initialization signal lines are located in any one of the first conductive layer, the second conductive layer, the third conductive layer, and the sixth conductive layer.

6. The display panel according to claim 5, wherein The driving array layer further includes a plurality of fifth power signal lines extending along the row direction and arranged along the column direction, and a plurality of sixth power signal lines extending along the column direction and arranged along the row direction. Each of the fifth power signal lines is connected to each of the sixth power signal lines, and the fifth power signal line and / or the sixth power signal line is connected to the second electrode of the light-emitting element; Preferably, the sixth power signal line is located in the third conductive layer or the fourth conductive layer. Alternatively, the driving array layer further includes a fifth conductive layer, and the sixth power signal line is located in any one of the third conductive layer, the fourth conductive layer, and the fifth conductive layer; the fifth power signal line is located in any one of the first conductive layer, the second conductive layer, and the third conductive layer. Alternatively, the driving array layer further includes a second active layer and a sixth conductive layer between the second conductive layer and the third conductive layer, and the fifth power signal line is located in any one of the first conductive layer, the second conductive layer, the third conductive layer, and the sixth conductive layer; Preferably, the display panel further includes: a light-emitting element layer located on a side of the driving array layer away from the substrate. The light-emitting element layer includes a plurality of light-emitting elements arranged in an array. Each light-emitting element includes a first electrode, a light-emitting functional layer, and a second electrode stacked in sequence. The first electrodes of the light-emitting elements are insulated from each other; Preferably, the second electrode is a whole-layer structure.

7. The display panel according to claim 6, wherein The driving array layer includes a plurality of first connection lines. The plurality of first connection lines include each of the first-type initialization signal lines and each of the fifth power signal lines. One first connection line is provided corresponding to each row of the pixel driving circuits; Along the column direction, the first-type initialization signal lines and the fifth power signal lines are alternately arranged; Preferably, the plurality of first-type initialization signal lines include a plurality of first initialization signal lines and a plurality of second initialization signal lines. The first initialization signal lines are used to provide the first initialization voltage, and the second initialization signal lines are used to provide the second initialization voltage; Along the column direction, the first initialization signal lines and the second initialization signal lines are alternately arranged; Preferably, the driving array layer includes a plurality of second connection lines. The plurality of second connection lines include each of the second-type initialization signal lines and each of the sixth power signal lines; One second connection line is provided between every two adjacent first-type power signal lines; Along the row direction, the second-type initialization signal lines and the sixth power signal lines are alternately arranged; Preferably, the plurality of second-type initialization signal lines include a plurality of third initialization signal lines and a plurality of fourth initialization signal lines. The third initialization signal lines are used to provide the first initialization voltage, and the fourth initialization signal lines are used to provide the second initialization voltage; Along the row direction, the third initialization signal lines and the fourth initialization signal lines are alternately arranged.

8. The display panel according to claim 7, characterized in that, The driving array layer further includes: a plurality of data lines extending along the column direction. One data line is connected to one column of pixel driving circuits; Preferably, the four data lines connected to the same driving group include a first data line, a second data line, a third data line, and a fourth data line. The first data line is connected to the first column of pixel driving circuits, the second data line is connected to the second column of pixel driving circuits, the third data line is connected to the third column of pixel driving circuits, and the fourth data line is connected to the fourth column of pixel driving circuits. The first data line and the second data line are respectively arranged on both sides of the first power signal line, and the third data line and the fourth data line are respectively arranged on both sides of the second power signal line; Preferably, a second connection line is arranged between two adjacent data lines.

9. The display panel according to claim 1, wherein It further includes: A light-emitting element layer, located on the side of the driving array layer away from the substrate. The light-emitting element layer includes a plurality of light-emitting elements arranged in an array. Along the row direction, every four columns of light-emitting elements are divided into a light-emitting element group, and the light-emitting elements in each light-emitting element group are arranged in the same way; Among the first column of light-emitting elements in the same light-emitting element group, the light-emitting elements located in the even rows are the first light-emitting elements, and the light-emitting elements located in the odd rows are the second light-emitting elements. The second column of light-emitting elements and the fourth column of light-emitting elements in the same light-emitting element group are both the third light-emitting elements. Among the third column of light-emitting elements in the same light-emitting element group, the light-emitting elements located in the even rows are the second light-emitting elements, and the light-emitting elements located in the odd rows are the first light-emitting elements, wherein the light-emitting colors of the first light-emitting element, the second light-emitting element, and the third light-emitting element are all different; Each driving group is connected to each light-emitting element group in a one-to-one correspondence. For the corresponding driving group and light-emitting element group, the pixel driving circuits in the odd rows of the first column of pixel driving circuits are respectively connected to the second light-emitting elements in the first column of light-emitting elements, and the pixel driving circuits in the even rows of the first column of pixel driving circuits are respectively connected to the second light-emitting elements in the third column of light-emitting elements; the pixel driving circuits in the odd rows of the second column of pixel driving circuits are respectively connected to the first light-emitting elements in the third column of light-emitting elements, and the pixel driving circuits in the even rows of the second column of pixel driving circuits are respectively connected to the first light-emitting elements in the first column of light-emitting elements; the pixel driving circuits in the odd rows of the third column of pixel driving circuits are connected to the odd-row third light-emitting elements in the second column of light-emitting elements, and the pixel driving circuits in the even rows of the third column of pixel driving circuits are connected to the even-row third light-emitting elements in the second column of light-emitting elements; the pixel driving circuits in the odd rows of the fourth column of pixel driving circuits are connected to the odd-row third light-emitting elements in the fourth column of light-emitting elements, and the pixel driving circuits in the even rows of the fourth column of pixel driving circuits are connected to the even-row third light-emitting elements in the fourth column of light-emitting elements.

10. A display device, characterized in that, It includes the display panel according to any one of claims 1-9.

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