Pixel driving circuit, pixel driving method and display equipment

Abstract

The invention discloses a pixel driving circuit, a pixel driving method and display equipment, and relates to the technical field of display, the pixel driving circuit comprises a plurality of pixel driving units arranged in a rectangle, and each pixel driving unit comprises a reset module, a charging module and a driving module. The reset module is used for pulling down the first node to a preset low potential in a reset stage; the charging module is used for charging the first node to a first voltage in a write-in stage, and the first voltage is a voltage sum of a data voltage on a data line and a to-be-counteracted threshold voltage existing in the charging module; the driving module is used for transmitting a driving voltage on a positive power supply voltage end and a real-time threshold voltage generated by the driving module into the light-emitting device based on a first voltage according to a driving signal accessed from a driving signal end in a light-emitting stage, the threshold voltage to be offset in the first voltage and the real-time threshold voltage are at least partially offset, and the threshold voltage to be offset in the second voltage and the real-time threshold voltage are at least partially offset. The display abnormity phenomenon caused by the inherent characteristics of the thin film transistor is solved.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and in particular, to a pixel driving circuit, a pixel driving method, and a display device. Background Art

[0002] In self-emitting displays, whether based on a thin-film transistor driving architecture of low-temperature polysilicon or oxide semiconductor types, display anomalies are caused by the inherent characteristics of the thin-film transistors.

[0003] Taking the thin-film transistors of low-temperature polysilicon as an example, the threshold voltage and carrier mobility thereof have non-uniform distributions, and the above parameters are directly related to the stability of the driving current of the thin-film transistors, thereby causing differences in the light-emitting intensity of the pixel units of the self-emitting display and resulting in display mottling. In addition, the hysteresis characteristic of the thin-film transistors causes the drain-source current to exhibit an asymmetric response characteristic when the gate voltage scanning direction changes, thereby inducing an afterimage phenomenon in high-frequency switching images such as checkerboards. At the same time, the threshold voltage drift phenomenon of the thin-film transistors causes fluctuations in the driving current due to changes in the working time and ambient temperature, further exacerbating the brightness non-uniformity of the displayed image. Summary of the Invention

[0004] The main purpose of the present application is to provide a pixel driving circuit, a pixel driving method, and a display device, aiming to solve the technical problem of display anomalies caused by the inherent characteristics of thin-film transistors.

[0005] To achieve the above object, the present application provides a pixel driving circuit, which includes a plurality of pixel driving units arranged in a rectangular pattern, and each pixel driving unit includes a reset module, a charging module, and a driving module;

[0006] The output terminal and the control terminal of the reset module are commonly connected to the upper-level scanning signal terminal, the input terminal of the reset module is electrically connected to the first node, and the reset module is used to pull down the first node to a preset low potential during the reset stage;

[0007] The input terminal of the charging module is connected to the data line, the control terminal of the charging module is connected to the current-level scanning line, the output terminal of the charging module is electrically connected to the first node, and the charging module is used to charge the first node to a first voltage during the writing stage, where the first voltage is the sum of the data voltage on the data line and the threshold voltage to be offset existing in the charging module;

[0008] The input terminals of the driving module are respectively connected to the first node and the positive power supply voltage terminal, the control terminal of the driving module is connected to the driving signal terminal, the output terminal of the driving module is connected to the light-emitting device, and the driving module is used to transmit, in the light-emitting stage, based on the first voltage, the driving voltage on the positive power supply voltage terminal, and the real-time threshold voltage generated by the driving module, into the light-emitting device, wherein at least part of the threshold voltage to be canceled in the first voltage cancels the real-time threshold voltage.

[0009] In one embodiment, a storage capacitor is provided in the pixel driving unit, the first node is located on the first capacitor terminal of the storage capacitor, and the reset module includes a first transistor;

[0010] The control terminal and the input terminal of the first transistor are respectively connected to the upper-level scanning signal terminal, and the output terminal of the first transistor is connected to the first capacitor terminal.

[0011] In one embodiment, the charging module includes a second transistor, a third transistor, and a fourth transistor;

[0012] The control terminal of the second transistor is connected to the current-level scanning line, the input terminal of the second transistor is connected to the data line, and the output terminal of the second transistor is connected to the output terminal of the third transistor;

[0013] The input terminal of the third transistor is connected to the input terminal of the fourth transistor, and the control terminal of the third transistor and the output terminal of the fourth transistor are commonly connected to the first capacitor terminal;

[0014] The control terminal of the fourth transistor is connected to the current-level scanning signal terminal.

[0015] In one embodiment, the driving module includes a fifth transistor, a third transistor, and a sixth transistor;

[0016] The control terminal of the fifth transistor is connected to the driving signal terminal, the input terminal of the fifth transistor is connected to the positive power supply voltage terminal, and the output terminal of the fifth transistor is connected to the input terminal of the third transistor;

[0017] The control terminal of the sixth transistor is connected to the driving signal terminal, the input terminal of the sixth transistor is connected to the output terminal of the third transistor, and the output terminal of the sixth transistor is connected to the positive electrode of the light-emitting device;

[0018] The second capacitor terminal of the storage capacitor is connected to the connection line between the fifth transistor and the positive power supply voltage terminal.

[0019] In one embodiment, the pixel driving unit further includes a timing control module;

[0020] The control terminal of the timing control module is respectively connected to the current-level scanning signal terminal and the upper-level scanning signal terminal, the input terminal of the timing control module is connected to the high-level voltage terminal, and the output terminal of the timing control module is connected to the low-level voltage terminal;

[0021] A timing control module is configured to adjust the level state of an output driving signal according to the signal level states of a local scanning signal terminal and a previous-stage scanning signal terminal.

[0022] In one embodiment, the timing control module includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

[0023] The control end of the seventh transistor is connected to the local scanning signal terminal, the control end of the eighth transistor is connected to the previous-stage scanning signal terminal, the input ends of the seventh transistor and the eighth transistor are commonly connected to a high-level voltage terminal, and the output ends of the seventh transistor and the eighth transistor are commonly connected to the input end of the ninth transistor;

[0024] The output end of the ninth transistor is connected to the input end of the tenth transistor, and the control end of the ninth transistor is connected to the local scanning signal terminal;

[0025] The output end of the tenth transistor is connected to a low-level voltage terminal, and the control end of the tenth transistor is connected to the previous-stage scanning signal terminal;

[0026] Wherein, the driving signal terminal is led out from the connection line between the seventh transistor and the eighth transistor and the ninth transistor.

[0027] In one embodiment, the pixel driving units on the same scanning line are connected to the same timing control module.

[0028] In addition, to achieve the above object, the present application also proposes a pixel driving method, which is applied to the pixel driving circuit as described above. The pixel driving circuit includes a plurality of pixel driving units arranged in a rectangular array, and each pixel driving unit includes a reset module, a charging module, and a driving module;

[0029] The pixel driving method includes:

[0030] In the reset stage, after pulling down the first node to a preset low potential through the reset module, enter the writing stage;

[0031] Control the charging module to write the data voltage on the data line and the threshold voltage to be offset existing in the charging module into the first node, and after charging the first node to a first voltage, enter the light-emitting stage;

[0032] Based on the driving module connected to the driving signal, transmit the first voltage, the driving voltage on the positive power supply voltage terminal, and the real-time threshold voltage generated by the driving module into the light-emitting device, wherein at least part of the threshold voltage to be offset in the first voltage cancels out with the real-time threshold voltage.

[0033] In one embodiment, the pixel driving unit further includes a timing control module, and the timing control module includes the following steps before the step of driving the driving module connected to the driving signal:

[0034] Based on the previous level scanning signal connected to the high level state and the current level scanning signal in the high level state, a driving signal in the low level state is generated, and the driving signal in the low level state is transmitted to the driving module to control the driving module to drive the light-emitting device to emit light.

[0035] In addition, to achieve the above objectives, the present application also proposes a display device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the pixel driving method as described above.

[0036] One or more technical solutions proposed in this application have at least the following technical effects:

[0037] A pixel driving circuit is proposed, which includes a plurality of pixel driving units arranged in a rectangular shape, each pixel driving unit includes a reset module, a charging module and a driving module. The output end and the control end of the reset module are connected to the previous level scanning signal end, the input end of the reset module is electrically connected to the first node, and the reset module is used to pull down the first node to a preset low potential in the reset stage; the input end of the charging module is connected to the data line, the control end of the charging module is connected to the current level scanning line, the output end of the charging module is electrically connected to the first node, and the charging module is used to charge the first node to a first voltage in the writing stage, wherein the first voltage is the sum of the data voltage on the data line and the voltage of the threshold voltage to be offset in the charging module; the input end of the driving module is connected to the first node and the positive power supply voltage end respectively, the control end of the driving module is connected to the driving signal end, the output end of the driving module is connected to the light-emitting device, and the driving module is used to transmit the first voltage, the driving voltage on the positive power supply voltage end and the real-time threshold voltage generated by the driving module to the light-emitting device according to the driving signal connected from the driving signal end in the light-emitting stage, wherein the threshold voltage to be offset in the first voltage and the real-time threshold voltage are at least partially offset.

[0038] That is, in this embodiment, through the reset module provided, before pixel driving, the potential on the first node of the pixel driving unit on the same scanning line is reset to a preset low potential, so as to offset the hysteresis characteristic of the thin film transistor, ensure that when the upper-level voltage changes in different directions, the change curves of the corresponding drain-source currents can coincide, thereby improving the display uniformity and suppressing the ghosting phenomenon; in addition, through the charging module, an additional threshold voltage to be offset is generated before the pixel emits light, and when the pixel is driven to emit light through the driving module, the additional threshold voltage to be offset is provided to the light-emitting device, so that it can at least partially offset the real-time threshold voltage existing when driving the light-emitting device to emit light, and to a certain extent reduce or eliminate the abnormal display reaction caused by the threshold voltage, that is, to solve the display abnormal phenomenon caused by the hysteresis and the inherent characteristic of the threshold voltage of the thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0041] Figure 1 It is a schematic flowchart provided for an embodiment of the pixel driving method of the present application;

[0042] Figure 2 It is a schematic diagram of the change curves of the gate voltage and the drain-source current in a conventional pixel driving unit;

[0043] Figure 3 It is a display schematic diagram when displaying a checkerboard-type image based on a conventional pixel driving unit;

[0044] Figure 4 It is a module schematic diagram of any pixel driving unit in the pixel driving circuit of the present application;

[0045] Figure 5 It is a structural schematic diagram of the pixel driving unit of the present application;

[0046] Figure 6 It is a structural schematic diagram of a conventional pixel driving circuit;

[0047] Figure 7 It is a control timing schematic diagram of the pixel driving unit of the present application;

[0048] Figure 8Schematic diagram of access to the timing control module in the pixel driving unit of the present application;

[0049] Figure 9 Schematic diagram of the device structure of the hardware operating environment involved in the pixel driving method in the embodiment of the present application.

[0050] Explanation of the reference numerals in the drawings:

[0051] 10. Pixel driving unit; A. First node;

[0052] 101. Reset module; T1. First transistor;

[0053] 102. Charging module; T2. Second transistor; T3. Third transistor; T4. Fourth transistor;

[0054] 103. Driving module; T5. Fifth transistor; T6. Sixth transistor;

[0055] 104. Timing control module; T7. Seventh transistor; T8. Eighth transistor; T9. Ninth transistor; T10. Tenth transistor;

[0056] G. Scanning signal terminal; S. Data line; P. Driving signal terminal; ELVDD. Positive power supply voltage terminal; ELVSS. Negative power supply voltage terminal; VGH. High-level voltage terminal; VGL. Low-level voltage terminal; C. Storage capacitor; D. Light-emitting device.

[0057] The realization of the object, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. Detailed implementation manners

[0058] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0059] In order to better understand the technical solutions of the present application, the following will be described in detail in conjunction with the drawings in the specification and specific implementation manners.

[0060] The main solution of the embodiment of this application is: a pixel driving circuit is proposed. The pixel driving circuit includes a plurality of pixel driving units arranged in a rectangular array, and each pixel driving unit includes a reset module, a charging module, and a driving module. Among them, the output terminal and the control terminal of the reset module are commonly connected to the upper-level scanning signal terminal, the input terminal of the reset module is electrically connected to the first node, and the reset module is used to pull down the first node to a preset low potential during the reset stage; the input terminal of the charging module is connected to the data line, the control terminal of the charging module is connected to the current-level scanning line, the output terminal of the charging module is electrically connected to the first node, and the charging module is used to charge the first node to a first voltage during the writing stage, where the first voltage is the sum of the data voltage on the data line and the threshold voltage to be offset existing in the charging module; the input terminals of the driving module are respectively connected to the first node and the positive power supply voltage terminal, the control terminal of the driving module is connected to the driving signal terminal, the output terminal of the driving module is connected to the light-emitting device, and the driving module is used to transmit, during the light-emitting stage, the driving signal received from the driving signal terminal, the first voltage, the driving voltage on the positive power supply voltage terminal, and the real-time threshold voltage generated by the driving module into the light-emitting device, where at least part of the threshold voltage to be offset in the first voltage cancels out the real-time threshold voltage.

[0061] In a self-emissive display, whether it is a thin-film transistor driving architecture based on low-temperature polysilicon or an oxide semiconductor type, display anomalies will be caused due to the inherent characteristics of the thin-film transistors. Taking the thin-film transistors of low-temperature polysilicon as an example, the threshold voltage and carrier mobility thereof have non-uniform distributions, and the above parameters are directly related to the stability of the driving current of the thin-film transistors, thereby resulting in differences in the light-emitting intensity of the pixel units of the self-emissive display and causing display mottling. In addition, the hysteresis characteristics of the thin-film transistors will cause the drain-source current to exhibit an asymmetric response characteristic when the gate voltage scanning direction changes, thereby inducing an afterimage phenomenon in high-frequency switching images such as checkerboards. At the same time, the threshold voltage drift phenomenon of the thin-film transistors will cause fluctuations in the driving current due to changes in the working time and ambient temperature, further exacerbating the brightness non-uniformity of the displayed image.

[0062] The present application provides a solution. By means of the provided reset module, before pixel driving, the potential on the first node of the pixel driving units on the same scanning line is reset to a preset low potential, thereby eliminating the capacitance charge deviation existing in the capacitance corresponding to the first node, ensuring that when the upper-level voltage changes in different directions, the change curves of the corresponding drain-source currents can coincide, so as to improve the display uniformity and suppress the afterimage phenomenon. In addition, through the charging module, an additional threshold voltage to be offset is generated before the pixel emits light, and when the pixel is driven to emit light through the driving module, the additional threshold voltage to be offset is provided to the light-emitting device, so that it can at least partially offset the real-time threshold voltage existing when the light-emitting device is driven to emit light, and to a certain extent reduce or eliminate the adverse display reflection caused by the threshold voltage, that is, to solve the display abnormal phenomenon caused by the hysteresis and the inherent characteristics of the threshold voltage of the thin-film transistor.

[0063] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication, and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device, a display device, etc. that can implement the above functions. Hereinafter, taking the display device as an example, this embodiment and the following embodiments will be described.

[0064] Based on this, an embodiment of the present application provides a pixel driving method, referring to Figure 1 , Figure 1 which is a schematic flowchart of an embodiment of the pixel driving method of the present application.

[0065] In this embodiment, the pixel driving method includes steps S10 to S30:

[0066] Step S10, in the reset stage, after the first node is pulled down to the preset low potential by the reset module, enter the writing stage.

[0067] In this embodiment, in each original pixel driving unit, a reset module is added. Through the reset module, before the scanning line where the pixel driving unit is located enters the light-emitting stage, it can first enter the reset stage. By pulling down the potential on the first node in the reset stage, the first nodes of the pixel driving units on this scanning line can be uniformly pulled down to a preset low potential.

[0068] Since the potential on the first node flows into the light-emitting device during the subsequent light-emitting stage, uniformly pulling down the potential of the first node to the same low potential can eliminate the potential offset in different pixel driving units on the same scanning line caused by residual charges. At the same time, because the threshold voltage of the thin-film transistor in the pixel driving unit drifts after long-term operation, resulting in distortion of the driving current flowing into the light-emitting device. Therefore, through this reset stage, the potential on the first node can also be periodically reset, so that the driving current flowing from the first node into the light-emitting device can return to the initial characteristic curve, effectively alleviating the brightness attenuation and Mura (display mottling) defects, and compensating for the threshold voltage drift when the thin-film transistor is turned on to drive the light-emitting device. And when the thin-film transistor is turned on to drive the light-emitting device, the thin-film transistor exhibits a current hysteresis characteristic when the voltage scanning direction is different. As shown in Figure 2 When the gate voltage (i.e., Vgs on the horizontal axis) changes in different directions, the change curves of the corresponding drain-source current (i.e., Ids on the vertical axis) do not coincide, resulting in an afterimage when the displayed image is a checkerboard type image as described in Figure 3 . Therefore, before driving the pixel driving units on the same scanning line to emit light through the reset stage, the first node is uniformly pulled down to the same preset low potential, so that the pixel driving units on the same scanning line can be electrified at the same potential, and then when the first node is charged subsequently, the potential change path on the first node can be unified, eliminating the difference in direction dependence, and thus reducing the display afterimage to a certain extent.

[0069] Step S20: Control the charging module to write the data voltage on the data line and the threshold voltage to be offset existing in the charging module into the first node. After charging the first node to the first voltage, enter the light-emitting stage.

[0070] In this embodiment, an additional charging module is added to each original pixel driving unit. The charging module in this embodiment can generate an additional threshold voltage to be offset during the execution stage for subsequent transmission into the light-emitting device to at least partially offset the real-time threshold voltage flowing into the light-emitting device during the light-emitting stage, realizing the suppression or elimination of the real-time threshold voltage.

[0071] Specifically, when the charging module enters the charging stage, the charging module writes the data voltage on the data line to the first node to charge the first node. During this process, the charging module generates an additional offset threshold voltage to be cancelled, which is also written to the first node, so that the voltage on the first node is charged to the data voltage + the offset threshold voltage (i.e., the first voltage), so that in the subsequent light-emitting stage, the offset threshold voltage can be at least partially cancelled with the real-time threshold voltage existing in the light-emitting stage, so as to reduce or eliminate the display anomaly phenomenon caused by the threshold voltage.

[0072] Step S30: Based on the driving module accessing the driving signal, the first voltage, the driving voltage on the positive power supply voltage terminal, and the real-time threshold voltage generated by the driving module are transmitted into the light-emitting device, wherein at least part of the offset threshold voltage in the first voltage is cancelled with the real-time threshold voltage.

[0073] In this embodiment, a driving module is added to each original pixel driving unit. The driving module can form a driving current from the first voltage on the first node and the driving voltage on the positive power supply voltage terminal and provide it to the light-emitting device. At the same time, during the driving process, the driving module generates a real-time threshold voltage, which also flows into the light-emitting device. Therefore, the real-time threshold voltage will be at least partially cancelled with the offset threshold voltage in the first voltage, which can reduce or eliminate the influence of the real-time threshold voltage on the light-emitting device to a certain extent.

[0074] Through the above steps, the inherent characteristics of the thin-film transistor, namely the hysteresis characteristic and the real-time threshold voltage of the thin-film transistor, are reduced or eliminated, and thus the existing abnormal display phenomenon is reduced or eliminated, effectively improving the surface uniformity and display smoothness of the self-luminous display to a certain extent.

[0075] Among them, the above pixel driving method can be based on, for example Figure 4 the following pixel driving circuit is implemented.

[0076] The pixel driving circuit includes a plurality of pixel driving units 10 arranged in a rectangle, and each pixel driving unit 10 includes a reset module 101, a charging module 102, and a driving module 103.

[0077] The output terminal and the control terminal of the reset module 101 are commonly connected to the upper-level scanning signal terminal (i.e., Figure 4 G(n - 1) in the figure), the input terminal of the reset module 101 is electrically connected to the first node A, and the reset module 101 is used to pull down the first node A to a preset low potential during the reset stage.

[0078] Such as Figure 4It can be seen that the output terminal and the control terminal of the reset module 101 in the pixel driving unit 10 proposed in this embodiment are commonly connected to the upper-level scanning signal terminal, and the input terminal is electrically connected to the first node A. By reusing the upper-level scanning signal and using it as the conduction signal for controlling the reset module 101 in the current-level pixel driving unit 10, when the reset module 101 enters the conduction state based on the upper-level scanning signal, a low-resistance path is formed between its input terminal and output terminal, forcing the potential on the first node A to be pulled down to a preset low potential, thereby realizing the potential reset and unification of the first node A on the same scanning line.

[0079] It should be noted that the preset low potential is the potential on the negative power supply voltage terminal ELVSS in the upper-level pixel driving unit 10.

[0080] The input terminal of the charging module 102 is connected to the data line S, the control terminal of the charging module 102 is connected to the current-level scanning line (i.e., Figure 4 Gn in it), and the output terminal of the charging module 102 is electrically connected to the first node A. The charging module 102 is used to charge the first node A to a first voltage during the writing stage, where the first voltage is the sum of the data voltage on the data line S and the threshold voltage to be offset existing in the charging module 102.

[0081] The charging module 102 included in the pixel driving unit 10 proposed in this embodiment has its input terminal connected to the data line S, can access the data voltage on the data line S, and at the same time controls the access to the current-level scanning signal terminal. Through multiplexing the current-level scanning signal for conduction control, the output terminal is connected to the first node A. When it enters the conduction state based on the current-level scanning signal, it will access the data voltage on the data line S and write this data voltage into the first node A. At the same time, when the charging module 102 enters the conduction state, it will generate an additional threshold voltage, that is, the threshold voltage to be offset, and this threshold voltage to be offset will also be written into the first node A and charge the first node A together with the data voltage. Therefore, the first voltage on the first node A in this embodiment is the data voltage + the threshold voltage to be offset. The purpose is that when the first voltage on the first node A is subsequently transmitted to the light-emitting device D, it can at least partially cancel the real-time threshold voltage existing during the pixel driving process, thereby reducing or eliminating the influence degree of the light-emitting device D by the real-time threshold voltage.

[0082] The input terminals of the driving module 103 are respectively connected to the first node A and the positive power supply voltage terminal ELVDD. The control terminal of the driving module 103 is connected to the driving signal terminal. The output terminal of the driving module 103 is connected to the light-emitting device D. The driving module 103 is configured to, during the light-emitting stage, according to the driving signal received from the driving signal terminal, transmit the first voltage, the driving voltage on the positive power supply voltage terminal ELVDD, and the real-time threshold voltage generated by the driving module 103 into the light-emitting device D, wherein at least partial cancellation occurs between the threshold voltage to be cancelled in the first voltage and the real-time threshold voltage.

[0083] Compared with the conventional pixel driving unit 10, the pixel driving unit 10 proposed in this embodiment further adds a driving module 103. The input terminals of the driving module 103 are respectively connected to the first node A and the positive power supply voltage terminal ELVDD, and the output terminal is connected to the light-emitting device D. When the driving signal received from the driving signal terminal is received at its control terminal, it can enter the conducting state. In the conducting state, the first voltage on the first node A and the driving voltage on the positive power supply voltage terminal ELVDD pass through the driving module 103 to provide a driving current to the light-emitting device D. During the conduction process of the driving module 103, there will be a real-time threshold voltage, and this real-time threshold voltage will also be transmitted into the light-emitting device D. At this time, at least partial cancellation occurs between the threshold voltage to be cancelled in the first voltage and this real-time threshold voltage, which can reduce or eliminate the adverse effect of the real-time threshold voltage on the light-emitting state of the light-emitting device D.

[0084] Specifically, the circuit structure of the pixel driving unit 10 can be referred to Figure 5 as shown.

[0085] Among them, a storage capacitor C is provided in the pixel driving unit 10. The first node A is located on the first capacitor terminal of the storage capacitor C. The reset module 101 includes a first transistor T1. The control terminal and the input terminal of the first transistor T1 are respectively connected to the upper-level scanning signal terminal (i.e., Figure 5 G(n - 1) in

[0086] ), and the output terminal of the first transistor T1 is connected to the first capacitor terminal. First, the conventional pixel driving unit 10 is described. Referring to Figure 6 , it can be known that the conventional pixel driving unit 10 has a 2T1C (i.e., two thin-film transistors T and one storage capacitor C1) structure. During the conduction process of its thin-film transistor T, the driving current transmitted to the light-emitting device D1 is b(V data +V th -V ELVDD ) 2 .

[0087] Among them, b is a constant, V data is the data voltage on the data line S, and V ELVDDis the positive power supply voltage terminal ELVDD, V th is the threshold voltage of the thin film transistor. It can be seen that the existing threshold voltage of the thin film transistor will directly affect the light-emitting device D1, resulting in uneven picture brightness and picture afterimage phenomena.

[0088] Therefore, based on the above problems, this embodiment proposes a reset module 101 structure as described in Figure 5 . The reset module 101 includes a first transistor T1. It can be seen that the control terminal and the input terminal of the first transistor T1 are respectively connected to the previous-level scan signal terminal, and the output terminal is connected to the first capacitance terminal of the storage capacitor C.

[0089] When the previous-level scan signal on the previous-level scan signal terminal jumps to the low level state, the gate voltage (i.e., the voltage on the control terminal) of the first transistor T1 will suddenly drop to the low potential, and the source voltage (i.e., the voltage on the input terminal) will also synchronously become the low potential. At this time, if there is charge in the storage capacitor C, it will cause a potential difference between the input terminal and the output terminal. The first transistor T1 is instantaneously turned on due to the response of the body diode, so that the charge in the storage capacitor C is output from the first capacitance terminal and discharged to the negative power supply voltage terminal ELVSS corresponding to the previous-level scan signal terminal through the source-drain path of the first transistor T1, pulling the potential on the first capacitance terminal down to the preset low potential of the negative power supply voltage terminal ELVSS, realizing the reset operation of the storage capacitor C.

[0090] At the same time, because the reset modules 101 on the same scan line are connected to the same previous-level scan signal terminal, their reset operations will pull the potential of the first capacitance terminal of the storage capacitor C on the same scan line down to the same preset low potential, realizing the unification of the potential of the first capacitance terminal. So that during the subsequent charging process of the first capacitance terminal, it can ensure the consistency of the charging direction of the storage capacitor C on the same scan line, cancel out the hysteresis characteristics brought by the threshold voltage of the transistors in the pixel driving unit 10, and thus avoid the picture residue phenomenon caused by the hysteresis characteristics.

[0091] Among them, the charging module 102 includes a second transistor T2, a third transistor T3, and a fourth transistor T4; the control terminal of the second transistor T2 is connected to the current-level scan line (i.e., Figure 5 Gn in), the input terminal of the second transistor T2 is connected to the data line S, and the output terminal of the second transistor T2 is connected to the output terminal of the third transistor T3; the input terminal of the third transistor T3 is connected to the input terminal of the fourth transistor T4, and the control terminal of the third transistor T3 and the output terminal of the fourth transistor T4 are commonly connected to the first capacitance terminal; the control terminal of the fourth transistor T4 is connected to the current-level scan signal terminal.

[0092] When the local scan signal output on the local scan line jumps to the low level state, the second transistor T2 enters the conducting state. Its input terminal starts to receive the data voltage from the data line S and transmits it to the output terminal. At the same time, since the control terminal of the fourth transistor T4 is connected to the local scan signal terminal, the fourth transistor T4 also enters the conducting state at this time. The input and output terminals of it form a low-resistance state, causing the potential on the input terminal of the third transistor T3 to be forced to the same level as the control terminal, that is, the control terminal and the input terminal of the third transistor T3 are short-circuited. The third transistor T3 presents a diode connection at this time.

[0093] The data voltage on the output terminal of the second transistor T2 flows into the input terminal of the fourth transistor T4 through the third transistor T3, and is given to the first capacitor terminal (i.e., the first node A) for charging through the output terminal of the fourth transistor T4. At the same time, there is a threshold voltage when the second transistor T2, the third transistor T3, and the fourth transistor T4 are conducting. This threshold voltage is the threshold voltage to be offset in this embodiment and will flow into the first capacitor terminal together with the data voltage for charging operation, charging the voltage on the first node A to the data voltage + the threshold voltage to be offset (i.e., the first voltage). That is, in the charging stage, a threshold voltage to be offset is pre-stored at the first node A through the charging module 102, which is used to offset the real-time threshold voltage that abnormally affects the light-emitting operation of the light-emitting device D in the subsequent light-emitting stage, so as to reduce or eliminate the influence of the real-time threshold voltage on the light-emitting device D.

[0094] For the convenience of marking, the first voltage on the first node A is marked as V data +V th1 ,where V data is the data voltage, and V th1 is the threshold voltage to be offset.

[0095] Among them, the driving module 103 includes a fifth transistor T5, a third transistor T3, and a sixth transistor T6; the control terminal of the fifth transistor T5 is connected to the driving signal terminal, the input terminal of the fifth transistor T5 is connected to the positive power supply voltage terminal ELVDD, and the output terminal of the fifth transistor T5 is connected to the input terminal of the third transistor T3; the control terminal of the sixth transistor T6 is connected to the driving signal terminal, the input terminal of the sixth transistor T6 is connected to the output terminal of the third transistor T3, and the output terminal of the sixth transistor T6 is connected to the positive electrode of the light-emitting device D; the second capacitor terminal of the storage capacitor C is connected to the connection line between the fifth transistor T5 and the positive power supply voltage terminal ELVDD.

[0096] When the driving signal outputted from the driving signal terminal jumps to a low level state, the fifth transistor T5 and the sixth transistor T6 will enter a conducting state. Among them, the fifth transistor T5 in the conducting state will access the driving voltage on the positive power supply voltage terminal ELVDD and transmit it to its output terminal, and will also obtain the first voltage on the first node A through the storage capacitor C, and transmit the first voltage on the first node A together with the driving voltage to its output terminal. Because the third transistor T3 is still diode-connected at this time, the driving voltage + first voltage on the output terminal of the fifth transistor T5 will be transmitted to the sixth transistor T6 through the third transistor T3, and then transmitted to the light-emitting device D through the turned-on sixth transistor T6, providing a driving current for the light-emitting device D.

[0097] The third transistor T3, the fifth transistor T5 and the sixth transistor T6 which are in the on state at the same time will have a real-time threshold voltage, and the real-time threshold voltage will flow into the light-emitting device D together with the driving voltage and the first voltage, that is, the driving current for driving the light-emitting device D at this time is expressed as: I = b (V data +V th1 -V ELVDD -V th2 ) 2 =b(V data -V ELVDD ) 2 .

[0098] Where I is the driving current, b is a constant, V ELVDD is the driving voltage, V th2 is the real-time threshold voltage. It can be known that the threshold voltage to be offset and the real-time threshold voltage will offset each other, so that the driving current for driving the light-emitting device D to emit light is composed of only the controllable data voltage and the driving voltage, that is, it can effectively avoid the threshold voltage of the turned-on transistor from affecting the brightness of the light-emitting device D, thereby causing display abnormality.

[0099] In a feasible implementation manner, step S30 may include step S31:

[0100] Step S31, based on the previous level scanning signal in the high level state and the current level scanning signal in the high level state, generates a low level driving signal, and transmits the low level driving signal to the driving module to control the driving module to drive the light-emitting device to emit light.

[0101] Further, in this embodiment, the driving signal for controlling the light-emitting stage changes based on the level states of the previous-stage scanning signal and the current-stage scanning signal. Since the reset stage and the charging stage in this embodiment are both initiated based on the previous-stage scanning signal and the current-stage scanning signal in the low-level state, when any one of the previous-stage scanning signal and the current-stage scanning signal is in the low-level state, the driving signal is in the high-level state, avoiding the situation where the driving of the light-emitting device is initiated during the reset stage or the charging stage and the effective cancellation of the real-time threshold voltage cannot be achieved.

[0102] Among them, step S31 can be implemented based on the timing control module 104.

[0103] The control terminals of the timing control module 104 are respectively connected to the current-stage scanning signal terminal and the previous-stage scanning signal terminal. The input terminal of the timing control module 104 is connected to the high-level voltage terminal VGH, and the output terminal of the timing control module 104 is connected to the low-level voltage terminal VGL. The timing control module 104 is used to adjust the level state of the output driving signal according to the signal level states of the current-stage scanning signal terminal and the previous-stage scanning signal terminal.

[0104] Refer to Figure 5 It can be seen that the driving signal in this embodiment is adjusted and output by the timing control module 104, whose control terminals are respectively connected to the current-stage scanning signal terminal and the previous-stage scanning signal terminal. Therefore, the level states of the current-stage scanning signal and the previous-stage scanning signal can be obtained in real time. Its input terminals are respectively connected to the high-level voltage terminal VGH and the low-level voltage terminal VGL. Therefore, when any one of the current-stage scanning signal and the previous-stage scanning signal is in the low-level state, the timing control module 104 will conduct and connect to the high-level voltage on the high-level voltage terminal VGH, and transmit the high-level voltage to the driving module 103 to control the driving module 103 to maintain the cut-off state. Only when both the current-stage scanning signal and the previous-stage scanning signal are in the high-level state, the timing control module 104 will be connected to the low-level voltage terminal VGL, pull down the level state of the driving signal through the low-level voltage terminal VGL, and transmit it to the driving module 103 to control the driving module 103 to conduct.

[0105] That is, in this embodiment, the current-stage scanning signal and the previous-stage scanning signal are further multiplexed to achieve the timing control between the reset stage, the charging stage, and the driving stage without the need to additionally set peripheral hardware to generate control signals, effectively reducing the hardware cost and the occupation of the panel space.

[0106] For the detailed control timing, refer to Figure 7 . It can be seen that during the reset stage (i.e., Figure 7 ts1 in Figure 7The scan signal output by G(n - 1) is in a low level state, and the scan signal of this stage (i.e., Figure 7 the scan signal output by Gn) is in a high level state. Therefore, at this time, the timing control module 104 accesses the high level voltage and outputs a driving signal in a high level state (i.e., Figure 7 the driving signal output by Pn); during the charging stage (i.e., Figure 7 ts2 in it), the scan signal of the previous stage is in a high level state, and the scan signal of this stage is in a low level state. Therefore, at this time, the timing control module 104 still accesses the high level voltage and outputs a driving signal in a high level state; during the driving stage (i.e., Figure 7 ts3 in it), the scan signals of the previous stage and this stage are both in a high level state. Therefore, at this time, the timing control module 104 is connected to the low level voltage terminal VGL and outputs a driving signal in a low level state.

[0107] Specifically, refer to Figure 5 as shown.

[0108] The timing control module 104 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10;

[0109] The control terminal of the seventh transistor T7 is connected to the scan signal terminal of this stage, the control terminal of the eighth transistor T8 is connected to the scan signal terminal of the previous stage, the input terminals of the seventh transistor T7 and the eighth transistor T8 are commonly connected to the high level voltage terminal VGH, and the output terminals of the seventh transistor T7 and the eighth transistor T8 are commonly connected to the input terminal of the ninth transistor T9; the output terminal of the ninth transistor T9 is connected to the input terminal of the tenth transistor T10, and the control terminal of the ninth transistor T9 is connected to the scan signal terminal of this stage; the output terminal of the tenth transistor T10 is connected to the low level voltage terminal VGL, and the control terminal of the tenth transistor T10 is connected to the scan signal terminal of the previous stage; among them, the driving signal terminal is led out from the connection line between the seventh transistor T7 and the eighth transistor T8 and the ninth transistor T9.

[0110] According to Figure 5 it can be known that the high level voltage is controlled and accessed by the seventh transistor T7 and the eighth transistor T8, and the low level voltage is controlled and accessed by the ninth transistor T9 and the tenth transistor T10. Among them, the seventh transistor T7 and the eighth transistor T8 are in a parallel structure. Therefore, the access of the high level voltage is affected by any one of the seventh transistor T7 and the eighth transistor T8; while the ninth transistor T9 and the tenth transistor T10 are in a series structure. Therefore, the connection to the low level voltage terminal VGL is affected by the ninth transistor T9 and the tenth transistor T10.

[0111] When the scan signal at this level is in the low - level state and the scan signal at the previous level is in the high - level state, the seventh transistor T7 and the tenth transistor T10 are in the conducting state, and the eighth transistor T8 and the ninth transistor T9 are in the cut - off state. Therefore, at this time, the driving signal terminal is connected to the high - voltage terminal VGH through the seventh transistor T7, the potential of the driving signal on the driving signal terminal is pulled up, and the sixth transistor T6 and the fifth transistor T5 are controlled to enter the cut - off state.

[0112] When the scan signal at this level is in the high - level state and the scan signal at the previous level is in the low - level state, the seventh transistor T7 and the tenth transistor T10 are in the cut - off state, and the eighth transistor T8 and the ninth transistor T9 are in the conducting state. Therefore, at this time, the driving signal terminal is connected to the high - voltage terminal VGH through the eighth transistor T8, and the sixth transistor T6 and the fifth transistor T5 still remain in the cut - off state.

[0113] When the scan signal at this level and the scan signal at the previous level are both in the high - level state, the seventh transistor T7 and the eighth transistor T8 are in the cut - off state, and the ninth transistor T9 and the tenth transistor T10 are in the conducting state. Therefore, at this time, the driving signal terminal is connected to the low - voltage terminal VGL through the ninth transistor T9 and the tenth transistor T10, the driving signal terminal is pulled down to the low - voltage level, and then a driving signal in the low - level state is output, so that the sixth transistor T6 and the fifth transistor T5 enter the conducting state.

[0114] Among them, the pixel driving units 10 on the same scan line are connected to the same timing control module 104. While realizing the unified light - emitting driving control of the pixel driving units 10 on the same scan line, it can also reduce the occupied area of the timing control module 104 on the panel, and avoid the problems of high device cost and large required panel area caused by the one - to - one connection between the pixel driving units 10 and the timing control module 104. For details, please refer to Figure 8 as shown.

[0115] Each pixel driving unit 10 on the current - level scan line (i.e., Gn in Figure 8 ) is connected to the Pn driving signal output by the same timing control module 104 to control the switching of the sixth transistor T6 and the fifth transistor T5; each pixel driving unit 10 on the next - level scan line (i.e., G(n + 1) in Figure 8 ) is connected to the P(n + 1) driving signal output by the same timing control module 104 to control the switching of the sixth transistor T6 and the fifth transistor T5.

[0116] Among them, because Figure 8 has the same structure as Figure 5 shown, the structure of Figure 8 will not be described repeatedly.

[0117] The present application provides a display device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the pixel driving method in the first embodiment above.

[0118] Reference is made below Figure 9 to FIG., which shows a schematic structural diagram of a display device suitable for implementing the embodiments of the present application. The display device in the embodiments of the present application may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), in-vehicle terminals (such as in-vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 9 The display device shown is only an example and should not impose any limitations on the functions and usage scope of the embodiments of the present application.

[0119] As Figure 9 shown, the display device may include a processing device 1001 (such as a central processing unit, a graphics processing unit, etc.), which may perform various appropriate actions and processes according to the program stored in the read-only memory 1002 or the program loaded from the storage device 1003 into the random access memory 1004. In the random access memory 1004, various programs and data required for the operation of the display device are also stored. The processing device 1001, the read-only memory 1002, and the random access memory 1004 are connected to each other through a bus 1005. The input / output interface 1006 is also connected to the bus. Generally, the following systems may be connected to the input / output interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 may allow the display device to communicate with other devices wirelessly or wiredly to exchange data. Although the figure shows a display device with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems may be alternatively implemented or had.

[0120] In particular, according to the embodiments disclosed in the present application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains program codes for executing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a read-only memory 1002. When the computer program is executed by a processing device 1001, the above-mentioned functions defined in the methods of the embodiments disclosed in the present application are executed.

[0121] The display device provided in the present application adopts the pixel driving method in the above-mentioned embodiment, and can solve the technical problem of display abnormal phenomena caused by the inherent characteristics of thin film transistors. Compared with the prior art, the beneficial effects of the display device provided in the present application are the same as those of the pixel driving method provided in the above-mentioned embodiment, and other technical features in the display device are the same as those disclosed in the method of the previous embodiment, and will not be elaborated here.

[0122] It should be understood that the various parts disclosed in the present application can be implemented by hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0123] As mentioned above, the above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, and all should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

[0124] The above are only some embodiments of the present application, and do not limit the patent scope of the present application. All equivalent structural transformations made under the technical concept of the present application by using the content of the specification and drawings of the present application, or directly / indirectly applied to other related technical fields, are included in the patent protection scope of the present application.

Claims

1. A pixel driving circuit, characterized in that, The pixel driving circuit includes a plurality of pixel driving units arranged in a rectangular array, and each of the pixel driving units includes a reset module, a charging module, and a driving module; The output terminal and the control terminal of the reset module are commonly connected to the upper-level scanning signal terminal, the input terminal of the reset module is electrically connected to the first node, and the reset module is configured to pull down the first node to a preset low potential during the reset stage; The input terminal of the charging module is connected to the data line, the control terminal of the charging module is connected to the current-level scanning line, the output terminal of the charging module is electrically connected to the first node, and the charging module is configured to charge the first node to a first voltage during the writing stage, wherein the first voltage is the sum of the data voltage on the data line and the threshold voltage to be canceled existing in the charging module; The input terminal of the driving module is respectively connected to the first node and the positive power supply voltage terminal, the control terminal of the driving module is connected to the driving signal terminal, the output terminal of the driving module is connected to the light-emitting device, and the driving module is configured to transmit, during the light-emitting stage, based on the driving signal received from the driving signal terminal, the first voltage, the driving voltage on the positive power supply voltage terminal, and the real-time threshold voltage generated by the driving module into the light-emitting device, wherein at least part of the threshold voltage to be canceled in the first voltage cancels out with the real-time threshold voltage.

2. The pixel driving circuit according to claim 1, wherein A storage capacitor is provided in the pixel driving unit, the first node is located on the first capacitor terminal of the storage capacitor, and the reset module includes a first transistor; The control terminal and the input terminal of the first transistor are respectively connected to the upper-level scanning signal terminal, and the output terminal of the first transistor is connected to the first capacitor terminal.

3. The pixel driving circuit according to claim 2, wherein The charging module includes a second transistor, a third transistor, and a fourth transistor; The control terminal of the second transistor is connected to the current-level scanning line, the input terminal of the second transistor is connected to the data line, and the output terminal of the second transistor is connected to the output terminal of the third transistor; The input terminal of the third transistor is connected to the input terminal of the fourth transistor, and the control terminal of the third transistor and the output terminal of the fourth transistor are commonly connected to the first capacitor terminal; The control terminal of the fourth transistor is connected to the current-level scanning line.

4. The pixel driving circuit according to claim 3, wherein The driving module includes a fifth transistor, the third transistor, and a sixth transistor; The control terminal of the fifth transistor is connected to the driving signal terminal, the input terminal of the fifth transistor is connected to the positive power supply voltage terminal, and the output terminal of the fifth transistor is connected to the input terminal of the third transistor; The control terminal of the sixth transistor is connected to the driving signal terminal, the input terminal of the sixth transistor is connected to the output terminal of the third transistor, and the output terminal of the sixth transistor is connected to the positive electrode of the light-emitting device; The second capacitor terminal of the storage capacitor is connected to the connection line between the fifth transistor and the positive power supply voltage terminal.

5. The pixel driving circuit according to claim 4, wherein The pixel driving unit further includes a timing control module; The control terminals of the timing control module are respectively connected to the current-stage scan signal terminal and the previous-stage scan signal terminal. The input terminal of the timing control module is connected to a high-level voltage terminal, and the output terminal of the timing control module is connected to a low-level voltage terminal; The timing control module is configured to adjust the level state of the output driving signal according to the signal level states of the current-stage scan signal terminal and the previous-stage scan signal terminal.

6. The pixel driving circuit according to claim 5, wherein The timing control module includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; The control terminal of the seventh transistor is connected to the current-stage scan signal terminal, the control terminal of the eighth transistor is connected to the previous-stage scan signal terminal, the input terminals of the seventh transistor and the eighth transistor are commonly connected to the high-level voltage terminal, and the output terminals of the seventh transistor and the eighth transistor are commonly connected to the input terminal of the ninth transistor; The output terminal of the ninth transistor is connected to the input terminal of the tenth transistor, and the control terminal of the ninth transistor is connected to the current-stage scan signal terminal; The output terminal of the tenth transistor is connected to the low-level voltage terminal, and the control terminal of the tenth transistor is connected to the previous-stage scan signal terminal; Wherein, the driving signal terminal is led out from the connection line between the seventh transistor and the eighth transistor and the ninth transistor.

7. The pixel driving circuit according to claim 5, wherein The pixel driving units on the same scan line are connected to the same timing control module.

8. A pixel driving method, characterized in that, The pixel driving method is applied to the pixel driving circuit according to any one of claims 1 to 7. The pixel driving circuit includes a plurality of pixel driving units arranged in a rectangular array, and each pixel driving unit includes a reset module, a charging module, and a driving module; The pixel driving method includes: In the reset stage, after pulling down the first node to a preset low potential through the reset module, enter the writing stage; Control the charging module to write the data voltage on the data line and the threshold voltage to be offset existing in the charging module into the first node, and charge the first node to a first voltage, then enter the light-emitting stage; Based on the driving module to which the driving signal is connected, transmit the first voltage, the driving voltage on the positive power supply voltage terminal, and the real-time threshold voltage generated by the driving module into the light-emitting device, wherein at least part of the threshold voltage to be offset in the first voltage cancels out with the real-time threshold voltage.

9. The pixel driving method according to claim 8, wherein The pixel driving unit further includes a timing control module. Through the timing control module, before the step of the driving module to which the driving signal is connected, further includes: Based on the previous-stage scan signal in a high-level state and the current-stage scan signal in a high-level state, generate a driving signal in a low-level state, and transmit the driving signal in the low-level state into the driving module to control the driving module to drive and emit light to the light-emitting device.

10. A display device, characterized in that, The display device includes: a memory, a processor, and a computer program stored on the memory and executable on the processor. The computer program is configured to implement the steps of the pixel driving method according to any one of claims 8 and 9.

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