Display device and driving method thereof

Abstract

The invention provides a display device and a driving method thereof, a plurality of sub-pixels in the display device are arranged along a first direction and a second direction, at least two sub-pixels are arranged between two adjacent data lines in the first direction, the data lines are used for transmitting data voltage with the same polarity to the plurality of sub-pixels on two sides of the data lines, and the data lines are used for transmitting data voltage with the same polarity to the plurality of sub-pixels on two sides of the data lines. The polarities of two data voltages transmitted by two adjacent data lines are opposite, the gate lines are electrically connected to at least part of sub-pixels with different polarities in the corresponding data voltages in the multiple sub-pixels arranged in the first direction, and the polarities of the multiple data voltages corresponding to the multiple sub-pixels arranged in the first direction change alternately. The uniformity of a display picture when a DLS framework of the liquid crystal display device adopts a polarity inversion technology of data voltage of adjacent pixels is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a display device and a driving method thereof. Background Art

[0002] In a DLS (Data Line Sharing) architecture in a display device, the number of source driver chips is reduced by reducing the number of data lines. At the same time, in a liquid crystal display device, by reversing the polarities of data voltages of adjacent pixels, the phenomenon of image sticking caused by all liquid crystal molecules in a continuous area deflecting in the same direction is avoided.

[0003] However, for the reversal of the polarities of data voltages of adjacent pixels, the potential jump of the gate signal causes the voltages of positive-polarity pixels and negative-polarity pixels to jump in the same direction, resulting in opposite trends of brightness change for pixels of different polarities. When the polarity change frequency of pixels in the row direction or column direction is low, an obvious boundary line appears between a continuous positive-polarity area and an adjacent continuous negative-polarity area, reducing the uniformity of the display screen. Summary of the Invention

[0004] An object of the present invention is to provide a display device and a driving method thereof to solve the technical problem of poor uniformity of the display screen caused by the technology of reversing the polarities of data voltages of adjacent pixels in the DLS architecture of an existing liquid crystal display device.

[0005] An embodiment of the present invention provides a display device, including:

[0006] A plurality of sub-pixels arranged along a first direction and a second direction;

[0007] A plurality of data lines, between two adjacent data lines in the first direction, at least two of the sub-pixels are provided, and the data lines are used to transmit data voltages of the same polarity to a plurality of the sub-pixels located on both sides of the data lines, and the polarities of the two data voltages respectively transmitted by two adjacent data lines are opposite;

[0008] A plurality of gate lines, the gate lines are electrically connected to at least some of the sub-pixels corresponding to different polarities among the data voltages of a plurality of the sub-pixels arranged along the first direction;

[0009] Wherein, the polarities of the plurality of data voltages corresponding to the plurality of the sub-pixels arranged along the first direction change alternately.

[0010] In some embodiments, the polarities of the plurality of data voltages corresponding to the plurality of the sub-pixels arranged along the second direction change alternately.

[0011] In some embodiments, two of the sub-pixels are provided between every two adjacent data lines.

[0012] For a plurality of the sub-pixels arranged along the first direction, the data line is electrically connected to one of the sub-pixels located on one side of the data line and adjacent to the data line and one of the sub-pixels located on the other side of the data line and spaced apart from the data line.

[0013] In some embodiments, a plurality of the data lines include a first data line, a second data line, and a third data line arranged in sequence along the first direction;

[0014] A plurality of the sub-pixels arranged along the first direction include a first sub-pixel close to the first data line and a second sub-pixel close to the second data line, which are located between the first data line and the second data line;

[0015] A plurality of the sub-pixels arranged along the first direction include a third sub-pixel close to the second data line and a fourth sub-pixel close to the third data line, which are located between the second data line and the third data line;

[0016] Wherein, the first data line is electrically connected to at least the second sub-pixel, the second data line is electrically connected to the first sub-pixel and the third sub-pixel, and the third data line is electrically connected to at least the fourth sub-pixel;

[0017] Alternatively, the first data line is electrically connected to at least the first sub-pixel, the second data line is electrically connected to the second sub-pixel and the fourth sub-pixel, and the third data line is electrically connected to at least the third sub-pixel.

[0018] In some embodiments, two of the gate lines are provided between two adjacent sub-pixels arranged along the second direction;

[0019] Of the plurality of sub-pixels arranged along the first direction, two sub-pixels electrically connected to the same data line are respectively electrically connected to two gate lines located on different sides of the two sub-pixels.

[0020] In some embodiments, of the plurality of sub-pixels arranged along the first direction, two sub-pixels located between two adjacent data lines are respectively electrically connected to two gate lines located on different sides of the two sub-pixels.

[0021] In some embodiments, a plurality of the data lines include a first data line, a second data line, and a third data line arranged in sequence along the first direction;

[0022] The plurality of sub-pixels arranged along the first direction include a first sub-pixel close to the first data line and a second sub-pixel close to the second data line, which are located between the first data line and the second data line;

[0023] The plurality of sub-pixels arranged along the first direction include a third sub-pixel close to the second data line and a fourth sub-pixel close to the third data line, which are located between the second data line and the third data line, and further include a fifth sub-pixel close to the third sub-pixel and a sixth sub-pixel close to the fourth sub-pixel, which are located between the third sub-pixel and the fourth sub-pixel;

[0024] Wherein, one of the first sub-pixel and the second sub-pixel is electrically connected to the first data line, and two of the third sub-pixel, the fourth sub-pixel, the fifth sub-pixel and the sixth sub-pixel, which are arranged at intervals, are electrically connected to the second data line, and the other two arranged at intervals are electrically connected to the third data line.

[0025] In some embodiments, three gate lines are provided between two adjacent sub-pixels arranged along the second direction;

[0026] Among the plurality of sub-pixels arranged along the first direction, three sub-pixels electrically connected to the same data line are respectively electrically connected to the corresponding three gate lines.

[0027] In some embodiments, two of the plurality of sub-pixels arranged along the first direction, which are located between two adjacent data lines, are respectively electrically connected to two gate lines located on different sides of the two; and

[0028] Among the four of the plurality of sub-pixels arranged along the first direction, which are located between two adjacent data lines, two are electrically connected to two gate lines located on one side of the four, and the other two are electrically connected to two gate lines located on the other side of the four sub-pixels.

[0029] An embodiment of the present invention further provides a driving method for a display device. The display device includes a plurality of sub-pixels arranged along a first direction and a second direction. The display device further includes a plurality of gate lines and a plurality of data lines. In the first direction, at least two sub-pixels are provided between two adjacent data lines. The gate lines are electrically connected to a sub-pixel group composed of corresponding partial sub-pixels among the plurality of sub-pixels arranged along the first direction. The driving method of the display device includes:

[0030] Control multiple ones of the gate lines to output corresponding multiple gate signals, so that at least some of the sub-pixels with different polarities among the corresponding multiple data voltages in the multiple sub-pixels arranged along the first direction are turned on simultaneously, and so that the corresponding multiple sub-pixel groups are turned on in sequence;

[0031] Control each of the multiple data lines to transmit data voltages of the same polarity to the multiple sub-pixels located on both sides of the data line, and control the polarities of the two data voltages respectively transmitted by two adjacent data lines to be opposite, so that the polarities of the multiple data voltages corresponding to the multiple sub-pixels arranged along the first direction change alternately, and so that the corresponding multiple sub-pixel groups emit light in sequence.

[0032] The present invention provides a display device and a driving method thereof. Multiple sub-pixels in the display device are arranged along a first direction and a second direction. In the first direction, at least two sub-pixels are provided between two adjacent data lines. The data lines are used to transmit data voltages of the same polarity to the multiple sub-pixels located on both sides of the data line. The polarities of the two data voltages respectively transmitted by two adjacent data lines are opposite. The gate line is electrically connected to at least some of the sub-pixels with different polarities among the corresponding data voltages in the multiple sub-pixels arranged along the first direction, and the polarities of the multiple data voltages corresponding to the multiple sub-pixels arranged along the first direction change alternately, improving the uniformity of the display screen when the DLS architecture of the liquid crystal display device adopts the polarity inversion technology of the data voltages of adjacent pixels. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a block diagram of the display device provided by the embodiment of the present invention.

[0034] Figures 2 to 4 It is a connection schematic diagram of multiple gate lines, multiple data lines and multiple sub-pixels provided by the embodiment of the present invention.

[0035] Figure 5 It is a connection schematic diagram of multiple gate lines, multiple data lines and multiple sub-pixels provided by the comparative example of the present invention.

[0036] Figure 6 Provided by the embodiment of the present invention Figure 2 Corresponding circuit layout diagram.

[0037] Figure 7 It is a flowchart of the driving method of the display device provided by the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention.

[0039] In the description of the present invention, terms such as "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the described features. Additionally, it should be noted that the accompanying drawings only provide structures that are relatively closely related to the present invention, and some details that are not closely related to the invention are omitted. The purpose is to simplify the drawings and make the inventive points clear at a glance, rather than indicating that the actual device is exactly the same as the attached Figure 1 model and not being a limitation on the actual device.

[0040] The mention of "embodiment" in this article means that the specific features, structures, or characteristics described in connection with the embodiment may be included in at least one embodiment of the present invention. The occurrence of this phrase at various times in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0041] The present invention provides a display device, and the display device includes, but is not limited to, the following embodiments and combinations of the following embodiments.

[0042] In some embodiments, as shown in Figures 1 to 4 Figure 16, the display device 100 includes: a plurality of sub-pixels P arranged along a first direction O1 and a second direction O2; a plurality of data lines (D1 to Dm), in the first direction O1, at least two of the sub-pixels P are provided between adjacent two of the data lines, and the data lines (other than the two data lines located on both sides of the plurality of sub-pixels P among D1 to Dm) are used to transmit data voltages of the same polarity (included in the data signal data) to the plurality of sub-pixels P located on both sides of the data line, and the polarities of the two data voltages respectively transmitted by adjacent two of the data lines (adjacent two of D1 to Dm) are opposite; a plurality of gate lines (G1 to Gn), the gate lines are electrically connected to at least some of the sub-pixels P with different polarities among the corresponding data voltages of the plurality of sub-pixels P arranged along the first direction O1; wherein, the polarities of the plurality of data voltages corresponding to the plurality of sub-pixels P arranged along the first direction O1 alternate. Wherein, both n and m are positive integers.

[0043] Among them, the display device 100 can be a liquid crystal display device. The display device 100 can include a panel main body 10 for displaying an image and a driver 20. The panel main body 10 includes the above-mentioned multiple gate lines (G1 to Gn), multiple data lines (D1 to Dm), and multiple sub-pixels P. The driver 20 can include a source driver 201 and a timing controller 202. The gate driver 203 in the display device 100 can be integrated into the above-mentioned panel main body 10 or driver 20. Only the former is taken as an example for illustration herein. Figure 1 Only the former is taken as an example for illustration herein.

[0044] As Figure 1 shown, taking the arrangement of multiple sub-pixels P in an array as an example, the first direction O1 and the second direction O2 can be the row direction and the column direction respectively. For example, they can be arranged in n' rows and m columns (n' is a positive integer greater than n). Among them, each gate line (one of G1 to Gn) is electrically connected to some sub-pixels P in the corresponding row (the polarities of the corresponding multiple data voltages are different) to output a corresponding gate signal gate (including a gate pulse for controlling the corresponding sub-pixel to turn on). The n rows of sub-pixels P (the transistors in the corresponding pixel circuits) are sequentially turned on under the control of n' gate signals gate (n' gate pulses among them). Each data line (one of D1 to Dm) is connected to multiple sub-pixels P in the corresponding column to output a corresponding data signal data. The multiple data signals data corresponding to multiple columns of sub-pixels P are matched so that when the sub-pixels P in the corresponding row are turned on, the corresponding m data voltages are respectively transmitted to the corresponding m sub-pixels P through m data lines.

[0045] Specifically, as Figures 1 to 4 shown, in this embodiment, at least two sub-pixels P are provided between two adjacent data lines. Each of the other data lines (one of D2 to Dm-1) except for the two on both sides of the multiple sub-pixels P is used to transmit data voltages with the same polarity to the multiple sub-pixels P on both sides of it, and the polarities of the two data voltages respectively transmitted by two adjacent data lines (two adjacent ones among D1 to Dm) are opposite. That is, for the multiple sub-pixels P in the same row, each of the other data lines except for the two on both sides of the multiple sub-pixels P transmits a data voltage to at least one sub-pixel P on one side of it and also transmits a data voltage with the same polarity to at least one sub-pixel P on the other side of it. Correspondingly, the two data lines (D1 and Dm) on both sides of the multiple sub-pixels P can transmit data voltages with corresponding polarities to at least one sub-pixel P on one side of them.

[0046] Therefore, in this embodiment, the polarities of the two data voltages respectively transmitted by two adjacent data lines (two adjacent ones among D1 to Dm) are set to be opposite (the positive polarity "+" and the negative polarity "-" respectively). Therefore, the polarities of the multiple data voltages received by the multiple sub-pixels P arranged in the first direction O1 can also be switched multiple times. The specific switching frequency can be determined according to the position of the data line to which each sub-pixel P is connected. For example Figure 5 As shown, when multiple sub-pixels P (for example, only including two sub-pixels P) located between two adjacent data lines are all connected to the data line on the same side (for example, the left side) of the two, the polarities of the multiple data voltages corresponding to the multiple sub-pixels P located between two adjacent data lines are the same. At this time, the more the number of sub-pixels P between two adjacent data lines, the lower the switching frequency of the polarities of the multiple data voltages corresponding to the first direction O1 is equivalent to.

[0047] As Figures 2 to 4 shown, the difference between this embodiment and Figure 5 is that the polarities of the multiple data voltages corresponding to the multiple sub-pixels P arranged in the first direction O1 change alternately. Specifically, in this embodiment, at least two sub-pixels P located between two adjacent data lines are electrically connected to the data lines at the corresponding positions (the specific positions are not limited) to receive the data voltages of the corresponding polarities, so as to make the polarities of two adjacent ones among the multiple sub-pixels P in the same row opposite, thereby achieving the highest switching frequency of the polarities of the multiple data voltages corresponding to the first direction O1.

[0048] It can be understood that, on the basis of reducing the number of data lines by adopting the DLS architecture to reduce the number of source drivers 201 in this embodiment, the same data line is set to transmit the data voltages of the same polarity to avoid increasing the power consumption due to the polarity switching of the data voltages in the same data signal data. At the same time, the polarities of the two data voltages respectively transmitted by two adjacent data lines are set to be opposite to avoid all liquid crystal molecules deflecting in the same direction for a long time to cause image sticking. And even if the potentials of multiple gate signals gate jump (at the end period of the corresponding gate pulses), causing the data voltages of the positive polarity and the data voltages of the negative polarity corresponding to the multiple sub-pixels P in the same row to jump in the same direction, resulting in the opposite brightness change trends of the sub-pixels P of the two polarities. However, the switching frequency of the polarities of the multiple data voltages corresponding to the multiple sub-pixels P arranged in the first direction O1 in this embodiment reaches its highest frequency. It can be considered that the brightness change situation of the display screen in at least the first direction O1 is approximately the average value of the brightness changes of two adjacent sub-pixels P. Therefore, the brightness change degree of the display screen in the first direction O1 is basically the same, improving the uniformity of the display screen.

[0049] In some embodiments, in combination with Figures 1 to 4As shown, the polarities of the multiple data voltages corresponding to the multiple sub-pixels P arranged along the second direction O2 alternate. Specifically, in this embodiment, by electrically connecting at least two sub-pixels P between adjacent two data lines in each row to the data lines at corresponding positions (the specific positions are not limited) to receive data voltages of corresponding polarities, it is possible to simultaneously make the polarities of adjacent ones among the multiple sub-pixels P in the same row opposite to each other and the polarities of adjacent ones among the multiple sub-pixels P in the same column opposite to each other.

[0050] It can be understood that the switching frequency of the polarities of the multiple data voltages corresponding to the multiple sub-pixels P in the same row in this embodiment reaches its highest frequency, and the switching frequency of the polarities of the multiple data voltages corresponding to the multiple sub-pixels P in the same column reaches its highest frequency, making the brightness change of the display screen in the first direction O1 and the second direction O2 approximately the average of the brightness changes of adjacent two sub-pixels P in their respective directions. Therefore, the brightness change degrees of the display screen in the first direction O1 and the second direction O2 are basically the same, further improving the uniformity of the display screen.

[0051] In some embodiments, as shown in combination with Figure 1 and Figure 2 two sub-pixels P are provided between every two adjacent data lines (adjacent ones among D1 to Dm); for the multiple sub-pixels P arranged along the first direction O1, the data line is electrically connected to one sub-pixel P adjacent to the data line on one side of the data line and one sub-pixel P spaced from the data line on the other side of the data line.

[0052] Combined with the above discussion, it can be known that the polarities of the two data voltages respectively transmitted by two adjacent data lines are opposite, and the polarities of the two data voltages corresponding to adjacent ones among the multiple sub-pixels P in the same row are also opposite. Taking the example of setting two columns of sub-pixels P between two adjacent data lines in this embodiment, and taking the multiple sub-pixels P in the same row as an example, since the polarities of the two sub-pixels P adjacent to both sides of the same data line are opposite, the data line can only be electrically connected to one of the two sub-pixels P (for example, on the "one side" of the data line) to provide a data voltage of corresponding polarity. And since the polarity of the data voltage corresponding to a sub-pixel P spaced from the data line on the "other side" of the data line is the same as the polarity of the data voltage corresponding to the above-mentioned sub-pixel P adjacent to the data line on the "one side" of the data line, this sub-pixel P can also be electrically connected to the above-mentioned data line.

[0053] For example Figure 2As shown, taking the polarities of multiple data voltages corresponding to multiple data lines (D1 to Dm) as alternating between positive polarity "+" and negative polarity "-", and the polarities of multiple data voltages corresponding to the first column of sub-pixels P to the first column of sub-pixels P as alternating between negative polarity "-" and positive polarity "+" as an example. For some of the data lines (the data lines with even subscripts in D2 to Dm-1), since the polarity of the data voltage transmitted by them is negative polarity "-", and the polarity of the data voltage required by the sub-pixels P adjacent to and on one side of the above data line in each row of sub-pixels P is also negative polarity "-". For example, the sub-pixels P on the left side and adjacent to the above data line in the even rows of sub-pixels P and the sub-pixels P on the right side and adjacent to the above data line in the odd rows of sub-pixels P can all be electrically connected to this data line, and the polarity of the data voltage required by the sub-pixels P spaced apart from and on one side of the above data line in each row of sub-pixels P is also negative polarity "-". For example, the sub-pixels P on the left side and spaced apart from the above data line in the odd rows of sub-pixels P and the sub-pixels P on the right side and spaced apart from the above data line in the even rows of sub-pixels P can all be electrically connected to this data line.

[0054] Specifically, as shown in combination with Figure 1 and Figure 2 Multiple data lines include a first data line, a second data line, and a third data line (such as D1, D2, D3 respectively) arranged in sequence along the first direction O1; multiple sub-pixels P arranged along the first direction O1 include a first sub-pixel P1 close to the first data line and a second sub-pixel P2 close to the second data line located between the first data line (such as D1) and the second data line (such as D2); multiple sub-pixels P arranged along the first direction O1 include a third sub-pixel P3 close to the second data line and a fourth sub-pixel P4 close to the third data line located between the second data line and the third data line (such as D3); wherein, the first data line (such as D1) is at least electrically connected to the second sub-pixel P2, the second data line (such as D2) is electrically connected to the first sub-pixel P1 and the third sub-pixel P3, the third data line (such as D3) is at least electrically connected to the fourth sub-pixel P4; or, the first data line (such as D1) is at least electrically connected to the first sub-pixel P1, the second data line (such as D2) is electrically connected to the second sub-pixel P2 and the fourth sub-pixel P4, the third data line (such as D3) is at least electrically connected to the third sub-pixel P3.

[0055] Taking the first data line, the second data line, and the third data line as D1, D2, and D3 respectively as an example, in each row of sub-pixels P, the first sub-pixel P1 and the second sub-pixel P2 are arranged along the first direction O1 and are located on the first data line and the second data line respectively, and the third sub-pixel P3 and the fourth sub-pixel P4 are located on the second data line and the third data line respectively. In the odd-numbered rows of sub-pixels P, the first data line and the second data line are respectively connected to the second sub-pixel P2 and the first sub-pixel P1, which are farther away from them, through longer connection lines, and the second data line and the third data line are respectively connected to the third sub-pixel P3 and the fourth sub-pixel P4, which are closer to them, through shorter connection lines. In the even-numbered rows of sub-pixels P, the first data line and the second data line are respectively connected to the first sub-pixel P1 and the second sub-pixel P2, which are closer to them, through shorter connection lines, and the second data line and the third data line are respectively connected to the fourth sub-pixel P4 and the third sub-pixel P3, which are farther away from them, through longer connection lines.

[0056] In summary, based on Figure 2 As shown, the polarities of the multiple data voltages corresponding to the multiple sub-pixels P present dot inversion, and the polarities of the multiple data voltages corresponding to the multiple data lines present column inversion. Then, it can be considered that in the multiple sub-pixels P of the odd-numbered rows, multiple groups of sub-pixels (including two sub-pixels P) located between multiple adjacent two data lines in sequence are alternately electrically connected to the corresponding data lines through longer connection lines and shorter connection lines. In the multiple sub-pixels P of the even-numbered rows, multiple groups of sub-pixels (including two sub-pixels P) located between multiple adjacent two data lines in sequence are alternately electrically connected to the corresponding data lines through shorter connection lines and longer connection lines.

[0057] In some embodiments, in combination with Figure 1 and Figure 2 As shown, there are two gate lines (adjacent ones among G1 to Gn) provided between two adjacent sub-pixels P arranged along the second direction O2; among the multiple sub-pixels P arranged along the first direction O1, the two sub-pixels P electrically connected to the same data line are respectively electrically connected to two gate lines located on different sides of the two sub-pixels P.

[0058] Combined with the above discussion, it can be seen that for multiple sub-pixels P in the same row, the data line will be electrically connected to a sub-pixel P on one side of it and a sub-pixel P on the other side of it. If the transistors in the two sub-pixels P connected to the data line are turned on simultaneously, the data voltage currently transmitted by the data line will act on the two sub-pixels P at the same time, resulting in mischarging of one of the sub-pixels P.

[0059] Therefore, in this embodiment, two gate lines are set between two adjacent rows of sub-pixels P, wherein one gate line can be electrically connected to a plurality of sub-pixels P connected to different data lines in a row of sub-pixels P adjacent to it, and the other gate line can be electrically connected to a plurality of sub-pixels P connected to different data lines in a row of sub-pixels P adjacent to it. At the same time, it is also achieved that two sub-pixels P in the same row that are electrically connected to the same data line are respectively electrically connected to two gate lines (two adjacent ones among G1 to Gn) located on different sides of the two sub-pixels, so that two sub-pixels P in the same row that are electrically connected to the same data line can be controlled by two gate signals gate to be turned on in time-sharing, thereby receiving corresponding data voltages in time-sharing. At the same time, the gate signal gate transmitted by each gate line can control the transistors in the plurality of sub-pixels P in the same row of sub-pixels P that are connected to different data lines to be turned on at the same time, so that the corresponding plurality of sub-pixels P are respectively affected by the plurality of data voltages transmitted by the plurality of data lines (D1 to Dm).

[0060] Specific, combined Figure 1 and Figure 2 As shown, two of the plurality of sub-pixels P arranged along the first direction O1 and located between two adjacent data lines are electrically connected to two gate lines (two adjacent ones among G1 to Gn) located on different sides of the two sub-pixels. In combination with the above discussion, it can be seen that since the data line is electrically connected to a sub-pixel P located on one side and adjacent to it and a sub-pixel P located on the other side and spaced therefrom, that is, two sub-pixels P located on both sides of the data line (for example, D2) and adjacent to it (that is, the second sub-pixel P2 and the third sub-pixel P3) are respectively connected to two different data lines (that is, D1 and D2), and a sub-pixel (the first sub-pixel P1) located on one side of the data line (for example, D2) and spaced therefrom is also connected to the data line, so it is necessary to meet the first sub-pixel P1 and the third sub-pixel P3 connected to the data line D2 need to be connected to different gate lines, and at the same time, the second sub-pixel P2 can be connected to the same gate line as one of the first sub-pixel P1 and the third sub-pixel P3, and at the same time, it is also necessary to consider the position of the sub-pixels in the row of sub-pixels P connected to the data line (for example, D3) located on the other side of the data line (for example, D2), so the two adjacent data lines are respectively electrically connected to the two gate lines located on different sides of the two, so as to facilitate the connection of the sub-pixels P in the same row and the two gate lines on both sides of them.

[0061] In some embodiments, in combination Figure 1 and Figure 3As shown, a plurality of the data lines (D1 to Dm) include a first data line, a second data line, and a third data line (such as D1, D2, and D3 respectively) arranged in sequence along the first direction; a plurality of the sub-pixels P arranged along the first direction O1 include a first sub-pixel P1 close to the first data line (such as D1) and located between the first data line and the second data line (such as D2), and a second sub-pixel P2 close to the second data line; a plurality of the sub-pixels P arranged along the first direction O1 include a third sub-pixel P3 close to the second data line (such as D2) and located between the second data line and the third data line (such as D3), a fourth sub-pixel P4 close to the third data line, and further include a fifth sub-pixel P5 close to the third sub-pixel P3 and located between the third sub-pixel P3 and the fourth sub-pixel P4, and a sixth sub-pixel P6 close to the fourth sub-pixel P4; wherein, one of the first sub-pixel P1 and the second sub-pixel P2 is electrically connected to the first data line (such as D1), and two of the third sub-pixel P3, the fourth sub-pixel P4, the fifth sub-pixel P5, and the sixth sub-pixel P6 that are arranged at intervals are electrically connected to the second data line (such as D2), and the other two arranged at intervals are electrically connected to the third data line D3.

[0062] Similarly, based on Figure 3 As shown, the polarities of the multiple data voltages corresponding to the multiple sub-pixels P present dot inversion, and the polarities of the multiple data voltages corresponding to the multiple data lines present column inversion. Different from Figure 2 this is that in this embodiment, multiple groups of sub-pixels located between multiple adjacent two data lines in sequence alternately include two sub-pixels P and four sub-pixels P. Therefore, the polarities of the data voltages required by at least one of the two sub-pixels P on one side of the data line (such as D2) and the polarities of the data voltages required by two of the four sub-pixels P on the other side that are arranged at intervals are the same as the polarity of the data voltage transmitted by this data line. Therefore, the data line can be electrically connected to three sub-pixels located on both sides of it and in the same row.

[0063] In some embodiments, in combination with Figure 1 and Figure 3 As shown, three of the gate lines (three consecutive ones among G1 to Gn) are provided between two adjacent sub-pixels P arranged along the second direction O2; three of the multiple sub-pixels P arranged along the first direction O1 that are electrically connected to the same data line are respectively electrically connected to the corresponding three gate lines.

[0064] Similarly, since for multiple sub-pixels P located in the same row, the data line is electrically connected to a sub-pixel P located on one side thereof and two sub-pixels P located on the other side thereof, if the transistors in the three sub-pixels P connected to the data line are turned on at the same time, the data voltage currently transmitted by the data line will act on the three sub-pixels P at the same time, causing two of the sub-pixels P to be mischarged.

[0065] Therefore, in this embodiment, three gate lines are set between two adjacent rows of sub-pixels P, wherein one gate line can be electrically connected to a plurality of sub-pixels P connected to different data lines in a row of sub-pixels P adjacent to it, and each of the other two gate lines can be electrically connected to a plurality of sub-pixels P connected to different data lines in a row of sub-pixels P adjacent to it. At the same time, three sub-pixels P in the same row that are electrically connected to the same data line are respectively electrically connected to the corresponding three gate lines (three consecutive ones from G1 to Gn), so that the three sub-pixels P in the same row that are electrically connected to the same data line can be controlled by three gate signals gate to be turned on in time-sharing, thereby receiving the corresponding data voltages in time-sharing. At the same time, the gate signal gate transmitted by each gate line can control the transistors in the plurality of sub-pixels P in the same row of sub-pixels P that are connected to different data lines to be turned on at the same time, so that the corresponding plurality of sub-pixels P are respectively affected by the plurality of data voltages transmitted by the plurality of data lines (D1 to Dm).

[0066] Specific, combined Figure 1 and Figure 3 As shown, two of the plurality of sub-pixels P arranged along the first direction O1 that are located between two adjacent data lines (for example, D1 and D2) (for example, the first sub-pixel P1 and the second sub-pixel P2) are respectively electrically connected to two of the gate lines (two adjacent ones from G1 to Gn, for example, G4 and G3) located on different sides of the two; and two of the four of the plurality of sub-pixels P arranged along the first direction O1 (for example, the third sub-pixel P3 to the sixth sub-pixel P6) that are located between two adjacent data lines (for example, the third sub-pixel P3 and the sixth sub-pixel P6) are electrically connected to the two gate lines (two adjacent ones from G1 to Gn, for example, G3 and G2) located on one side of the four, and the other two of the four (for example, the fourth sub-pixel P4 and the fifth sub-pixel P5) are electrically connected to the two gate lines (two adjacent ones from G1 to Gn, for example, G4 and G5) located on the other side of the four.

[0067] Similarly, it can be known that since the data line is electrically connected to one of the two sub-pixels P on one side thereof and two of the four sub-pixels P spaced apart in the middle on the other side thereof, a total of three scan lines need to be provided on both sides of the sub-pixels P in this row, and it is only necessary that the two sub-pixels P between two adjacent data lines are connected to different gate lines, and the two groups of sub-pixels P spaced apart among the four sub-pixels P between two adjacent data lines are connected to different gate lines.

[0068] In other embodiments, as shown in combination with Figure 1 and Figure 4 , there are four consecutive sub-pixels P arranged along the first direction O1 between every two adjacent data lines, and for multiple sub-pixels P in the same row, the data line (other than the two data lines located on both sides of the multiple sub-pixels P among D1 to Dm) is electrically connected to two of the four sub-pixels P spaced apart on one side thereof and two of the four sub-pixels P spaced apart on the other side thereof, and the distance between the sub-pixel P connected to the data line on one side thereof and the data line is less than the distance between the sub-pixel P connected to the data line on the other side thereof and the data line.

[0069] Specifically, still define the first data line, the second data line, and the third data line (for example, D1, D2, D3 respectively) as shown in Figure 4 , the first sub-pixel P1 to the eighth sub-pixel P8, then the first data line (i.e., D1) is at least connected to the corresponding first sub-pixel P1 and third sub-pixel P3, the second data line (i.e., D2) is connected to the corresponding second sub-pixel P2, fourth sub-pixel P4, sixth sub-pixel P6, and eighth sub-pixel P8, and the third data line (i.e., D3) is at least connected to the corresponding fifth sub-pixel P5 and seventh sub-pixel P7.

[0070] Correspondingly, at this time, since the data line is electrically connected to four sub-pixels P in the same row on both sides thereof, four corresponding gate lines need to be provided for each row of sub-pixels P to at least provide four corresponding gate signals gate for the above four sub-pixels respectively, so that the transistors in the four are turned on in a time-sharing manner. That is, there are four gate lines (four consecutive ones among G1 to Gn) between two adjacent sub-pixels P arranged along the second direction O2; among the multiple sub-pixels P arranged along the first direction O1, the four that are electrically connected to the same data line are respectively electrically connected to the corresponding four gate lines.

[0071] Specifically, as shown in Figure 6 , it can be understood as the local layout diagram corresponding to the above Figure 2 . As shown in combination with Figure 1 , Figure 2 and Figure 6As shown, the sub-pixel P may include a pixel electrode Pi and a corresponding transistor T. The gate g of the transistor T may be electrically connected (e.g., integrally formed) to the corresponding gate line, the source s of the transistor T may be electrically connected (e.g., integrally formed) to the corresponding data line, and the drain d of the transistor T may be electrically connected (e.g., implemented through a via) to the corresponding pixel electrode Pi. Among them, a corresponding common electrode Acom may be provided between each of the sub-pixels P in the same row and each of the gate lines on its two sides. The common electrodes Acom on both sides of the sub-pixels P in the same row also extend to penetrate between two adjacent sub-pixels P in the same row. Moreover, the common electrode Acom may also be overlapped with the drains d of multiple transistors T of the corresponding sub-pixels P in the same row to form a corresponding storage capacitor, and at the same time, the common electrode Acom is used to transmit a common voltage. Further, the above-mentioned multiple common electrodes Acom may be electrically connected to the periphery of the panel body 10 through traces to form a complete current path.

[0072] Among them, in the above-mentioned embodiment as Figures 2 to 4 shown, multiple sub-pixels form multiple pixel units PU arranged along a first direction O1 and a second direction O2. The pixel unit PU includes a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B with different colors arranged along the first direction O1. That is, the multiple sub-pixels P in the first direction O1 include a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B with different colors, and the multiple sub-pixels P in the second direction O2 are the first sub-pixel R, the second sub-pixel G, or the third sub-pixel B of the same color.

[0073] Of course, the first sub-pixel R, the second sub-pixel G, and the third sub-pixel B in the pixel unit PU may also be arranged along the first direction O1, and the multiple sub-pixels P in the same row may be the first sub-pixel R, the second sub-pixel G, or the third sub-pixel B of the same color. At this time, optionally, only a corresponding gate line may be provided for each row of sub-pixels P, that is, the number of gate lines may be equal to the number of rows of sub-pixels P, so that each gate line is electrically connected to a corresponding row of sub-pixels P. At this time, although the multiple sub-pixels P electrically connected to the same data line in the same row are connected to the same gate line, resulting in the corresponding transistors being turned on simultaneously, since their colors are the same, even if the three are affected by the same data voltage, it will not cause mischarging of different color data voltages. At this time, the resolution of the display screen is less than the number of pixel units.

[0074] The present invention also provides a driving method for a display device, combined with Figures 1 to 4As shown, the display device 100 includes a plurality of sub-pixels P arranged in a first direction O1 and a second direction O2. The display device 100 further includes a plurality of gate lines (G1 to Gn) and a plurality of data lines (D1 to Dm). In the first direction O1, at least two of the sub-pixels P are provided between two adjacent data lines. The gate lines are electrically connected to a sub-pixel group formed by corresponding partial sub-pixels among the plurality of sub-pixels arranged in the first direction O1. Specifically, reference may be made to the discussion about the display device 100 above.

[0075] Among them, as Figure 7 shown, the driving method of the display device includes but is not limited to the following steps:

[0076] S1, controlling a plurality of the gate lines to output corresponding plurality of gate signals, so that at least some of the sub-pixels with different polarities in the corresponding data voltages among the plurality of sub-pixels arranged in the first direction are turned on simultaneously, and so that corresponding plurality of sub-pixel groups are turned on in sequence;

[0077] Combined with the definition above, a plurality of sub-pixels electrically connected to the same gate line in the same row of sub-pixels P are defined as a sub-pixel group. Therefore, controlling a plurality of gate pulses in the plurality of gate signals gate output by a plurality of gate lines can control corresponding transistors in a plurality of sub-pixel groups to be turned on in sequence. At the same time, for the same row of sub-pixels P, at least two sub-pixels P with different polarities must be connected to different data lines, so they can belong to the same sub-pixel group and can be turned on simultaneously to obtain different data voltages through different data lines;

[0078] S2, controlling each of the plurality of data lines to transmit data voltages with the same polarity to a plurality of the sub-pixels located on both sides of the data line, and controlling the polarities of the two data voltages respectively transmitted by two adjacent data lines to be opposite, so that the polarities of the plurality of data voltages corresponding to the plurality of sub-pixels arranged in the first direction change alternately, and so that corresponding plurality of sub-pixel groups emit light in sequence;

[0079] As described above, on the basis of reducing the number of data lines by adopting the DLS architecture to reduce the number of source drivers 201, the same data line is set to transmit data voltages of the same polarity to avoid the polarity switching of the data voltages in the same data signal data, which increases power consumption. At the same time, the polarities of the two data voltages respectively transmitted by two adjacent data lines are set to be opposite to avoid all liquid crystal molecules deflecting in the same direction for a long time, resulting in image sticking. And the frequency of the polarity switching of the multiple data voltages corresponding to the multiple sub-pixels P arranged in the first direction O1 reaches its highest frequency. Even when the potentials of the multiple gate signals gate jump (at the end period of the corresponding gate pulses), the brightness change of the display screen in at least the first direction O1 is approximately the average of the brightness changes of two adjacent sub-pixels P, improving the uniformity of the display screen.

[0080] The above has introduced in detail the display device and its driving method provided by the embodiments of the present invention. Specific examples are used in this article to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the technical solution and its core idea of the present invention; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display device, characterized in that, Comprising: A plurality of sub-pixels arranged along a first direction and a second direction; A plurality of data lines, in the first direction, at least two of the sub-pixels are provided between two adjacent data lines, and the data lines are used to transmit data voltages of the same polarity to a plurality of the sub-pixels located on both sides of the data lines, and the polarities of the two data voltages respectively transmitted by two adjacent data lines are opposite; A plurality of gate lines, the gate lines are electrically connected to at least some of the sub-pixels with different polarities among the corresponding data voltages of a plurality of the sub-pixels arranged along the first direction; Wherein, the polarities of the plurality of data voltages corresponding to the plurality of sub-pixels arranged along the first direction alternate.

2. The display device according to claim 1, wherein The polarities of the plurality of data voltages corresponding to the plurality of sub-pixels arranged along the second direction alternate.

3. The display device according to claim 1 or 2, characterized in that, Two of the sub-pixels are provided between every two adjacent data lines; For the plurality of sub-pixels arranged along the first direction, the data line is electrically connected to one of the sub-pixels adjacent to the data line on one side of the data line and one of the sub-pixels spaced from the data line on the other side of the data line.

4. The display device according to claim 3, characterized in that The plurality of data lines include a first data line, a second data line, and a third data line arranged in sequence along the first direction; The plurality of sub-pixels arranged along the first direction include a first sub-pixel close to the first data line and a second sub-pixel close to the second data line located between the first data line and the second data line; The plurality of sub-pixels arranged along the first direction include a third sub-pixel close to the second data line and a fourth sub-pixel close to the third data line located between the second data line and the third data line; Wherein, the first data line is at least electrically connected to the second sub-pixel, the second data line is electrically connected to the first sub-pixel and the third sub-pixel, and the third data line is at least electrically connected to the fourth sub-pixel; Or, the first data line is at least electrically connected to the first sub-pixel, the second data line is electrically connected to the second sub-pixel and the fourth sub-pixel, and the third data line is at least electrically connected to the third sub-pixel.

5. The display device according to claim 3, wherein Two of the gate lines are provided between two adjacent sub-pixels arranged along the second direction; Among the plurality of sub-pixels arranged along the first direction, the two electrically connected to the same data line are respectively electrically connected to two gate lines located on different sides of the two.

6. The display device according to claim 5, wherein, Among the plurality of sub-pixels arranged along the first direction, the two located between two adjacent data lines are respectively electrically connected to two gate lines located on different sides of the two.

7. The display device according to claim 1 or 2, characterized in that, The plurality of data lines include a first data line, a second data line, and a third data line arranged in sequence along the first direction; The plurality of sub-pixels arranged along the first direction include a first sub-pixel close to the first data line and a second sub-pixel close to the second data line located between the first data line and the second data line; The plurality of sub-pixels arranged along the first direction include a third sub-pixel near the second data line and located between the second data line and the third data line, a fourth sub-pixel near the third data line, and further include a fifth sub-pixel near the third sub-pixel and located between the third sub-pixel and the fourth sub-pixel, and a sixth sub-pixel near the fourth sub-pixel; Among them, one of the first sub-pixel and the second sub-pixel is electrically connected to the first data line, and two of the third sub-pixel, the fourth sub-pixel, the fifth sub-pixel, and the sixth sub-pixel that are arranged at intervals are electrically connected to the second data line, and the other two arranged at intervals are electrically connected to the third data line.

8. The display device according to claim 7, wherein, There are three gate lines provided between two adjacent sub-pixels arranged along the second direction; Among the plurality of sub-pixels arranged along the first direction, three that are electrically connected to the same data line are respectively electrically connected to corresponding three gate lines.

9. The display device according to claim 8, wherein, Among the plurality of sub-pixels arranged along the first direction, two that are located between two adjacent data lines are respectively electrically connected to two gate lines on different sides of the two. And Among the four of the plurality of sub-pixels arranged along the first direction that are located between two adjacent data lines, two are electrically connected to two gate lines on one side of the four, and the other two of the four are electrically connected to two gate lines on the other side of the four sub-pixels.

10. A driving method for a display device, characterized in that, The display device includes a plurality of sub-pixels arranged along a first direction and a second direction. The display device further includes a plurality of gate lines and a plurality of data lines. In the first direction, at least two sub-pixels are provided between two adjacent data lines. The gate lines are electrically connected to a sub-pixel group formed by corresponding partial sub-pixels among the plurality of sub-pixels arranged along the first direction. The driving method of the display device includes: Controlling the plurality of gate lines to output corresponding plurality of gate signals, so that at least some of the sub-pixels with different polarities among the corresponding plurality of data voltages of the plurality of sub-pixels arranged along the first direction are simultaneously turned on, and so that the corresponding plurality of sub-pixel groups are sequentially turned on; Controlling each of the plurality of data lines to transmit data voltages of the same polarity to the plurality of sub-pixels on both sides of the data line, and controlling the polarities of the two data voltages respectively transmitted by two adjacent data lines to be opposite, so that the polarities of the corresponding plurality of data voltages of the plurality of sub-pixels arranged along the first direction alternate, and so that the corresponding plurality of sub-pixel groups emit light sequentially.

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