Semiconductor process method and semiconductor structure

Abstract

The invention provides a semiconductor process method and a semiconductor structure. The method comprises the steps that a patterned hard mask layer is arranged on a to-be-etched structure, and sparse gaps and dense gaps expose the upper surface of the to-be-etched structure; arranging an accumulation adjusting layer on the upper surface of the to-be-etched structure exposed from the gap; and performing dry etching along the sparse gaps and the dense gaps to obtain a first groove and a second groove. According to the method, pre-deposition is carried out before the grooves with different widths are etched, accumulation adjusting layers with different thicknesses are obtained in the patterned gaps with different widths, the etching speed of the grooves with different widths is adjusted and controlled, and the etching depths of the grooves with different sizes are uniform; meanwhile, the width ratio range of the sparse gaps and the dense gaps is set, so that the etching depth uniformity of the grooves with different sizes is further ensured; in addition, O2 is needed for etching the structure to be etched, the accumulation adjusting layer is arranged by using part of raw materials for etching the groove, the improvement method is simple, the cost is low, and popularization and application in the actual industry are facilitated.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a semiconductor process method and a semiconductor structure. Background Art

[0002] During the dry etching process, the micro-loading effect is a relatively prominent problem. The micro-loading effect refers to the phenomenon that within the same design pattern, the etching rate is different due to different pattern densities. When etching in a dense area, more reactants are consumed than in a sparse area, resulting in the reactants in the dense area not reaching in time, causing a supply imbalance and a decrease in the etching rate. As a result, the etching rate in the pattern-dense area is lower than that in the sparse area. As Figure 1 shown, the micro-loading effect will cause the etching depth of small-sized trenches to be shallower than that of large-sized trenches, making the etching results of trenches with different sizes uneven, and making it difficult to achieve the etching depth uniformity of trenches or holes with different aspect ratios in the etching process.

[0003] Poor uniformity of the trench etching depth will increase the uncertainty of process parameters, resulting in a decrease in product consistency, and easily affecting the yield of mass production; it also easily leads to inconsistencies and parameter drifts in the electrical performance parameters (such as resistance) at various positions of the device, thereby affecting the overall performance and reliability of the product.

[0004] Therefore, there is an urgent need for a structure or method that can solve the micro-loading effect in dry etching and improve the etching depth uniformity of trenches with different sizes during the etching process.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a semiconductor process method and a semiconductor structure for solving the problem of poor etching depth uniformity of trenches with different sizes during the dry etching process in the prior art.

[0007] To achieve the above purpose, the present invention provides a semiconductor process method, and the semiconductor process method includes:

[0008] Provide an etching structure, and dispose a patterned hard mask layer on the etching structure; the gaps between the patterns of the patterned hard mask layer expose the upper surface of the etching structure, the gaps include sparse gaps and dense gaps, and the ratio of the width of the sparse gap to the width of the dense gap is greater than 1;

[0009] Dispose a stacking adjustment layer on the upper surface of the etching structure exposed by the gaps;

[0010] Using the patterned hard mask layer as a mask, dry-etch downward along the sparse gaps and the dense gaps to obtain a first trench located below the sparse gap and a second trench located below the dense gap within the etching structure.

[0011] Optionally, the ratio of the width of the sparse gap to the width of the dense gap is 1.05 - 1.3.

[0012] Optionally, the etching structure is a silicon substrate, and the stacking adjustment layer is a Si-O polymer.

[0013] Optionally, the hard mask layer includes silicon oxide.

[0014] Optionally, the Si-O polymer is obtained by plasma chemical vapor deposition by introducing SiCl4 and O2 plasmas.

[0015] Optionally, the flow rate ratio of the introduced SiCl4 to O2 is 1:2.

[0016] Optionally, the duration of introducing SiCl4 and O2 is 10 seconds - 20 seconds.

[0017] Optionally, the method for disposing the stacking adjustment layer is plasma chemical vapor deposition.

[0018] Optionally, the ratio of the thickness of the stacking adjustment layer disposed in the sparse gap to the thickness of the stacking adjustment layer disposed in the dense gap is a first ratio, the ratio of the aspect ratio of the first trench to the aspect ratio of the second trench is a second ratio, and the first ratio and the second ratio are in a linear proportional relationship.

[0019] The present invention further provides a semiconductor structure, which is obtained by using any one of the above semiconductor process methods, and the semiconductor structure includes: a first trench and a second trench, the first trench and the second trench have the same depth, and the ratio of the width of the first trench to the width of the second trench is greater than 1.

[0020] As above, the semiconductor process method and the semiconductor structure of the present invention have the following beneficial effects:

[0021] The present invention pre - deposits before grooves with different etching widths, so as to obtain stacking adjustment layers with different thicknesses in the patterned voids of different widths of the hard mask layer, realizing the regulation of the etching rate when etching subsequent grooves with different widths, and making the etching depths obtained after etching grooves of different sizes have uniformity;

[0022] The present invention limits the size ratio range of grooves with different widths by setting the width ratio range of sparse voids and dense voids, thereby further ensuring the uniformity of the etching depths of grooves of different sizes;

[0023] The present invention utilizes the process conditions that the structure to be etched requires O2 during etching itself, and directly uses the raw materials for the etched part of the groove etching to set up the stacking adjustment layer, making the improvement method simple and low - cost, which is conducive to popularization and use in the actual industry. Description of the Drawings

[0024] Figure 1 It shows a schematic structural diagram before etching in different graphic dense areas in the prior art.

[0025] Figure 2 It shows a schematic diagram of the micro - loading effect after etching in different graphic dense areas in the prior art.

[0026] Figure 3 It shows a flowchart of the steps in the semiconductor process method of Embodiment 1 of the present invention.

[0027] Figure 4 It shows a schematic structural diagram of setting the patterned hard mask layer in an example of Step 1 of the semiconductor process method of Embodiment 1 of the present invention.

[0028] Figure 5 It shows a schematic structural diagram of setting the stacking adjustment layer in Step 2 of the semiconductor process method of Embodiment 1 of the present invention.

[0029] Figure 6 It shows a schematic structural diagram of obtaining the first groove and the second groove in Step 3 of the semiconductor process method of Embodiment 1 of the present invention.

[0030] Figure 7 It shows a schematic structural diagram of the semiconductor structure of Embodiment 3 of the present invention.

[0031] Explanation of the Reference Numerals in the Drawings

[0032] 1. Structure to be etched; 2. Sparse void; 3. Dense void; 4. First groove; 5. Second groove; 6. Hard mask layer; 7. First hard mask layer; 8. Second hard mask layer; 9. Stacking adjustment layer. Detailed Embodiment

[0033] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] When detailing the embodiments of the present invention, for the convenience of description, the schematic diagrams showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0035] For the convenience of description, spatial relationship terms such as "beneath", "below", "lower than", "under", "above", "on" may be used herein to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to cover other directions of the device in use or operation, in addition to the directions depicted in the drawings.

[0036] In the context of the present application, the structure in which the first feature is "above" the second feature described may include an embodiment in which the first and second features are in direct contact, and may also include an embodiment in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0037] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex; the numerical ranges given in the present invention default to include the two boundary values of the numerical range without special limitations.

[0038] During the process of dry etching, the micro-loading effect is a frequently encountered and relatively significant problem. The micro-loading effect refers to the phenomenon that in the same design pattern, due to the difference in pattern density, the etching rate is inconsistent. Specifically, when etching in the area with a dense pattern, since more reactants are consumed than in the area with a sparse pattern, the supply of reactants cannot be replenished in time, resulting in a supply imbalance. This imbalance further leads to a decrease in the etching rate, making the etching rate in the area with a dense pattern lower than that in the area with a sparse pattern. As Figure 1 - Figure 2As shown, the microloading effect causes the etching depth of the smaller second trench to be shallower than that of the larger first trench, which directly leads to non-uniformity in the etching results of trenches of different sizes. Therefore, it becomes extremely difficult to achieve uniform etching depth for trenches or holes with different aspect ratios in the etching process. Poor uniformity of the trench etching depth not only increases the uncertainty of process parameters but also leads to a decrease in product consistency, which is likely to affect the yield in mass production. In addition, it is prone to cause inconsistencies and parameter drifts in the electrical performance parameters (such as resistance) at various positions of the device, thereby affecting the overall performance and reliability of the product. This phenomenon is particularly critical in the field of microelectronics manufacturing. Therefore, the existence of the microloading effect may have a significant impact on the quality and performance of the final product, thus posing challenges to the entire production process and product quality control.

[0039] Example 1:

[0040] As Figure 3 shown, this example provides a semiconductor process method, and the semiconductor process method includes:

[0041] Step 1: Provide an etching structure to be etched, and set a patterned hard mask layer on the etching structure to be etched; the gaps between the patterns of the patterned hard mask layer expose the upper surface of the etching structure to be etched, and the gaps include sparse gaps and dense gaps, and the ratio of the width of the sparse gaps to the width of the dense gaps is greater than 1;

[0042] Step 2: Set a stacking adjustment layer on the upper surface of the etching structure to be etched exposed by the gaps;

[0043] Step 3: Use the patterned hard mask layer as a mask to dry-etch downward along the sparse gaps and the dense gaps to obtain a first trench below the sparse gaps and a second trench below the dense gaps in the etching structure to be etched.

[0044] The semiconductor process method of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the semiconductor process method protected by the present invention, and those skilled in the art can make changes according to the actual preparation steps.

[0045] First, perform Step 1. Provide an etching structure 1 to be etched, and set a patterned hard mask layer 6 on the etching structure 1 to be etched; the gaps between the patterns of the patterned hard mask layer 6 expose the upper surface of the etching structure 1 to be etched, and the gaps include sparse gaps 2 and dense gaps 3, and the ratio of the width of the sparse gaps 2 to the width of the dense gaps 3 is greater than 1.

[0046] Specifically, the solution of the present invention is used to solve the problem of poor trench depth uniformity caused by forming trenches with different widths. Therefore, the voids between the patterns of the patterned hard mask layer 6 used as a mask here need to include two types of voids, namely the sparse voids 2 and the dense voids 3, with a width ratio not equal to 1.

[0047] Specifically, the sparse voids 2 and the dense voids 3 are only used to illustrate the situation where there are two different trench widths. In specific application scenarios, there may be more than two different void sizes, all within the protection scope of the present invention. Voids of more than two different sizes can obtain trenches of more than two different widths, so as to reflect the solution of the present invention to the problem of poor depth uniformity caused by trenches of different widths.

[0048] In one embodiment, the hard mask layer 6 includes silicon oxide. Specifically, the hard mask layer 6 may be a material formed by mixing other suitable materials and silicon oxide in addition to silicon oxide.

[0049] By setting the material of the hard mask layer 6 as a mixed material including silicon oxide, the etching selectivity of the hard mask layer 6 for a specific material can be improved by adjusting the material combination, thereby realizing more precise pattern transfer; and the mechanical strength and wear resistance of the hard mask layer can be improved, reducing damage during lithography and etching; optimizing the optical properties of the hard mask layer, improving the resolution and contrast of lithography, and being applicable to high-precision and high-resolution lithography processes.

[0050] In one embodiment, the hard mask layer 6 is silicon oxide.

[0051] By setting the material of the hard mask layer 6 as silicon oxide, it is easy to prepare and has a relatively low cost, being applicable to large-scale industrial production; in addition, the silicon oxide hard mask layer 6 has good compatibility with the etchant in subsequent process steps, which can ensure the smooth progress of the etching process, thereby further improving the manufacturing efficiency and yield rate of semiconductor devices.

[0052] Specifically, the material of the hard mask layer 6 can also be selected as other suitable hard mask materials according to application requirements, all within the protection scope of the present invention.

[0053] In one embodiment, the method for setting the patterned hard mask layer 6 includes: setting a first hard mask layer 7 on the structure to be etched 1; setting a second hard mask layer 8 on the first hard mask layer 7, and the thickness of the second hard mask layer 8 is greater than that of the first hard mask layer 7; patterning the second hard mask layer 8, and the voids between the patterned second hard mask layers 8 expose the upper surface of the first hard mask layer 7, and the voids include sparse voids 2 and dense voids 3, as Figure 4As shown; continue to pattern the exposed first hard mask layer 7, and the gaps between the patterns of the patterned first hard mask layer 7 expose the upper surface of the structure to be etched 1, and the gaps include sparse gaps 2 and dense gaps 3.

[0054] In the present invention, by first patterning the relatively thick second hard mask layer 8 and then using the second hard mask layer 8 as a mask to pattern the first hard mask layer 7, a thin first mask layer with weak anti-plasma etching ability can form high-resolution patterns. At the same time, the thick second hard mask layer 8 has higher anti-plasma erosion resistance and can maintain the integrity of the patterns during the long patterning process, avoiding the failure of the first hard mask layer 7 in a high-temperature or high-energy environment and resulting in pattern distortion, thereby further improving the overall pattern accuracy of the patterning of the hard mask layer 6.

[0055] Then, perform step 2, as Figure 5 shown, a stacking adjustment layer 9 is provided on the upper surface of the structure to be etched 1 exposed by the gap.

[0056] In the present invention, after setting the patterned hard mask layer 6 and before the etching process to obtain the trench, a stacking adjustment layer 9 is provided on the exposed upper surface of the structure to be etched 1. By using the different surface areas within the gaps of different widths of the hard mask layer 6, the deposition thickness of the stacking adjustment layer 9 obtained in the sparse gap 2 is higher, and the deposition thickness of the stacking adjustment layer 9 obtained in the dense gap 3 is lower. Thus, when etching the structure to be etched 1 downward starting from the stacking adjustment layer 9 subsequently, the dry etching rate of the first trench 4 located below the sparse gap 2 is slowed down more significantly by the stacking adjustment layer 9 with a higher deposition thickness, while the effect of slowing down the dry etching rate of the second trench 5 located below the dense gap 3 by the stacking adjustment layer 9 with a lower deposition thickness is poor. Thereby, the etching rates of the first trench 4 and the second trench 5 can be made uniform finally, and the effect that the depths of the finally obtained first trench 4 and second trench 5 are uniform is beneficial to improving the product consistency and the yield of mass production. At the same time, it avoids inconsistent electrical performance parameters or parameter drift at each position of the device, ensuring the overall performance and reliability of the device.

[0057] In one embodiment, the structure to be etched 1 is a silicon substrate, and the stacking adjustment layer 9 is a Si-O polymer.

[0058] Specifically, in the present invention, by setting the material of the stacking adjustment layer 9 as a Si-O polymer, the deposition of the stacking adjustment layer 9 can be achieved by using SiCl4 and O2, so that the same O2 as that used in the subsequent dry etching of the silicon substrate with SF6 and O2 can be used, reducing the proportion of introducing new process materials, improving the convenience of technical improvement using this solution, reducing the improvement cost, and being beneficial to the popularization and use of the improvement solution.

[0059] Specifically, the material of the stacking adjustment layer 9 can also be selected as other suitable materials according to requirements, all within the protection scope of the present invention.

[0060] In one embodiment, the flow ratio of the introduced SiCl4 and O2 is 1:2.

[0061] By setting the flow ratio of SiCl4 and O2 in the present invention, the chemical reaction that occurs can be made as sufficient as possible, optimizing the composition and structure of the stacking adjustment layer 9, so that the reaction rate and uniformity can be better controlled, improving the film quality of the obtained stacking adjustment layer 9, and reducing unnecessary material waste and environmental pollution, which conforms to the development trend of green manufacturing.

[0062] Specifically, both the introduced SiCl4 and O2 are gases.

[0063] In one embodiment, the flow rate of the introduced SiCl4 is 40 sccm - 60 sccm, and the flow rate of the introduced O2 is 80 sccm - 120 sccm.

[0064] Specifically, sccm is Standard Cubic Centimeter per Minute.

[0065] In one embodiment, 50 sccm of SiCl4 and 100 sccm of O2 gas are introduced.

[0066] Specifically, the above flow rate data are the flow rate range data commonly used in the existing process. Since the deposition rate and thickness of the stacking adjustment layer 9 can be accurately controlled by setting the flow rate of the gases introduced when forming the stacking adjustment layer 9, the specific flow rates of SiCl4 and O2 in practical applications are adjusted and set according to the thickness of the stacking adjustment layer 9 required in the process, and are not limited to the above range.

[0067] In one embodiment, during the plasma deposition using SiCl4 and O2, a radio frequency power supply with a power of 1000 W is used to ionize SiCl4 and O2 to generate plasma.

[0068] Specifically, a radio frequency power supply with other suitable powers can also be used to generate plasma, all within the protection scope of the present invention.

[0069] In one embodiment, the duration of introducing SiCl4 and O2 is 10 seconds - 20 seconds.

[0070] By setting the time range for introducing gas when forming the stacking adjustment layer 9, the present invention can precisely control the formation process of the stacking adjustment layer 9, avoiding poor quality of the stacking adjustment layer 9 caused by deposition for too long or too short a time. The setting of this time range not only ensures the uniformity and compactness of the stacking adjustment layer 9, but also ensures the compatibility of the stacking adjustment layer 9 with subsequent process steps. By optimizing this time parameter, the present invention further improves the stability and reliability of the semiconductor process, providing strong support for manufacturing high-quality semiconductor structures.

[0071] Specifically, the present invention can also select other suitable settings for the duration of the reaction gas introduced to obtain the stacking adjustment layer 9, all within the protection scope of the present invention.

[0072] In one embodiment, the method for setting the stacking adjustment layer 9 is plasma chemical vapor deposition.

[0073] The present invention obtains the stacking adjustment layer 9 by using plasma chemical vapor deposition, so that the same plasma equipment as that for subsequent dry etching can be used, avoiding the need to add new equipment for the improvement solution, further reducing the use cost of the improvement solution, and improving the practical application feasibility.

[0074] Specifically, the present invention can also select other suitable methods to obtain the stacking adjustment layer 9, all within the protection scope of the present invention.

[0075] In one embodiment, Si-O polymer is obtained by introducing SiCl4 and O2 plasmas for plasma chemical vapor deposition.

[0076] The present invention obtains the Si-O polymer as the stacking adjustment layer 9 by introducing SiCl4 and O2 plasmas for plasma chemical vapor deposition, so that the same plasma equipment and O2 raw materials as those for subsequent dry etching can be used, avoiding the need to add new equipment for the improvement solution, and reducing the new reaction materials to be introduced, further reducing the use cost of the improvement solution, and improving the practical application feasibility.

[0077] Specifically, the SiCl4 and O2 plasmas are formed by introducing SiCl4 gas and O2 gas into the plasma reaction chamber and then being ionized for plasma chemical vapor deposition.

[0078] Finally, step 3 is performed, as Figure 6 shown, using the patterned hard mask layer 6 as a mask to dry-etch downward along the sparse void 2 and the dense void 3 to obtain the first trench 4 below the sparse void 2 and the second trench 5 below the dense void 3 within the to-be-etched structure 1.

[0079] Through the setting of the stacking adjustment layer 9 in the foregoing step 2 of the present invention, the etching rates of the first trench 4 and the second trench 5 obtained in the subsequent step 3 are controlled, so that the first trench 4 and the second trench 5 with higher depth uniformity can be obtained, thereby improving the overall performance and yield of the device.

[0080] In one embodiment, when dry etching downward along the sparse voids 2 and the dense voids 3, SF6 and O2 are used as etching gases for plasma dry etching.

[0081] Embodiment 2:

[0082] This embodiment provides a semiconductor process method. Other features of the semiconductor process method are basically the same as those in Embodiment 1, and the differences are as follows:

[0083] In this embodiment, the ratio of the width of the sparse void 2 to the width of the dense void 3 is 1.05 - 1.3.

[0084] By setting the ratio range of the widths of the sparse void 2 and the dense void 3, the present invention can ensure the optimal effect of the stacking adjustment layer 9 on the etching depth uniformity between the first trench 4 and the second trench 5.

[0085] Specifically, the present invention can also select other suitable ratio ranges of the widths of the sparse void 2 and the dense void 3, all within the protection scope of the present invention. When the ratio range of the widths of the sparse void 2 and the dense void 3 exceeds 1.05 - 1.3, it is difficult to achieve a linear adjustment of the depths of the first trench 4 and the second trench 5 by simply setting the stacking adjustment layer 9, so that the high uniformity of the finally obtained trench depths cannot reach the optimal state.

[0086] In one embodiment, the ratio of the thickness of the stacking adjustment layer 9 provided in the sparse void 2 to the thickness of the stacking adjustment layer 9 provided in the dense void 3 is a first ratio, the ratio of the depth-to-width ratio of the first trench 4 to the depth-to-width ratio of the second trench 5 is a second ratio, and there is a linear proportional relationship between the first ratio and the second ratio.

[0087] Specifically, when the ratio of the width of the sparse void 2 to the width of the dense void 3 is 1.05 - 1.3, a linear proportional relationship can be formed between the thickness ratio of the stacking adjustment layer 9 and the ratio of the depth-to-width ratios of the trenches, thereby ensuring the uniformity of the obtained trench depths. However, a linear proportional relationship can also be formed between the thickness ratio of the stacking adjustment layer 9 and the ratio of the depth-to-width ratios of the deep trenches by setting other conditions when setting the stacking adjustment layer 9, so as to improve the trench depth uniformity within other trench width ratio ranges, all within the protection scope of the present invention.

[0088] Embodiment 3:

[0089] This embodiment provides a semiconductor structure, which is obtained by using any one of the semiconductor process methods in Embodiments 1-2, such as Figure 7 As shown, the semiconductor structure includes: a first trench 4 and a second trench 5. The first trench 4 and the second trench 5 have the same depth, and the ratio of the width of the first trench 4 to the width of the second trench 5 is greater than 1.

[0090] In the present invention, by using the foregoing semiconductor process method to obtain the first trench 4 and the second trench 5 with different widths, the depth uniformity of the first trench 4 and the second trench 5 in the obtained semiconductor structure can be made higher, so as to achieve the performance parameter uniformity and reliability at different positions of the device, and improve the product consistency and the product production yield.

[0091] In summary, for the semiconductor process method and the semiconductor structure of the present invention, by performing pre-deposition before etching trenches with different widths, a stacking adjustment layer with different thicknesses can be obtained in the patterned voids with different widths of the hard mask layer, so as to realize the regulation of the etching rate when etching subsequent trenches with different widths, and make the etching depths obtained after etching trenches of different sizes have uniformity; at the same time, by setting the width ratio range of the sparse voids and the dense voids, the size ratio range of the trenches with different widths is restricted, thereby further ensuring the etching depth uniformity of the trenches with different sizes; in addition, by using the process condition that O2 is required for etching the structure to be etched itself, the raw materials for etching the etched part of the trench are directly used to realize the setting of the stacking adjustment layer, making the improved method simple and low-cost, and facilitating the popularization and use in the actual industry.

[0092] Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0093] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor process method, characterized in that, The semiconductor process method includes: Providing an etching structure, and disposing a patterned hard mask layer on the etching structure; the gaps between the patterns of the patterned hard mask layer expose the upper surface of the etching structure, and the gaps include sparse gaps and dense gaps, and the ratio of the width of the sparse gaps to the width of the dense gaps is greater than 1; Disposing a deposition adjustment layer on the upper surface of the etching structure exposed by the gaps; Using the patterned hard mask layer as a mask to etch downward along the sparse gaps and the dense gaps by dry etching to obtain a first trench below the sparse gaps and a second trench below the dense gaps in the etching structure.

2. The semiconductor process method according to claim 1, characterized in that, The ratio of the width of the sparse gaps to the width of the dense gaps is 1.05 - 1.

3.

3. The semiconductor process method according to claim 1, wherein The etching structure is a silicon substrate, and the deposition adjustment layer is a Si-O polymer.

4. The semiconductor process method according to claim 3, wherein, The hard mask layer includes silicon oxide.

5. The semiconductor process method according to claim 3, wherein The Si-O polymer is obtained by plasma chemical vapor deposition by introducing SiCl4 and O2 plasmas.

6. The semiconductor process method according to claim 5, characterized in that, The flow ratio of the introduced SiCl4 and O2 is 1:

2.

7. The semiconductor process method according to claim 5, characterized in that, The duration of introducing SiCl4 and O2 is 10 seconds - 20 seconds.

8. The semiconductor process method according to claim 1, wherein The method of disposing the deposition adjustment layer is plasma chemical vapor deposition.

9. The semiconductor process method according to any one of claims 1-8, characterized in that, The ratio of the thickness of the deposition adjustment layer disposed in the sparse gaps to the thickness of the deposition adjustment layer disposed in the dense gaps is a first ratio, the ratio of the aspect ratio of the first trench to the aspect ratio of the second trench is a second ratio, and a linear proportional relationship exists between the first ratio and the second ratio.

10. A semiconductor structure, characterized in that, The semiconductor structure is obtained by using the semiconductor process method according to any one of claims 1 - 9, and the semiconductor structure includes: a first trench and a second trench, the first trench and the second trench have the same depth, and the ratio of the width of the first trench to the width of the second trench is greater than 1.

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